MP8007GV-P [MPS]
FULLY-INTEGRATED 802.3AF-COMPATI;
| 型号： | MP8007GV-P |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | FULLY-INTEGRATED 802.3AF-COMPATI |
| 文件： | 总27页 (文件大小：1181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP8007
Fully-Integrated 802.3af-Compatible PoE
PD Interface with 13W Primary-side
Regulated Flyback or Buck Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP8007 is an integrated IEEE 802.3af
compatible PoE Powered Device with PD
interface and power converter. It is targeted for
isolated or non-isolated 13W PoE application.
Compatible with 802.3af Specifications
Support 13W PoE Power Application
100V 0.48Ω PD Integrated Pass Switch
120mA PD Inrush Current
840mA PD Operation Current Limit
Auxiliary Adaptor ORing Power Supply
Integrated 180V Switching Power MOSFET
Supports Primary-Side Regulated Flyback
without Opto-Coupler Feedback
Supports Low-side Switch Buck Converter
Up to 3A Programmable Switching Current
Limit
The PD interface has all the functions of IEEE
802.3af, including detection, classification,
120mA inrush current, 840mA operation current
limit as well as 100V Hot-swap MOSFET.
The DCDC converter uses fixed peak current
and
variable
frequency
discontinuous
conduction mode (DCM) to regulate constant
output voltage. The primary-side regulation
without opto-coupler feedback in flyback mode
simplifies the design while buck mode
continues minimizes the solution size for non-
isolated applications. A 180V integrated power
MOSFET optimizes the device for various wide
voltage applications.
OLP, OVP, Open-Circuit, and Thermal
Protection
Minimal External Components
Available in QFN-28 (4mmx5mm) Package
APPLICATIONS
IEEE 802.3af-Compliant Devices
Security Camera
VoIP Phones
WLAN Access Points
IoT Devices
The MP8007 features protection including over
current protection, over voltage protection, open
circuit protection and thermal shutdown.
The MP8007 can support a front-end solution
for PoE-PD application with minimum external
component, it is available in QFN-28
(4mmX5mm) package.
All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For
MPS green status, please visit MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks
of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
90
85
80
75
70
65
60
55
50
45
40
10
100
1000
MP8007 Rev.1.0
6/27/2016
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1
MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP8007GV
QFN-28 (4mm X 5mm)
See blew
* For Tape & Reel, add suffix –Z (e.g. MP8007GV–Z)
TOP MARKING
MPS: MPS prefix:
Y: year code;
WW: week code:
MP8007: part number;
LLLLLL: lot number;
PACKAGE REFERENCE
TOP VIEW
MP8007 Rev.1.0
6/27/2016
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
Thermal Resistance (8)
QFN-28 (4mmx5mm) ……. ….…40
θJA
θJC
9 °C/W
ABSOLUTE MAXIMUM RATINGS (1)
Pins Voltage Respects to VSS: (2)
VDD, RTN, DET, T2P, AUX, GND, AGND
..............................................-0.3V to +100V
CLASS, FTY ................................-0.3V to +6.5V
Pins Voltage Respects to GND(2):
VDD ............................................-0.3V to +100V
SW..............................................-0.7V to +180V
FB1 ...........................................-0.7V to +6.5V(3)
VCC(4), MODE, ILIM, PG..............-0.3V to +6.5V
Pins Voltage Respects to VDD:
Notes:
1) Exceeding these ratings may damage the device.
2) GND and AGND must be connected to RTN
3) Refer to the “Converter Output Voltage Setting” section.
4) VCC voltage can be pulled higher than this rating, but the
external pull-up current should be limited. Refer to “VCC
sinking current” rating and “VCC Power Supply Setting”
section.
5) When VDD to Adapter-ground voltage is high, AUX-VDD
voltage may exceed -6.5V if the divider resistor is not
appropriate, in this condition VDD will clamp the -6.5V voltage
on AUX pin, but the current should be limited by external
resistor.
6) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
AUX, FB2.....................................-6.5V to +0.3V
Pins Current:
T2P ........................................................... 10mA
VCC Sinking Current............................ 1.5 mA(4)
AUX Sinking Current.............................. -5 mA(5)
FB1 Sinking Current.............................. ±1 mA(3)
(6)
Continuous Power Dissipation (TA=+25)
QFN28 4X5……………………….…..……3.12W
Junction Temperature...............................150C
Lead Temperature ....................................260C
Storage Temperature............... -65C to +150C
7) The device is not guaranteed to function outside of its
operating conditions.
8) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (7)
Supply Voltage VDD .............................0V to 57V
Switching Voltage VSW ................-0.5V to +150V
Maximum T2P Current................................ 5mA
Maximum VCC Sinking Current............ 1.2mA(4)
Maximum AUX Sinking Current ............. -3 mA(5)
Maximum FB1 Sinking Current.......... ±0.5 mA(3)
Maximum Switching Frequency............ 200 kHz
Maximum Switching Current Limit ................. 3A
Operating Junction Temp. (TJ). -40°C to +125°C
MP8007 Rev.1.0
6/27/2016
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
ELECTRICAL CHARACTERISTICS
VDD, CLASS, DET, T2P and RTN voltages are referred to VSS, and all other pin voltages are
referred to GND, GND and RTN are shorted together. VDD – VSS = 48V, VSS = 0V; RDET = 24.9kΩ,
RCLASS =41.2Ω. TJ = -40°C to +125°C, typical values are tested at TJ = 25C, unless otherwise
noted.
PD Interface Section
Parameter
Symbol Condition
Min
Typ
Max
Units
Detection
Detection on
Detection off
DET Leakage Current
VDET-ON VDD Rising
1.9
11
V
V
VDET-OFF VDD Rising
VDET-LK VDET=VDD=57V, Measure IDET
0.1
5
μA
V
DD=10.1V, float DET pin, not in
Bias Current
12
μA
Mark event, Measure ISUPPLY
VDD=2.5V, Measure ISUPPLY
VDD=10.1V, Measure ISUPPLY
96
99
102
425
μA
μA
Detection Current
IDET
395
410
Classification
Classification Stability Time
90
μs
13V<VDD< 21V
1mA<ICLASS< 42mA
VCLASS Output Voltage
VCLASS
1.1
1.16
1.21
V
13≤VVDD≤21V, Guaranteed by VCLASS
RCLASS=578Ω, 13V≤VDD≤21V
RCLASS=110Ω, 13V≤VDD≤21V
1.8
9.9
2
2.4
10.55
18.7
28.15
40.4
11.3
19.8
29.7
42.6
Classification Current
ICLASS
mA
RCLASS=62Ω, 13V≤VDD≤21V
RCLASS=41.2Ω, 13V≤VDD≤21V
RCLASS=28.7Ω, 13V≤VDD≤21V
17.7
26.6
38.2
Classification Lower
Threshold
Class Regulator Turns on, VDD
Rising
VCL-ON
VCL-OFF
VCL-HYS
11.8
21
12.5
22
13
23
V
V
V
Classification Upper
Threshold
Class Regulator Turns off, VDD
Rising
Low side Hysteresis
High side Hysteresis
0.8
0.5
5
Classification Hysteresis
Mark Event Reset Threshold VMARK-L
4.5
11
5.5
12
2
V
V
Max Mark Event Voltage
Mark Event Current
VMARK-H
IMARK
11.5
1.5
0.5
mA
kΩ
Mark Event Resistance
RMARK 2-point Measure at 7V and 10V
IIN-CLASS VDD = 17.5V, CLASS Floating
ILEAKAGE VCLASS = 0 V, VDD = 57V
12
IC Supply Current during
Classification
220
300
1
μA
μA
Class Leakage Current
PD UVLO
VDD Turn on Threshold
VDD Turn off Threshold
VDD-VSS-R VDD Rising
VDD-VSS-F VDD Falling
35
29
37.5
31
40
33
V
V
VDD-VSS-
VDD UVLO Hysteresis
4.9
V
HYS
IC Supply Current during
Operation
IIN
450
μA
MP8007 Rev.1.0
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
ELECTRICAL CHARACTERISTICS (continued)
VDD, CLASS, DET, T2P and RTN voltages are referred to VSS, and all other pin voltages are
referred to GND, GND and RTN are shorted together. VDD – VSS = 48V, VSS = 0V; RDET = 24.9kΩ,
RCLASS =41.2Ω. TJ = -40°C to +125°C, typical values are tested at TJ = 25C, unless otherwise
noted.
PD Interface Section
Parameter
Symbol Condition
Min
Typ
Max
Units
Pass Device and Current Limit
On Resistance
RON-RTN IRTN=600mA
0.48
1
Ω
Leakage Current
V
DD=VRTN=57V
15
μA
IRTN-LK
ILIMIT
IINRUSH VRTN=2V
VRTN Falling
Current Limit
VRTN=1V
720
80
840
120
1.2
920
mA
mA
V
Inrush Current Limit
Inrush Current Termination
Inrush to Operation Mode
Delay
TDELAY
100
10
1
ms
V
Current Fold-back Threshold
VRTN Rising
RTN Rising to Inrush Current
V
Fold-back Deglitch Time
ms
Fold-back
T2P
T2P Output Low Voltage
IT2P=2mA, respect to VSS
VT2P=48V
0.1
0.3
1
V
T2P Output High Leakage
Current
μA
AUX
AUX High Threshold
Voltage(9)
Respect to VDD
-2.3
2
V
AUX Low Threshold
Voltage(9)
Respect to VDD
VDD -VAUX=6V
-0.6
V
AUX Leakage Current
PG
μA
PG Output High Voltage
PG pin floating
5.5
30
V
PG is logic high, pull down PG
pin to 0V
Source Current Capability
PG Pull Down Resistance
μA
PG is logic low, pull up PG pin
to 1V
460
kΩ
V
PG High-Level Voltage to
Enable DCDC Converter
VPG-EN-H
VPG-EN-L
3.9
PG Low-Level Voltage to
Disable DCDC Converter
1.3
V
PD Thermal Shutdown
Thermal Shut down
Temperature(10)
TPD-SD
150
20
ºC
ºC
Thermal Shut down
Hysteresis(10)
TPD-HYS
MP8007 Rev.1.0
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
ELECTRICAL CHARACTERISTICS (continued)
VDD, CLASS, DET, T2P and RTN voltages are referred to VSS, and all other pin voltages are
referred to GND, GND and RTN are shorted together. VDD – VSS = 48V, VSS = 0V; RDET = 24.9kΩ,
RCLASS =41.2Ω. TJ = -40°C to +125°C, typical values are tested at TJ = 25C, unless otherwise
noted.
DCDC Converter Section
Parameter
Symbol Condition
Min
Typ
Max
Units
Converter Power Supply and UVLO
Converter VDD UVLO
Rising Threshold
VDD-RTN-R PG-RTN=5V, Test VDD-RTN
VDD-RTN-F PG-RTN=5V, Test VDD-RTN
10.5
11.6
12.8
V
Converter VDD UVLO
Falling Threshold
VCC Regulation(11)
7.4
4.8
4.3
8.2
5.4
4.7
9
V
V
V
VCC
Load = 0mA to 10mA
5.9
5.1
VCC UVLO Rising
Threshold(11)
VDD is higher than UVLO, VCC
rising
VCC-R
VCC UVLO Falling
Threshold(11)
VDD is higher than UVLO, VCC
falling
VCC-F
IQ
4
4.5
4.8
V
VFB1 = 2.2 V, VFB2 = VDD, Test
Quiescent Current
0.87
mA
supply from VDD to VSS
Voltage Feedback
Respect to GND, TJ = 25°C
1.94
1.93
1.99
1.99
10
2.04
2.05
50
V
V
FB1 Reference Voltage
VREF1
IFB1
Respect to GND, TJ = -40°C to
+125°C
FB1 Leakage Current
Respect to GND, VFB1 = 2V
nA
mV
Flyback Mode DCM Detect
Threshold on FB1
VDCM1 Respect to GND
25
50
75
FB1 Open-circuit Threshold VFB1OPEN
-90
-60
-20
mV
FB1 OVP Threshold
VFB1OVP
120%
125%
130%
VREF1
Minimum Diode Conduction
Time for FB1 Sample
TSAMPLE
1.4
2.2
-1.88
-1.88
10
3
-1.805
-1.8
50
μs
V
Respect to VDD, TJ = 25°C
-1.955
-1.96
FB2 Reference Voltage
VREF2
IFB2
Respect to VDD, TJ = -40°C to
+125°C
V
FB2 Leakage Current
Respect to VDD, VFB2 = -2V
nA
V
Buck Mode DCM Detect
Threshold on SW
VDCM2 Respect to VDD
RON-SW VCC = 5.4V
0
0.14
Switching Power Device
On Resistance
0.8
Ω
Current Sense
Switching Current Limit
ILIMIT
TLEB
RILIM = 53.6kΩ, L = 47μH
1.85
2.05
450
2.25
A
Switching Current Leading-
edge Blanking Time
ns
MP8007 Rev.1.0
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
ELECTRICAL CHARACTERISTICS (continued)
VDD, CLASS, DET, T2P and RTN voltages are referred to VSS, and all other pin voltages are
referred to GND, GND and RTN are shorted together. VDD – VSS = 48V, VSS = 0V; RDET = 24.9kΩ,
RCLASS =41.2Ω. TJ = -40°C to +125°C, typical values are tested at TJ = 25C, unless otherwise
noted.
DCDC Converter Thermal Shutdown
Thermal Shutdown
TSD
150
20
ºC
ºC
Temperature(10)
Thermal Shutdown
Hysteresis(10)
THYS
9) If VDD-AUX>2.3V, IC enable adapter input, if VDD-AUX<0.6V, IC enable PSE input. Refer to "Wall adaptor detection and operation"
section for AUX setting.
10) Guaranteed by characterization, not tested in production.
11) The maximum VCC UVLO rising threshold is higher than the minimum VCC regulation in the EC table due to production distribution.
However, for one unit, VCC regulation is higher than the VCC UVLO rising threshold. The VCC UVLO rising threshold is about 87 percent
of the VCC regulation voltage, and the VCC UVLO falling threshold is about 83 percent of the VCC regulation voltage in one unit.
MP8007 Rev.1.0
6/27/2016
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
TYPICAL CHARACTERISTICS
VIN = 48V, VOUT = 12V, IOUT = 1A, TA = 25°C, unless otherwise noted.
MP8007 Rev.1.0
6/27/2016
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
TYPICAL CHARACTERISTICS (continued)
VIN = 48V, VOUT = 12V, IOUT = 1A, TA = 25°C, unless otherwise noted.
MP8007 Rev.1.0
6/27/2016
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 48V, VOUT = 12V, IOUT = 1A, TA = 25°C, unless otherwise noted.
MP8007 Rev.1.0
6/27/2016
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 48V, VOUT = 12V, IOUT = 1A, TA = 25°C, unless otherwise noted.
I
= 10mA
I
= 1A
OUT
OUT
V
/AC
OUT
1V/div.
V
V
OUT
OUT
5V/div.
5V/div.
V
V
IN
IN
50V/div.
50V/div.
V
V
SW
SW
50V/div.
50V/div.
I
OUT
500mA/div.
I
I
PRI
PRI
2A/div.
2A/div.
V
/AC
OUT
V
OUT
200mV/div.
V
OUT
5V/div.
V
2V/div.
5V/div.
FB1
V
IN
50V/div.
V
SW
V
SW
50V/div.
50V/div.
I
OUT
500mA/div.
I
I
PRI
PRI
2A/div.
2A/div.
V
OUT
5V/div.
V
FB1
2V/div.
V
SW
50V/div.
I
PRI
2A/div.
MP8007 Rev.1.0
6/27/2016
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
PIN FUNCTIONS
PIN#
Name
AUX
DET
N/C
Description
Auxiliary power input detector. Use this pin for adaptor power supply application.
Drive VDD-AUX higher than 2.3V to disable hot-swap MOSFET and CLASS pin
function, and force T2P and PG active.
1
2
Connect 24.9kΩ resistor between VDD and DET for PoE detection.
3, 11, 14,
15, 19, 22,
28
Not connected internally, can be connected to GND pin and exposed thermal pad in
layout.
4
VDD
FB2
Positive power supply terminal from PoE input power rail.
Feedback pin for non-isolated buck solution. Connect FB2 to VDD in flyback
application
5
Buck mode or flyback mode select pin. MODE is pulled up internally to VCC through
6
MODE a 1.5µA current source. Float MODE for buck application mode; connect MODE to
GND for flyback application mode.
7
8
FB1
Feedback for fly-back solution. Connect FB1 to GND in buck application
DCDC converter switching current limit program pin. Connect ILIM to GND through a
resistor to program the peak current limit.
ILIM
Analog power return for DCDC converter control circuit. Connect to GND through
single point.
9
AGND
Supply bias voltage pin, powered through internal LDO from VIN. It is recommended
to connect a capacitor (no less than 1µF) between VCC and GND.
10
VCC
SW
12,13
16,17
Drain of converter switching MOSFET.
Switching converter power return. Connect to RTN for PoE power supply. Exposed
thermal pad can be connected to GND plane for heat sink.
GND
PD supply power good indicator. This signal will enable the DCDC converter
internally. It is pulled up by internal current source in output high condition, suggest
float it in application.
18
PG
20,21
23,24
25
RTN
VSS
FTY
Drain of PD Hot-swap MOSFET, connect GND and AGND to this pin.
Negative power supply terminal from PoE input power rail.
Factory use only, must be connected to VSS in application.
26
CLASS Connect resistor from CLASS to VSS to program classification current.
Type 2 PSE indicator, open-drain output. Pulled low to VSS indicates the presence of
a Type-2 PSE or AUX is enabled.
27
T2P
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
FUNCTION DIAGRAM
VDD
AUX
Detection
2.7V - 10.1V
Inrush and
Current Limit
DET
T2P
Startup Delay
Control
VSS
Classification
14.5V – 20.5V
CLASS
Control Logic
and
0/30μA
Gate Driver
PG
Mark Event
6.9V – 10.1V
5.5V
Current /
Voltage Sense
VSS
VCC
RTN
Power Supply
Management
DCDC Enable
FB1
DCM Detection
SW
Feedback
Sampling
Driver
Management
Protection
FB2
Current Sense
ILIMT Program
GND
AGND
MODE
ILIM
Figure 1: Functional Block Diagram
MP8007 Rev.1.0
6/27/2016
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
OPERATION
Compared with IEEE802.3af, the IEE802.3at
standard establishes a higher power allocation
for Power-over-Ethernet while maintaining
backwards compatibility with the existing
converter. The PD interface also has 802.3at
function, but DCDC converter only support 13
W output, so MP8007 is only used for 802.3af
power design. Along with the PSE it operates
as a safety device to supply voltage only when
the power sourcing equipment recognizes a
unique, tightly specified resistance at the end of
an unknown length of Ethernet cable. After
powered from PSE, the MP8007 will regulate
the output voltage based on application with
isolated or non-isolated topology. Figure 1
shows the function diagram of this device, and
Figure 2 shows typical PD interface power
operation sequence.
IEEE802.3af
systems.
Power
Sourcing
Equipments (PSE) and Powered Devices (PD)
are distinguished as Type-1 complying with the
IEEE 802.3af power levels, or Type-2
complying with the IEEE 802.3at power levels.
IEEE802.3af/at standard establishes a method
of communication between PD and PSE with
detection, classification and mark event.
The MP8007 is one integrated PoE solution
with IEEE 802.3af PD interface and 13W DCDC
Figure 2: PD Interface Operation Description
Detection
The detection resistance seen from PI is the
result of the input bridge resistance in series
with the VDD loading. The input bridge
resistance is partially cancelled by MP8007
effective leakage resistance during detection.
The RDET connected between DET and VDD pin
is presented as a load to the PSE in the
Detection Mode, when the PSE applies two
“safe” voltages between 2.7V to 10.1V while
measuring the change in current drawn in order
to determine the load resistance. 24.9kꢀ(1%)
resistor between VDD and DET pins is
recommended to present one correct signature,
and the valid signature resistance seen from
power interface (PI) is between 23.7kꢀ and
26.3kꢀ.
Classification
The classification mode can specify to the PSE
the expected load range of the device under
power, so that the PSE can intelligently
distribute power to as many loads as it can
within its maximum current capability. The
classification mode is active between 14.5V and
MP8007 Rev.1.0
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
20.5V. MP8007 presents
classification mode as showing in Table 1.
a
current in
input capacitor CBULK. The startup charging
current is around 120mA.
Table 1– CLASS Resistor Selection
If RTN drops to lower than 1.2V, the hot-swap
current limit will change to 840mA. After the
TDELAY from UVLO starting, MP8007 will assert
PG signal and go from the startup mode to the
running mode if inrush period elapse, the PG
signal can enable down-stream DCDC
converter internally.
Max. Input
Classification RCLASS
Current (mA)
Class
Power to
PD (W)
12.95
3.84
(Ω)
0
1
2
3
4
2
578
110
62
41.2
28.7
10.55
18.7
28.15
40.4
6.49
12.95
25.5
If VDD-VSS drops below falling UVLO, the Hot-
swap MOSFET and DCDC converter both are
disabled.
2-Event Classification
If output current overloads on the internal pass
MOSFET, current limit works and VRTN-VSS rises.
If VRTN rises above 10V for longer than 1ms, or
rises above 20V, the current limit reverts to the
inrush value, and PG is pulled down internally
to disable DCDC regulator at the same time.
MP8007 can be used as a Type-1 PD as class
0–3 in Table 1, it also distinguishes class 4 with
2-event
classification.
Generally
it
is
recommended to set MP8007 in class 0-3
because the DCDC converter can only deal
with 13W power.
Figure 3 shows the current limit, PG and T2P
work logic during startup from PSE power
supply.
In 2-event classification, the Type-2 PSE reads
the power classification twice. Figure 2 presents
an example of a 2-event classification. The first
classification event occurs when the PSE
presents a voltage between 14.5V-to-20.5V to
MP8007 and the MP8007 presents a class 4
loads current. The PSE then drops the input
voltage into the mark voltage range of 6.9V to
10.1V, signaling the first mark event. MP8007
presents a load current between 0.5mA to 2mA
in the mark event voltage range
The PSE repeats this sequence, signaling the
second classification and second mark event.
The PSE then applies power to MP8007 and
MP8007 charges up the DCDC input capacitor
CBULK (C1 of schematic on page 1) with a
controlled inrush current. When CBULK is fully
charged, the T2P pin presents an active low
signal with respect to VSS after TDELAY. The T2P
output becomes inactive when the MP8007
input voltage VDD falls below UVLO as figure 3
work flow shows. With class 0-3 setting in
MP8007, 2-event classification and T2P can be
ignored.
PD Interface UVLO and Current Limit
When PD is powered by PSE and VDD is
higher than turn on threshold, the Hot-swap
switch will start pass a limited current IINRUSH to
charge the down stream DC-to-DC converter’s
Figure 3: Startup Sequence
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
Wall
Power
Adaptor
Detection
and
Operation
For applications where an auxiliary power
source such as a wall adapter is used to power
the device, the MP8007 features wall power
adapter detection as showing in figure 4. Once
the input voltage (VDD - VSS) exceeds about
11.5V, the MP8007 enable wall adapter
detection. The wall power adapter detection
resistor divider is connected from VDD to
negative terminal of adaptor, and DADP3 is
added for more accurate hysteresis. There is a
-2.3V reference voltage from AUX to VDD for
adaptor detection. The adaptor is detected
when AUX voltage triggers:
Figure 4: Adaptor Power Detection
Power Good Indicator (PG)
The PG signal is driven by internal current
source. After TDELAY from UVLO starting and
RTN drops to 1.2V, or a wall power adapter is
detected, the PG signal will be pulled high to
indicate power condition and enable the
downstream DCDC converter. Figure 3 shows
the PG logic when powering from PSE, PG will
be high if adaptor is detected.
RADPUP
(1)
2.3V
VDD VAUX (VADP VDADP3 )
RADPUP RADPDOWN
Where, VADP is adaptor voltage, VDADP3 is the
zener voltage, RADPUP and RADPDOWN are the
AUX divider resistors from adaptor power.
If applied adapter voltage is much higher than
the design adapter voltage, VDD-VAUX voltage
will be high, if it is higher than 6.5V, the
MP8007 inner circuit will clamp the VDD-VAUX
voltage at 6.5V, then a current will flow out
through the AUX pin, the current should be
limited lower than 3mA by external resistor
(RADPUP/RADPDOWN or RT resistor from the resistor
divider to AUX PIN.)
To make MP8007 work stable with adaptor
power, one Schottky diode DAPD1 (D4 in
schematic on page 1) is required between
negative terminal of adaptor and VSS. DAPD2
(D5 in schematic on page 1) is used to block
reverse current between adaptor and PSE
power source. When a wall adapter is detected,
the internal MOSFET between RTN and VSS
turns off, classification current is disabled and
T2P becomes active. The PG signal is active
when adaptor power is detected, so that it can
enable the downstream DCDC converter even
input hot-swap MOSFET is disabled.
DCDC Converter Startup and Power Supply
Once PD input overrides its UVLO, it will charge
DCDC converter’s input capacitor (between
VDD and RTN) with PD inrush current limit.
DCDC converter has an internal start-up circuit.
When voltage between VDD and GND is higher
than 4.3 V, the capacitor at VCC is charged
through the internal LDO. Normally VCC is
regulated at 5.4 V (if VDD is high enough). With
the exception of PD interface UVLO, the DCDC
converter has an additional VIN UVLO (11.6V)
and VCC UVLO (4.7V). When VDD-GND is
higher than the 11.6V UVLO, VCC is charged
higher than the 4.7V UVLO, and PG pin is
pulled high by PD interface, DCDC converter
starts switching.
VCC can be powered from the transformer
auxiliary winding to save IC power loss. Refer
to the “Vcc Power Supply Setting” section for
more details.
Flyback and Buck Mode Converter
The DCDC converter supports both flyback and
buck topology applications. Connect MODE to
GND to set the DCDC converter in flyback
mode, and float MODE to set the DCDC
converter in buck mode. MODE is pulled up
internally to VCC through a 1.5µA current source.
Do not connect MODE to VDD externally in
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
1
2
buck mode, and do not place a resistor
between MODE and GND in flyback mode.
(6)
IOUT
DIPK
Converter Switching Work Principle
Where, D is the inductor current conducting
duty cycle.
After startup, DCDC converter works in
discontinuous conduction mode (DCM). The
second switching cycle will not start until the
inductor current drops to 0A. In each cycle, the
internal MOSFET is turned on, and the current-
sense circuit senses the current IP(t) internally.
Use Equation (2) to calculate the rate at which
the current rises linearly in flyback mode:
dIp(t)
dt
V
IN
(2)
Figure 6—Inductor current waveform
Converter Light-Load Control
LM
In flyback mode (if the load decreases), DCDC
converter stretches down the frequency
automatically to reduce the power transferring
while keeping the same IPK in each cycle. An
approximate 10 kHz minimum frequency is
applied to detect the output voltage even at a
very light load. During this condition, the
switching IPK jumps between 20 percent of the
normal IPK and 100 percent of the normal IPK to
reduce the power transferring. The DCDC
converter still transfers some energy to the
output even if there is no load on the output due
to the 10 kHz minimum frequency. This means
that some load is required to keep the output
voltage in regulation, or else VOUT will rise and
trigger OVP.
When IP(t) rises up to IPK, the internal MOSFET
turns off (see Figure 5). The energy stored in
the primary-side inductance transfers to the
secondary-side through the transformer.
Figure 5—Primary-side current waveform
The primary-side inductance (LM) stores energy
in each cycle as a function of Equation (3):
1
E LMIP2K
(3)
2
In buck mode, the DCDC converter has no
minimum frequency limit, so it stretches down
to a very low frequency and regulates the
output automatically even there is no load on
the output.
Calculate the power transferred from the input
to the output with Equation (4):
1
P LMIP2KF
(4)
S
2
Frequency Control
Where FS is the switching frequency. When IPK
is constant, the output power depends on FS
and LM.
By monitoring the auxiliary winding voltage in
flyback mode or monitoring the SW voltage in
buck mode, the DCDC converter detects and
regulates the inductor current in DCM. The
frequency is controlled by the peak current, the
current ramp slew rate, and the load current.
The maximum frequency occurs when the
DCDC converter runs in critical conduction
mode, providing the maximum load power. The
DCDC converter switching frequency should be
lower than 200 kHz in the design.
Use Equation (5) to calculate the rate at which
the current rises linearly in buck mode:
dIp(t)
dt
V VOUT
IN
(5)
LM
The internal MOSFET turns off when IP(t) rises
to IPK (see Figure 6). The output current is
calculated with Equation (6):
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
Output Voltage Control
Where ILIM is the current limit in A, VL is the
voltage applied on the inductor when the
MOSFET turns on, R3 is the setting resistor in
In flyback application, the DCDC converter
detects the auxiliary winding voltage from FB1
during the secondary-side diode conduction
period.
kꢀ, and L is the inductor in μH.
The current limit cannot be programmed higher
than 3A.
Assume the secondary winding is the master,
and the auxiliary winding is the slave. When the
secondary-side diode conducts, the FB1
voltage is calculated with Equation (7):
If Input voltage is very low, the inductor current
may increase slowly, it will take a long time to
meet the setting current limit. MP8007
integrates a ~7us max on time. After the max
on time, MOSFET will turn off, even the
inductor current doesn`t meet the setting
current limit.
NA
NS
R2
(7)
VFB1
(VOUT VD1F )
R1 R2
Where:
Converter Leading-Edge Blanking
VD1F is the output diode forward-drop voltage.
VOUT is the output voltage.
Transformer parasitic capacitance induces a
current spike on the switching power FET when
the power switch turns on. The DCDC converter
includes a 450 ns leading-edge blanking period
to avoid falsely terminating the switching pulse.
During this blanking period, the current sense
comparator is disabled, and the gate driver
cannot switch off.
NA and NS are the turns of the auxiliary winding
and the secondary-side winding, respectively.
R1 and R2 are the resistor dividers for sampling.
The output voltage differs from the secondary-
winding voltage due to the current-dependant
diode forward voltage drop. If the secondary-
winding voltage is always detected at a fixed
secondary current, the difference between the
output voltage and the secondary-winding
voltage is a fixed VD1F. DCDC converter starts
sampling the auxiliary-winding voltage after the
internal power MOSFET turns off for 0.7 μs and
finishes the sampling after the secondary-side
diode conducts for 3μs. This provides good
regulation when the load changes. However,
the secondary diode conducting period must be
longer than 3μs in each cycle, and the FB1
signal must be smooth in 0.7μs after the switch
turns off.
DCDC Converter DCM Detection
The DCDC switching regulator operates in
discontinuous conduction mode in both flyback
and buck modes.
In flyback mode, the DCDC converter detects
the falling edge of the FB1 voltage in each cycle.
The second cycle switching will not start unless
the chip detects a 50 mV falling edge on FB1.
In buck mode, the DCDC converter detects the
falling edge of the SW voltage in each cycle.
The second cycle switching will not start unless
the chip detects 0.14 V falling edge between
VSW-VDD.
With a buck solution, there is one FB2 pin
referred to VDD. It can be used as the
reference voltage for the buck application. The
output voltage is referred to VDD and does not
have the same GND as the input power.
Over-Voltage & Open-Circuit Protection
In flyback mode, the DCDC converter includes
over-voltage protection (OVP) and open-circuit
protection. If the voltage at FB1 exceeds 125
percent of VREF1, or FB1’s -60 mV falling edge
cannot be detected because the feedback
resistor is removed, immediately the DCDC
converter shuts off the driving signal and enters
hiccup mode by re-charging the internal
capacitor. The DCDC converter resumes
normal operation when the fault is removed.
Programming the Switching Current Limit
The switching converter current limit is set by
an external resistor (R3 in schematic on page 1)
from ILIM to ground. The value of R3 can be
estimated with Equation (8):
100 VL 0.18
(8)
ILIM
R3
L
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
In buck mode, if the voltage at FB2 is higher
than the reference voltage, the DCDC converter
stops switching immediately.
Thermal Shutdown
Thermal shutdown is implemented to prevent
the chip from thermally running away. MP8007
has separated temperature monitor circuit for
PD and switching devices, DC converter
thermal protection won't affect PD interface but
PD temperature protection will turn off both PD
and DC converter. When the temperature is
lower than its recovery threshold, thermal
shutdown is gone and the chip is enabled.
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
VADP
VDD
APPLICATION INFORMATION
RADPUP
Detection Resistor
PG
AUX
VSS
In the Detection Mode, a resistor connected
between DET and VDD pin is needed as a load
to the PSE. The resistance is calculated as a
ΔV/ΔI, with an acceptable range of 23.7kꢀ to
26.3kꢀ. Use a typical value of 24.9kꢀ as
detection resistor.
RADPDOWN
RTN
DADP3
DADP1
DADP2
Adaptor GND
Classification Resistor
Figure 7: Wall Adaptor Detection Circuit
In order to distribute power to as many loads as
possible from PSE, a resistor between CLASS
and VSS pins is used to classify the PD power
level, which draws a fixed current set by
classification resistor. The power supplied to
PD set by classification resistor is shown in
Table 1. Typical voltage on CLASS pin is 1.16V
in classification range, and it produces about
33mW power loss on class resistor in Class 3
condition.
To prevent the converter from operating at an
excessively low adapter voltage, choose a
startup voltage, VSTART approximately 80% of
nominal. Assuming that the adapter voltage is
48V, Let RADPUP=3kꢀ, RADPDOWN=8.06kꢀ and
DADP3=30V as Equation (1). Re-check the
adapter turn-on and turn-off voltage:
RADPUP RADPDOWN
VADPON 30 2.3
RADPUP
(9)
38.5V
RADPUP RADPDOWN
(10)
32.2V
Protection TVS
VADPOFF 30 0.6
RADPUP
To limit input transient voltage within the
absolute maximum rating, a TVS across the
rectified voltage (VDD-VSS) must be used. A
SMAJ58A, or equivalent, is recommended for
general indoor applications. Outdoor transient
levels or special applications require additional
protection.
The VDD-AUX voltage differential voltage is
4.88V when adapter input is 48V. If much
higher adapter voltage is applied and divided
voltage on AUX pin is higher than 6.5V,
RADPDOWN and DADP3 must be able to limit the
current from AUX to adapter-GND less than
3mA, or else additional resistor from tap of
resistor divider to AUX pin is needed to limit the
current.
PD Input Capacitor
An input bypass capacitor (from VDD to VSS)
of 0.05μF to 0.12μF is needed for IEEE
802.3af/at standard specification. Typically a
0.1μF, 100V ceramic capacitor is used.
One small package Schottky diode with 100V
voltage rating (such as BAT46W) is usually
suggested for DADP1. The voltage rating of DADP2
must also be 100V or higher while current rating
must be higher than load current. Low voltage
drop Schottky diode (such as SS1H10) is
recommended to reduce conduction power-loss.
Wall Power Adaptor Detection Circuit
When an auxiliary power source such as a wall
power adapter is used to power the device, the
divider resistors RADPUP, RADPDOWN and DADP3
must be chosen as shown in figure 7 to satisfy
the Equation (1) for correct wall power adaptor
detection.
Power Good (PG) Indicator Signal
MP8007 integrates one PG indicator. PG pin is
used to indicate the PD inrush period finishes
and enable the DCDC converter internally. The
PG pin is an active-high output with internal
driven, consequently it can be floated to enable
DCDC converter. Pull PG pin low externally can
disable the DCDC regulator of MP8007.
RADPUP with typical 3kꢀ value is suggested to
balance the power loss and DADP1&DADP2
leakage current discharge.
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
In PG high condition, PG pin is pulled up by
internal 30μA current source while clamped by
one 5.5V zener between PG and RTN. In PG
low condition, internal 30μA current source is
disabled and PG pin is pulled low by about
460k Ω pull-down resistor between PG and
RTN(GND). Generally, float PG for automatic
startup after power is connected. PG pin can be
pulled low externally but the signal sink current
capability must be higher than the internal
current source. The zener on PG pin is used to
clamp internal 30μA current, do not connect
external signal with higher than 5.5V voltage to
PG pin.
VCC Power Supply Setting
The VCC voltage is charged through the internal
LDO by VDD. Normally, VCC is regulated at
5.4V, typically. A capacitor no less than 1µF is
recommended for decoupling between VCC and
GND.
In flyback mode, VCC can be powered from the
transformer auxiliary winding to save the high-
voltage LDO power loss.
T2P Indicator Connection
The T2P pin is an active-low, open-drain output
which indicates the presence of a Type-2 PSE
or AUX is enabled. An opto-coupler is usually
used as the interface from the T2P pin to
circuitry on output of the converter as figure 8
shown. A high-gain opto-coupler and a high-
impedance (for example, CMOS) receiver are
recommended.
Figure 9: Supply VCC from auxiliary winding
The auxiliary winding supply voltage can be
calculated with Equation (11):
NA
(11)
VCC
(VOUT VD1F ) VDAUXF
NS
Where NA and NS are the turns of the auxiliary
winding and the output winding, VD1F is the
output rectifier diode voltage drop, and VDAUXF is
the DAUX voltage drop in Figure 9.
VCC voltage is clamped at about 6.2V by one
internal Zener diode. The clamp current
capability is about 1.2mA. If the auxiliary
winding power voltage is higher than 6.2V
(especially in a heavy-load condition), a series
resistor (RAUX) is necessary to limit the current
to VCC. For simple application, supply the VCC
power through the internal LDO directly.
Figure 8: T2P Indicator Circuit
Converter Output Voltage Setting
Considering T2P sinking current (2mA typical),
T2P output low voltage 0.1V and diode forward
voltage drop, choose RT2P=23.7kꢀ to match the
typical 48V VDD input. Suppose VOUT of DCDC
converter is 12V, usually choose RT2P-O=20kꢀ
based on the CRT even it may vary with
temperature, LED bias current and aging.
In DCDC converter, there are two feedback
pins for different application modes.
In flyback mode, the converter detects the
auxiliary winding voltage from FB1. R1 and R2
are the resistor dividers for the feedback
sampling
(see
Figure
10).
If lighten a LED from VDD to T2P to indicate the
T2P`s activity, the RT2P’s resistance can be
higher to match the LED`s max current and
reduce the power-loss.
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
full-load condition. The maximum frequency is
affected by the peak current limit, the
inductance, and the input/output voltage.
Generally, design the maximum frequency must
be lower than 200kHz.
GND
R2
Na
FB1
R1
In buck mode, the maximum frequency occurs
when the buck runs in critical continuous
conduction mode. The frequency can be
calculated:
Figure 10: Feedback in isolation application
(V VOUT ) VOUT
When the primary-side power MOSFET turns
off, the auxiliary-winding voltage is sampled.
IN
(14)
F
SW _MAX
ILIM L V
IN
The output voltage is estimated:
Where, ILIM is the IPK set by the current limit
resistor.
VREF1 (R1 R2 ) NS
(12)
VOUT
VD1F
R2
NA
With a lighter load, the frequency is lower than
the maximum frequency above.
Where,
In flyback mode, design the maximum
frequency with the minimum input voltage and
the maximum load condition. Calculate the
frequency with Equation:
NS is the transformer secondary-side winding
turns.
NA is the transformer auxiliary winding turns.
VD1F is the rectifier diode forward drop.
VREF1 is the reference voltage of FB1 (1.99V,
typically).
1
(15)
F
SW
TON TCON TDELAY
When the primary-side power MOSFET turns
on, the auxiliary winding forces a negative
voltage to FB1. The FB1 voltage is clamped to
less than -0.7V internally, but the clamp current
should be limited to less than -0.5mA by R1.
For example, if the auxiliary winding forces
-11V to R1, to make the current flowing from
FB1 to R1 lower than -0.5mA, R1 resistance
must be higher than 22kꢀ (if ignoring R2
current).
Where:
TON is the MOSFET one pulse turn-on time
determined with Equation:
ILIM LM
(16)
TON
V
IN
LM is the transformer primary-winding
inductance.
TCON is the rectifier diode current conducting
time and can be calculated:
Generally, select R2 with a 10kꢀ to 50kꢀ
resistor to limit noise and provide an
appropriate R1 for the -0.5mA negative current
limit.
NS ILIM LM
NP (VOUT VD1F
(17)
TCON
)
In buck application, the feedback pin is FB2.
The output voltage can be estimated:
Where, NS is the transformer secondary-side
winding turns. NP is the transformer primary-
side winding turns.
R1 R2
(13)
VOUT
VREF2
R2
TDELAY is the resonant delay time from the
rectifier diode current drop to 0A to the
auxiliary-winding voltage drop to 0V. The
resonant time can be tested on the board
(estimate around 0.5μs).
Where, VREF2 is the reference voltage of FB2
-1.88V, typically.
Maximum Switching Frequency
In flyback mode, the DCDC converter samples
the feedback signal within 3μs after the primary-
When DCDC converter works in DCM, the
frequency reaches its maximum value during a
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
side MOSFET turns off. The secondary-side
In buck application, the worst Vout ripple can be
estimated with Equation (22):
diode conduction time in Equation (17) should
be higher than 3μs. This time period, combined
with the duty cycle, determines the maximum
frequency.
0.5ILIM2 L(V VD1F
)
IN
(22)
VOUTP _P
C2(V VOUT )(VOUT VD1F
)
IN
Leakage Inductance
The transformer’s
decreases system efficiency and affects the
output current and voltage precision. Optimize
the transformer structure to minimize the
leakage inductance. Aim for
inductance less than 3 percent of the primary-
winding inductance.
Converter Input Capacitor Selection
An input capacitor is required to supply the AC
ripple current to the inductor while limiting noise
at the input source. A low ESR capacitor is
required to keep the noise to the IC at a
minimum. Ceramic capacitors are preferred, but
tantalum or low ESR electrolytic capacitors will
suffice. For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency. The ripple will be the worst at light
load. The required input capacitance can be
estimated:
leakage
inductance
a
leakage
RCD Snubber for Flyback
The transformer leakage inductance causes
spikes and excessive ringing on the MOSFET
drain voltage waveform, affecting the output
voltage sampling 0.7µs after the MOSFET turns
off. The RCD snubber circuit limits the SW
voltage spike (see Figure 11).
0.5ILIM TON
(18)
C1
V
INP _P
Where C1 is the DCDC converter input bulk
capacitor value, VINP-P is the expected input
ripple, and TON is the MOSFET turn-on time.
In an isolated application, TON is calculated:
ILIM LM
(19)
TON
V
IN
In a non-isolation application, TON is calculated:
ILIM L
(20)
TON
V VOUT
IN
Where L is the buck`s inductor value.
Figure 11: RCD snubber
Converter Output Capacitor Selection
The power dissipation in the snubber circuit is
estimated with Equation (23):
The output capacitor maintains the DC output
voltage. For best results, use ceramic
capacitors or low ESR capacitors to minimize
the output voltage ripple. For ceramic
capacitors, the capacitance dominates the
impedance at the switching frequency.
1
P
LK ILIM2 F
(23)
SN
S
2
Where, LK is the leakage inductance.
Since R4 consumes the majority of the power,
R4 is estimated with Equation (24):
In flyback application, the worst output ripple
occurs under a light-load condition; the worst
output ripple can be estimated:
2
VSN
(24)
R4
P
SN
Where, VSN is the expected snubber voltage on
C4.
0.5NP ILIM TCON
VOUTP_P
(21)
NS C2
Where,
C2 is the output capacitor value.
OUTP-P is the output ripple.
The snubber capacitor C4 can be designed to
get appropriate voltage ripple on the snubber
using Equation (25):
V
Normally, a 44μF or higher ceramic capacitor is
recommended as the output capacitor. This
allows a small Vo ripple and stable operation.
VSN
(25)
VSN
R4C4F
S
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
dummy load is a tradeoff between efficiency
Generally, a 15 percent ripple is acceptable.
and load regulation. For applications using
Figure 14, a minimum load of around 10mA is
recommended.
Buck Inductor Selection
The inductor is required to transfer the energy
between the input source and the output
capacitors. Unlike normal application where
inductors determine the inductor ripple, the
DCDC converter always works in DCM while
VIN, VOUT, and ILIM are constant. The inductor
only determines the speed of the current rising
and falling, which determines the switching
period. The expected maximum frequency can
determine the inductor value using Equation
(26):
PCB Layout Guide
A good layout of the PoE front-end and high-
frequency switching power supply is critical.
Poor layout may result in reduced performance,
excessive EMI, resistive loss, and system
instability. For best results, refer to Figure 12
and Figure 13 and follow the guidelines in
below:
For PD interface circuit:
(V V OUT )(VOUT VD1F
)
1
IN
(26)
1. All components place must follow power
flow, from RJ-45, Ethernet transformer,
diode bridges, TVS, to 0.1-μF capacitor and
DCDC converter input bulk capacitor.
L
(V VD1F )IPEAK
FSW
IN
FSW is the expected maximum switching
frequency, which should be lower than 200kHz
in general setting.
2. Make all leads as short as possible with
wide power traces.
Converter Output Diode Selection
3. The spacing between VDD (48V) and VSS
must comply with safety standards like
IEC60950.
The output rectifier diode supplies current to the
output capacitor when the internal MOSFET is
off. Use a Schottky diode to reduce loss due to
the diode forward voltage and recovery time.
4. Place the PD interface circuit ground planes
referenced to VSS, while place the
In isolation application, the diode should be
rated for a reverse voltage greater than
Equation (27):
switching
converter
ground
planes
referenced to RTN/GND.
5. The exposed PAD must be connected to
GND, it can not be connected to VSS.
V NS
IN
(27)
VD1 VOUT
VPD1
NP
6. If adaptor power detection is enabled, the
AUX divider resistor should be close to AUX
pin. And diode D5 (between VSS and RTN)
should be placed close to VSS and RTN.
VPD1 can be selected at 40 percent to 100
percent of VOUT + VIN x NS/NP. An RC or RCD
snubber circuit for the output diode D1 is
recommended.
For flyback circuit:
In buck mode, the diode reverse voltage
equates to the input voltage. A 20 percent ~ 40
percent margin is recommended.
1. Keep the input loop as short as possible
between the input capacitor, transformer,
SW, and GND plane for minimal noise and
ringing.
In both applications, the current rating should
be higher than the maximum output current.
2. Keep the output loop between the rectifier
diode, the output capacitor, and the
transformer as short as possible.
Converter Dummy Load
When the system operates without a load in
flyback mode, the output voltage rises above
the normal operation voltage because of the
minimum switching frequency limitation. Use a
dummy load for good load regulation. A large
dummy load decreases efficiency, so the
3. Keep the clamp loop circuit between D2, C4,
and the transformer as small as possible.
4. Place the VCC capacitor close to VCC for
the best decoupling. The current setting
resistor R3 should be placed as close to
ILIM
and
AGND
as
possible.
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
5. Keep the feedback trace far away from
Via
noise sources (such as SW). The trace
connecting FB1 should be short.
C1
C2
Top Layer
Bottom Layer
D1
6. Use a single point connection between
power GND and signal GND. Vias around
D3
U1
C5
GND
and
the
thermal
pad
are
recommended to lower the die temperature.
R6
L1
C3
R3
Refer to Figure 12 for flyback circuit layout,
D4
which is referred to schematic
on page 1.
R8 R7 R5
D5
R2 R1
Figure 13: Recommended buck layout
Design Example
Below is a design example following the
application guidelines for the following
specifications:
Table 2 – Flyback Design Example
Figure 12: Recommended flyback layout
VDD-VSS
RDET
RCLASS
VADAPTER
VOUT
37V–57V (PoE Supply)
For buck circuit:
24.9kꢀ
41.2ꢀ
48V
1. Keep the input loop as short as possible
between the input capacitor, rectifier diode,
SW, and GND plane for minimal noise and
ringing.
12V
IOUT
1A
2. Keep the output loop between the rectifier
diode, the output capacitor, and the inductor
as short as possible.
The typical application circuit in Figure 14
shows the detailed application schematic, and
is the basis for the typical performance
waveforms. Typically, the device is powered by
PSE (VDD-VSS=48V). When an adapter voltage
above than 38.5V presents, the internal
MOSFET between RTN and VSS turns off,
instead the device is powered by the adapter
whatever the PSE voltage is. For more detailed
device applications, please refer to the related
Evaluation Board Datasheets.
3. Place the VCC capacitor close to VCC for
the best decoupling. The current setting
resistor R3 should be placed as close to
ILIM and AGND as possible.
4. Connect the output voltage sense and VDD
power supply from the output capacitor with
parallel traces. The feedback trace should
be far away from noise sources (such as
SW). The trace connected to FB2 should be
short. The trace for VDD power should be
wider.
5. Use a single point connection between
power GND and signal GND. Vias around
GND
and
the
thermal
pad
are
recommended to lower the die temperature
Refer to Figure 13 for buck circuit layout.
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
TYPICAL APPLICATION CIRCUIT
Figure 14: Flyback Application Circuit, VIN=37-57V PoE oring 48V Adaptor Input, VOUT=12V@1A.
Figure 15: Flyback Application Circuit, VIN=37-57V, No adaptor input, VOUT=5V@2.5A.
Figure 16: Buck Application Circuit, VIN=37-57V PoE Input, No adapter input, VOUT=12V@1A
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MP8007 ― IEEE 802.3AF PD WITH 13W FLYBACK / BUCK CONVERTER
PACKAGE INFORMATION
QFN28 (4mmX5mm)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP8007 Rev.1.0
6/27/2016
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