MP5455 [MPS]
Peak Power Assist for Smart/AI-Enabled Speakers and Low-Power Applications;
| 型号： | MP5455 |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Peak Power Assist for Smart/AI-Enabled Speakers and Low-Power Applications |
| 文件： | 总17页 (文件大小：650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP5455
Peak Power Assist for Smart/AI-Enabled
Speakers and Low-Power Applications
The Future of Analog IC Technology
DESCRIPTION
FEATURES
Power Back-Up Management Circuit
Input Current Limiter with Integrated 60mΩ
MOSFET
The MP5455 is intelligently designed as a
power storage system, releasing energy as
needed during peak loading events, providing
an efficient solution for smart speakers. It is
also capable of providing back-up power in the
event of a power failure targeting solid state
drive supplications.
Wide 2.7V to 7V Operating Input Range
Up to 4.5A Input Current Limit
Reverse-Current Protection
Adjustable dV/dt Slew Rate for Bus Voltage
Start-Up
The internal input current limit block with dV/dt
control prevents inrush current during system
start-up. The storage capacitors charge while
sufficient power load is applied. At peak loading,
energy is released to maintain adequate power
levels and prevent fluctuating performance.
MPS’s patented power back-up control circuit
minimizes the storage capacitor requirement.
This control circuit pumps the input voltage to a
higher storage voltage and releases the energy
over a hold-up time to the system in the case of
an input outage. Storage and release voltages
are both programmable for different system
requirements.
Over-Temperature Protection (OTP)
Available in a QFN-20 (3mmx4mm)
Package
APPLICATIONS
Peak Power Smoother for Smart Speakers
Artificial Intelligence (AI)-Enabled Speakers
Power Back-Up
Battery Hold-Up Supplies
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
The MP5455 requires a minimal number of
readily
available,
standard,
external
components and is available in a QFN-20
(3mmx4mm) package.
TYPICAL APPLICATION
Storage Release
VB Load = 2A, CSTRG = 220µFx2
CH1: VB
1V/div.
CH2: VSTRG
10V/div.
CH3: VSW
10V/div.
CH1:IB
2A/div.
5ms/div.
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
1
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP5455GL
QFN-20 (3mmx4mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MP5455GL–Z)
TOP MARKING
MP: MPS prefix
Y: Year code
W: Week code
5455: Digits of the part number
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
VIN
20
VB VBO
18
19
DVDT
1
17
ICH
FBS
FBB
NC
ILIM
2
3
4
5
6
7
16
15
VIN_MON
14 AGND
VS_MON
13
12
NC
EN
CST
ENCH
11 BST
8
10
9
PGND SW STRG
QFN-20 (3mmx4mm)
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
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© 2018 MPS. All Rights Reserved.
2
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
Thermal Resistance (4)
QFN-20 (3mmx4mm)..............48...... 10... °C/W
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN)................................... 8.0V
NOTES:
VSTRG ...............................................-0.3V to 35V
VSW....................................-0.3V to VSTRG + 0.3V
VBST ...................................-0.3V to VSTRG + 6.5V
1) Exceeding these ratings may damage the device.
2) The maximum power dissipation is a function of the maximum
junction temperature TJ (MAX), the junction-to-ambient
thermal resistance θJA, and the ambient temperature TA. The
maximum continuous power dissipation at any ambient
temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA.
Exceeding the maximum allowable power dissipation
produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
circuitry protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
VCST .................................................-0.3V to 40V
All other pins..................................-0.3V to 6.5V
Continuous power dissipation (TA = +25°C) (2)
................................................................... 2.6W
Junction temperature................................150°C
Lead temperature .....................................260°C
Operating temperature............... -40°C to +85°C
4) Measured on JESD51-7, which is 4-layer PCB.
Recommended Operating Conditions (3)
Supply voltage (VIN)..........................2.7V to 7V
Bus voltage (VB).................................2.7V to 6V
Storage voltage (VSTRG)..................... VIN to 30V
Operating junction temp. (TJ)... -40°C to +125°C
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
3
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
ELECTRICAL CHARACTERISTICS
VIN = 5.0V, TA = 25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max
Units
V
Input supply voltage range
Supply current (shutdown)
Supply current (quiescent)
Thermal shutdown (5)
VIN
2.7
7
2
2
IS
IQ
VEN = 0V
μA
VEN/ENCH = 2V, VFBB/FBS = 1V
mA
°C
TSD
150
30
Thermal shutdown
hysteresis (5)
THYS
INUVR
INUVHYS
ENR
°C
V
VIN under-voltage lockout
threshold rising
2.5
0.4
2.7
0.5
1.2
VIN under-voltage lockout
threshold hysteresis
0.3
0.4
V
EN/ENCH UVLO threshold
rising
V
EN/ENCH UVLO threshold
falling
ENF
V
Current limit MOSFET on
resistance
RDSON
60
65
mΩ
RILIM = 1.07kꢀ
RILIM = 1.2kꢀ
RILIM = 1.4kꢀ
4.6
4.1
3.7
Continuous current limit
Off-state leakage current
ILIM
A
-10%
0.5
10%
2
VIN = 6V, VB = 0V or VB = 6V,
VIN = 0V
ILEAK
μA
DVDT pin floating
Cdv/dt = 10nF
0.9
10
1.5
Rise time (dV/dt)
ms
mA
mA
τR
ICH PRE
ICH
Cdv/dt = 100nF
100
130
500
400
200
0.79
Pre-charge current
ICH pin floating
RICH = 100kꢀ
RICH = 200kꢀ
Charge peak current in
boost mode
Feedback voltage
VFBB, VFBS
IDUMP
0.77
0.81
V
A
Buck mode dumping current
limit
5
VB under-voltage lockout
threshold rising (6)
INUVBR
1.8
2.2
0.25
2.5
V
V
VB under-voltage lockout
threshold hysteresis (6)
INUVBHYS
0.15
0.35
NOTES:
5) Guaranteed by characterization, not tested in production.
6) VB UVLO is applied to energy storage and release circuitry.
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
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© 2018 MPS. All Rights Reserved.
4
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
TYPICAL ELECTRICAL CHARACTERISTICS
VIN = 5V, TA = 25°C, unless otherwise noted.
Quiescent Current Vs. Input Voltage
EN = ENCH = high, VFBB = VFBS = 1V
VB Rising Time vs. DVDT Capacitance
2
1.5
1
120
100
80
60
40
20
0
0.5
0
0
20
40
60
80
100
2
3
4
5
6
7
INPUT VOLTAGE (V)
DVDT CAPACITANCE (nF)
VIN to VB Current Limit vs. Limit
Resistor
VIN to VB Current Limit vs. Temperature
RLIM = 1.4kꢀ
5
4
3
2
1
8
7
6
5
4
3
2
1
0
-40 -20
0
20 40 60 80 100 120 140
0
2
4
6
8
10
ILIM RESISTOR (kΩ)
JUNCTION TEMPERATURE (ºC)
Reference Voltage vs. Temperature
0.81
0.8
0.79
0.78
0.77
FBB
FBS
-40 -20
0
20 40 60 80 100 120 140
JUNCTION TEMPERATURE(ºC)
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
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© 2018 MPS. All Rights Reserved.
5
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 3.5V, VSTRG = 23.5V, CSTRG = 100µFx2, VRELEASE = 3.2V, L = 4.7µH, TA = 25°C, unless
otherwise noted.
Storage Voltage vs. Charging Time
RICH = 100kꢀ
Release Time vs. Storage Capacitance
160
140
120
100
80
25
20
15
10
5
IB=1A
IB=2A
IB=3A
60
CSTRG=200uF
CSTRG=1000uF
40
20
0
0
0
200
400
600
800 1000 1200
0
500
1000
1500
2000
2500
CHARGE TIME (ms)
STORAGE CAPACITANCE(μF)
Release Efficiency
L = wurth_744311470
100
VBLoad=1A
VBLoad=2A
95
90
85
80
75
5
10
15
20
25
30
STRG VOLTAGE (V)
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
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© 2018 MPS. All Rights Reserved.
6
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 3.5V, VSTRG = 23.5V, CSTRG = 100µFx2, VRELEASE = 3.2V, L = 4.7µH, TA = 25°C, unless
otherwise noted.
Input Power-On
VB Load = 1A
ENCH Turn-On
VB Load = 1A
CH1: VB
1V/div.
CH1: VB
1V/div.
CH2: VSTRG
10V/div.
CH2: VSTRG
10V/div.
CH3: VSW
10V/div.
CH3: VSW
10V/div.
CH1:IL
1A/div.
CH1:IL
1A/div.
50ms/div.
50ms/div.
Storage Release
VB Load = 1A, CSTRG = 100µFx2
Storage Release
VB Load = 10mA, CSTRG = 100µFx2
CH1: VB
1V/div.
CH1: VB
1V/div.
CH2: VSTRG
10V/div.
CH2: VSTRG
10V/div.
CH3: VSW
10V/div.
CH3: VSW
10V/div.
CH1:IB
1A/div.
CH1:IB
1A/div.
200ms/div.
5ms/div.
Storage Release
VB Load = 2A, CSTRG = 100µFx2
Storage Release
VB Load = 2A, CSTRG = 220µFx2
CH1: VB
1V/div.
CH1: VB
1V/div.
CH2: VSTRG
10V/div.
CH2: VSTRG
10V/div.
CH3: VSW
10V/div.
CH3: VSW
10V/div.
CH1:IB
2A/div.
CH1:IB
2A/div.
2ms/div.
5ms/div.
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
7
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 3.5V, VSTRG = 23.5V, CSTRG = 100µFx2, VRELEASE = 3.2V, L = 4.7µH, TA = 25°C, unless
otherwise noted.
Storage Release
VB Load = 2A, CSTRG = 1000µF
Storage Release
VB Load = 2A, CSTRG = 2200µF
CH1: VB
1V/div.
CH1: VB
1V/div.
CH2: VSTRG
10V/div.
CH2: VSTRG
10V/div.
CH3: VSW
10V/div.
CH3: VSW
10V/div.
CH1:IB
2A/div..
CH1:IB
2A/div.
5ms/div.
10ms/div.
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
8
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
PIN FUNCTIONS
Pin #
Name
Description
Slew rate control pin for VB during start-up. Leave DVDT floating for the default
soft-start time (around 0.9ms from 0V to 5V).
1
DVDT
2
3
4
5
NC
ILIM
VIN MON
VS MON
Factory use only. Leave NC floating.
Input current limit setting. Do not leave ILIM floating.
Factory use only. Leave VIN MON floating or pull VIN MON up to VB.
Factory use only. Leave VS MON floating or pull VS MON up to VB.
On/off control pin for the MP5455. When EN is pulled low, all functions of the
MP5455 are disabled (for both the input current limiter and the charge/release
circuitry). Ensure that the EN voltage is high during release.
On/off control pin for the charge/release circuitry. When ENCH is pulled down, the
release circuitry is disabled. Note that ENCH must be kept high to achieve energy
release.
6
7
EN
ENCH
8
9
PGND
SW
Power ground.
Switching node for the charge/release circuitry. Connect a small inductor between
SW and VBO.
Storage voltage. Connect the appropriate storage capacitors for the energy storage
and release operation.
Bootstrap pin for the charge/release circuitry. The internal bi-directional switcher
requires a bootstrap capacitor (100nF) from BST to SW to supply the high-side switch
driver voltage during release.
High-side switch driving voltage storage. The MP5455 supports energy, even when
the storage voltage is close to the VB-regulated voltage.
No connection.
10
11
12
STRG
BST
CST
13
14
15
16
NC
AGND
FBB
IC signal ground.
Bus voltage feedback sense. FBB sets the bus release voltage.
Storage voltage feedback sense. FBS sets the storage voltage.
Boost mode current limit adjustment. Do not pull ICH to VCC or an external voltage
source.
Internal boost. VBO is the input voltage after passing through the input isolation
MOSFET.
FBS
17
18
19
ICH
VBO
VB
Internal bus voltage. Place a 22μF to 47μF ceramic capacitor as close to VB as
possible.
Input supply voltage. The MP5455 operates from an unregulated 2.7V to 7V input.
Place a ceramic capacitor 0.1µF or larger as close to VIN as possible. A TVS diode at
the input is necessary if the VIN spike is high. Refer to the Selecting the Input
Capacitor and TVS section on page 12 for additional details.
20
VIN
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
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© 2018 MPS. All Rights Reserved.
9
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
It is strongly recommended to enable ENCH
after VB has settled (see Figure 2). Since
OPERATION
The MP5455 is an energy storage and
management unit in a QFN-20 (3mmx4mm)
package. The MP5455 provides a very compact
and efficient energy management solution for
applications requiring power back-up or hold-up
supplies. MPS’s patented lossless energy
storage and release management circuits use a
bidirectional buck/boost converter to achieve
optimal energy transfer and provide the most
cost-effective energy storage solution.
release mode is triggered when FBB is lower
than 0.79V (although there is a 23mV
hysteresis between boost mode and release
mode), VB may be pulled back low and enter
release mode accidently. To prevent this,
enable ENCH after VB settles. In some high-
current charges, boost mode can be
programmed by ICH. Figure 2 shows the
charging build-up process when ENCH is
enabled after VB settles.
The integrated boost converter raises the
energy-storage voltage level. The storage
feedback resistor divider sets the storage
voltage. If the input shuts down suddenly, the
internal buck converter transfers the energy
from the storage capacitor to the bus and holds
the bus voltage when the system consumes
energy from the storage capacitor. The buck
converter can work in 100% duty cycle
operation to deplete the stored energy
completely.
VIN
EN&ENCH
VB DVDT
Charge-Up
FBB=0.813V
VB
STRG Boost Mode
VSTRG
STRG Pre-Charge Mode
Power-On DelayTime
Figure 1: Charging Process
Start-Up
When VIN starts up, the bus voltage (VB) is
charged from 0 to VIN, approximately. The VB
rising slew rate is controlled by the dV/dt
capacitance. This function prevents input inrush
current and provides protection to the entire
system.
VIN
EN
ENCH
VB
VB DVDT
Charge-Up
EHCH is used to enable the storage charge and
release circuitry. If ENCH is already high before
VB finishes the dV/dt process, the storage
charge circuitry works automatically when VIN
is higher than the under-voltage lockout (UVLO)
threshold (typically 2.5V). The storage charge
circuitry operates in two modes: pre-charge
mode (where STRG is charged to VB using a
current source) and boost mode (where STRG
is charged to set the voltage). The pre-charge
mode charges STRG up to VB using a near-
constant current source (around 130mA). When
STRG is close to VB and VB is higher than a
certain threshold (where the corresponding FBB
is higher than 0.813V), boost mode is initiated.
STRG Boost Mode
VSTRG
STRG Pre-Charge Mode
Power-On Delay Time
Figure 2: Charging Process when EN and ENCH
Are Separated
Storage Voltage
After the start-up period, the internal boost
converter regulates the storage voltage
automatically to a set value. The MP5455 uses
burst mode to minimize the converter’s power
loss. When the storage voltage drops below the
set voltage, burst mode initiates and charges
the storage capacitor. During the burst period,
the current limit and the low-side MOSFET (LS-
FET) control the switch. When the LS-FET
turns on, the inductor current increases until it
reaches its current limit. The boost-current limit
can be programmed by an ICH resistor. By
Boost mode charges STRG to the target
voltage. Figure 1 shows the charging build-up
process when ENCH is high before VB starts
up.
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
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© 2018 MPS. All Rights Reserved.
10
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
floating ICH, the boost current limit is set to
Input Current Limit
around 500mA. After reaching the current limit,
the LS-FET turns off for the set minimum off-
time. At the end of this minimum off-time, if the
feedback voltage remains below the 0.79V
internal reference, the LS-FET turns on again.
Otherwise, the MP5455 waits until the voltage
drops below the threshold before turning on the
LS-FET.
The input current limiter controls the input
inrush current of the internal hot-swap MOSFET
carefully to prevent an inrush current from the
input to the bus. A capacitor connected to
DVDT sets the soft-start time. Despite the soft-
start process, ILIM can limit the steady-state
current.
Connect a resistor between ILIM and GND to
set the current limit.
Release
The MP5455 monitors the input and bus
voltages continuously. Once the bus voltage
drops below the selected release voltage (such
as when losing input power), the internal boost
converter stops charging and works in buck-
release mode. In buck mode, the MP5455
transfers energy from the high-voltage storage
capacitor to the low-voltage bus capacitor.
Determine the release voltage by selecting
resistor values for the bus resistor divider.
Reverse-Current Protection
The hot-swapping circuit uses reverse-current
protection to prevent the storage energy from
transferring back to the input when energy is
released from the storage capacitors to bus.
The hot-swap MOSFET turns on when the input
voltage exceeds the VIN UVLO threshold
during start-up or when input voltage is about
0.2V higher than VB. The hot-swap MOSFET
turns off when input voltage falls below the bus
voltage during release.
The released buck applies fixed-frequency
constant-on-time (COT) control and enables
fast transition between the charge and release
modes. The buck converter works at 100% duty
cycle until the storage capacitor voltage
approaches the bus voltage. Then the storage
and bus voltages drop until they reach the
DC/DC converter’s UVLO threshold (see Figure
3).
Start-Up Sequencing
Connect a capacitor across DVDT to program
the soft-start time. During soft start, the energy
storage capacitors charge. Very short dV/dt
times can trigger the current-limit threshold.
Select the DVDT capacitor based on the
storage capacity.
VSTRG
VB
Release VB Regulation
Voltage
Figure 3: Release Times
MP5455 Rev. 1.01
2/2/2018
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11
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
Select a higher R9 and R10 value to account
for the bleed current. For example, if R10 is
14kꢀ, calculate R9 with Equation (2):
APPLICATION INFORMATION
Selecting Input Capacitor and TVS
Capacitors at VIN are recommended to absorb
possible voltage spikes during input power turn-
on, input switch hard-off (during power-off), or
other special conditions. The application
determines the capacitor. For example, if the
input power trace is too long (with higher
parasitic inductance) during the input switch
hard-off period, more energy pumps into the
input. This means more input capacitors are
needed to ensure that the input voltage spike
remains in a safe range. Use a capacitor 0.1µF
or larger based on the spike condition.
14k(VSTORAGE VFBS
)
R9
VFBS
(2)
For a 12V storage voltage, R9 is 200kꢀ.
Table 1 lists the recommended resistors for
different storage voltages.
Table 1: Resistor Pairs for VSTORAGE
V
STORAGE (V)
R9 (kΩ)
127
200
R10 (kΩ)
8
12
20
14
14
14
340
Consider inrush current requirements when
selecting an input capacitor. Typically, more
input capacitors result in a higher input inrush
current during hot-plugging. A smaller input
capacitor is needed for a smaller inrush current.
The MP5455 works normally with a very small
input capacitor. However, this leads to a
possible high voltage spike. An efficient solution
is to add a TVS diode at the input to absorb the
possible input voltage spike. At the same time,
keep the inrush current small during hot-
plugging. A typical TVS diode, like SMA6J5.0A,
is recommended.
Selecting the Release Voltage and VB
Capacitors
Select the release voltage by choosing the
external feedback resistors R1 and R2 (see
Figure 5).
VB
R1
FBB
CB
R2
Setting the Storage Voltage
Figure 5. Release Feedback Circuit
Set the storage voltage by choosing the
external feedback resistors (R9 and R10) (see
Figure 4).
Similarly, the release voltage is calculated with
Equation (3):
R1
STRG
VRELEASE (1
) VFBB
R2
(3)
R9
Where VFBB is 0.79V, typically. Generally, select
R1 to be about 10kꢀ and CB to be 22µF to
47µF. Table 2 lists the recommended resistor
values for different release voltages.
FBS
Cstorage
R10
Table 2: Resistor Pairs for VRELEASE
Figure 4: Storage Feedback Circuit
VRELEASE (V)
R1 (kΩ)
10.5
R2 (kΩ)
2.43
The storage voltage is determined with
Equation (1):
4.2
2.9
10.7
4.02
R9
VSTORAGE (1
) VFBS
R10
(1)
Where VFBS is 0.79V, typically. R9 and R10 are
not critical for normal operation.
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
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© 2018 MPS. All Rights Reserved.
12
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
Selecting the Storage Capacitor
Setting the Input Hot-Swap Current Limit
Connect a resistor from ILIM to GND to set the
current limit value. For example, a 1.2kꢀ
resistor sets the current limit to about 4.1A.
Table 3 lists the recommended resistors for
different current limit values.
The storage capacitor stores energy during
normal operation and releases this energy
to VB when VIN loses input power. Use a
general-purpose electrolytic capacitor or low-
profile POS capacitor for most applications.
One 4.7µF ceramic capacitor is recommended
if the electrolytic capacitor ESR is high.
Table 3: ILIM vs. RLIM
I
LIM (A)
4.6
4.1
RLIM (kΩ)
1.07
1.2
Select a storage capacitor with a voltage rating
that exceeds the targeted storage voltage.
Consider the capacitance reduction with the DC
voltage offset when choosing the capacitors.
Different capacitors have different capacitance
de-rating performances. Choose a capacitor
with enough voltage rating to guarantee enough
capacitance.
3.7
1.4
1.6
3.2
Selecting the Inductor
The inductor is necessary to supply constant
current to the load. Since boost mode and buck
mode share the same inductor and the buck
mode current is generally higher, an inductor
that at least supports the buck mode releasing
current is recommended.
The required capacitance depends on the
length of the dying gasp for a typical application.
Assume the release current is IRELEASE when VB
is regulated at VRELEASE for the DC/DC converter,
the storage is VSTORAGE, and the required dying
gasp time is τDASP. The required storage
capacitance is then calculated with Equation (4):
Select the inductor based on the buck release
mode. If the storage voltage is VS, then the
release voltage is VR, and the buck running is
fixed at 500kHz. The inductance value can be
calculated with Equation (5):
2 VRELEASE IRELEASE DASP
CS
VS2TORAGE VR2ELEASE
VR
VR
VS
(4)
L
(1
)
IL F
SW
(5)
Consider the power loss during release. The
buck converter can run up to 85% efficiency in
most applications. Select storage capacitance
at 1.18xCS to ensure enough releasing time. If
IRELEASE = 1A, τDASP = 20ms, VSTORAGE = 23.5V,
and VRELEASE = 3.2V, then the required storage
capacitance is 280μF.
Where ∆IL is the peak-to-peak inductor ripple
current, which can be set in the range of 30% to
40% of the full releasing current.
The inductor should not saturate under the
maximum inductor peak current.
Setting the Bus Voltage Rise Time
For typical applications using a 5V input supply,
set the storage voltage above 10V to utilize the
high-voltage energy fully and minimize storage
capacitance requirements. Use a 16V POS
capacitor or 25V electrolytic capacitors.
Connect a capacitor to DVDT to set the bus
voltage start-up slew rate and soft-start time.
Leave DVDT floating for the default soft-start
time (around 0.9ms from 0V to 5V). Table 4 lists
the recommended capacitors for different soft-
start times at a 5V input condition.
Selecting the External Diode
An external diode parallel with the high-side
power MOSFET (HS-FET) is optional for
normal charge mode operation. This diode
improves the boost efficiency if the boost peak
current is high. The voltage rating should be
higher than the storage voltage, and the current
rating should be higher than the current
programmed by ICH.
Table 4: Soft Start vs. Capacitor Value
τR (mS)
10
Cdv/dt (nF)
10
100
100
MP5455 Rev. 1.01
2/2/2018
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MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
(7)
PCB Layout Guidelines
Efficient PCB layout is critical for stable operation.
A 4-layer layout is recommended to achieve
better thermal performance and simplify layout.
For best results, refer to Figure 6 and follow the
guidelines below.
1) Use short, wide, and direct traces in the high-
current paths (VIN, VB, VBO, SW, STRG,
and GND).
2) Place the decoupling capacitor across VB
and GND as close as possible.
3) Place the decoupling capacitor across STRG
and GND as close to the pins as possible.
Inner Layer 1
4) Keep the switching node SW short and away
from the feedback network.
5) Place the external feedback resistors next to
FB.
6) Keep the BST voltage path (BST, C5, and
SW) as short as possible.
NOTE:
7) The corresponding schematic can be found on page 1. Note
that the STRG bulk capacitors C7A and C7B are not shown in
the schematic
Inner Layer 2
Top Layer
Bottom Layer
Figure 6: Recommended Layout
MP5455 Rev. 1.01
2/2/2018
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14
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
Design Example
Table 5 shows a design example following the
application guidelines for the specifications below.
Table 5: Design Example
Parameter
Input voltage
Charge voltage
Bus release
voltage
Boost inductor
peak current
Buck max output
current
Symbol Value Units
VIN
VSTRG
3.5
23.5
V
V
VRLS
3.2
0.4
2
V
A
A
ICHARGE
IRELEASE
The detailed application schematic is shown in
Figure 7. The typical performance and circuit
waveforms are shown in the Typical Performance
Characteristics section. For more device
applications, please refer to the related
evaluation board datasheets.
MP5455 Rev. 1.01
2/2/2018
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15
MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
TYPICAL APPLICATION CIRCUIT
Figure 7: Detailed Application Schematic
MP5455 Rev. 1.01
2/2/2018
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MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS
PACKAGE INFORMATION
QFN-20 (3mmx4mm)
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP5455 Rev. 1.01
2/2/2018
www.MonolithicPower.com
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© 2018 MPS. All Rights Reserved.
17
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