MP3212DQ [MPS]

1.3A, 1MHz Step-up Regulator with Integrated Input Disconnect Switch;
MP3212DQ
型号: MP3212DQ
厂家: MONOLITHIC POWER SYSTEMS    MONOLITHIC POWER SYSTEMS
描述:

1.3A, 1MHz Step-up Regulator with Integrated Input Disconnect Switch

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MP3212  
1.3A, 1MHz Step-up Regulator  
with Integrated Input Disconnect Switch  
DESCRIPTION  
FEATURES  
The MP3212 is a high efficiency, fixed frequency,  
current-mode boost converter with input  
disconnect, inrush current limiting, internal soft-  
start and compensation.  
Up to 88% Efficiency  
2.3V to 5.5V Input Voltage  
Up to 28V Output  
1 MHz Fixed Switching Frequency  
Integrated Power MOSFET  
Integrated Input Disconnect Switch  
Zero Current Shutdown Mode  
Internal Soft-Start  
Internal Compensation  
Automatic Pulse Frequency Modulation  
Mode at Light Load  
Inrush Current Limiting  
1.3A Typical Switch Current Limit  
Under voltage lockout  
The 1MHz switching frequency allows for smaller  
external components producing a compact  
solution for a wide range of load currents. The  
input disconnect feature provides complete  
isolation from output to input when the device is in  
either shutdown mode or fault condition. The  
internal compensation minimizes the external  
component count and soft-start limits the  
current during startup.  
The MP3212  
automatically transitions into pulse-frequency  
modulation mode to achieve better efficiency at  
light load. The input voltage range of 2.3V to  
5.5V can generate 28V at up to 100mA.  
Over Voltage Protection  
Thermal Shutdown  
10-Pin QFN (3x3mm) Package  
The MP3212 includes under-voltage lockout,  
current limit, over voltage protection and  
thermal shutdown. In addition to cycle by cycle  
current limit at power switch, the average  
current is also monitored at disconnect switch  
to prevent damage in the event of output  
overload.  
APPLICATIONS  
Low Noise Power Supply  
Wimax RF Amp Power Supply  
GPRS/GSM RF Amp Power Supply  
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green  
status, please visit MPS website under Quality Assurance. “MPS” and “The  
Future of Analog IC Technology” are Registered Trademarks of Monolithic  
Power Systems, Inc.  
The MP3212 is offered in a compact 10-pin  
QFN (3x3mm) package.  
TYPICAL APPLICATION  
MP3212 Rev. 1.0  
7/17/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
1
MP32121.3A, 1MHz, STEP-UPREGULATORWITHINTEGRATEDINPUTDISCONNECTSWITHCH  
ORDERING INFORMATION  
Part Number*  
Package  
Top Marking  
Temperature  
QFN10 (3mm x 3mm)  
MP3212DQ  
7F  
40C to +85C  
* For Tape & Reel, add suffix Z (e.g. MP3212DQZ). For RoHS Compliant Packaging, add suffix LF (e.g.  
MP3212DQLFZ)  
PACKAGE REFERENCE  
ABSOLUTE MAXIMUM RATINGS (1)  
VDD to GND................................. 0.3V to +6V  
VOUT to GND............................. 0.3V to +35V  
VSW to GND .............................. 0.5V to +36V  
All Other Pins................................ 0.3V to +6V  
Continuous Power Dissipation (TA = +25°C) (2)  
………………………………………………....2.5W  
Junction Temperature..............................150C  
Lead Temperature ...................................260C  
Storage Temperature.............. 65C to +150C  
Recommended Operating Conditions (3)  
Supply Voltage VIN..........................2.3V to 5.5V  
Output Voltage VOUT ............................. 28Vmax  
Operating Temperature ............ 40C to +85C  
Thermal Resistance (4)  
θJA θJC  
QFN10 (3×3mm) ....................50 ......12 ...C/W  
Notes:  
1) Exceeding these ratings may damage the device.  
2) The maximum allowable power dissipation is a function of the  
maximum junction temperature TJ (MAX), the junction-to-  
ambient thermal resistance θJA, and the ambient temperature  
TA. The maximum allowable continuous power dissipation at  
any ambient temperature is calculated by PD (MAX) = (TJ  
(MAX)-TA)/θJA. Exceeding the maximum allowable power  
dissipation will cause excessive die temperature, and the  
regulator will go into thermal shutdown. Internal thermal  
shutdown circuitry protects the device from permanent  
damage.  
3) The device is not guaranteed to function outside of its  
operating conditions.  
4) Measured on JESD51-7, 4-layer PCB.  
MP3212 Rev. 1.0  
7/17/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
2
MP32121.3A, 1MHz, STEP-UPREGULATORWITHINTEGRATEDINPUTDISCONNECTSWITHCH  
ELECTRICAL CHARACTERISTICS  
VDD = 3.6V, VGND = VSHDN = 0V, TA = 25C. CIN=10F, COUT=3.3F, L=10H, R1=10k, R2=133k,  
unless otherwise noted  
Parameter  
Symbol  
Condition  
Min Typ Max Units  
Supply Operating Voltage (1)  
VDD  
2.3  
5.5  
V
V
Under Voltage Lockout High  
Threshold  
VUVLO,HI  
VUVLO,LO  
VDD rising  
VDD falling  
2.2 2.3  
Under Voltage Lockout Low  
Threshold  
1.8  
2
V
Shutdown Current  
Supply Current (PFM)  
Supply Current (PWM)  
Switching Frequency  
Minimum On time  
Maximum Duty Cycle  
SW On-Resistance  
SW Leakage  
IQ,SHDN  
IQ(PFM)  
IQ(PWM)  
FSW  
VSHDN = VDD  
Not switching  
Not switching  
1
180  
A  
A  
A  
400  
0.85  
90  
1
1.15 MHz  
tON, MIN  
DMAX  
RDS (ON)  
ISW  
80  
ns  
%
VFB = 0V  
I(SW) = 100mA  
VSHDN = VDD, VSW = 30V  
0.4  
1
5
A  
SW Current Limit  
ILIM  
1.3  
0.2  
A
IOUT = 50mA, t>2.048ms(2)  
SHDN = 0V  
Input Disconnect On-Resistance  
Input Disconnect Leakage Current  
RDS (ON)_VDDOUT  
ISW_VDDOUT  
VDDOUT = 0V  
1
A  
mA  
Soft Inrush Current Source at  
VDDOUT  
VDD VDDOUT = 0.5V, tON  
<2.048ms(2)  
ISS_VDDOUT  
120  
Logic High Voltage  
VHI  
VLO  
2
V
V
Logic Low Voltage  
0.7  
Pull-up Resistor  
RUP  
Enabled, Input at GND  
1
M  
V
FB Voltage  
VFB  
1.2 1.23 1.26  
FB Input Bias Current  
Leakage Current when Disabled  
Thermal Shutdown  
IFB  
VFB = 1.23V  
-0.1  
31  
0.1  
A  
A  
C  
C  
V
ILEAKAGE  
TSHDN_TH  
TSHDN_HYS  
VOV  
Disabled, Input at GND  
1
150  
25  
Thermal Shutdown Hysteresis  
Over-voltage Thershold  
Over-current Thershold  
Load Regulation  
FB=GND  
34  
IOI  
t>2.048ms(2), DC current  
IOUT = 50mA to 100mA  
1.7  
0.1  
A
ΔVOUT / ΔIOUT  
%
VDD = 3.6V to 2.6V, IOUT  
50mA  
=
Line Regulation  
ΔVOUT / ΔVDD  
0.1  
%/V  
Notes:  
1) Minimum supply operating voltage needs to be above 2.5V at -40C.  
2) Timer is around 2ms-4ms.  
3) Guaranteed by design, not tested.  
MP3212 Rev. 1.0  
7/17/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
3
MP32121.3A, 1MHz, STEP-UPREGULATORWITHINTEGRATEDINPUTDISCONNECTSWITHCH  
PIN FUNCTIONS  
QFN10  
Pin #  
Name Description  
1
2
PGND Power Ground. The ground return for COUT and internal switch  
VDDOUT Input voltage after passing through the input isolation FET  
3
VDD  
NC  
FB  
Actual input voltage before the isolation FET  
No Connect  
4
5
Feedback voltage.  
6
NC  
No Connect  
7
AGND Analog ground  
8
SHDN Shutdown. Active high  
VOUT Output Voltage  
9
10  
SW  
Switch node.  
MP3212 Rev. 1.0  
7/17/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
4
MP32121.3A, 1MHz, STEP-UPREGULATORWITHINTEGRATEDINPUTDISCONNECTSWITHCH  
TYPICAL PERFORMANCE CURVES  
VIN = 3.3V, VOUT = 18V, TA = +25ºC, unless otherwise noted.  
MP3212 Rev. 1.0  
7/17/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
5
MP32121.3A, 1MHz, STEP-UPREGULATORWITHINTEGRATEDINPUTDISCONNECTSWITHCH  
TYPICAL PERFORMANCE CURVES (continued)  
VIN = 3.3V, VOUT = 18V, TA = +25ºC, unless otherwise noted.  
MP3212 Rev. 1.0  
7/17/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
6
MP32121.3A, 1MHz, STEP-UPREGULATORWITHINTEGRATEDINPUTDISCONNECTSWITHCH  
BLOCK DIAGRAM  
Figure 1Functional Block Diagram  
MP3212 Rev. 1.0  
7/17/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
7
MP32121.3A, 1MHz, STEP-UPREGULATORWITHINTEGRATEDINPUTDISCONNECTSWITHCH  
OPERATION  
The MP3212 uses a constant frequency, peak  
current mode boost regulation architecture to  
regulate the feedback voltage. The operation of  
the MP3212 can be understood by referring to  
the block diagram of Figure 1.  
The MP3212 has internal soft start control and  
internal loop compensation to save external  
components.  
The MP3212 monitors input under voltage  
conditions, output over voltage conditions, and  
over temperature events for input under voltage  
lockout, output over voltage protection and over  
temperature protection.  
At the beginning of each cycle, the power  
MOSFET-M1 turns on, to prevent sub-harmonic  
oscillations at duty cycles greater than 50%, a  
stabilizing ramp is added to the output of the  
current sense amplifier. When the output voltage  
of current sense amplifier equals to the output  
voltage of error amplifier, the power MOSFET-M1  
turns off.  
Start-Up Sequence  
After SHDN pin is pulled low, or a restart is  
triggered by the fault condition, MP3212 will go  
through a start up sequence described as below.  
At the beginning of start up, the VDDOUT switch  
is configured as the current source to regulate  
the inrush current, and pre-charge the capacitor  
at Vout. There is 2ms timer to make sure the  
capacitor at Vout is charged up close to Vin  
minus a diode drop. However, if Vout is still not  
charged up after timeout, MP3212 will stay in this  
mode.  
The voltage at the output of the error amplifier is  
an amplified version of the difference between  
the 1.23V reference voltage and the feedback  
voltage. The peak inductor current is  
corresponded to the error amplifier output. If the  
feedback voltage starts to drop, the output of  
error amplifier increases, which results in more  
current flowing through the power MOSFET-M1  
and thus increases the power delivered to the  
output. The use of current mode control improves  
transient response.  
After 2ms timeout, if Vout is charged up close to  
Vin minus a diode drop, then the VDDOUT  
switch will be fully turned on and connect the  
inductor to VDD. MP3212 will enter soft start.  
To prevent the battery from discharging, when  
MP3212 is disabled, the inductor is automatically  
disconnected from the input supply.  
The error amplifier voltage is increased slowly  
during soft start to prevent overshoot. When VFB  
approaches the internal band-gap voltage, the  
MP3212 starts normal operation.  
Fault Control  
FAULT DESCRIPTION  
FAULT CONDITION  
V(VDD) < VUVLO,LO  
FAULT REACTION  
Disables I/Os and waits until V(VDD)  
reaches VUVLO,HI on to begin with the  
start-up sequence  
Under-voltage at VDD  
Disables VDDOUT switch and SW switch  
and immediately restarts the start-up  
sequence  
Disables VDDOUT switch and SW switch  
and waits until output voltage V(VOUT)  
drops to VOV- VOV_Hys to restart the start-  
up sequence  
Over-current drawn from VDDOUT  
Over-voltage at VOUT  
I(VDDOUT) > IOI  
V(VOUT) > VOV  
Disables VDDOUT switch and SW switch  
and waits until junction temp drops to  
TSHDN_TH- TSHDN_HYS to restart the start-up  
sequence  
Over Temperature on chip  
Tj > TSHDN_TH  
MP3212 Rev. 1.0  
7/17/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
8
MP32121.3A, 1MHz, STEP-UPREGULATORWITHINTEGRATEDINPUTDISCONNECTSWITHCH  
required to keep the noise at the IC to a  
Maximum Duty Cycle  
minimum. Ceramic capacitors are preferred, but  
tantalum or low-ESR electrolytic capacitors may  
also suffice.  
The maximum duty cycle Dmax will determine  
the maximum output voltage that the MP3212  
can provide. The maximum duty cycle is defined  
by the minimum off time of the switch.  
Use an input capacitor value greater than 4.7μF.  
The capacitor can be electrolytic, tantalum or  
ceramic. However since it absorbs the input  
switching current it requires an adequate ripple  
current rating. Use a capacitor with RMS current  
rating greater than the inductor ripple current  
(see Selecting The Inductor to determine the  
inductor ripple current).  
DMAX = 1 toFF*Fosc  
PFM Mode  
During the light load condition, the MP3212  
automatically enters pulse frequency modulation  
(PFM) mode. In PFM mode, most of the internal  
circuitry is turned off, only keeping alive the  
active circuitry required to regulate the output  
voltage.  
To ensure stable operation, place the input  
capacitor as close to the IC as possible.  
Alternately a smaller high quality ceramic 0.1μF  
capacitor may be placed closer to the IC with the  
larger capacitor placed further away. If using this  
technique, the larger capacitor can be a tantalum  
or electrolytic type. All ceramic capacitors should  
be placed close to the MP3212.  
Isolation From VIN (SHDN=High)  
To prevent the battery from discharging the  
MP3212 is automatically disconnected from the  
battery when put in shutdown mode. The  
MP3212 has an internal, low resistance isolation  
FET that opens when the SHDN pin is pulled  
high.  
Selecting the Output Capacitor  
Average Current Monitor at the Disconnect  
Switch  
If the average current is above the over current  
set value VOI, the isolation switch is open, the  
boost switch is opened, MP3212 then  
immediately goes into start-up mode.  
The output capacitor is required to maintain the  
DC output voltage. Low ESR capacitors are  
preferred to keep the output voltage ripple to a  
minimum. The characteristic of the output  
capacitor also affects the stability of the  
regulation control system. Ceramic, tantalum, or  
low  
ESR  
electrolytic  
capacitors  
are  
recommended. In the case of ceramic capacitors,  
the impedance of the capacitor at the switching  
frequency is dominated by the capacitance, and  
so the output voltage ripple is mostly independent  
of the ESR. The output voltage ripple is  
estimated to be:  
APPLICATION INFORMATION  
Components referenced below apply to  
Typical Application Circuit on page 1.  
Setting the Output Voltage  
Set the output voltage by selecting the resistive  
voltage divider ratio. Use 10kΩ for the low-side  
resistor R2 of the voltage divider. Determine the  
high-side resistor R1 by the equation:  
V
IN  
1-  
ILOAD  
VOUT  
VRIPPLE  
COUT fSW  
R2(VOUT VFB )  
R1   
VFB  
Where VRIPPLE is the output ripple voltage, VIN and  
VOUT are the DC input and output voltages  
respectively, ILOAD is the load current, fSW is the  
switching frequency, and COUT is the capacitance  
of the output capacitor.  
where VOUT is the output voltage.  
For R2 = 10kΩ and VFB = 1.23V, then  
R1 (kΩ) = 8.13 x (VOUT 1.23) kΩ.  
In the case of tantalum or low-ESR electrolytic  
capacitors, the ESR dominates the impedance at  
the switching frequency, and so the output ripple  
is calculated as:  
Selecting the Input Capacitor  
An input capacitor is required to supply the AC  
ripple current to the inductor, while limiting noise  
at the input source. A low ESR capacitor is  
MP3212 Rev. 1.0  
7/17/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
9
MP3212PRODUCT DESCRIPTION IN A PINCOUNT PACKAGE TYPE  
should be rated for a reverse voltage greater than  
the output voltage used. The average current  
rating must be greater than the maximum load  
current expected, and the peak current rating  
must be greater than the peak inductor current.  
VIN  
(1  
)ILOAD  
VOUT  
ILOAD RESR VOUT  
VRIPPLE  
COUT fSW  
VIN  
Where RESR is the equivalent series resistance of  
the output capacitors.  
Layout Consideration  
High frequency switching regulators require very  
careful layout for stable operation and low noise. All  
components must be placed as close to the IC as  
possible. Keep the path between the SW pin,  
output diode, output capacitor and GND pin  
extremely short for minimal noise and ringing. The  
input capacitor must be placed close to the IN pin  
for best decoupling. All feedback components must  
be kept close to the FB pin to prevent noise  
injection on the FB pin trace. The ground return of  
the input and output capacitors should be tied close  
to the GND pin. See the MP3212 demo board  
layout for reference.  
Choose an output capacitor to satisfy the output  
ripple and load transient requirements of the  
design. A 3.3μF ceramic capacitor is suitable for  
most applications.  
Selecting the Inductor  
The inductor is required to force the higher output  
voltage while being driven by the input voltage. A  
larger value inductor results in less ripple current  
that results in lower peak inductor current,  
reducing stress on the internal N•Channel.switch.  
However, the larger value inductor has a larger  
physical size, higher series resistance, and/or  
lower saturation current.  
A 10µH inductor is recommended for most  
applications. However, a more exact inductance  
value can be calculated. A good rule of thumb is  
to allow the peak-to-peak ripple current to be  
approximately 30-50% of the maximum input  
current. Make sure that the peak inductor current  
is below 75% of the current limit at the operating  
duty cycle to prevent loss of regulation due to the  
current limit. Also make sure that the inductor  
does not saturate under the worst-case load  
transient and startup conditions. Calculate the  
required inductance value by the equation:  
VIN (VOUT - V )  
IN  
L   
VOUT fSW  I  
VOUT ILOAD  
(MAX)  
IIN(MAX)  
I   
V   
IN  
30%50%IN(MAX)  
I
Where ILOAD (MAX) is the maximum load current, ΔI is  
the peak-to-peak inductor ripple current, and η is  
efficiency.  
Selecting the Diode  
The output rectifier diode supplies current to output  
when the internal MOSFET is off. To reduce losses  
due to diode forward voltage and recovery time,  
use a Schottky diode with the MP3212. The diode  
MP3212 Rev. 0.91  
7/17/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
10  
MP32121.3A, 1MHz, STEP-UPREGULATORWITHINTEGRATEDINPUTDISCONNECTSWITHCH  
PACKAGE INFORMATION  
3mm x 3mm QFN10  
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third  
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not  
assume any legal responsibility for any said applications.  
MP3212 Rev. 1.0  
7/17/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
11  

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