MP28248GD [MPS]
High-Efficiency, Fast-Transient, 3A, 4.2V-20V Input Synchronous Step-down Converter in a QFN12 (2x3mm) Package;
| 型号： | MP28248GD |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | High-Efficiency, Fast-Transient, 3A, 4.2V-20V Input Synchronous Step-down Converter in a QFN12 (2x3mm) Package |
| 文件： | 总19页 (文件大小：747K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP28248
High-Efficiency, Fast-Transient, 3A, 4.2V-20V Input
Synchronous Step-down Converter
in a QFN12 (2x3mm) Package
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP28248 is a fully-integrated, high-
efficiency, synchronous, step-down, switch
mode converter. It offers a very compact
solution that can achieve a 3A continuous
output current over a wide input supply range
with excellent load and line regulation. The
MP28248 operates at high efficiency over a
wide output-current load range.
Wide 4.2V to 20V Operating Input Range
3A Output Current
Low RDS(ON) Internal Power MOSFETs
Proprietary Switching-Loss Reduction
Technique
Soft Startup/Shutdown
Programmable Switching Frequency
SCP, OCP, UVP, OVP, and Thermal
Shutdown
Output Adjustable from 0.815V to 13V
Available in a QFN12 (2mmx3mm) Package
Constant-On-Time control mode provides fast
transient response and eases loop stabilization.
Full protective features include short-circuit
protection, over-current protection, over-voltage
protection, under-voltage protection, and
thermal shutdown.
APPLICATIONS
Networking Systems
Distributed Power Systems
The MP28248 requires a minimal number of
readily-available standard external components.
All MPS parts are lead-free and adhere to the RoHS directive. For MPS
green status, please visit MPS website under the Products, Quality
Assurance page.
This device is available in a space-saving
2mmx3mm 12-pin QFN package.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
100
90
80
Vin=12V
70
60
50
40
0.01
0.1
1
10
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
1
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
ORDERING INFORMATION
Part Number
MP28248GD*
Package
Top Marking
ACR
QFN12 (2x3mm)
*For Tape & Reel, add suffix –Z (e.g. MP28248GD–Z).
PACKAGE REFERENCE
TOP VIEW
GND
12
11
10
9
GND
SW
GND
SW
1
2
3
4
5
SW
BST
VCC
EN
IN
8
FREQ
FB
7
6
SS
QFN12 (2x3mm)
Thermal Resistance (4)
QFN12 (2mmx3mm)...............70...... 15... °C/W
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ....................................... 22V
V
V
SW..................................... -0.3V to (VIN + 0.3V)
BS ....................................................... VSW + 6V
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
I
VIN (RMS)........................................................ 3.5A
All Other Pins..................................-0.3V to +6V
(2)
Continuous Power Dissipation (TA = 25°C)
QFN12 (2X3mm)........................................ 1.8W
Junction Temperature ..............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (3)
Supply Voltage VIN ...........................4.2V to 20V
Output Voltage VOUT.....................0.815V to 13V
Maximum Junction Temp. (TJ)... -40°C to 125°C
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
2
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = 25°C, unless otherwise noted.
Parameters
Symbol Condition
Min
Typ
0
Max
Units
μA
μA
mΩ
mΩ
μA
A
Supply current (shutdown)
Supply current (quiescent)
HS switch-on resistance(5)
LS switch-on resistance(5)
Switch leakage
IIN
IQ
VEN = 0V
VEN = 2V, VFB = 0.9V
440
120
50
490
HSRDS-ON
LSRDS-ON
SWLKG
ILIMIT
VEN = 0V, VSW = 0V or 12V
After Soft-Start time-out
R7 = 600kꢀ, VOUT = 1.2V
R7 = 200kꢀ, VOUT = 1.2V
R7 = 120kꢀ, VOUT = 1.2V
0
1
Current limit
4
5
480
160
100
125
5
ns
One-shot on-time
tON
ns
ns
Minimum off time
tOFF
ns
tFB-OCP IL=ILIM=1 FB=0.6V
μs
Fold-back off Time(5)
tFB-SCP
IL=ILIM=1 FB=0.2V
10
μs
OCP hold-off time(5)
Feedback voltage
tOC
IL=ILIM=1 FB=0.6V
50
μs
VFB
TA=25°C
807
815
823
mV
Feedback current
IFB
VFB=815mV
30
1.3
500
1.5
0
50
nA
V
EN rising threshold
EN threshold hysteresis
ENVth-Hi
ENVth-Hys
1.05
1.6
mV
µA
µA
µA
μA
VEN = 2V
EN input current
IEN
VEN = 0V
Soft-start charging current
Soft stop charging current
ISS
ISS
VSS = 0V
VSS=0.815V
14
4.5
VIN under-voltage lockout
threshold rising
INUVVth
3.1
V
VIN under-voltage lockout
threshold hysteresis
INUVHYS
300
mV
Thermal shutdown
TSD
150
25
°C
°C
Thermal shutdown hysteresis
TSD-HYS
Note:
5) Guaranteed by design and characterization
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
3
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
PIN FUNCTIONS
QFN12
(2x3mm)
Pin #
Name Description
System Ground. Reference ground for the regulated output voltage. Requires special
consideration during PCB layout.
1, 11, 12
GND
SW
2, 10,
exposed pad
Switch Output. Connect using wide PCB traces.
Bootstrap. Requires a capacitor connected between SW and BST pins to form a
floating supply across the high-side switch driver.
3
4
5
BST
VCC
EN
Internal Bias Supply. Decouple with a 1µF ceramic capacitor as close to the pin as
possible.
EN = 1 to enable the MP28248. For automatic start-up, connect EN pin to VIN with a
pull-up resistor.
Soft-Start. Connect an external SS capacitor to program the soft-start time for the
switch mode regulator. When the EN pin goes high, an internal current source (14µA)
charges up the SS capacitor and the SS voltage smoothly ramps up from 0 to VFB.
When the EN pin goes low, an internal current source (4.5μA) discharges the SS
capacitor and the SS voltage smoothly drops.
6
SS
Feedback. Sets the output voltage when connected to the tap of an external resistor
divider that is connected between output and GND.
7
8
9
FB
FREQ
IN
Frequency. Set during CCM operation. Connect a resistor R7 to IN to set the switching
frequency. Decouple with a 1nF capacitor.
Supply Voltage. The MP28248 operates from a +4.2V to +20V input rail. Requires C1 to
decouple the input rail. Use wide PCB traces and multiple vias to make the connection.
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
4
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
TYPICAL CHARACTERISTICS
VIN=12V, Vout=1.2V, L=2μH, TA=+25°C,unless otherwise noted.
Enable Supply Current vs.
Input Voltage
Disable Supply Current vs.
Input Voltage
No Load Supply Current vs.
Input Voltage
550
540
530
520
510
500
490
480
470
460
450
700
600
500
400
300
200
100
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
4
8
12
16
20
4
8
12
16
20
0
5
10
15
20
VCC vs. Input Voltage
VCC vs. Io
Fs vs. Input Voltage
480
470
460
450
440
430
420
410
400
5.3
5.2
5.1
5
5.2
5.16
5.12
5.08
5.04
5
IO=0A
IO=3A
IO=1.5A
4.9
4.8
4.7
5
10
15
20
0
0.5
1
1.5
2
2.5
3
4
8
12
16
20
Fs vs.Output Current
BST vs. Vin
Current Limit vs. Temperature
7
6
5
4
3
2
1
0
5.5
5
500
450
400
350
300
250
200
150
100
50
Vin=20V
No Load
Vin=12V
Vin=4.5V
4.5
4
3.5
Full Load
3
2.5
0
0
0.5
1
1.5
2
2.5
3
4
8
12
16
20
-40 -20
0
20 40 60 80 100
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
5
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
TYPICAL CHARACTERISTICS (continued)
VIN=12V, Vout=1.2V, L=2μH, TA=+25°C,unless otherwise noted.
5.5
500
490
480
470
460
450
440
430
420
410
400
5.15
5.25
5.13
5
4.75
5.11
5.09
4.5
4.25
4
5.07
3.75
3.5
-40 -20
5.05
-40 -20
0
20 40 60 80 100
0
20 40 60 80 100
-40 -20
0
20 40 60 80 100
5.5
4.25
4
5.25
5
3.75
3.5
4.75
4.5
4.25
4
3.25
3
2.75
3.75
3.5
2.5
-40 -20
0
20 40 60 80 100
-40 -20
0
20 40 60 80 100
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
6
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 1.2V, L = 2µH, TA = 25°C, unless otherwise noted.
Efficiency vs. Load Current
Power Loss vs. Load Current Efficiency vs. Load Current
Vo=1.2V
Vo=1.2V
1200
1000
100
90
100
Vin=12V
Vin=5V
Vin=12V
Vin=8V
95
90
85
80
80
70
60
50
40
800
600
400
200
0
Vin=20V
Vin=20V
Vin=12V
Vin=20V
75
70
Vin=5V
0
0.01
0.1
1
10
0.5
1
1.5
2
2.5
3
0.01
0.1
1
10
OUTPUT CURRENT(A)
OUTPUT CURRENT(A)
OUTPUT CURRENT(A)
Power Loss vs. Load Current
Load Regulation
Vo=1.2V
Line Regulation
Vo=1.2V
0.6
0.4
0.2
0
1600
1400
1200
1000
800
600
400
200
0
1.5
1
No Load
Half Load
Full Load
Vin=20V
0.5
0
-0.2
-0.4
-0.6
Vin=20V
Vin=12V
Vin=12V
Vin=5V
-0.5
-1
-0.8
-1
Vin=8V
-1.2
-1.5
4
8
12
16
20
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
INPUT VOLTAGE(V)
OUTPUT CURRENT(A)
OUTPUT CURRENT(A)
Case Temperature Rise vs.
Vo vs. Vin
Vo vs. Io
Vo=1.2V
Output Current
Vo=1.2V
Vo=1.2V
25
20
15
10
5
1.195
1.186
1.184
1.182
1.18
1.19
Vin=20V
1.185
No Load
1.178
1.176
1.174
1.172
1.17
1.18
1.175
1.17
Half Load
Vin=20V
Vin=12V
Vin=12V
Full Load
Vin=5V
1.168
1.166
1.164
1.165
1.16
0
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
5
10
15
OUTPUT CURRENT(A)
OUTPUT CURRENT(A)
INPUT VOLTAGE(V)
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
7
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 2µH, TA = 25°C, unless otherwise noted.
Shut Down Through Vin
Start Up Through EN
Start Up Through EN
Io=3A
Io=0A
Io=3A
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
8
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 2µH, TA = 25°C, unless otherwise noted.
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
9
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
BLOCK DIAGRAM
IN
Current Sense
Amplifer
FREQ
+
-
RSEN
5V LDO
OC
VCC
Over-Current
Timer
Refresh
Timer
BST
BSTREG
+
-
ILIM
OFF
Timer
REFERENCE
0.4V
EN
HS-FET
HS Ilimit
Comparator
HS
Driver
PWM
xS
Q
1MEG
1.0V
0.8V
xR
LOGIC
SW
SOFT
START/STOP
SS
FB
VCC
ON
Timer
+
START
Loop
+
-
LS-FET
LS
Driver
Comparator
Current
Modulator
+
-
UV
GND
UV Detect
Comparator
AGND
OV
+
-
OV Detect
Comparator
Figure 1: Functional Block Diagram
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
10
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
to zero, and the switching frequency (fSW) is fairly
constant. Figure 2 shows the timing diagram
during this operation.
OPERATION
PWM Operation
The MP28248 is a fully-integrated, synchronous,
rectified, step-down switch converter. The device
uses constant-on-time (COT) control to provide
fast transient response and easy loop
stabilization. At the beginning of each cycle, the
high-side MOSFET (HS-FET) turns ON
whenever the feedback voltage (VFB) is lower
than the reference voltage (VREF)—a low VFB
indicates insufficient output voltage. The input
voltage and the frequency-set resistor determine
the ON period as follows:
Light-Load Operation
During light-load operation—when the output
current is low—the MP28248 reduces the
switching frequency to maintain high efficiency,
and the inductor current drops near zero. When
the inductor current reaches zero, the LS-FET
driver goes into tri-state (high Z). The current
modulator controls the LS-FET and limits the
inductor current to around -1mA as shown in
Figure 3. Hence, the output capacitors discharge
slowly to GND through LS-FET, R1, and R2. This
operation greatly improves device efficiency
when the output current is low.
9.3R7(k)
tON
40(ns)
(1)
V (V) 0.4
IN
After the ON period elapses, the HS-FET enters
the OFF state. By cycling HS-FET between the
ON and OFF states, the converter regulates the
output voltage. The integrated low-side MOSFET
(LS-FET) turns on when the HS-FET is in its OFF
state to minimize the conduction loss.
Figure 3: Light-Load Operation
Shoot-through occurs when both the HS-FET
and the LS-FET are turned on at the same time,
causing a dead short between input and GND.
Shoot-through dramatically reduces efficiency,
and the MP28248 avoids this by internally
generating a dead-time (DT) between when HS-
FET turns off and LS-FET turns on, and when
LS-FET turns off and HS-FET turns on.
Light-load operation is also called skip mode
because the HS-FET does not turn on as
frequently as during heavy-load conditions. The
frequency at which the HS-FET turns on is a
function of the output current—as the output
current increases, the time period that the current
modulator regulates becomes shorter, and the
HS-FET turns on more frequently. The switching
frequency increases in turn. The output current
reaches the critical level when the current
modulator time is zero, and can be determined
using the following equation:
Heavy-Load Operation
(V -VOUT )VOUT
IN
IOUT
=
(2)
2LfSW V
IN
The device reverts to PWM mode once the
output current exceeds the critical level. After
that, the switching frequency stays fairly constant
over the output current range.
Figure 2: Heavy-Load Operation
During heavy-load operation—when the output
current is high—the MP28248 enters continuous-
conduction mode (CCM) where the HS-FET and
LS-FET repeat the on/off operation described for
PWM operation, the inductor current never goes
MP28248 Rev 1.0
1/5/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
11
MP28248 – 3A, 3.3V-20V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN 2X3MM QFN
noise immunity proportional to the steepness of
VFB’s downward slope. However, VFB ripple does
BST
not directly affect noise immunity.
VS L OPE1
VNOISE
N1
LSG
VF B
C3
VR E F
VCC
C5
HS Driver
L
SW
J itter
Figure 5: Jitter in PWM Mode
COUT
VS L OP E 2
VNOISE
VFB
Figure 4: Floating Driver and Bootstrap Charging
VREF
The floating power MOSFET driver is powered by
an external bootstrap capacitor. This floating
driver has its own UVLO protection with a rising
threshold of 2.2V and a hysteresis of 150mV.
The bootstrap capacitor is charged from VCC
through N1 (Figure 4). N1 turns on when the LS-
FET turns on and turns off when the LS-FET
turns off.
HS Driver
Jitter
Figure 6: Jitter in Skip Mode
Ramp with Large ESR Capacitor
For POSCAP or other types of capacitors with
large ESR as the output capacitors, the ESR
ripple dominates the output ripple, and the slope
on the FB is related to the ESR. Figure 7 shows
an equivalent circuit in PWM mode with the HS-
FET off and without an external ramp circuit. Go
to the application information section for design
recommendations for large ESR capacitors.
Switching Frequency
MP28248 uses constant-on-time control because
there is no dedicated oscillator in the IC. The
input voltage is feed-forwarded to the on-time
one-shot timer through the resistor R7. The duty
ratio is kept as VOUT/VIN, and the switching
frequency is fairly constant over the input voltage
range. The switching frequency can be
determined with the following equation:
106
fSW (kHz)=
(3)
9.3R7 (kΩ) V (V)
IN
+tDELAY (ns)
V (V)-0.4 VOUT (V)
IN
Where tDELAY is the comparator delay, and equals
approximately 40ns.
Figure 7: Simplified Circuit in PWM Mode without
External Ramp Compensation
MP28248 is optimized to operate at high
switching frequency with high efficiency. High
switching frequency makes it possible to use
small-sized LC filter components to save system
PCB space.
To realize a stable output without an external
ramp, select an ESR value using the following
equation:
Jitter and FB Ramp Slope
tSW
tON
2
0.7
Jitter occurs in both PWM and skip modes when
the noise in the VFB ripple propagates a delay to
the HS-FET driver, as shown in Figure 5 and
Figure 6. Jitter can affect system stability, with
(4)
RESR
COUT
Where tSW is the switching period.
MP28248 Rev. 1.0
1/5/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
12
MP28248 – 3A, 3.3V-20V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN 2X3MM QFN
Ramp with small ESR Capacitor
used or not. Figure 9 shows the simplified circuit
of the skip mode when both the HS-FET and LS-
FET are off.
When using ceramic output capacitors, the ESR
is insufficient to stabilize the system and requires
external ramp compensation. The application
section discusses this in further depth.
Figure 9: Simplified Circuit in Skip Mode
The downward slope of the VFB ripple in skip
mode can be determined as follow:
.
Figure 8: Simplified Circuit in PWM Mode with
External Ramp Compensation
VREF
( R R //Ro)C
2
(10)
VSLOPE2
1
OUT
Figure 8 shows a simplified external ramp
compensation circuit (R4 and C4) for PWM mode,
with the HS-FET off. Chose R1, R2, and C4 of
the external ramp to meet the following condition:
Where RO is the equivalent load resistor.
As shown in Figure 6, VSLOPE2 in skip mode is
lower than that is in the PWM mode, so generally
the jitter in skip mode is larger. For a system with
less jitter in light-load condition, select smaller
VFB resistors, though smaller resistors decrease
the light-load efficiency.
9
1
1
R1 R2
R1+R2
<
+R
(5)
2πfSW C4
5
Where:
When using a large-ESR capacitor on the output,
add a 10µF or smaller ceramic capacitor in
parallel to minimize ESL effects.
IR4 IC4 IFB IC4
(6)
(7)
And VRAMP on VFB can then be estimated as:
Soft-Start/Stop
V VOUT
R4 C4
R1 //R2
IN
The MP28248 employs a soft start/stop (SS)
mechanism to ensure smooth output during
power up and power shut-down. When the EN
pin goes high, an internal current source (14μA)
charges up the external SS cap. The SS cap
voltage takes over the REF voltage to the PWM
comparator. The output voltage smoothly ramps
up with the SS voltage. Once the SS voltage
reaches VREF, it continues to ramp up while the
PWM comparator only compares the VREF and
the VFB. At this point, the soft start finishes and it
enters into steady state operation.
VRAMP
tON
R1 //R2 R9
The downward slope of the VFB ripple then
follows:
VRAMP
toff
VOUT
R4 C4
(8)
VSLOPE1
As shown in equation 8, either reduce R4 or C4 if
there is instability in PWM mode. If C4 can not be
reduced further due to limitation from equation 5,
then reduce R4. For stable PWM operation,
design Vslope1 based on equation 9.
When the EN pin goes low, an internal 4.5μA
current source discharges the external SS cap
voltage. Once the SS voltage falls below the
tSW
t
+
ON -RESRCOUT
2
Io(mA)
tSW -ton
0.7π
(9)
-Vslope1
VOUT +
2LCOUT
VREF, the PWM comparator will only compare the
VFB to the SS voltage. The output voltage will
decrease smoothly with the SS voltage until the
voltage level zeros out at high load. The SS cap
value can be determined as follows:
Where IO is the load current.
In skip mode, the downward slope of the VFB
ripple is the same whether the external ramp is
MP28248 Rev. 1.0
1/5/2012
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13
MP28248 – 3A, 3.3V-20V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN 2X3MM QFN
MP28248 has UVLO protection. When VIN
exceeds the UVLO rising threshold voltage, the
chip powers up. It shuts off when VIN is less than
the UVLO falling threshold voltage. This is non-
latch protection.
tSS ms I A
SS
(11)
CSS nF
VREF
V
If the output capacitors are large, avoid setting a
short SS time to avoid hitting the current limit
during SS. Table 1 lists SS times with different
external capacitor value.
Thermal Shutdown
The junction temperature of the IC is monitored
internally. If the junction temperature exceeds the
threshold value (typically 150°C), the converter
shuts off. This is non-latch protection. There is
about 25°C hysteresis. Once the junction
temperature drops to around 125°C, it initiates a
soft start.
Table 1: Soft-Start Time vs. Capacitor Value
tSS(ms)
CSS(nF)
0.58
10
1.92
2.74
33
47
3.96
5.82
68
100
Over-Current Protection and Short-Circuit
Protection
The MP28248 has cycle-by-cycle over-current
limit control that monitors the inductor current
during the HS-FET ON state. Once the inductor
current exceeds the current limit, the HS-FET
turns off. At the same time, the OCP timer—set
at 50µs—starts. OCP will trigger if the current
reaches or exceeds the current limit every cycle
during those 50µs, and the MP28248 enters
hiccup mode to periodically restart the part.
If VFB < 0.5xVREF and the current hits its limit, the
MP28248 triggers the short-circuit protection
(SCP) immediately and the MP28248 enters
hiccup mode to periodically restart the part.
If VFB < 0.5xVREF and the inductor current peak
value exceeds the set current limit threshold,
MP28248 enters hiccup mode to periodically
restart the part. This protection mode is
especially useful when the output shorts to
ground, greatly reducing the average short-circuit
current and any thermal build-up to protect the
regulator. The MP28248 exits the hiccup mode
once the over current condition is removed.
Over-Voltage Protection (OVP)
MP28248 monitors the output voltage through
the tap of a resistor divider connected to FB.
When VFB exceeds 1.25xVREF, MP28248 triggers
OVP. LS-FET is then left on, while the HS-FET is
off. Exiting OVP requires power cycling the
MP28248.
UVLO protection
MP28248 Rev. 1.0
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14
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
equation 7. Select an appropriate R2: typically in
APPLICATION INFORMATION
Setting the Output Voltage—Large ESR
Capacitors
the range of 5kꢀ to 50kꢀ for most applications;
use a relatively large R2 when VO is low—
e.g.,1.05V—and a small R2 when VO is high.
Determine R1 as follows:
For applications that use electrolytic or POS
capacitors as output capacitors, the output
voltage is set by feedback resistors R1 and R2
as shown in Figure 10.
R2
(13)
R1=
V
R2
FB(AVG)
-
(VOUT -VFB(AVG) ) R4+R9
Where VFB(AVG) is the average value on the FB pin.
Its value in skip mode is lower than in PWM
mode, meaning load regulation is strictly
conditional to to the VFB(AVG). Line regulation is
also related to VFB(AVG). For improved load or line
regulation, use a lower VRAMP as per equation 9.
Figure 10: Simplified Circuit of POS Capacitor
To design the feedback circuit, first select a value
for R2: a small R2 will lead to considerable
quiescent current loss while a large R2 makes
the FB pin noise-sensitive. For best results,
choose a value between 5kꢀ and 50kꢀ for R2,
and choose a comparatively larger R2 when VO
is low—e.g. 1.05V—and a smaller R2 when VO is
high. Then determine R1 using the following
equation that takes the output ripple into
consideration:
For PWM mode, use the following equation to
determine VFB(AVG)
:
1
R1 //R2
V
VREF VRAMP
(14)
FB(AVG)
2
R1 //R2 R9
Typically R9 is 0ꢀ, but the appropriate non-zero
value, as per equation 15, improves noise
immunity. Select
a
value that is around
0.2×R1//R2 to minimize its effect on VRAMP
.
1
R9
1
(15)
VOUT
VOUT VREF
2C4 2fSW
2
(12)
R1
R2
VREF
To simplify the calculation of R1 for equation 14,
add a DC-blocking capacitor, CDC, to filter the DC
influence from R4 and R9. Figure 12 shows a
Where VOUT is the output ripple determined by
equation 21.
simplified
circuit
with
external
ramp
compensation and a DC-blocking capacitor.
Approximating R1 is now much easier with CDC
using equation 16 for PWM mode.
Setting the Output Voltage—Small ESR
Capacitors
1
(VOUT VREF VRAMP
)
2
R1
R2
(16)
1
VREF VRAMP
2
Select a CDC value at least 10× the value of C4
for better DC blocking, though do not select a
CDC that exceeds 0.47µF to avoid long start-up
times. Larger CDC values improve FB noise
immunity when combined with smaller R1 and R2
values to limit system start-up effects. Note that
even with CDC, the load and line regulation are
still VRAMP-related.
Figure 11: Simplified Circuit with Ceramic
Capacitor
When using a low-ESR ceramic capacitors on
the output, add an external voltage ramp to the
FB pin. As Figure 11 shows, the resistive divider
and the ramp voltage, VRAMP, influences the
output voltage. As discussed in the previous
section, the VRAMP can be calculated as per
MP28248 Rev 1.0
1/5/2012
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15
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
1
IOUT
ΔV =
(20)
IN
4 fSW CIN
Output Capacitor
The output capacitor maintains the DC output
voltage. Use ceramic or POSCAP capacitors for
best results. The output voltage ripple can be
estimated as:
VOUT
V
1
(1 OUT )(RESR
(21)
)
Figure 12: Simplified Ceramic Capacitor Circuit
with DC Blocking Capacitor
VOUT
fSW L
V
8 fSW COUT
IN
For ceramic capacitors, the impedance at the
switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a capacitor
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance and should be placed as close to
the VIN pin as possible. Capacitors with X5R and
X7R ceramic dielectrics are recommended
because they are fairly stable with temperature
fluctuations.
VOUT
VOUT
(22)
VOUT
(1
)
8 fSW2 LCOUT
V
IN
The output voltage ripple caused by ESR is very
small and requires an external ramp to stabilize
the system. The external ramp can be generated
through resistor R4 and capacitor C4 following
equations 5, 8 and 9.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
For POSCAP capacitors, the ESR dominates the
impedance at the switching frequency. The ramp
voltage generated from the ESR is high enough
to stabilize the system and therefore does not
need an external ramp. Use a minimum ESR
value of around 12mꢀ to ensure stable converter
operation. For simplification, the output ripple can
be approximated as:
VOUT
VOUT
(17)
ICIN IOUT
(1
)
V
V
IN
IN
The worst-case condition occurs at VIN = 2VOUT
where:
,
IOUT
VOUT
V
ICIN
(18)
VOUT
(1 OUT )RESR (23)
2
fSW L
V
IN
For simplification, choose an input capacitor with
an RMS current rating greater than half of the
maximum load current.
The application design must also consider the
maximum output capacitor value. If the output
capacitor value is too high, the output voltage
can’t reach the designated value during the soft-
start time, and then the device will fail to regulate.
The maximum output capacitor value CO_MAX can
be approximately by:
The input capacitance value determines the input
voltage ripple of the converter. If there is an input
voltage ripple requirement in the system, choose
the input capacitor that meets the specification.
The input voltage ripple can be estimated as
follows:
CO _MAX (ILIM_ AVG IOUT ) tss / VOUT (24)
Where ILIM_AVG is the average start-up current
during soft-start period and tss is the soft-start
time.
IOUT
V
VOUT
ΔV =
OUT 1-
(19)
IN
fSW CIN
V
V
IN
IN
Under worst-case conditions where VIN = 2VOUT
:
MP28248 Rev. 1.0
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16
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
Table 2: 1.2V VOUT (L = 2μH)
Inductor
VIN
R7
R4 C4
R1
R2
FSW
VOUT
(V)
The inductor supplies constant current to the
output load while being driven by the switched
input voltage. A larger-value inductor will result in
less ripple current that will result in lower output
ripple voltage. However, a larger-value inductor
will have a larger physical footprint, higher series
resistance, and/or lower saturation current. A
good rule for determining the inductance value is
to design the peak-to-peak ripple current in the
inductor to be in the range of 30% to 40% of the
maximum output current, and that the peak
inductor current is below the maximum switch
current limit. The inductance value can be
calculated by:
(V)
(Ω)
(Ω) (F)
(Ω)
(Ω)
(Hz)
12 1.2 301k 806k 220p 17.4k 40.2k 440k
Table 3: 1.8V VOUT (L = 2μH)
VIN
(V)
R7 R4 C4 R1 R2 FSW
(Ω) (Ω) (F) (Ω) (Ω) (Hz)
VOUT
(V)
12
1.8 402k 649k 220p 30k 24.3k 500k
Table 4: 2.5V VOUT (L = 2μH)
VIN R7 R4 C4
(Ω) (F) (Ω) (Ω) (Hz)
R1
R2 FSW
VOUT
(V) (V) (Ω)
12 2.5 499k 499k 330p 21.5k 10k 544k
Table 5: 3.3V VOUT (L = 4.7μH)
VOUT
(V)
VIN
R7
R4
C4
R1 R2 FSW
VOUT
VOUT
(V)
(Ω)
(Ω)
(F)
(Ω) (Ω) (Hz)
L=
(1-
)
(25)
fSW ΔIL
V
IN
12 3.3 680k 806k 330p 31.6k 10k 520k
Table 6: 5V VOUT (L = 8μH)
Where ΔIL is the peak-to-peak inductor ripple
VIN
(V)
R7
(Ω)
R4
C4 R1
R2 FSW
current.
VOUT
(V)
(Ω) (F) (Ω) (Ω) (Hz)
The inductor should not saturate under the
maximum inductor peak current, where the peak
inductor current can be calculated by:
12
5
1M 1.2M 220p 53.6k 10k 544k
The detailed application schematic is shown in
Figure 13. The typical performance and circuit
waveforms have been shown in the Typical
Performance Characteristics section. For more
possible applications of this device, please refer
to related Evaluation Board Data Sheets.
VOUT
VOUT
(26)
ILP IOUT
(1
)
2fSW L
V
IN
Design Example
Some design examples with typical outputs are
provided in the following tables:
Typical Application Schematic
U1
R3
4.2V-20V
0
9
3
IN
BST
VIN
J1
NS
C1A
25V
R7
MP28248
301k
C3
GND
SW
L1
7443552200
C7
1nF
1.2V@3A
VOUT
2
SW
SW
VOUT
C2A
1210
C2B
1210
8
4
C2C
0603
C2D
NS
FREQ
VCC
10
D1
NS
R4
806K
C4
VCC
GND
220pF
C5
R5
R1
R9
499k
17.4k
0
7
FB
5
6
EN
SS
EN
SS
R8
NS
R2
40.2k
C6
33nF
Figure 13: Detailed Application Schematic
MP28248 Rev. 1.0
1/5/2012
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17
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
Layout Recommendation
1) The high current paths (GND, IN, and SW)
should be placed very close to the device
with short, wide, and direct traces.
The external feedback resistors should be placed
next to the FB pin. Make sure that there is no via
on the FB trace.
2) Put the input capacitors as close to the IN
and GND pins as possible.
5) Keep the BST voltage path (BST, R3, C3,
and SW) as short as possible.
3) Put the decoupling capacitor as close to the
VCC and GND pins as possible.
6) Use a four-layer board to achieve better
thermal performance.
4) Keep the switching node SW short and away
from the feedback network.
MP28248 Rev. 1.0
1/5/2012
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© 2012 MPS. All Rights Reserved.
18
MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)
PACKAGE INFORMATION
QFN12 (2x3mm)
0.45
0.55
0.20
0.30
1.90
2.10
12
PIN 1 ID
MARKING
0.35
0.45
1.10
11
1
0.35
0.45
0.40
0.00
2.90
3.10
PIN 1 ID
INDEX AREA
0.20
0.30
0.50
BSC
5
7
0.35
0.45
0.35
0.45
6
TOP VIEW
BOTTOM VIEW
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
1.90
0.60
0.25
1.80
1.30
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) JEDEC REFERENCE DRAWING IS JEDEC MO-220
5) DRAWING IS NOT TO SCALE.
0.90
0.60
0.20
0.00
0.25
1.45
0.50
0.70
0.70
0.25
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP28248 Rev 1.0
1/5/2012
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© 2012 MPS. All Rights Reserved.
19
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