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HR1200 [MPS]

High-Performance Digital PFC+LLC Combo Controller;
HR1200
型号： HR1200
厂家： MONOLITHIC POWER SYSTEMS    MONOLITHIC POWER SYSTEMS
描述：

High-Performance Digital PFC+LLC Combo Controller

功率因数校正
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HR1200  
High-Performance  
Digital PFC+LLC Combo Controller  
The Future of Analog IC Technology  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
FEATURES  
DESCRIPTION  
•
Meets EuP Lot 6 and COC Version 5 Tier 2  
Specifications  
The HR1200 integrates a digital PFC controller  
and a half-bridge resonant controller into a  
single chip. It uses very low power at no-load or  
ultra-light load, making it compliant with Energy  
Using Product Directive (EuP) Lot 6 and Code  
of Conduct Version 5 Tier 2 specifications.  
•
•
HV Current Source for Start-Up  
Smart X-Cap Discharger when AC is  
Removed  
•
•
•
•
Standard I2C Interface  
1K EEPROM to Store Parameters  
User-Friendly GUI for Digital PFC  
High Efficiency from Light Load to Full Load  
by CCM/DCM Multi-Mode Control  
High PF Due to Patented Input Capacitor  
Current Compensation  
The PFC of the HR1200 employs a patented  
average current control scheme, which can  
operate in CCM and DCM multi-mode  
according to the instantaneous condition of the  
input voltage and output load. The IC exhibits  
excellent efficiency and high PF at light load.  
When operating in CCM, the controller can be  
used in applications up to 500W with minimal  
board size limitations. The performance of the  
PFC can be optimized by programming multiple  
parameters through an I2C GUI. Programming  
is completed either by the factory or by the  
customer using a detailed user guide.  
•
•
•
•
•
•
•
•
Programmable Frequency Jittering  
Programmable Brown-In and Brown-Out  
Programmable Soft Start  
Cycle-by-Cycle Current Limit  
Open-Loop Protection  
LLC Controller  
600V High-Side Gate Driver with Integrated  
Bootstrap Diode and High dV/dt Immunity  
Adaptive Dead-Time Adjustment of HB LLC  
with Minimum and Maximum Limit  
Burst Mode Switching  
Safe Start-Up in Case of Fault  
Two-Level Over-Current Protection (OCP)  
Latch Shutdown Protection  
UTE  
The half-bridge LLC converter achieves high  
efficiency with zero-voltage switching (ZVS).  
The HR1200 implements an adaptive dead-time  
adjustment (ADTA) function, so the LLC  
converter can achieve easily ZVS from heavy  
load to light load. In addition, the HR1200 can  
prevent the LLC converter from operating in  
capacitive mode, making it more robust and  
easier to design.  
•
•
•
•
•
•
•
Over-Temperature Protection (OTP)  
Capacitance Mode Protection  
The HR1200 integrates a high-voltage (HV)  
current source inside the IC for start-up,  
• APPLICATIONS  
•
Notebook Adapters  
All-in-One or Gaming Power Supply  
Desktop PC and ATX Power  
General AC/DC Power Supply up to 600W  
LCD TV and Plasma TV Power Supply  
MPS CONFIDENTIAL  
eliminating the traditional start-up resistor or  
T DISTRIB  
•
•
•
•
external circuit. When the AC input is removed,  
the HV current source functions as an X-cap  
discharger, eliminating the need for a resistor  
for X-cap discharging. These features reduce  
the size of the BOM list and power consumption  
at no load.  
MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For  
MPS green status, please visit the MPS website under quality assurance. “MPS”  
and “The Future of Analog IC Technology” are registered trademarks of  
Monolithic Power Systems, Inc.  
Full protection features include thermal  
shutdown, over-current protection (OCP), over-  
voltage protection (OVP), and brown-in/brown-  
out protection.  
Analog digital adaptive modulation (ADAM) and advanced asynchronous  
mode (AAM) are trademarks of Monolithic Power Systems, Inc.  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
1
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
TYPICAL APPLICATION  
UTE  
MPS CONFIDENTIAL  
T DISTRIB  
Figure 1: Typical Application  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
2
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
ORDERING INFORMATION  
Part Number*  
Package  
Top Marking  
HR1200GM-xxxx**  
HR1200GY-xxxx**  
TSSOP-28  
SOIC-28  
See Below  
See Below  
*For Tape & Reel, add suffix –Z (e.g. HR1200GM–Z)  
** “xxxx” is the configuration code identifier for the register settings stored in the EEPROM. The default number is  
“0000.” Each “x” can have a hexadecimal value between 0 and F. Please consult an MPS FAE to create this  
unique number, even if ordering the “0000” code.  
TOP MARKING  
MPS: MPS prefix  
YY: Year code  
WW: Week code  
HR1200: First six digits of the part number  
LLLLLLLLL: Lot number  
UTE  
PACKAGE REFERENCE  
MPS DEL  
T DIIB  
TSSOP-28  
SOIC-28  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
3
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
Thermal Resistance(4)  
TSSOP-28………………...........….82.......20....°C/W  
θJA  
θJC  
Recommended Operating Conditions(1)  
HVpk ......................................................<= 500V  
Supply voltage (VCC) .........................14V to 30V  
Operating junction temp........... -40°C to +125°C  
SOIC-28………………..……….......60.......30....°C/W  
Absolute Maximum Ratings(2)  
Parameter  
Symbol  
Condition  
Min  
Max  
Units  
General  
Total power dissipation(3)  
Storage temperature  
Junction temperature  
Lead temperature  
Ptotal  
Tstg  
1.56  
+150  
+150  
260  
W
°C  
°C  
°C  
Tamb = 125°C  
-55  
-40  
Tj  
TLEAD  
Voltage  
Voltage on HV  
VHV  
VBST  
VSW  
Continues  
-0.5V  
-1  
+700  
+618  
+618  
+618  
50  
V
V
V
V
Floating supply voltage  
Floating ground voltage  
Voltage on high-side gate driver  
Floating ground max. slew rate  
Voltage on VCC  
-3  
VHSG  
dVSW/dt  
VCC  
V/nS  
UTE  
-0.5  
-0.5  
-0.5  
-0.5  
-6.5  
-0.3  
-0.5  
-0.5  
+38  
V
V
V
V
V
V
V
V
Voltage on VREG  
VDD  
+14  
Voltage on low-side gate driver  
Voltage on PFC gate driver  
Voltage on CS  
VLSG  
VPFCG  
VCS  
+14  
+14  
+6.5  
Self-limited  
6.5  
Voltage on HBVS  
VHBVS  
Other analog pins  
Other digital pins  
2
GNDP/GNDS to  
GNDD  
Analog ground to digital ground  
-0.3  
+0.3  
V
Current  
Current on HBVS  
Source current of FSET  
ESD(4)  
IHBVS  
IFSET  
-65  
+65  
2
mA  
mA  
Human body  
model  
All pins  
2000  
V
V
V
MPS CONFIDENTIAL  
T DISTRIB  
All pins  
All pins  
Machine model  
200  
500  
Charged device  
model  
NOTES:  
1) The device is not guaranteed to function outside of its operating conditions.  
2) Exceeding these ratings may damage the device.  
3) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-to-ambient thermal  
resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is  
calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature,  
causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage.  
4) Measured on JESD51-7, 4-layer PCB.  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
4
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
ELECTRICAL CHARACTERISTICS  
VHV > 65V, VCC = 23V, TA = -40°C~125°C, currents entering the IC are positive, unless otherwise  
noted.  
Parameter  
Symbol  
Condition  
Min  
Typ  
Max  
Units  
High-Voltage Start-Up Current Source (HV)  
Breakdown voltage  
VHVBR  
IHVNOR  
IHVLimit  
IHVoff  
700  
5.1  
0.8  
V
Normal charge current  
VHV = 100V, VCC = 15V  
VHV = 100V, VCC = 0V  
VHV = 400V, VCC = 24V  
7
1.4  
7
8.9  
2.1  
10  
mA  
mA  
µA  
Supply current when fault occurs  
Leakage current when turned off  
IC Power Supply (VCC)  
IC turn-on threshold voltage when  
HV is detected  
VCCON(HV)  
VHV > VHVON  
20  
21.5  
23.1  
V
UV protection threshold  
IC release threshold  
VCCUVP  
VCCRST  
ICC(nor)  
10.6  
8.4  
11.5  
9
12.3  
9.6  
V
V
Operation current, normal  
7
mA  
Start-up current  
ICC-start1  
VCC = 20V  
0.48  
0.5  
mA  
Current at fault  
ICC-Disable  
TIMER = 4V  
mA  
UTE  
Regulated Power Supply (VREG)  
Ireg = 0mA  
11  
12  
12.8  
12.6  
11.3  
8.6  
V
V
V
V
Regulated output voltage  
Vreg  
Ireg = 30mA  
10.8  
10.2  
7.7  
11.8  
10.7  
8.2  
Turn-on threshold  
VregON  
UVP  
VregUVP  
Power Supply for Digital Core (V3.3)  
I3V3 = 0mA  
3V3 = 15mA  
3.0  
3.2  
3.4  
V
V
Voltage regulation range  
V3v3  
I
2.95  
3.15  
3.35  
X-Cap Discharger (HV)  
Discharger time  
TX-d  
0.8  
1.5  
2.1  
ms  
PFC Gate Driver  
Ron(H)  
Ron(L)  
Sourcing 20mA  
Sinking 20mA  
4.5  
2.5  
Ω
Ω
Gate-on resistor  
MPS CONFIDENTIAL  
Voltage fall time  
Voltage rise time  
Tf  
Tr  
CGate = 1nF  
10  
ns  
ns  
T DISTRIB  
CGate = 1nF  
15  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
5
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
ELECTRICAL CHARACTERISTICS (continued)  
VHV > 65V, VCC = 20V, TA = -40°C~125°C, currents entering the IC are positive, unless otherwise  
noted.  
Parameter  
Symbol  
Condition  
TA = 25°C  
At normal  
Min  
Typ  
Max  
Units  
Reference Current (RES)  
Voltage regulation range  
System Clock  
VRt  
1.245  
1.25  
1.255  
V
fosc_nor  
20  
1
MHz  
MHz  
Clock frequency  
fosc_nopwm At fault or burst off  
AC Input Sensing (ACIN)  
Voltage range  
KACIN = 0.0032  
0
0
1.6  
1.6  
V
V
PFC Feedback (FBP)  
Voltage range  
KACIN = 0.0032  
Current Sense (CSP)  
Voltage range  
KACIN = 0.0032  
0
1.6  
V
Bias current in CSP  
ADC for ACIN, FB, and CSP  
ADC voltage reference  
ADC resolution  
Icsp-bias  
RRES = 20kꢀ  
61.7  
62.5  
63.3  
µA  
UTE  
1.593  
1.600  
10  
1.607  
V
bits  
Acquisition time  
350  
ns  
Integral non-linearity (INL) (6)  
Differential non-linearity (DNL) (6)  
Offset error(6)  
±7.0  
±4.5  
±0.5  
±1.5  
LSB  
LSB  
LSB  
LSB  
Gain error(6)  
DAC for OVP and OCL  
Reference voltage  
Resolution  
1.593  
1.600  
7
1.607  
V
bits  
Integral non-linearity (INL) (6)  
Differential non-linearity (DNL) (6)  
Offset error(6)  
±1.5  
±0.3  
±0.2  
±1.5  
LSB  
LSB  
LSB  
LSB  
Gain error(6)  
MPS CONFIDENTIAL  
DAC for Set Comparator  
T DISTRIB  
Reference voltage  
Resolution  
1.593  
1.600  
10  
1.607  
V
bits  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
Preliminary Specifications Subject to Change © 2015 MPS. All Rights Reserved.  
6
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
ELECTRICAL CHARACTERISTICS (continued)  
VHV > 65V, VCC = 20V, TA = -40°C~125°C, currents entering the IC are positive, unless otherwise  
noted.  
Parameter  
Symbol  
Condition  
Min  
Typ  
±4.5  
±2.0  
±0.5  
±1.5  
Max Units  
LSB  
Integral non-linearity (INL) (6)  
Differential non-linearity (DNL) (6)  
Offset error (6)  
LSB  
LSB  
Gain error (6)  
LSB  
Comparator for Set Signal, OVP, and OCL  
Offset voltage  
60  
360  
mV  
I2C Characteristics (SCL/SDA) (5)  
Input high voltage (VIH)  
Input low voltage (VIL)  
Output low voltage (VOL)  
I2C Timing Characteristics (5)  
Operating frequency range  
Bus free time  
2.1  
V
V
V
0.8  
0.4  
100  
400  
kHz  
Between stop and start  
4.7  
4.0  
4.7  
4.0  
300  
250  
25  
μs  
Holding time  
μs  
UTE  
Repeated start condition set-up time  
Stop condition set-up time  
Data hold time  
μs  
μs  
ns  
ns  
ms  
μs  
μs  
μs  
Data set-up time  
Clock low time out  
35  
Clock low period  
4.7  
4.0  
Clock high period  
50  
Clock/data fall time  
300  
Clock/data rise time  
1000  
μs  
High-Side Floating Gate Driver Supply (BST, SW)  
BST leakage current  
ILKBST  
ILKSW  
VBST = 600V  
VSW = 582V  
10  
10  
µA  
µA  
SW leakage current  
Current Sensing of the Half-Bridge (CSHB)  
Frequency shift threshold  
VCS-OCR OCR  
0.72  
0.79  
0.86  
1.55  
V
V
MPS CONFIDENTIAL  
OCP threshold  
VCS-OCP OCP  
1.41  
1.48  
T DISTRIB  
Current polarity comparator ref when  
HSG is on  
VCSPR  
VCSNR  
80  
mV  
mV  
Current polarity comparator ref when  
LSG is on  
-80  
Output Voltage Sense (SO)  
Latch protection on SO  
VSO-Latch  
VSO-SFP  
ISO-PU  
3.3  
3.45  
2.0  
3.6  
V
V
Start-up failure protection on SO  
Pull-up current on SO  
1.91  
2.09  
100  
nA  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2015 MPS. All Rights Reserved.  
7
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
ELECTRICAL CHARACTERISTICS (continued)  
VHV > 65V, VCC = 20V, TA = -40°C~125°C, currents entering the IC are positive, unless otherwise  
noted.  
Parameter  
Symbol  
Condition  
Min  
Typ  
Max  
Units  
Oscillator (FSET, CT)  
TJ = 25°C  
TJ = -40°C~125°C  
48  
47  
50  
50  
52  
%
%
Output duty cycle  
D
53  
Oscillation frequency  
CT peak value  
fosc  
600  
3.94  
0.95  
2.06  
kHz  
V
VCTP  
VCTV  
VREF  
tDMIN  
tDMAX  
tD_float  
tD-CMP  
3.54  
0.79  
1.88  
3.74  
0.87  
1.97  
240  
1
CT valley value  
V
Voltage reference at FSET  
V
ns  
µs  
Dead time  
0.82  
230  
1.24  
350  
HBVS floating  
290  
50  
Timer for CMP  
µs  
Half-Bridge Voltage Sensing (HBVS)  
Voltage clamp  
VHBVS-C  
7.5  
V
UTE  
Minimum voltage for the  
change rate to be detected  
dVmin/dt  
Td  
CHBVS = 5pF, typically  
190  
V/µs  
Turn-on delay  
Slope finish to turn-on delay  
130  
120  
ns  
Soft-Start Function (SS)  
Discharge resistance  
Standby Function (BURST)  
Disable threshold  
Rd  
VCS > VCS-OCR  
ꢀ
Vth  
1.18  
100  
1.23  
40  
1.28  
V
Hysteresis  
Vhys  
mV  
Delayed Shutdown (TIMER)  
VTIMER = 1V, VCS = 0.85V,  
Charge current  
ICHARGE  
140  
25  
180  
µA  
µA  
V
SO = 3V  
Charge current for SFP  
ICHARGE_SFP SO < 2.5V  
Threshold for forced operation  
at maximum frequency  
Vth1  
1.87  
3.25  
1.97  
2.07  
Shutdown threshold  
Vth2  
3.45  
3.65  
0.35  
V
V
MPS CONFIDENTIAL  
Restart threshold  
Low-Side Gate Driver (LSG)  
Peak source current (5)  
Peak sink current (5)  
Sourcing resistor  
Sinking resistor  
Vth3  
0.23  
0.29  
T DISTRIB  
Isourcepk  
Isinkpk  
Rsource  
Rsink  
tf  
0.75  
0.87  
4
A
A
ꢀ
2
ꢀ
Fall time  
20  
20  
ns  
ns  
Rise time  
tr  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
8
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
ELECTRICAL CHARACTERISTICS (continued)  
VHV > 65V, VCC = 20V, TA = -40°C~125°C, currents entering the IC are positive, unless otherwise  
noted.  
Parameter  
Symbol  
Condition  
Min  
Typ  
Max  
Units  
High-Side Gate Driver (HSG, Referenced to SW)  
Peak source current (5)  
Peak sink current (5)  
Sourcing resistor  
Isourcepk  
Isinkpk  
Rsource  
Rsink  
tf  
0.74  
0.87  
4
A
A
ꢀ
Sinking resistor  
2
ꢀ
Fall time  
20  
20  
ns  
ns  
Rise time  
tr  
Thermal Shutdown  
Thermal shutdown threshold  
Thermal recovery threshold  
145  
120  
°C  
°C  
NOTE:  
(5) Guaranteed by design.  
(6) Guaranteed by characterization test.  
UTE  
MPS CONFIDENTIAL  
T DISTRIB  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
9
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
TYPICAL CHARACTERISTICS  
24  
22  
20  
18  
16  
14  
1.4  
1.3  
1.2  
1.1  
2
V
On  
CC  
OVP DAC  
OCL DAC  
Set DAC  
V
UVP  
CC  
12  
10  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
UTE  
64  
2
V
11  
8
REG  
1.8  
63  
62  
61  
1.6  
5
2
1.4  
1.2  
3V3  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
MPS CONFIDENTIAL  
5
4
3.5  
3
T DISTRIB  
1000  
Latch  
4
3
2
1
0
Max DT  
800  
CT Peak  
600  
400  
200  
SFP  
CT Valley  
2.5  
Min DT  
Fixed DT  
2
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2015 MPS. All Rights Reserved.  
10  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
TYPICAL CHARACTERISTICS (continued)  
1.35  
1.3  
4
3
2
1
0
2.5  
2.25  
2
Force to Max FSW  
Restart  
1.25  
Shut Down  
Restart  
Stop  
0
1.2  
1.75  
1.5  
1.15  
-50  
50  
100  
150  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
UTE  
60  
55  
50  
2
OCP  
1.5  
1
OCR  
45  
40  
0.5  
0
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
MPS CONFIDENTIAL  
T DISTRIB  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
11  
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
TYPICAL PERFORMANCE CHARACTERISTICS  
VIN = 85V~265V, VOUT = 12V, IOUT = 20A, TA = 25°C, unless otherwise noted.  
1.01  
1
95  
94  
93  
92  
91  
90  
89  
94  
93  
92  
91  
90  
89  
88  
Test Result  
Test Result  
With compensation  
0.99  
0.98  
0.97  
0.96  
0.95  
0.94  
0.93  
0.92  
0.91  
Without compensation  
0
20  
40  
60  
80 100  
0
20  
40  
60  
80 100  
0
20  
40  
60  
80 100  
UTE  
16  
14  
12  
10  
8
0.35  
0.3  
0.25  
0.2  
0.15  
0.1  
EN61000-3 Class C  
6
4
V
=230VAC  
IN  
V
=120VAC  
IN  
0.05  
2
0
0
0
20  
40  
60  
80 100  
3 7 11 15 19 23 27 31 35 39  
MPS CONFIDENTIAL  
T DISTRIB  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
12  
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
VIN = 85V~265V, VOUT = 12V, IOUT = 20A, TA = 25°C, unless otherwise noted.  
V
IN  
100V/div.  
V
IN  
I
IN  
2A/div.  
I
100V/div.  
PFC  
I
2A/div.  
IN  
2A/div.  
I
R
2A/div.  
UTE  
V
V
LG  
OUT  
I
PFC  
5V/div.  
5V/div.  
2A/div.  
I
R
2A/div.  
V
HG  
I
R
5V/div.  
I
2A/div.  
R
V
BUS  
2A/div.  
V
SW  
100V/div.  
100V/div.  
I
PFC  
5A/div.  
MPS CONFIDENTIAL  
T DISTRIB  
V
LG  
5V/div.  
V
V
OUT  
OUT  
5V/div.  
V
5V/div.  
HG  
5V/div.  
I
I
R
R
I
2A/div.  
BUS  
100V/div.  
2A/div.  
R
V
2A/div.  
V
BUS  
100V/div.  
V
SW  
100V/div.  
I
I
PFC  
5A/div.  
PFC  
5A/div.  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
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© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
VIN = 85V~265V, VOUT = 12V, IOUT = 20A, TA = 25°C, unless otherwise noted.  
V
TIMER  
V
V
LG  
TIMER  
1V/div.  
5V/div.  
V
1V/div.  
SO  
V
V
HG  
SO  
2V/div.  
5V/div.  
2V/div.  
V
CS  
V
CS  
1V/div.  
V
HBVS  
2V/div.  
1V/div.  
V
CC  
V
CC  
5V/div.  
5V/div.  
V
SW  
100V/div.  
UTE  
V
V
OUT  
OUT  
AC Coupled  
500mV/div.  
AC Coupled  
500mV/div.  
V
TIMER  
I
I
1V/div.  
R
R
2A/div.  
2A/div.  
V
SO  
V
V
BUS  
100V/div.  
BUS  
100V/div.  
1V/div.  
V
OUT  
I
5V/div.  
I
PFC  
PFC  
2A/div.  
2A/div.  
MPS CONFIDENTIAL  
T DISTRIB  
V
LG  
5V/div.  
V
TIMER  
I
1V/div.  
R
2A/div.  
V
SO  
V
SW  
2V/div.  
100V/div.  
V
HG to GND  
V
CC  
100V/div.  
5V/div.  
I
R
5A/div.  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2015 MPS. All Rights Reserved.  
14  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
PIN FUNCTIONS  
Package  
Pin #  
Name  
Description  
1
SDA  
I2C data bus. Connect a pull-up resistor from SDA to V3.3.  
Input voltage sensing. ACIN is connected internally to ADC. The voltage is used  
for on-time calculation and brown-in/brown-out protection. The ratio of the external  
resistor divider should be 0.0032. It is recommended to connect a 680pF capacitor  
from ACIN to GNDD.  
2
ACIN  
Reference current for producing system clock and bias voltage on CSP. RES  
connects internally to a precise reference voltage of 1.25V. The reference current is  
produced by connecting a 20kꢀ, 0.5% resistor from RES to GNDD.  
3
4
RES  
CSP  
Sensing of PFC inductor current. A 20kꢀ, 0.5% resistor should be connected to  
CS to produce a bias voltage of 1.25V.  
5
6
7
GNDD  
GNDP  
GATEP  
Ground reference for digital core of PFC.  
Ground reference of the PFC gate driver and the LLC low-side gate driver.  
Gate driver output of PFC.  
Provides regulated power supply for PFC and LLC gate drivers or external  
circuits.  
8
VREG  
UTE  
Low-side gate driver of HB. The driver is capable of a minimum 0.5A sourcing  
current and a minimum 1A peak sinking current to drive the lower MOSFET of the  
half-bridge leg. LSG is actively tied to GND during UVLO.  
9
LSG  
Setting of protection and recovery time. Connect a capacitor and a resistor from  
TIMER to GNDS to set both over-current protection delay and recovery delay.  
10  
TIMER  
Latch function. SO can be used for OVP or OTP. If the SO voltage exceeds 3.5V,  
the IC stops switching immediately and remains latched off until VCC drops below  
VCCRST. If the SO start-up voltage is below 2.5V after the TIMER voltage reaches  
2.5V when LLC is enabled, the IC stops operating.  
SO  
11  
IC supply power. When the power is on, VCC is charged up by HVCS internally  
and then powered by the auxiliary power supply.  
12  
13  
14  
15  
VCC  
NC  
Not connected in the SOIC28 and removed in the TSSOP28 to increase  
creepage distance.  
High-voltage current source for the IC start-up. HV also acts as an X-cap  
discharger when the input voltage drops out.  
HV  
Voltage bootstrap. BST is connected externally to a capacitor to build a power  
supply to drive the high-side MOSFET of the HB LLC.  
BST  
MPS CONFIDENTIAL  
16  
HSG  
Gate driver output for the high-side MOSFET of the HB LLC.  
T DISTRIB  
17  
SW  
Reference of the high-side gate driver and bootstrap cap.  
Not connected in the SOIC28 and removed in the TSSOP28 to increase  
creepage distance.  
18  
NC  
Slope sensing to achieve adaptive dead-time adjustment. Connect a 5pF high-  
voltage capacitor between SW and HBVS. LLC works with about 300ns of fixed  
dead time when HBVS is floating.  
HBVS  
19  
20  
GNDS  
Reference ground of LLC and power management circuits.  
Provides over-current regulation, over-current protection, and capacitive-  
mode protection for the half-bridge LLC. The resonant current can be sensed by  
a sense resistor or a capacitive divider. Please note that all functions are disabled  
when CSHB is connected to GND.  
CSHB  
21  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
www.MonolithicPower.com  
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© 2015 MPS. All Rights Reserved.  
15  
Preliminary Specifications Subject to Change  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
PIN FUNCTIONS (continued)  
Package  
Pin #  
Name  
Description  
Burst mode control. If the voltage on BURST is lower than 1.25V, the IC stops  
operation and resumes when the voltage exceeds 1.25V with a hysteresis of about  
40mV. During burst mode, soft start is not activated. This function helps reduce  
power loss at a lighter load.  
BURST  
22  
FSET provides a precise and stable 2V reference voltage. Current flowing out of  
FSET regulates the switching frequency and output voltage. Resistors and  
optocouplers (FB) connected to FSET determine the minimum and maximum, as  
well as the operating switching frequency, of the LLC converter.  
23  
24  
FSET  
CT  
Current-controlled oscillator for producing switching cycles. Current flowing  
out of FSET is mirrored to charge and discharge the capacitor connected from CT to  
GNDS, which determines the switching frequency of the converter.  
Soft start for LLC. Connect an external capacitor from SS to GND, and a resistor to  
FSET, to set both the maximum oscillator frequency and the time constant for the  
frequency shift during start-up. An internal switch discharges the capacitor when the  
chip turns off to guarantee a soft start (all protection features are listed except CMP).  
SS  
25  
26  
Provides a stable 3.3V voltage for digital PFC core or external circuit. A 10µF  
decoupling ceramic capacitor connected from V3.3 to GNDS is recommended.  
V3.3  
Voltage sensing of PFC output. The voltage of FBP is sampled by ADC . It is also  
UTE  
used in on-time calculation, OVP/OLP, and digital PI. The ratio of the external  
resistor divider should be 0.0032. It is recommended to connect a 680pF capacitor  
from FBP to GNDD.  
27  
28  
FBP  
SCL  
I2C serial clock input. SCL must be connected to a pull-up resistor to V3.3.  
MPS CONFIDENTIAL  
T DISTRIB  
DO NO  
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12/11/2015  
Preliminary Specifications Subject to Change  
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© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
FUNCTIONAL BLOCK DIAGRAM  
Ihv_nor = 7mA  
Level  
Shifter  
LDO  
Vreg  
Power Supply Management  
X-Cap Discharger  
Vreg  
LDO  
V3.3  
PWM(3.3V)  
LDO  
OCR  
OCP  
V1.8V  
+0.8V  
+1.5V  
LLC  
Control  
Logic  
PFC  
DAC  
Control  
Logic  
UTE  
100µA  
ADC  
MUX  
Current Direction  
Latch  
+/-80mV  
+3.5V  
LLC_BO/BI (3.3V)  
LLC_Sych (3.3V)  
SFP  
DAC  
+2.5V  
OVP_PFC  
1.9V  
SS_ok  
Ifmin  
OLP_PFC  
SS_Ctrl  
2V  
EEPROM  
I2C  
CCO  
1.24V  
1.25V  
MPS CONFIDENTIAL  
Figure 2: Functional Block Diagram  
T DISTRIB  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
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© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
FUNCTION DESCRIPTION  
The HR1200 is a combo controller that  
integrates digital PFC and HB LLC controllers.  
VCC  
Vreg  
HV  
Ihv_fault=1.4mA  
I
I
hv_nor7mA  
hv_off=7uA  
REGULATOR  
Ich_max=30mA  
Bias  
LDO  
Reset  
X-cap  
discharger  
HV Start up  
Control  
Vreg=11.5V  
Short  
Protection  
1.2V  
Power Supply Management  
3.3V  
UVLO(in)  
CONTROL  
22V/13v  
OFF/ON  
The optimized power source inside the IC  
reduces the no-load power consumption and  
provides robust operation due to sufficient fault  
protection. This power supply also includes a  
high-voltage current source for the IC during  
start-up and the X-cap discharge function when  
the AC input drops out.  
UVLO  
Logic  
8.8v  
10.7v/8.8v  
Reset  
UVLO(in)  
Level  
shift  
UVLO(3.3v)  
Figure 3: Block Diagram of Power Supply  
VHV  
IHV  
System Functions  
The HR1200 integrates functions that improve  
system performance, including an X-cap  
discharger, an IC on/off control, a power good  
signal, and an interface between the PFC stage  
and the LLC stage for synchronous operation.  
t
7mA  
7mA  
1.4mA  
7uA  
7uA  
7mA  
Vcc  
22V  
VCCON(HV)  
13V  
9V  
VCCUVP  
VCCRST  
1.2V  
t
Digital PFC Controller  
Vreg  
Vreg  
11.5v  
10.7V  
8.2V  
UTE  
VregON  
VregUVP  
The HR1200 uses a digital PFC controller to  
integrate digital logic, ADC, DAC, and  
comparators to achieve PFC functionality. The  
digital PFC controller also includes I2C  
communication functions and EEPROM for  
programming design parameters.  
t
VUVLO  
V3.3  
t
t
t0 t1 t2 t3 t4  
t5 t6t7  
t8 t9 t10 t11  
t15  
Figure 4: Operation Waveform of Power Supply  
HB LLC Controller  
High-Voltage Start-Up Input (HV)  
The HB LLC converter can generate a  
regulated and isolated output voltage from the  
400V DC bus. With adaptive dead-time control,  
the HB LLC controller helps the converter  
operate in ZVS in a wider load range, improving  
the efficiency of the converter at light load. The  
IC implements anti-capacitive mode operation  
protection, allowing for a robust product design.  
A 7mA current source charges VCC internally  
when a voltage greater than 30V is applied to HV.  
If VCC is lower than 1.2V, the charge current  
from HV is limited to ICC_Limit (typically 1.4mA),  
preventing excessive power loss caused by a  
VCC short circuit during start-up.  
During normal operation, the voltage on VCC  
rises quickly after start-up, and the HV current  
source switches to the nominal current (IHVNOR),  
PART 1: POWER SUPPLY MANAGEMENT  
MPS CONFIDENTIAL  
typically 7mA. IHVNOR charges the capacitor  
The power supply management function has  
four output pins: HV, VCC, VREG, and V3.3.  
Figure 3 and Figure 4 show a block diagram  
T DISTRIB  
connected to VCC externally, and VCC ramps  
up. The HV current source is switched off when  
VCC exceeds the start-up level (VCCON),  
typically 22V. The HV current source turns on  
again when VCC drops below VCCUVP, typically  
13V. Once the HV current source is turned off,  
the leakage current into HV should be below  
and the operation timing, as  
well as the  
waveform of the power management circuit.  
I
HVoff (typically 7µA).  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
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© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
IC Supply Input (VCC)  
V3.3 for Digital Logic  
VCC provides the operational power for most of  
the internal circuits. The IC can start up from  
the HV start-up current source.  
V3.3 is a stabilized power supply for the internal  
digital logic. It is the output of an LDO with its  
input connected to VCC internally. The output  
of V3.3 is connected to a digital section with an  
internal bonding wire. When VCC is larger than  
If the start-up current comes from HV when  
VCC reaches its start level (VCCON), the internal  
LDO is powered on. VREG begins building up,  
and the IC begins operating if no fault condition  
occurs. VCC is then powered by the auxiliary  
winding of the HBC transformer. Once VCC  
drops below VCCUVP, the following actions occur:  
V
CCRST plus a hysteresis of about 0.5V, the V3.3  
LDO is enabled. It can be disabled only when  
VCC is lower than VCCRST  
.
The capacitor on V3.3 should be in the range of  
4.7µF to 10µF to guarantee that V3.3 is stable.  
There is an LDO with  
downstream of 3.3V that powers the internal  
digital circuits.  
a
1.8V output  
• The IC stops operating, and the PFC  
controller stops switching immediately.  
However, the HB LLC controller continues to  
operate until the low-side MOSFET becomes  
active.  
UVLO (3.3V Signal)  
The UVLO (3.3V signal) is an enable signal for  
both the digital PFC and LLC controllers. When  
VCC is larger than VCCUVP, and Vreg is larger than  
10.7V, UVLO (3.3V signal) goes high.  
• The VREG LDO is disabled.  
The HV current source charges VCC until VCC  
is charged to VCCON, and then VREG LDO is  
turned on again. If the IC enters latch mode, the  
latch status remains until VCC falls below  
UTE  
PART 2: SYSTEM FUNCTIONS  
X-Cap Discharger  
VCCRST  
.
X-capacitors are critical components that are  
placed at the input terminals of the power  
supply to filter out differential EMI noise. If the  
AC line voltage is removed, redundant voltage  
present on the X-cap might cause harm to the  
user. Safety standards require the voltage to be  
discharged to a safe voltage within a certain  
time frame.  
To operate from an external DC power source  
but not from HV, please refer to the HR1201 as  
an alternative.  
Regulated Output (VREG)  
An internal LDO is added to stabilize voltage in  
order to:  
• supply the internal PFC driver.  
Commonly, resistors are placed in parallel with  
the X-cap across the AC line to provide a  
discharge path. However, these discharge  
resistors consume power constantly while the  
• supply the internal low-side driver of HB LLC.  
• supply the internal high-side driver of HB LLC  
via a bootstrap diode.  
AC is connected and are  
a
significant  
contributor to power consumption at no-load or  
• supply a reference voltage.  
MPS CONFIDENTIAL  
standby conditions.  
T DISTRIB  
LDO is enabled only after VCC is higher than  
The HR1200 HV incorporates a smart X-cap  
VCCON (HV). This ensures that any optional  
discharger, so the discharge resistors can be  
external circuitry connected to VDD does not  
eliminated. The operating waveform is shown in  
dissipate any of the start-up current.  
Figure 5.  
The IC begins switching only when Vreg is higher  
than VregON, typically 10.7V. If Vreg falls below  
VregUVP, typically 8.2V, the IC and the PFC  
controller stop switching immediately. The HB  
LLC controller continues until the low-side gate  
is active.  
DO NO  
HR1200 Rev 0.1  
12/11/2015  
www.MonolithicPower.com  
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© 2015 MPS. All Rights Reserved.  
19  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
Figure 5: Operating Waveform of X-Cap  
Figure 6: Operating Waveform of X-Cap  
Discharger when AC Recovers  
Discharger when AC is Removed  
In a normal stage, the HV current source is off.  
The leakage current in HV is small, so power  
consumption is reduced significantly. Once the  
AC voltage is disconnected, after a detection  
time window (Timer 1, typically 96ms), the IC  
controls the internal 6mA current source  
automatically to discharge energy from the X-  
cap to VCC within the Timer 3 period, typically  
32ms. The IC stops for an additional Timer 3  
period to detect AC. If no AC is re-applied  
during this last time period, the IC continues  
discharging during the Timer 2 period (typically  
48ms) until VHV is below 35V. Once VHV drops  
below 35V, VCC is discharged quickly by the  
internal current source, which speeds up  
recovery when the IC is in latch mode.  
UTE  
Over-Temperature Protection (OTP)  
Once the internal thermal sensor senses that  
the IC temperature is over 145°C, the IC stops  
switching immediately, and both the LDO for  
VREG and V3.3 are disabled.  
If the IC  
temperature rises above 100°C, the high-  
voltage current source is disabled. The IC is  
enabled again when VCC drops below 8V. If  
the IC temperature drops below 100°C, the IC  
starts up again.  
IC On/Off Control  
The IC is turned off by pulling FBP down to  
GND with an external MOSFET (see Figure 7).  
If the FB voltage is less than 0.2V, both the  
PFC and LLC disable the PWM switching  
during operation or start-up. The IC is turned on  
If the AC recovers in HV again during the Timer  
MPS CONFIDENTIAL  
3 period, a new start-up procedure begins (see  
Figure 6).  
again when the FBP voltage is higher than  
T DISTRIB  
0.3V. The IC can also be turned off from the  
secondary side through an optocoupler.  
If the X-cap discharge function is enabled, VCC  
should be regulated between VCCON and VCCXCD  
to avoid over-stressing VCC.  
The X-cap discharge function is very flexible,  
and allows users to choose an X-cap value to  
optimize differential mode EMI filtering without  
worrying about the effect of the required bleed  
resistors on the standby power budget and  
system no-load.  
Figure 7: IC On/Off Control  
DO NO  
HR1200 Rev 0.1  
12/11/2015  
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20  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
The IC can be disabled by programming  
Digital PFC Timing  
EEPROM through I2C and MPS’ GUI (see  
Table 1).  
Figure 8 shows the timing of the digital PFC  
block.  
Table 1: IC Disabled through I2C and MPS’ GUI  
Timing of the Power Supply  
Once VCC rises above 9V, 3.3V ramps up and  
a downstream, internal LDO produces a stable  
1.8V power supply for the internal digital logic  
and system clocks. The ‘rst’ signal is set high  
when both 3.3V and 1.8V are stable. When  
UVLO (3.3V signal) is validated, the IC enables  
OSC, ADC, DAC, and the comparators. An  
enable signal is set high after a 20µs UVLO  
(3.3V signal) delay, which indicates the digital  
core is ready to begin operation.  
PFC and LLC Interface  
There are two signals between the PFC and the  
LLC:  
1. D2D brown-in/out signal (see Figure 8)  
If the output voltage is higher than the VD2D-BI  
voltage, the D2D_BI/BO signal is set high,  
enabling the LLC stage. The LLC stage is  
disabled when the output voltage drops  
below VD2D-BO. This function guarantees that  
LLC operates within a proper input voltage  
range, preventing LLC from running in  
capacitive mode.  
UTE  
VD2D-BI and VD2D-BO are programmable  
through I2C. The register address for VD2D-BI  
is one word (16h and 17h), and the register  
address for VD2D-BO is one word (18h and  
19h). The value in the register can be  
calculated using Equation (1):  
1023  
1.6  
⎛
⎞
(1)  
DEC2HEX VD2D_BI × 0.0032×  
⎜
⎟
⎠
⎝
Figure 8: Power Supply Sequence of Digital  
Controller  
2. LLC burst synchronize signal  
When LLC operates in burst mode, PFC  
burst mode can be synchronized with LLC  
burst mode. This is achieved by setting bit 7  
of register 56h high. When bit 7 is low, the  
LLC and PFC burst independently.  
Timing of the Digital Core  
If the enable signal is high, ADC begins  
MPS CONFIDENTIAL  
sampling VACIN and VFB. If the AC input meets  
T DISTRIB  
the brown-in condition and no open-loop fault is  
found on FB, the AC_BI/BO signal is set high,  
and the PFC soft starts until the output reaches  
the target value. While the PFC output voltage  
ramps up, the downstream LLC begins  
operating if the D2D_BI/BO signal is set high.  
PART 3: PFC CONTROLLER  
The state-of-the-art CCM/DCM control scheme  
reduces the RMS current drawn from the AC  
mains by ensuring good input current shaping  
in both CCM and DCM. The control scheme  
reduces the switching frequency when the load  
is reduced, achieving higher efficiency and a  
higher power factor at light load.  
DO NO  
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21  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
Reference Current (RES)  
Figure 11 shows the input voltage level defined  
for different functions. All parameters can be  
programmed through the I2C and GUI.  
RES is connected internally to a precise  
reference voltage of 1.25V (see Figure 9).  
RES should be connected to a 20kꢀ, 0.5%  
resistor externally, making the reference  
current about 62.5µA. This current is mirrored  
and flows out of CSP. If CSP is connected  
externally to a 20kꢀ resistor, a bias voltage of  
1.25V on CSP is produced, which keeps the  
CSP voltage positive (see Figure 15).  
Figure 11: Input Voltage Level for Different  
Functions  
Input Brown-In/Brown-Out  
If VACIN is larger than the brown-in threshold  
Figure 9: Reference Current  
UTE  
(VIN-BI), the IC is ready to begin switching. If  
VACIN is less than VIN-BO for the length of one  
timer period, the IC stops switching. VIN-BI and  
VIN-BO are 10-bit values and are stored in the  
registers 38h to 3Bh. Their values can be  
calculated using Equation (2):  
The reference current flowing out of RES is also  
mirrored to produce a system clock (see Figure  
10).  
1023  
1.6  
⎛
⎞
(2)  
DEC2HEX VVI_BI ×0.0032×  
⎜
⎟
⎠
⎝
The brown-in and brown-out timer is set in  
register 3Ch (see Table 2).  
Table 2: Brown-In/Out Timer in Register 3Ch  
VIN Brown-In/Out Timer, Reg 3Ch  
Bit Item  
Description  
7:4 VIN_BI_TIME  
3:0 VIN_BO_TIME  
Brown-in time  
Brown-out time  
Figure 10: System Clock Generator  
High/Low Line  
The system clock switches from 20MHz to  
1MHz when PWM turns off (i.e., burst off, OVP,  
OCP, etc.). This reduces IC power consumption.  
MPS CONFIDENTIAL  
T DISTRIB  
The high line is determined when the input  
voltage is larger than VIN_highline. The low line is  
determined when the input voltage is less than  
VIN_lowline with a hysteresis of about 10V. The  
high/low line signal sets the soft-start time and  
the resonant time for the valley turn-on. Also, it  
regulates the output voltage at different levels  
to optimize the efficiency of the PFC stage.  
Input Voltage Sensing  
The HV voltage is a rectified, sinusoidal  
waveform. It is attenuated by a resistor divider  
with a fixed ratio of 0.0032 connected to ACIN.  
The ADC samples the voltage on ACIN and  
delivers an input voltage value, a peak voltage  
value, and the frequency of the input voltage.  
This information is used for on-time calculation,  
The high/low line is separated into two ranges:  
VIN_level1 and VIN_level2  
achieves different compensation values for  
improving PF at different input voltage ranges.  
,
respectively. This  
AC brown-in/brown-out protection, capacitor  
DO NO  
current compensation, and X-cap discharging.  
HR1200 Rev 0.8  
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
The thresholds are 8-bit data. The value can be  
Output Fast OVP  
set using Equation (3):  
VOUT-fastOVP is 7-bit data stored in register 37h. It  
is programmable through the I2C GUI and is  
typically set to 430V. VOUT-fastOVP is converted to  
an analog signal by a 7-bit DAC and is  
compared to the FB voltage. If the output  
voltage is larger than VOUT-fastOVP, the PFC stops  
switching. If the output voltage reduces to 400V,  
the PFC begins switching again. Figure 13  
shows the OVP circuit.  
256  
1.6  
⎛
⎞
(3)  
DEC2HEX Vin_highlow ×0.0032×  
⎜
⎟
⎠
⎝
Input OVP  
If the input voltage is larger than VIN-OVP, the IC  
does not start up or is turned off, suspending  
the switching. The input OVP threshold is  
programmable in reg 4Ah.  
Output Voltage Sensing  
Similar to input voltage sensing, the output  
voltage is attenuated by a resistor divider with a  
0.0032 ratio connected to FBP. The voltage on  
FBP is sampled by ADC. The results are used  
for on-time calculation and protections.  
Figure 13: OVP Circuit  
A blanking time is inserted in OVP, making the  
IC immune to switching noise interference (see  
Figure 14). TOVP-t and TOVP-r are both  
programmable in reg 60h.  
Figure 12 shows the input voltage level that is  
defined for different functions. All parameters  
can be programmed through the I2C GUI.  
UTE  
Figure 14: Output Fast OVP  
Fast Loop  
In a dynamic load event, the PFC output  
voltage decreases due to the low bandwidth of  
the voltage control loop, which may cause the  
output voltage to fall out of the regulated range.  
Fast loop is activated when the output voltage  
is lower than VOUT-fast loop. Ki and Kp of the digital  
PI are changed with X times the normal value,  
depending on the GUI setting, so the output  
voltage of the PFC is regulated faster at the  
Figure 12: Output Voltage Level for Different  
Functions  
Output Regulation  
To optimize efficiency, the output voltage can  
be auto-regulated according to the input voltage  
and output power. The output voltage is divided  
into two ranges by VIN_highline and is divided into  
four ranges according to output power level,  
which can be programmed by registers from  
06h to 0Bh. Therefore, the IC can auto-regulate  
eight output voltages accordingly.  
MPS CONFIDENTIAL  
dynamic load event.  
T DISTRIB  
Open Loop or IC Disable Condition  
If the FBP voltage is less then VOUT-OLP (when  
VOUT = 60V, typically), this condition is  
considered an open-loop or IC disabling  
condition. The IC does not start up, and PWM  
switching is disabled during the operation. The  
IC restarts when the FBP voltage is larger than  
VOUT-OLP-Recovery (when VOUT = 90V, typically).  
The open loop is achieved by software, and the  
value is fixed.  
DO NO  
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23  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
Over-Current Protection (OCP)  
Peak Current Sensing  
The PFC inductor current is sensed by RCSP  
and produces a negative voltage. A precise  
current source (Ibias) exits CSP and produces a  
positive bias voltage on Rbias (see Figure 15).  
If the voltage at CSP is less than zero, over-  
current protection is enabled. The PFC stops  
switching immediately, and OCP_trig is set high  
simultaneously. The digital core detects this  
status and disables the PWM. The OCP is  
released by the OCP_release signal.  
The OCP function is disabled by setting bit 4 of  
45h to logic low. The OCP behavior mode is  
programmed by register 45h. It can be  
programmed to hiccup, auto-restart with timer,  
or latch. The default setting is hiccup. The timer  
is set in register 46h.  
A programmable LEB1 (TOCP_Blanking) of about  
200ns is implemented to avoid error sensing  
due to switching noise.  
The OCP function is used to avoid over-  
stressing when the inductor is shorted, or the  
current is too large.  
UTE  
Figure 17 shows the operating waveforms of  
the OCP function.  
Figure 15: Current Sense Circuit in CSP  
The CSP voltage can be calculated with  
Equation (4):  
(4)  
Vcsp(t) = VCSP−Bias(t)− Vcs(t)  
Overall, the CSP voltage is positive (see  
Figure 16). The ADC samples VCSP_Bias on a  
regular basis (VCSP_Bias = 1.25V, typically). VCS  
can be calculated using Equation (4) above.  
Figure 17: OCP Operation Waveform  
MPCONFIDENTIAL  
Over-Current Limit (OCL)  
T DISTRIB  
The inductor current uses a cycle-by-cycle limit  
by setting the appropriate RCS and VI-OCL. VI-OCL  
can be programmed in register 44h and can be  
converted to an analog signal by a 7-bit DAC. A  
programmable LEB1 (TOCl_Blanking) of about  
200ns is inserted to avoid switching noise if the  
digital core is turned on (similar to TOCl_Blanking).  
Figure 16: Voltage Waveform in CSP  
DO NO  
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
Digital PFC Control Scheme  
Mode Decision  
Figure 18 shows the flowchart of the digital PFC  
control scheme.  
The HR1200 has three operation modes:  
continuous conduction mode (CCM) (see  
Figure 20), variable frequency discontinuous  
conduction mode (VF-DCM) (see Figure 21),  
and  
constant  
frequency  
discontinuous  
conduction mode (CF-DCM) (see Figure 22).  
CCM can be calculated with Equation (7):  
Ipk (n) < 2Iref (n)  
(7)  
Figure 20: CCM Control Signals  
UTE  
VF-DCM can be calculated with Equation (8):  
Ts _max  
(8)  
Ipk (n) > 2Iref (n)⋅  
Figure 18: Flowchart of PFC Control Scheme  
Digital Current Reference  
T
s
The digital PI compensates the voltage loop. Its  
output (Vcomp(n)) is sent to the multiplier for  
current reference calculation (see Figure 19).  
Vcomp  
Vin2_ avg  
Kp s + Ki  
Vn  
s
Figure 21: VF-DCM Control Signals  
Figure 19: Current Reference  
CF-DCM can be calculated with Equation (9):  
The digital current reference is calculated  
using Equation (5):  
T
s _max  
2Iref (n) < Ipk (n) < 2Iref (n)⋅  
(9)  
MPS CONFIDENTIAL  
Ts  
T DISTRIB  
Vcomp(n)  
(0.5⋅ Vin _pk (n))2  
(5)  
Iref (n) = V (n)  
Where Ts_max is the maximum switching period,  
programmable in registers 23h to 27h.  
in  
On-Time Calculation  
The on-time can be calculated using Equation  
(6):  
Vo_ref − V (n)  
in  
(6)  
T (n) =  
⋅T  
on  
s
Vo_ref  
Where  
Ts  
is  
the  
switching  
period,  
programmable in registers 1Eh to 22h.  
DO NO  
Figure 22: CF-DCM Control Signal  
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
Soft Start (SS)  
Burst-mode operation is synchronized with the  
LLC_sync signal. If the LLC_sync signal is high,  
the PFC PWM switching is turned off. Once the  
output voltage is lower than VOUT-level4 - 5V, the  
PFC turns on again, even if the LLC_sync  
signal is high and remains on until the output  
voltage ramps up to 400V.  
Once the AC input voltage is larger than VIN-BI  
the Vin_ok signal pulls high, and the HR1200  
initiates a soft start (see Figure 23).  
,
When the PFC recovers from burst mode, it  
operates in critical conduction mode (CRM) for  
the first five switching cycles.  
Capacitive Current Compensation  
The traditional PFC control only regulates the  
inductor current to match the shape of the input  
voltage. However, the input capacitor current is  
not controlled and may deteriorate PF. PF  
worsens when using a larger capacitor or a  
higher input voltage.  
Figure 23: Soft-Start Sequence  
The output voltage rises from the rectified  
output voltage to the target value. When  
softstart_flag is set high, the soft start is  
complete.  
To improve PF, the HR1200 implements a  
patented method of compensating for PF  
The soft-start time can be calculated with  
Equation (10):  
UTE  
deterioration. The compensation data is stored  
in registers 4Bh to 4Eh, corresponding to  
2
bit _num −1  
softstart _time =(vout _t arget −vout _start )⋅ ⋅slewrate  
(10)  
T
different  
input  
voltage  
levels.  
With  
V
adc _ref  
compensation, the PF is improved at all input  
voltage levels.  
Where VOUT-target is the target value of the output  
voltage, VOUT-start is the soft-start value of the  
output voltage, Bit_num = 12 is the ADC data  
bit, and Vadc _ ref is the reference voltage of ADC,  
Frequency Jittering  
The switching frequency is modulated by a  
triangular waveform with the frequency of fm.  
The switching frequency is modulated to the  
maximum switching frequency at the peak of  
the triangle and modulated to the minimum  
switching frequency at its valley.  
typically 1.6V.  
The slew rate is different in the high line and the  
low line. The slew rate in the high line is  
programmable in register 1Ch; the slew rate in  
the low line is programmable in register 1Dh.  
Figure 24 shows the algorithm to modulate the  
switching frequency in order to reduce EMI  
noise.  
Burst-Mode Operation  
At light load, the IC should run in burst mode for  
better efficiency or less no-load power  
MPS CONFIDENTIAL  
consumption. When the output load becomes  
T DISTRIB  
smaller than the programmed threshold (for  
example, a 5% rated load), the PFC enters  
burst mode. The threshold can be programmed  
in register 2Dh for high line and register 2Fh for  
low line. In burst mode, the switching duty is  
calculated based on the 5% rated load, and the  
output is regulated between VOUT-level4 with a 5V  
hysteresis. This keeps the PFC switching when  
the output voltage is below VOUT-level4 - 5V. The  
PFC stops switching when the output voltage  
Figure 24: Frequency Jittering  
ramps up to VOUT-level4  
.
DO NO  
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
The parameters of fsw-max, fsw-min, and fm can be  
the capacitor swings between the peak  
threshold and the valley threshold to determine  
the oscillator frequency.  
programmed by the I2C GUI for best EMI  
performance.  
EEPROM  
The source current of FSET uses the current  
source -1 (IS-1) to charge the CT capacitor. The  
current mirror ratio inside the HR1200 is 1A/A.  
When an oscillating cycle starts, IS-1 charges  
the CT capacitor until the voltage triggers the  
peak threshold voltage. The discharge current  
source (IS-2) with twice the source current of  
FSET is then turned on. Therefore, the CT  
capacitor discharges with the source current of  
FSET. When the voltage on the CT capacitor  
drops to the valley threshold voltage, the IS-2  
turns off and a new oscillating cycle begins.  
The HR1200 applies EEPROM as the NVM. It  
has 1K bytes of data memory and 16 bytes of  
security memory.  
There are only two commands used to operate  
EEPROM:  
1. Read all the data from EEPROM to the  
memory map. This process operates  
automatically before the controller runs or  
receives  
a
RESTORE_USER_ALL  
command (51h) from the I2C.  
2. Write all the data from the memory map to  
EEPROM. This process operates when it  
receives a STORE_USER_ALL command  
(50h) from the I2C.  
I2C Communication and GUI  
UTE  
The HR1200 has a standard I2C interface. It is  
recommended to select an I2C tool with a  
100kHz clock frequency. The I2C can read and  
write the memory map. The I2C can also send a  
command to load the data from the EEPROM to  
the memory map, or reload the data from the  
memory map to EEPROM with the graphic user  
interface (GUI) (see Figure 25). For details,  
please refer to the “User Guideline_HR1200  
GUI and I2C Kit” and “User Guideline_HR1200  
Layout” files available on the MPS website.  
Figure 26: Oscillator Block Diagram  
CCO only starts when both UVLO_3.3V and  
D2D_BI are high. When CT starts charging up,  
LSG switches on first. When CT ramps to VCTP  
,
LSG switches off and CT holds for a period of  
dead time. Once the dead time expires, CT  
ramps down and HSG turns on. When CT  
drops below VCTN, HSG switches off. A full  
switching cycle repeats unless UVLO_3.3V  
switches low or the IC latches off.  
Figure 27 shows the detailed CT waveform  
from start-up to steady state.  
MDENTIAL  
T DISTRIB  
Figure 25: HR1200 I2C GUI  
PART 4: LLC CONTROLLER  
Oscillator (FSET)  
Figure 26 shows the block diagram of the  
oscillator. A modulated current charges and  
Figure 27: CT Waveform from Start-Up to Steady  
discharges the capacitor on CT. The voltage on  
DO NO  
State  
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
The RC network connected to FSET externally  
determines the switching frequency, as well as  
the soft-start switching frequency.  
converter starts or restarts safely, the soft-start  
function starts the switching frequency at a high  
value until the value is controlled by the closed  
loop. The soft start can be achieved easily  
using an external RC series circuit.  
Rfmin, when connected from FSET to GND,  
contributes to the maximum resistance of the  
external RC network when the phototransistor  
is blocked. Therefore, it sets the minimum  
source current from FSET, which determines  
the minimum switching frequency.  
At start-up, the SS voltage is 0V, so the soft-  
start resistor (RSS) is in parallel to Rfmin. Rfmin  
and RSS determine the initial frequency using  
Equation (16):  
1
Under normal operation, the phototransistor  
modulates the current through Rfmax to  
modulate the frequency for output voltage  
regulation. When the phototransistor is  
saturated, the current through Rfmax is at its  
maximum, setting the frequency to its maximum  
as well.  
fstart  
=
(16)  
3⋅CT ⋅(Rfmin||Rss )  
During start-up, CSS charges until its voltage  
reaches the reference (2V), and the current  
through RSS drops to zero. This period lasts for  
a duration equal to 5x(RSSxCSS). During this  
period, the switching frequency changes  
following an exponential curve. Initially, the CSS  
charge decays relatively quickly, but the rate  
slows progressively. After this period ends, the  
output voltage is still not close to the setting  
An RC tank connected in series between FSET  
and GND is used to shift the frequency at start-  
up (please see the “Soft Start” section on page  
26 for more details).  
UTE  
value, so the feedback loop takes over after  
start-up.  
The operation period is expressed with  
Equation (11):  
1
With a soft start, the input current increases  
gradually until the output voltage reaches the  
setting point with little overshoot.  
(11)  
fs =  
CT ⋅3⋅RFSET  
Where, RFSET is the total equivalent resistor on  
FSET.  
Select the soft-start RC network using Equation  
(17) and Equation (18):  
The minimum and maximum frequency can be  
calculated using Equation (12) and Equation  
(13):  
Rfmin  
fstart  
Rss  
=
(17)  
−1  
fmin  
1
fmin  
=
(12)  
(13)  
3⋅10-3  
3⋅CT ⋅Rfmin  
Css  
=
(18)  
Rss  
1
fmax  
=
3⋅CT ⋅(Rfmin || Rfmax  
)
Select an initial frequency (fstart) at least 4 x fmin.  
Select CSS as a trade-off between the desired  
MPS CONFIDENTIAL  
The values of Rfmin and Rfmax can be calculated  
using Equation (14) and (15):  
soft-start operation and the OCP speed.  
T DISTRIB  
Adaptive Dead-Time Adjustment (HBVS)  
1
Rfmin  
=
(14)  
(15)  
Traditional fixed dead-time control results in  
hard switching at a light load or a larger Lm  
design. The adaptive dead-time control function  
adjusts automatically by detecting the dV/dt of  
the HB mid-point, which enables the LLC  
converter to achieve high efficiency from light  
load to full load due to ZVS. With the ADTA  
function, the design of thermal management  
and Lm of the transformer is easier.  
3⋅CT ⋅ fmin  
Rfmin  
Rfmax  
=
fmax  
−1  
fmin  
Soft Start (SS)  
For the resonant half-bridge converter, the  
power delivered is inversely proportional to the  
switching frequency. To ensure that the  
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HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
The HR1200 incorporates an intelligent ADTA  
logic circuit, which is capable of capturing the  
SW dV/dt and automatically inserting a proper  
dead time via an external high-voltage capacitor  
(typically 5pF), coupled between SW and HBVS.  
Figure 28 shows the simplified block diagram of  
ADTA.  
Once HSG switches off, SW begins swinging  
from a high voltage to a low voltage due to the  
resonant tank current (Ir). A negative dV/dt  
draws a current from HBVS via CHBVS. HBVS is  
pulled down depending on the rate of dV/dt and  
Figure 28: Block Diagram of ADTA  
Figure 29 shows the operation waveform of  
ADTA. Figure 30 illustrates the possible dead  
time with ADTA logic. There are three kinds of  
possible dead time: minimum dead time (tDMIN,  
typically 240ns), maximum dead time (tDMAX,  
typically 1µs), and adjusted dead time (between  
CHBVS. If the differential current is higher than  
the internal comparator current, HBVS is pulled  
down to zero and is clamped at zero. When SW  
stops slewing and the differential current  
elapses accordingly, HBVS begins ramping up.  
LSG turns on after a minimum dead time.  
t
DMIN and tDMAX).  
The duration from the time HSG switches off to  
the time LSG turns on is defined as the dead  
time, which relies on the completion of SW’s  
transition. When LSG switches off, SW swings  
from zero to high, creating a positive differential  
current via CHBVS. The dead time adjusts to the  
current information automatically.  
When the transition time of SW is smaller than  
UTE  
tDMIN, the logic prevents the gate from providing  
output until tDMIN is reached. This prevents any  
shoot-through of the high-side and low-side  
MOSFETs. A maximum dead time (tDMAX = 1µs)  
forces the gate to turn on. A dead time that is  
too long leads to duty cycle loss and soft  
switching loss.  
To avoid damaging HBVS, the differential  
current should not be higher than 65mA.  
Otherwise, a smaller value for CHBVS must be  
selected to meet Equation (19):  
dv  
(19)  
id = CHBVS  
< 65mA  
dt  
However, if the value for CHBVS is too small to  
detect dV/dt, the minimum voltage change rate  
(dVmin/dt) must be considered to design an  
appropriate CHBVS  
.
First, calculate the peak magnetizing current (Im)  
MPS CONFIDENTIAL  
with Equation (20):  
T DISTRIB  
V
in  
Im =  
(20)  
8⋅Lm ⋅ fmax  
Then CHBVS is designed using Equation (21):  
C
700μA  
oss  
CHBVS  
>
(21)  
Im  
2
Figure 29: Operation Waveform of ADTA  
Where Coss is the output capacitance when Vds  
equals zero. For a typical design, Lm = 870µH,  
VIN = 450Vdc, and fsmax = 140kHz. CHBVS is  
4.5pF, so 5pF is suitable for most MOSFETs  
DO NO  
(see Figure 28).  
HR1200 Rev 0.1  
12/11/2015  
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29  
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
Figure 30: Dead Time in ADTA  
If HBVS is shorted to GND, LLC stops switching.  
If HBVS is floating, the internal circuit cannot  
detect the differential current in HBVS, and the  
fixed dead time (300ns) takes effect.  
Figure 32: Operating Principle of CMP  
Capacitive-Mode Protection (CMP)  
At t0, the low-side gate driver turns off for the  
first time. CSNEG is high, which means the  
current is at the right polarity, so the converter  
operates in inductive mode. The capacitive-  
When the resonant HB converter output  
overloads or short circuits, CMP causes the  
converter to run into the capacitive region. In  
capacitive mode, the voltage applied to the  
resonant tank is lagging off the current of the  
resonant tank. Under this condition, the body  
diode on one of the MOSFETs switches on, so  
the switching of the other MOSFET should be  
blocked to avoid a device failure.  
UTE  
mode protection circuit is not active.  
At t1, the high-side gate driver turns off for the  
first time. CSPOS is high, so the current is at  
the right polarity, and the converter operates in  
inductive mode. The capacitive-mode protection  
circuit is not active.  
The functional block diagram of CMP is shown  
in Figure 31.  
At t2, the low-side gate driver turns off for a  
second time. CSNEG is zero, which means the  
converter is operating in capacitive mode. The  
body diode of the low-side MOSFET takes over  
the current after the low-side MOSFET is turned  
off. SW does not swing high, so HBVS cannot  
catch dV/dt until the current returns to the  
correct polarity. The dead time remains high,  
and VCO is held. Another MOSFET is not  
switched on. Therefore, the part effectively  
Vbus  
BST  
HSG  
DRIVER  
CBOOT  
HSG  
SW  
2V  
HG  
FSET  
SS  
Lr  
Iset  
Discharge:  
OCR/OCP  
CMP  
VDD  
LSG  
LG  
Restart  
LSG  
DRIVER  
Cr  
GNDP  
SET  
Q
Q
D
-80mV  
CLK  
CLK  
Capacitive  
detected  
CL  
R
CSHB  
SET  
Q
Q
D
80mV  
1.5v  
130uA  
CMP  
CL  
R
TIMER  
2.0v  
Protection  
Timer  
3.5v  
OCP  
Control  
Logic  
0.3v  
0.8v  
OCP  
MPS CONFIDENTIAL  
avoids capacitive switching.  
HR1200  
T DISTRIB  
At t3, the current returns to the correct polarity,  
and another MOSFET is turned on after dV/dt is  
captured effectively.  
Figure 31: CMP and OCP Block Diagram  
Figure 32 shows the operating current principle  
of capacitive mode protection. CSPOS and  
CSNEG stand for the current polarity, which is  
generated by comparing the voltage of CS with  
the internal +80mV and -80mV voltage  
reference.  
If the corrected current polarity from t2 to t5  
cannot be detected, or the current is very small  
and is not capable of pulling SW up or down,  
eventually another MOSFET is forced to switch  
on when the timer for CMP (50µs) expires (as  
shown by the dashed line in Figure 32).  
DO NO  
HR1200 Rev 0.1  
12/11/2015  
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30  
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
The VSS control signal controls the soft start.  
The period for the TIMER voltage to rise  
from 2V to 3.5V can be approximated using  
Equation (22):  
When capacitive-mode operation is detected,  
the VSS control signal is high. The signal turns  
on an internal MOSFET to pull CSS voltage low.  
Therefore, the switching frequency increases  
quickly to limit the power delivery to the output.  
VSS control is reset when the first gate driver is  
switched off (after CMP). The switching  
frequencies decrease smoothly until the control  
loop takes over.  
tOP = 104 ⋅CTimer  
(22)  
The above status remains until the TIMER  
voltage decreases to 0.3V due to RTimer  
slowly discharging CTimer. The IC then  
restarts. This time period is calculated using  
Equation (23):  
3.5  
(23)  
≈ 2.5RTimer ⋅CTimer  
Over-Current Regulation and Over-Current  
Protection (CSHB, TIMER)  
tOFF=RTimer ⋅CTimer ⋅ln  
0.3  
The OCR limits the energy transferred from  
the primary to the secondary winding during  
an overload or short-circuit period. However,  
excessive power consumption due to high  
continuous currents can damage the  
secondary-side windings and rectifiers. By  
incorporating the TIMER function, the IC  
provides additional protection to reduce the  
average power consumption. When OCR is  
The HR1200 provides two-level over-current  
protection (see Figure 33):  
1. Over-current regulation  
The first level of protection occurs when the  
voltage on CSHB exceeds 0.8V. Two actions  
take place:  
a. The transistor connected between SS and  
GND internally is turned on for at least 10µs,  
which causes the CSS voltage to drop,  
resulting in a sharp increase in the oscillator  
frequency. Hence, energy transferred to the  
output is reduced.  
UTE  
triggered, the converter enters a hiccup-like  
protection mode that operates intermittently.  
Figure 33 shows the timing procedure.  
b. An internal 130µA current source turns on to  
charge CTimer and raises the TIMER voltage.  
If the CSHB voltage drops below 0.8V (10mV  
hysteresis) before the TIMER voltage  
reaches 2V, the discharging of CSS and the  
charging of CTIMER stops. The converter then  
resumes normal operation.  
t
OC is the time for the voltage on CTimer to rise  
from 0V to 2V. It is actually a delay time for  
over-current regulation. There is no simple  
relationship between tOC and CTimer. Select  
Figure 33: OCR Timing Sequence  
2. Over-current protection  
MPS CONFIDENTIAL  
CTimer based on experimental results.  
T DISTRIB  
The second level of protection triggers when  
If the CS voltage remains larger than 0.8V  
after the voltage on CTimer rises to 2V, CSS is  
discharged continuously, and the internal  
130µA current continues to charge CTIMER  
until the TIMER voltage reaches 3.5V. This  
allows the IC to turn off all gate driver  
outputs.  
the CSHB voltage rises to 1.5V. Normally,  
this condition happens when the CSHB  
voltage continues rising during a short circuit.  
The IC stops switching immediately and  
CTimer is charged by an internal 130µA  
current source until VTimer reaches 3.5V. The  
IC restarts when VTimer falls below 0.3V.  
The OCP provides a high-speed over-current  
limitation. It works in auto-recovery mode  
when OCP triggers.  
DO NO  
HR1200 Rev 0.1  
12/11/2015  
www.MonolithicPower.com  
31  
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© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
Current Sensing  
This method is simple, but it causes  
unnecessary power consumption on the sense  
resistor.  
The HR1200 uses two methods for sensing  
current: lossless current sensing and sense  
resistor current sensing. Generally, lossless  
current sensing is used in high-power  
applications (see Figure 34).  
Figure 35: Current Sensing with a Sense  
Resistor  
Design the sense resistor using Equation (28):  
Figure 34: Current Sensing with Lossless  
Network  
0.8  
(28)  
RS <  
ICrpk  
To design the lossless current sensing network,  
use Equation (24):  
LLC Brown-In/Brown-Out (D2D BI/BO)  
Cr  
UTE  
Cs ≤  
(24)  
LLC is stopped when the D2D BI/BO signal is  
low and recovers as soon as the D2D BI/BO  
signal goes high.  
100  
To avoid triggering the capacitive detection  
threshold of 80mV, RS should fulfill the condition  
in Equation (25):  
Burst-Mode Operation (BURST)  
Under light-load or no-load, the maximum  
frequency limits the resonant half-bridge  
switching frequency. To control the output  
voltage and limit the power consumption, the  
HR1200 enables the converter to operate in  
burst mode to greatly reduce the average  
switching frequency, thus reducing the average  
residual magnetizing current and the related  
power losses.  
Cr  
80mV  
Im  
(25)  
RS >  
(1+  
)
CS  
However, RS should simultaneously meet  
Equation (26):  
Cr  
0.8  
ICrpk  
Rs<  
⋅(1+  
)
(26)  
CS  
Where ICrpk is the peak current of the resonant  
tank at low input voltage and full load, which is  
expressed in Equation (27):  
MPS CONFIDENTIAL  
NV f  
ICrpk = ( O s )2 + ( O  
4Lm 2N  
I π  
2
T DISTRIB  
(27)  
)
Where N is the turn ratio of the transformer, lo  
and Vo are the output current and voltage, fs is  
the switching frequency, and Lm is the  
magnetizing inductance.  
Figure 36: Burst-Mode Operation Set-Up  
The R1 and C1 networks are used to attenuate  
the switching noise on CS. The time constant  
should be no larger than 100ns.  
An alternative solution is to use a sense resistor  
DO NO  
in series with the resonant tank (see Figure 35).  
HR1200 Rev 0.1  
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© 2015 MPS. All Rights Reserved.  
32  
12/11/2015  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
Figure 36 shows a typical circuit connecting  
switching. Because there is a resistor in parallel  
with the TIMER cap, the TIMER voltage is  
pulled low, and the IC attempts another restart  
until the TIMER voltage falls below 0.3V.  
Figure 38 shows the SFP timing.  
BURST to the feedback signal. RBURST and  
CBURST must be optimized to adjust the number  
of switching cycles during burst-on, which  
reduces no-load power consumption. Rfmax can  
determine the maximum switching frequency to  
run in burst mode. This determines the level of  
the output load needed to run in burst mode.  
Unplug from  
transient  
main input  
Over load  
SO  
Or short  
2.5V  
t
Error  
signal  
Figure 37 illustrates burst-mode operation.  
When the output load decreases, the BURST  
voltage also decreases. If the BURST voltage  
drops below 1.23V, the HR1200 stops switching  
both the HSG and LSG gate driver outputs and  
connects CT to GNDS internally. Meanwhile,  
the SYN signal is set high. Once the voltage on  
BURST exceeds 1.23V by a hysteresis of 40mV,  
the HR1200 resumes normal operation and  
sets the SYN signal to low. The SYN signal is  
used to synchronize the burst of PFC to LLC.  
t
LG/HG  
t
Soft  
Start  
SS  
t
TIMER  
3.5V  
2V  
0.3V  
t
t
SFP  
SFP  
Figure 38: SFP Timing  
During burst-mode operation, the soft-start  
function is not activated.  
UTE  
Connect SO to the resistor divider from V3.3 if  
the SO functions are not needed.  
High-Side Gate Driver (HSG)  
The external BST capacitor provides energy to  
the high-side gate driver. An integrated  
bootstrap diode charges this capacitor through  
VCC. This diode simplifies the external driving  
circuit for the high-side switch, allowing the BST  
capacitor to charge when the low-side MOSFET  
is on.  
To provide enough gate driver energy  
(considering the BST capacitor charging time),  
use a 100nF to 1μF capacitor for the BST  
capacitor (see Figure 39).  
Figure 37: Bust-Mode Operation  
Latch Protection (SO)  
If the SO voltage exceeds the 3.5V threshold,  
the IC latches off. The latch can only be  
released when VCC drops below the VCCRST  
threshold. This function can be used for OVP or  
OTP.  
MPS CONFIDENTIAL  
T DISTRIB  
Start-Up Failure Protection (SFP, SO)  
During start-up, the TIMER cap begins charging  
up with an internal 25µA current. If the SO  
voltage is less than 2.5V when the TIMER  
voltage rises up to 2V, then the IC treats this as  
a
fault condition. The HR1200 begins  
Figure 39: High-Side Gate Driver  
discharging the SS capacitance, and TIMER  
continues ramping up. When the TIMER  
voltage reaches 3.5V, the HR1200 stops  
charging TIMER,  
D
and b  
O
oth PFC  
N
and LLC stop  
O
HR1200 Rev 0.1  
12/11/2015  
www.MonolithicPower.com  
33  
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© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
Low-Side Gate Driver (LSG)  
LSG provides the gate driver signal for the low-  
side MOSFET. The maximum absolute rating  
table shows the maximum LSG voltage is 14V.  
Under certain conditions, a large voltage spike  
occurs on LSG due to oscillations from the long  
gate-driver wire, the MOSFET parasitic  
capacitance, and the small gate-driver resistor.  
Since this voltage spike is dangerous to LSG,  
add a 13V Zener diode close to LSG and GND  
(see Figure 40).  
UTE  
Figure 40: Low-Side Gate Drive  
MPS CONFIDENTIAL  
T DISTRIB  
DO NO  
HR1200 Rev 0.1  
12/11/2015  
www.MonolithicPower.com  
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© 2015 MPS. All Rights Reserved.  
34  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
PROTECTION SUMMARY  
Pin  
VCC  
VCC  
VREG  
SO  
Symbol  
Description  
Affected  
Action  
VCC_UVP  
Under-voltage protection for VCC  
Short-circuit protection for VCC  
Under-voltage protection for VREG  
Latch protection  
System  
System  
System  
System  
System  
System  
System  
PFC  
Disable  
Disable and limited I  
VCC_SCP  
VVreg_UVP  
VSO_Latch  
VSO_SFP  
HV  
Disable and limited I (Vdd)  
ch  
Shutdown and latch  
Re-start with timer out  
Disable  
Suspend switching  
Program with restart or latch off  
Suspend switching  
Restart with timer out  
SO  
Start-up failure protection  
Over-temperature protection  
Line input under-voltage protection  
Current limit of PFC  
Over voltage of PFC  
Open-loop protection  
OTP  
ACIN  
CSP  
FBP  
FBP  
Brown out  
OCP_PFC  
OVP_PFC  
OLP_PFC  
PFC  
System  
LLC Brown  
In/out  
LLC stage under-voltage protection  
HBC  
Suspend switching  
FBP  
UVP_PFC  
OCR_HBC  
Under-voltage protection for PFC out  
Over-current regulation of HBC  
HBC  
HBC  
Suspend switching  
CSHB  
Restart with timer out  
CSHB  
OCP_HBC  
Over-current protection HBC  
HBC  
Shutdown, restart with timer out  
UTE  
CSHB  
CSHB  
Pin  
VCC  
VCC  
VREG  
SO  
CMR  
ADT  
Capacitive mode regulation  
Adaptive dead time  
HBC  
HBC  
Increasing switching frequency  
Prevent hard switching  
Action  
Disable  
Disable and limit IHV  
Symbol  
VCC_UVP  
VCC_SCP  
Vreg_UVP  
VSO_Latch  
VSO_SFP  
Description  
Affected  
System  
System  
System  
System  
Under-voltage protection for VCC  
Short-circuit protection for VCC  
Under-voltage protection for VREG  
Latch protection  
Disable and limit I (Vdd)  
ch  
Shutdown and latch  
SO  
Start-up failure protection  
Over-temperature protection  
Line input under-voltage protection  
Current limit of PFC  
Over voltage of PFC  
Open-loop protection  
System  
System  
System  
PFC  
PFC  
System  
Restart with timer out  
Disable  
Suspend switching  
Program with restart or latch off  
Suspend switching  
Restart with timer out  
OTP  
Brown-out  
OCP_PFC  
OVP_PFC  
OLP_PFC  
LLC brown-in/-  
out  
ACIN  
CSP  
FBP  
FBP  
LLC stage under-voltage protection  
HBC  
Suspend switching  
Under-voltage protection for PFC  
out  
FBP  
UVP_PFC  
HBC  
Suspend switching  
M
C
P
SHB  
S
OCR_  
C
HBC  
O
Over  
N
-current  
F
regul  
I
atio  
D
n of HB  
E
C
N
HB  
T
C
I
R
A
estart with timer out  
L
T DISTRIB  
Shutdown, restart with timer  
out  
Increasing switching frequency  
Prevent hard switching  
CSHB  
OCP_HBC  
Over-current protection HBC  
HBC  
CSHB  
CSHB  
CMR  
ADT  
Capacitive mode regulation  
Adaptive dead time  
HBC  
HBC  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2015 MPS. All Rights Reserved.  
35  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
TYPICAL APPLICATION CIRCUIT  
2
1
1
2
2
1
V G 1  
V D 1  
V S  
1
2
1
2
1
S V C C  
1
2
3
4
3
4
1
2
1
2
V S 2  
2
3
V D 2  
V G 2  
1
1
2
2
2
3
2
3
1
2
1
2
3
1
2
C
S V C  
2
1
UTE  
V S 2  
V G  
2
2
V S 1  
1
1
4
2
3
1
V D  
V D 1  
1
2
1
2
1
2
2
1
2
1
3
4
3
4
B U V S _  
2
3
2
3
2
1
1
2
1
2
2
1
3
4
3
4
2
1
MPS CONFIDENTIAL  
T DISTRIB  
3
3 V  
1
2
1
2
3
4
3
4
Figure 41: Application Circuit  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2015 MPS. All Rights Reserved.  
36  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
PACKAGE INFORMATION  
TSSOP-28  
UTE  
MPS CONFIDETIAL  
T DISTRIB  
DO NO  
HR1200 Rev 0.8  
12/11/2015  
Preliminary Specifications Subject to Change  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
37  
© 2015 MPS. All Rights Reserved.  
HR1200 – HIGH-PERFORMANCE DIGITAL PFC+LLC COMBO CONTROLLER  
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE  
PACKAGE INFORMATION  
SOIC-28  
UTE  
MPS CONFIDENTIAL  
T DISTRIB  
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third  
DO NO  
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not  
assume any legal responsibility for any said applications.  
HR1200 Rev 0.8  
12/11/2015  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
38  
Preliminary Specifications Subject to Change  
© 2015 MPS. All Rights Reserved.  

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