XPC862PZP66 [MOTOROLA]
32-BIT, 66MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357;
| 型号： | XPC862PZP66 |
| 厂家： | 
MOTOROLA |
| 描述： | 32-BIT, 66MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357 时钟 外围集成电路 |
| 文件： | 总82页 (文件大小：530K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
MPC862 EC/D
Rev. 0.2, 11/2001
MPC862 Family
Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC862 family (refer to Table 1 for a list
of devices). The MPC862P is the superset device of the MPC862 family.
This document contains the following topics:
Topic
Page
Part I, “Overview”
1
Part II, “Features”
2
Part III, “Maximum Tolerated Ratings”
Part IV, “Thermal Characteristics”
Part V, “Power Dissipation”
6
7
8
Part VI, “DC Characteristics”
8
Part VII, “Thermal Calculation and Measurement”
Part VIII, “Layout Practices”
9
12
12
38
40
63
64
68
81
Part IX, “Bus Signal Timing”
Part X, “IEEE 1149.1 Electrical Specifications”
Part XI, “CPM Electrical Characteristics”
Part XII, “UTOPIA AC Electrical Specifications”
Part XIII, “FEC Electrical Characteristics”
Part XIV, “Mechanical Data and Ordering Information”
Part XV, “Document Revision History
Part I Overview
The MPC862 is a derivative of Motorola’s MC68360 Quad Integrated Communications
Controller (QUICC™) and part of the PowerQUICC™ family of devices. It is a versatile
single-chip integrated microprocessor and peripheral combination that can be used in a variety
of controller applications and communications and networking systems. The MPC862
provides enhanced ATM functionality over that of other ATM-enabled members of the
MPC860 family.
The CPU on the MPC862 is a 32-bit MPC8xx core that incorporates memory management
units (MMUs) and instruction and data caches. The communications processor module (CPM)
from the MC68360 QUICC has been enhanced by the addition of the inter-integrated
Features
2
controller (I C) channel. The memory controller has been enhanced, enabling the MPC862 to support any
type of memory, including high-performance memories and new types of DRAMs. A PCMCIA socket
controller supports up to two sockets. A real-time clock has also been integrated.
Table 1 shows the functionality supported by the members of the MPC862 family.
Table 1. MPC862 Family Functionality
Cache
Ethernet
Part
SCC
Instruction
Cache
Data Cache
10T
10/100
MPC862DT
MPC862DP
MPC862SR
MPC862T
4 Kbyte
16 Kbyte
4 Kbyte
4 Kbyte
16 Kbyte
4 Kbyte
8 Kbyte
4 Kbyte
4 Kbyte
8 Kbyte
Up to 2
Up to 2
Up to 4
Up to 4
Up to 4
1
1
2
2
4
4
4
—
1
MPC862P
1
Unless otherwise specified, the PowerQUICC unit is referred to as the MPC862 in this document.
Part II Features
The following list summarizes the key MPC862 features:
•
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
– 16-Kbyte instruction caches (MPC862P and MPC862DP) are four-way, set-associative
with 256 sets; 4-Kbyte instruction caches (MPC862T, MPC862SR, and MPC862DT) are
two-way, set-associative with 128 sets.
– 8-Kbyte data caches (MPC862P and MPC862DP) are two-way, set-associative with 256
sets; 4-Kbyte data caches (MPC862T, MPC862SR, and MPC862DT) are two-way,
set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
•
The MPC862 provides enhanced ATM functionality over that of the MPC860SAR. The MPC862
adds major new features available in “enhanced SAR” (ESAR) mode, including the following:
— Multiple APC priority levels available to support a range of traffic pace requirements
— Port-to-port switching capability without the need for RAM-based microcode
2
MPC862FamilyHardwareSpecifications
MOTOROLA
Features
— Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
— Optional statistical cell counters per PHY
2
— Parameter RAM for both SPI and I C can be relocated without RAM-based microcode.
— Supports full-duplex UTOPIA master (ATM side) operation using a “split” bus
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
•
•
•
•
Operates at up to 80 MHz
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, flash EPROMs, and other memory
devices.
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
•
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
Fast Ethernet controller (FEC)
•
•
— Simultaneous MII (100Base-T) and UTOPIA operation when using the UTOPIA multiplexed
bus.
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Interrupts
•
— Seven external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
MOTOROLA
MPC862FamilyHardwareSpecifications
3
Features
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
Communications processor module (CPM)
— RISC controller
•
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT
MODE, and RESTART TRANSMIT)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8-Kbytes of dual-port RAM
— 16 serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
Four baud rate generators
•
•
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
Four SCCs (serial communication controllers)
— Serial ATM capability on all SCCs
— Optional UTOPIA port on SCC4
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
Two SMCs (serial management channels)
— UART
•
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
One serial peripheral interface (SPI)
•
•
— Supports master and slave modes
— Supports multiple-master operation on the same bus
2
One inter-integrated circuit (I C) port
4
MPC862FamilyHardwareSpecifications
MOTOROLA
Features
— Supports master and slave modes
— Multiple-master environment support
•
Time-slot assigner (TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, clocking
— Allows dynamic changes
— Can be internally connected to six serial channels (four SCCs and two SMCs)
Parallel interface port (PIP)
•
•
— Centronics interface support
— Supports fast connection between compatible ports on MPC862 or MC68360
PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports two independent PCMCIA sockets
— 8 memory or I/O windows supported
•
Low power support
— Full on—All units fully powered
— Doze—Core functional units disabled except time base decrementer, PLL, memory controller,
RTC, and CPM in low-power standby
— Sleep—All units disabled except RTC, PIT, time base, and decrementer with PLL active for
fast wake up
— Deep sleep—All units disabled including PLL except RTC, PIT, time base, and decrementer.
— Power down mode— All units powered down except PLL, RTC, PIT, time base and
decrementer
•
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: = ¹ < >
— Each watchpoint can generate a break point internally
3.3 V operation with 5-V TTL compatibility except EXTAL and EXTCLK
357-pin ball grid array (BGA) package
•
•
The MPC862 is comprised of three modules that each use the 32-bit internal bus—the MPC8xx core, the
system integration unit (SIU), and the communication processor module (CPM). The MPC862P block
diagram is shown in Figure 1.
MOTOROLA
MPC862FamilyHardwareSpecifications
5
Maximum Tolerated Ratings
16-Kbyte
Instruction Cache
Instruction
Bus
System Interface Unit (SIU)
Unified
Bus
Memory Controller
Instruction MMU
32-Entry ITLB
Embedded
MPC8xx
Internal
Bus Interface Bus Interface
Unit Unit
External
Processor
8-Kbyte
Data Cache
Load/Store
Bus
Core
System Functions
Real-Time Clock
Data MMU
32-Entry DTLB
PCMCIA/ATA Interface
Fast Ethernet
Controller
DMAs
FIFOs
4
Interrupt
8-Kbyte
16Virtual
Serial
Parallel I/O
Timers Controllers Dual-Port RAM
and
2
Independent
DMA
Channels
10/100
Base-T
Media Access
Control
4 Baud Rate
Generators
32-Bit RISC Controller
and Program
ROM
Parallel Interface Port
and UTOPIA
Timers
MII
SCC1
SCC2
SCC3
SCC4
SMC1 SMC2
SPI
I2C
TimeSlot Assigner
Serial Interface
Figure 1. MPC862P Block Diagram
Part III Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the MPC862. Table 2
provides the maximum ratings.
Table 2. Maximum Tolerated Ratings
(GND = 0V)
Rating
Supply voltage 1
Symbol
VDDH
Value
Unit
-0.3 to 4.0
-0.3 to 4.0
-0.3 to 4.0
-0.3 to 4.0
V
V
V
V
V
VDDL
KAPWR
VDDSYN
Vin
Input voltage 2
GND-0.3 to VDDH
6
MPC862FamilyHardwareSpecifications
MOTOROLA
Thermal Characteristics
Table 2. Maximum Tolerated Ratings (Continued)
(GND = 0V)
Rating
Symbol
TA(min)
Value
Unit
Temperature 3 (standard)
0
˚C
˚C
˚C
˚C
˚C
Tj(max)
TA(min)
Tj(max)
Tstg
95
-40
105
Temperature 3 (extended)
Storage temperature range
-55 to +150
1
The power supply of the device must start its ramp from 0.0 V.
2
Functional operating conditions are provided with the DC electrical specifications in Table 5.
Absolute maximum ratings are stress ratings only; functional operation at the maxima is not
guaranteed. Stress beyond those listed may affect device reliability or cause permanent
damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage.
This restriction applies to power-up and normal operation (that is, if the MPC862 is unpowered,
voltage greater than 2.5 V must not be applied to its inputs).
3
Minimum temperatures are guaranteed as ambient temperature, TA. Maximum temperatures
are guaranteed as junction temperature, T.
j
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for example, either GND or V ).
CC
Part IV Thermal Characteristics
Table 3 shows the thermal characteristics for the MPC862.
Table 3. MPC862 Thermal Resistance Data
Rating
Environment
Single layer board (1s)
Symbol
Value
Unit
Junction to ambient 1
Natural Convection
Air flow (200 ft/min)
RqJA
40
25
32
21
15
7
°C/W
2
3
Four layer board (2s2p) RqJMA
3
Single layer board (1s)
Four layer board (2s2p)
RqJMA
RqJMA
RqJB
RqJC
YJT
3
Junction to board 4
5
Junction to case
Junction to package top 6 Natural Convection
2
Air flow (200 ft/min)
YJT
3
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board,
and board thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
2
3
4
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
MOTOROLA
MPC862FamilyHardwareSpecifications
7
Power Dissipation
5
Indicates the average thermal resistance between the die and the case top surface as measured by the
cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature. For exposed pad packages where the pad would be expected to be soldered, junction to
case thermal resistance is a simulated value from the junction to the exposed pad without contact
resistance.
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.
6
Part V Power Dissipation
Table 4 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal,
and 2:1 mode, where CPU frequency is twice bus speed.
Table 4. Power Dissipation (P )
D
Die Revision
Frequency
Typical1
Maximum 2
Unit
0
50 MHz
66 MHz
66 MHz
80 MHz
656
TBD
722
851
735
TBD
762
909
mW
mW
mW
mW
(1:1 Mode)
0
(2:1 Mode)
1
2
Typical power dissipation is measured at 3.3V.
Maximum power dissipation is measured at 3.5V.
NOTE
Values in Table 4 represent VDDL based power dissipation and do not
include I/O power dissipation over VDDH. I/O power dissipation varies
widely by application due to buffer current, depending on external
circuitry.
Part VI DC Characteristics
Table 5 provides the DC electrical characteristics for the MPC862.
Table 5. DC Electrical Specifications
Characteristic
Symbol
Min
Max
3.6
3.6
Uni t
Operating voltage at 40 MHz or less
VDDH, VDDL, VDDSYN
3.0
V
V
V
KAPWR (power-down mode) 2.0
KAPWR (all other operating VDDH - 0.4 VDDH
modes)
Operating voltage greater than 40 MHz
VDDH, VDDL, KAPWR,
VDDSYN
3.135
3.465
V
KAPWR (power-down mode) 2.0
3.6
V
V
KAPWR (all other operating VDDH - 0.4 VDDH
modes)
Input High Voltage (all inputs except EXTAL and EXTCLK) VIH
2.0
5.5
V
8
MPC862FamilyHardwareSpecifications
MOTOROLA
Thermal Calculation and MeasurementEstimation with Junction-to-Ambient Thermal Resistance
Table 5. DC Electrical Specifications (Continued)
Characteristic
Symbol
Min
GND
Max
0.8
Uni t
Input Low Voltage
VIL
VIHC
Iin
V
EXTAL, EXTCLK Input High Voltage
0.7*(VCC) VCC+0.3 V
Input Leakage Current, Vin = 5.5V (Except TMS, TRST,
DSCK and DSDI pins)
—
—
—
100
µA
µA
µA
Input Leakage Current, Vin = 3.6V (Except TMS, TRST,
DSCK, and DSDI)
IIn
IIn
10
Input Leakage Current, Vin = 0V (Except TMS, TRST,
DSCK and DSDI pins)
10
Input Capacitance 1
Cin
—
20
—
pF
V
Output High Voltage, IOH = -2.0 mA, VDDH = 3.0V
Except XTAL, XFC, and Open drain pins
VOH
2.4
Output Low Voltage
VOL
—
0.5
V
IOL = 2.0 mA (CLKOUT)
IOL = 3.2 mA 2
IOL = 5.3 mA 3
IOL = 7.0 mA (TXD1/PA14, TXD2/PA12)
IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET)
1
Input capacitance is periodically sampled.
2
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/VFLS(0:1),
IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3,
RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8,
TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5,
TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1,
L1TCLKB/TOUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28,
BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1/SDACK1/PB23,
SMSYN2/SDACK2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19,
L1ST2/RTS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14,
L1ST1/RTS1/DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11,
TGATE1/CD1/PC10, CTS2/PC9, TGATE2/CD2/PC8, SDACK2/L1TSYNCB/PC7, L1RSYNCB/PC6,
SDACK1/L1TSYNCA/PC5, L1RSYNCA/PC4, PD15, PD14, PD13, PD12, PD11, PD10, PD9, PD8, PD5, PD6, PD7,
PD4, PD3, MII_MDC, MII_TX_ER, MII_EN, MII_MDIO, MII_TXD[0:3]
3
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD,
WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A,
ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30)
Part VII Thermal Calculation and Measurement
For the following discussions, P = (VDD x IDD) + PI/O, where PI/O is the power dissipation of the I/O
D
drivers.
7.1 Estimation with Junction-to-Ambient Thermal
Resistance
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
T = T +( R
x P )
D
J
A
qJA
MOTOROLA
MPC862FamilyHardwareSpecifications
9
Thermal Calculation and MeasurementEstimation with Junction-to-Case Thermal Resistance
where:
T = ambient temperature ºC
A
R
= package junction-to-ambient thermal resistance (ºC/W)
qJA
P = power dissipation in package
D
The junction-to-ambient thermal resistance is an industry standard value which provides a quick and easy
estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated
that errors of a factor of two (in the quantity T -T ) are possible.
J
A
7.2 Estimation with Junction-to-Case Thermal
Resistance
Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
R
= R
+ R
qJA
qJC qCA
where:
R
= junction-to-ambient thermal resistance (ºC/W)
= junction-to-case thermal resistance (ºC/W)
= case-to-ambient thermal resistance (ºC/W)
qJA
qJC
qCA
R
R
R
is device related and cannot be influenced by the user. The user adjusts the thermal environment to
qJC
affect the case-to-ambient thermal resistance, R
. For instance, the user can change the air flow around
qCA
the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the
thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful
for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink
to the ambient environment. For most packages, a better model is required.
7.3 Estimation with Junction-to-Board Thermal
Resistance
A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a two resistor
model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case
covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the
top of the package. The junction-to-board thermal resistance describes the thermal performance when most
of the heat is conducted to the printed circuit board. It has been observed that the thermal performance of
most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see
Figure 2.
10
MPC862FamilyHardwareSpecifications
MOTOROLA
Thermal Calculation and MeasurementEstimation Using Simulation
1 0 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0
0
2 0
4 0
6 0
8 0
Board Temperture Rise Above Ambient Divided by Package
Power
Figure 2. Effect of Board Temperature Rise on Thermal Behavior
If the board temperature is known, an estimate of the junction temperature in the environment can be made
using the following equation:
T = T +( R
x P )
D
J
B
qJB
where:
R
= junction-to-board thermal resistance (ºC/W)
qJB
T = board temperature ºC
B
P = power dissipation in package
D
If the board temperature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground
plane.
7.4 Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is needed. The simple
two resistor model can be used with the thermal simulation of the application [2], or a more accurate and
complex model of the package can be used in the thermal simulation.
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (Y ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T +( Y x P )
J
T
JT
D
where:
MOTOROLA
MPC862FamilyHardwareSpecifications
11
Layout PracticesReferences
Y
= thermal characterization parameter
JT
T = thermocouple temperature on top of package
T
P = power dissipation in package
D
The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC using
a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be
positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over
the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
7.6 References
Semiconductor Equipment and Materials International
805 East Middlefield Rd
(415) 964-5111
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifications
(Available from Global Engineering Documents)
800-854-7179 or
303-397-7956
JEDEC Specifications
http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its
Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
Part VIII Layout Practices
Each VCC pin on the MPC862 should be provided with a low-impedance path to the board’s supply. Each
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1
µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip VCC and GND should be kept to less than half an inch
per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes.
All output pins on the MPC862 have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching
times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths
of six inches are recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins.
Part IX Bus Signal Timing
Table 6 provides the bus operation timing for the MPC862 at 33 MHz, 40 Mhz, 50 MHz and 66 Mhz.
The maximum bus speed supported by the MPC862 is 66 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC862 used at 80MHz must be configured for a 40 MHz bus).
12
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
The timing for the MPC862 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for
minimum delays.
Table 6. Bus Operation Timings
33 MHz
40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B1 CLKOUT period
30.30 30.30 25.00 30.30 20.00 30.30 15.15 30.30 ns
B1a EXTCLK to CLKOUT phase skew
(EXTCLK > 15 MHz and MF <= 2)
-0.90
-2.30
-0.60
0.90
2.30
0.60
-0.90 0.90 -0.90 0.90 -0.90 0.90
-2.30 2.30 -2.30 2.30 -2.30 2.30
-0.60 0.60 -0.60 0.60 -0.60 0.60
-2.00 2.00 -2.00 2.00 -2.00 2.00
ns
ns
ns
B1b EXTCLK to CLKOUT phase skew
(EXTCLK > 10 MHz and MF < 10)
B1c CLKOUT phase jitter (EXTCLK > 15
1
MHz and MF <= 2)
B1d CLKOUT phase jitter1
-2.00
—
2.00
0.50
2.00
ns
%
%
B1e CLKOUT frequency jitter (MF < 10) 1
—
—
0.50
2.00
—
—
0.50
2.00
—
—
0.50
2.00
B1f CLKOUT frequency jitter (10 < MF <
500) 1
—
B1g CLKOUT frequency jitter (MF > 500) 1
—
—
3.00
0.50
—
—
—
3.00
0.50
—
—
—
3.00
0.50
—
—
—
3.00
0.50
—
%
%
2
B1h Frequency jitter on EXTCLK
B2 CLKOUT pulse width low
B3 CLKOUT width high
B4 CLKOUT rise time 3
B533 CLKOUT fall time3
12.12
12.12
—
10.00
10.00
—
8.00
8.00
—
6.06
6.06
—
ns
ns
ns
ns
ns
—
—
—
—
4.00
4.00
—
4.00
4.00
—
4.00
4.00
—
4.00
4.00
—
—
—
—
—
B7 CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31), DP(0:3)
invalid
7.58
6.25
5.00
3.80
B7a CLKOUT to TSIZ(0:1), REG, RSV,
AT(0:3), BDIP, PTR invalid
7.58
7.58
—
—
6.25
6.25
—
—
5.00
5.00
—
—
3.80
3.80
—
—
ns
ns
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1),
VF(0:2) IWP(0:2), LWP(0:1), STS
4
invalid
B8 CLKOUT to A(0:31), BADDR(28:30)
RD/WR, BURST, D(0:31), DP(0:3) valid
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
B8a CLKOUT to TSIZ(0:1), REG, RSV,
AT(0:3) BDIP, PTR valid
B8b CLKOUT to BR, BG, VFLS(0:1),
VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS
Valid 4
B9 CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31), DP(0:3),
TSIZ(0:1), REG, RSV, AT(0:3), PTR
High-Z
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
7.58 13.58 6.25 12.25 5.00 11.00 3.80 11.29 ns
B11 CLKOUT to TS, BB assertion
MOTOROLA
MPC862FamilyHardwareSpecifications
13
Bus Signal TimingReferences
Table 6. Bus Operation Timings (Continued)
33 MHz
40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
2.50
Max
Min
2.50
Max
Min
2.50
Max
Min
2.50
Max
B11a CLKOUT to TA, BI assertion (when
driven by the memory controller or
PCMCIA interface)
9.25
9.25
9.25
9.75
ns
B12 CLKOUT to TS, BB negation
7.58 14.33 6.25 13.00 5.00 11.75 3.80
2.50 11.00 2.50 11.00 2.50 11.00 2.50
8.54
9.00
ns
ns
B12a CLKOUT to TA, BI negation (when
driven by the memory controller or
PCMCIA interface)
B13 CLKOUT to TS, BB High-Z
7.58 21.58 6.25 20.25 5.00 19.00 3.80 14.04 ns
B13a CLKOUT to TA, BI High-Z (when driven 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
by the memory controller or PCMCIA
interface)
B14 CLKOUT to TEA assertion
B15 CLKOUT to TEA High-Z
2.50 10.00 2.50 10.00 2.50 10.00 2.50
9.00
ns
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B16 TA, BI valid to CLKOUT (setup time)
9.75
—
—
9.75
—
—
9.75
—
—
6.00
4.50
—
—
ns
ns
B16a TEA, KR, RETRY, CR valid to CLKOUT 10.00
(setup time)
10.00
10.00
B16b BB, BG, BR, valid to CLKOUT (setup
8.50
—
—
—
—
—
—
—
8.50
1.00
2.00
6.00
1.00
4.00
2.00
—
—
—
—
—
—
—
8.50
1.00
2.00
6.00
1.00
4.00
2.00
—
—
—
—
—
—
—
4.00
2.00
2.00
6.00
2.00
4.00
2.00
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
5
time)
B17 CLKOUT to TA, TEA, BI, BB, BG, BR
valid (hold time).
1.00
B17a CLKOUT to KR, RETRY, CR valid (hold 2.00
time)
B18 D(0:31), DP(0:3) valid to CLKOUT
6.00
1.00
4.00
2.00
6
rising edge (setup time)
B19 CLKOUT rising edge to D(0:31),
DP(0:3) valid (hold time) 6
B20 D(0:31), DP(0:3) valid to CLKOUT
7
falling edge (setup time)
B21 CLKOUT falling edge to D(0:31),
DP(0:3) valid (hold Time) 7
B22 CLKOUT rising edge to CS asserted
GPCM ACS = 00
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
8.00 8.00 8.00 8.00 ns
B22a CLKOUT falling edge to CS asserted
GPCM ACS = 10, TRLX = 0
—
—
—
—
B22b CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 0
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns
B22c CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 1
B23 CLKOUT rising edge to CS negated
GPCM read access, GPCM write
access ACS = 00, TRLX = 0 & CSNT =
0
2.00
8.00
2.00
8.00
2.00
8.00
2.00
8.00
ns
14
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
Table 6. Bus Operation Timings (Continued)
33 MHz
40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B24 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 0.
5.58
13.15
—
—
4.25
—
3.00
—
1.79
—
ns
ns
ns
B24a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11 TRLX = 0
—
10.50
—
8.00
—
5.58
—
B25 CLKOUT rising edge to OE, WE(0:3)
asserted
9.00
9.00
9.00
9.00
B26 CLKOUT rising edge to OE negated
2.00
9.00
—
2.00
9.00
—
2.00
9.00
—
2.00
9.00
—
ns
ns
B27 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 1
35.88
29.25
23.00
16.94
B27a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 1
43.45
—
—
35.50
—
—
28.00
—
—
20.73
—
—
ns
ns
B28 CLKOUT rising edge to WE(0:3)
negated GPCM write access CSNT = 0
9.00
9.00
9.00
9.00
B28a CLKOUT falling edge to WE(0:3)
negated GPCM write access TRLX = 0,
CSNT = 1, EBDF = 0
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
B28b CLKOUT falling edge to CS negated
GPCM write access TRLX = 0, CSNT =
1 ACS = 10 or ACS = 11, EBDF = 0
—
14.33
—
13.00
—
11.75
—
10.54 ns
B28c CLKOUT falling edge to WE(0:3)
negated GPCM write access TRLX = 0,
CSNT = 1 write access TRLX = 0,
CSNT = 1, EBDF = 1
10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns
B28d CLKOUT falling edge to CS negated
GPCM write access TRLX = 0, CSNT =
1, ACS = 10, or ACS = 11, EBDF = 1
—
17.99
—
—
16.00
—
—
14.13
—
—
12.31 ns
B29 WE(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access, CSNT = 0,
EBDF = 0
5.58
13.15
4.25
10.5
4.25
10.5
35.5
35.5
3.00
8.00
3.00
8.00
28.00
28.00
1.79
5.58
1.79
5.58
20.73
29.73
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
B29a WE(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 0
—
—
—
B29b CS negated to D(0:31), DP(0:3), High Z 5.58
GPCM write access, ACS = 00, TRLX =
0 & CSNT = 0
—
—
—
B29c CS negated to D(0:31), DP(0:3) High-Z 13.15
GPCM write access, TRLX = 0, CSNT =
—
—
—
1, ACS = 10, or ACS = 11 EBDF = 0
B29d WE(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 0
43.45
—
—
—
B29e CS negated to D(0:31), DP(0:3) High-Z 43.45
GPCM write access, TRLX = 1, CSNT =
—
—
—
1, ACS = 10, or ACS = 11 EBDF = 0
MOTOROLA
MPC862FamilyHardwareSpecifications
15
Bus Signal TimingReferences
Table 6. Bus Operation Timings (Continued)
33 MHz
40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
8.86
Max
Min
Max
Min
Max
Min
Max
B29f WE(0:3) negated to D(0:31), DP(0:3)
High Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 1
—
6.88
—
5.00
—
3.18
—
ns
B29g CS negated to D(0:31), DP(0:3) High-Z 8.86
GPCM write access, TRLX = 0, CSNT =
1 ACS = 10 or ACS = 11, EBDF = 1
—
—
—
—
—
6.88
—
—
—
—
—
5.00
—
—
—
—
—
3.18
—
—
—
—
—
ns
ns
ns
ns
ns
B29h WE(0:3) negated to D(0:31), DP(0:3)
High Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 1
38.67
31.38
31.38
4.25
24.50
24.50
3.00
17.83
17.83
1.79
B29i CS negated to D(0:31), DP(0:3) High-Z 38.67
GPCM write access, TRLX = 1, CSNT =
1, ACS = 10 or ACS = 11, EBDF = 1
B30 CS, WE(0:3) negated to A(0:31),
BADDR(28:30) Invalid GPCM write
5.58
8
access
B30a WE(0:3) negated to A(0:31),
BADDR(28:30) Invalid GPCM, write
access, TRLX = 0, CSNT = 1, CS
negated to A(0:31) invalid GPCM write
access TRLX = 0, CSNT =1 ACS = 10,
or ACS == 11, EBDF = 0
13.15
10.50
8.00
5.58
B30b WE(0:3) negated to A(0:31) Invalid
GPCM BADDR(28:30) invalid GPCM
write access, TRLX = 1, CSNT = 1. CS
negated to A(0:31) Invalid GPCM write
access TRLX = 1, CSNT = 1, ACS = 10,
or ACS == 11 EBDF = 0
43.45
8.36
—
—
35.50
6.38
—
—
28.00
4.50
—
—
20.73
2.68
—
—
ns
ns
ns
ns
B30c WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access, TRLX = 0, CSNT = 1. CS
negated to A(0:31) invalid GPCM write
access, TRLX = 0, CSNT = 1 ACS = 10,
ACS == 11, EBDF = 1
B30d WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access TRLX = 1, CSNT =1, CS
negated to A(0:31) invalid GPCM write
access TRLX = 1, CSNT = 1, ACS = 10
or 11, EBDF = 1
38.67
1.50
—
31.38
1.50
—
24.50
1.50
—
17.83
1.50
—
B31 CLKOUT falling edge to CS valid - as
requested by control bit CST4 in the
corresponding word in the UPM
6.00
6.00
6.00
6.00
B31a CLKOUT falling edge to CS valid - as
requested by control bit CST1 in the
corresponding word in the UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
16
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
Table 6. Bus Operation Timings (Continued)
33 MHz
40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
1.50
Max
Min
1.50
Max
Min
1.50
Max
Min
1.50
Max
B31b CLKOUT rising edge to CS valid - as
requested by control bit CST2 in the
corresponding word in the UPM
8.00
8.00
8.00
8.00
ns
B31c CLKOUT rising edge to CS valid- as
requested by control bit CST3 in the
corresponding word in the UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns
B31d CLKOUT falling edge to CS valid, as
requested by control bit CST1 in the
corresponding word in the UPM EBDF
= 1
B32 CLKOUT falling edge to BS valid- as
requested by control bit BST4 in the
corresponding word in the UPM
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
ns
B32a CLKOUT falling edge to BS valid - as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF
= 0
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
B32b CLKOUT rising edge to BS valid - as
requested by control bit BST2 in the
corresponding word in the UPM
1.50
8.00
1.50
8.00
1.50
8.00
1.50
8.00
ns
B32c CLKOUT rising edge to BS valid - as
requested by control bit BST3 in the
corresponding word in the UPM
7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns
B32d CLKOUT falling edge to BS valid- as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF
= 1
B33 CLKOUT falling edge to GPL valid - as 1.50
requested by control bit GxT4 in the
6.00
1.50
6.00
1.50
6.00
1.50
6.00
ns
corresponding word in the UPM
B33a CLKOUT rising edge to GPL Valid - as 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns
requested by control bit GxT3 in the
corresponding word in the UPM
B34 A(0:31), BADDR(28:30), and D(0:31) to 5.58
CS valid - as requested by control bit
CST4 in the corresponding word in the
UPM
—
—
—
4.25
10.50
16.75
—
—
—
3.00
—
—
—
1.79
5.58
9.36
—
—
—
ns
ns
ns
B34a A(0:31), BADDR(28:30), and D(0:31) to 13.15
CS valid - as requested by control bit
CST1 in the corresponding word in the
UPM
8.00
B34b A(0:31), BADDR(28:30), and D(0:31) to 20.73
CS valid - as requested by CST2 in the
corresponding word in UPM
13.00
MOTOROLA
MPC862FamilyHardwareSpecifications
17
Bus Signal TimingReferences
Table 6. Bus Operation Timings (Continued)
33 MHz
40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B35 A(0:31), BADDR(28:30) to CS valid - as 5.58
requested by control bit BST4 in the
—
4.25
10.50
16.75
—
3.00
—
1.79
5.58
9.36
—
ns
corresponding word in the UPM
B35a A(0:31), BADDR(28:30), and D(0:31) to 13.15
BS valid - As Requested by BST1 in the
corresponding word in the UPM
—
—
—
—
8.00
—
—
—
—
ns
ns
B35b A(0:31), BADDR(28:30), and D(0:31) to 20.73
BS valid - as requested by control bit
BST2 in the corresponding word in the
UPM
13.00
B36 A(0:31), BADDR(28:30), and D(0:31) to 5.58
GPL valid as requested by control bit
GxT4 in the corresponding word in the
UPM
—
4.25
—
3.00
—
1.79
—
ns
9
B37 UPWAIT valid to CLKOUT falling edge
6.00
—
—
—
—
6.00
1.00
7.00
7.00
—
—
—
—
6.00
1.00
7.00
7.00
—
—
—
—
6.00
1.00
7.00
7.00
—
—
—
—
ns
ns
ns
ns
B38 CLKOUT falling edge to UPWAIT valid 9 1.00
B39 AS valid to CLKOUT rising edge10
7.00
7.00
B40 A(0:31), TSIZ(0:1), RD/WR, BURST,
valid to CLKOUT rising edge
B41 TS valid to CLKOUT rising edge (setup 7.00
time)
—
—
7.00
2.00
—
—
—
7.00
2.00
—
—
—
7.00
2.00
—
—
—
ns
ns
ns
B42 CLKOUT rising edge to TS valid (hold
time)
2.00
B43 AS negation to memory controller
signals negation
—
TBD
TBD
TBD
TBD
1
2
Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.
If the rate of change of the frequency of EXTAL is slow (I.e. it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (I.e., it does not stay at an extreme value for a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.
3
4
The timings specified in B4 and B5 are based on full strength clock.
The timing for BR output is relevant when the MPC862 is selected to work with external bus arbiter. The timing for
BG output is relevant when the MPC862 is selected to work with internal bus arbiter.
The timing required for BR input is relevant when the MPC862 is selected to work with internal bus arbiter. The
timing for BG input is relevant when the MPC862 is selected to work with external bus arbiter.
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input
signal is asserted.
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only
for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
5
6
7
8
9
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified
in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 18.
The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior
specified in Figure 21.
10
18
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
Figure 3 is the control timing diagram.
2.0V
2.0V
CLKOUT
0.8V
0.8V
A
B
2.0V
0.8V
2.0V
0.8V
Outputs
Outputs
Inputs
A
B
2.0V
0.8V
2.0V
0.8V
D
C
2.0V
0.8V
2.0V
0.8V
D
C
2.0V
0.8V
2.0V
0.8V
Inputs
A
B
C
D
Maximum output delay specification
Minimum output hold time
Minimum input setup time specification
Minimum input hold time specification
Figure 3. Control Timing
Figure 4 provides the timing for the external clock.
CLKOUT
B1
B1
B3
B2
B4
B5
Figure 4. External Clock Timing
Figure 5 provides the timing for the synchronous output signals.
MOTOROLA
MPC862FamilyHardwareSpecifications
19
Bus Signal TimingReferences
CLKOUT
B8
B7
B9
B9
Output
Signals
B8a
B8b
B7a
Output
Signals
B7b
Output
Signals
Figure 5. Synchronous Output Signals Timing
Figure 6 provides the timing for the synchronous active pull-up and open-drain output signals.
CLKOUT
B13
B11
B12
B12a
B15
TS, BB
TA, BI
TEA
B13a
B11a
B14
Figure 6. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing
Figure 7 provides the timing for the synchronous input signals.
20
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
CLKOUT
TA, BI
B16
B16a
B16b
B17
B17a
B17
TEA, KR,
RETRY, CR
BB, BG, BR
Figure 7. Synchronous Input Signals Timing
Figure 8 provides normal case timing for input data. It also applies to normal read accesses under the control
of the UPM in the memory controller.
CLKOUT
B16
B17
TA
B18
B19
D[0:31],
DP[0:3]
Figure 8. Input Data Timing in Normal Case
Figure 9 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the
UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
MOTOROLA
MPC862FamilyHardwareSpecifications
21
Bus Signal TimingReferences
CLKOUT
TA
B20
B21
D[0:31],
DP[0:3]
Figure 9. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 10 through Figure 13 provide the timing for the external bus read controlled by various GPCM
factors.
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B22
B23
B25
B26
B19
OE
B28
WE[0:3]
B18
D[0:31],
DP[0:3]
Figure 10. External Bus Read Timing (GPCM Controlled—ACS = 00)
22
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
CLKOUT
TS
B11
B8
B12
A[0:31]
CSx
B23
B22a
B24
B25
B26
B19
OE
B18
D[0:31],
DP[0:3]
Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)
CLKOUT
TS
B11
B8
B12
B22b
B22c
A[0:31]
CSx
B23
B24a
B25
B26
B19
OE
B18
D[0:31],
DP[0:3]
Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)
MOTOROLA
MPC862FamilyHardwareSpecifications
23
Bus Signal TimingReferences
CLKOUT
B11
B12
TS
B8
A[0:31]
CSx
B23
B22a
B27
B26
B19
OE
B27a
B22b B22c
B18
D[0:31],
DP[0:3]
Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11)
Figure 14 through Figure 16 provide the timing for the external bus write controlled by various GPCM
factors.
24
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
CLKOUT
TS
B11
B8
B12
B30
A[0:31]
CSx
B22
B23
B25
B28
WE[0:3]
OE
B26
B29b
B29
B8
B9
D[0:31],
DP[0:3]
Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)
MOTOROLA
MPC862FamilyHardwareSpecifications
25
Bus Signal TimingReferences
CLKOUT
B11
B12
TS
A[0:31]
CSx
B8
B30a B30c
B23
B22
B28b B28d
B25
B29c B29g
WE[0:3]
OE
B26
B29a B29f
B28a B28c
B8
B9
D[0:31],
DP[0:3]
Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)
26
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
CLKOUT
TS
B11
B12
B8
B30b B30d
A[0:31]
CSx
B22
B28b B28d
B23
B25
B29e B29i
WE[0:3]
OE
B26
B29d B29h
B29b
B8
B28a B28c
B9
D[0:31],
DP[0:3]
Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)
Figure 17 provides the timing for the external bus controlled by the UPM.
MOTOROLA
MPC862FamilyHardwareSpecifications
27
Bus Signal TimingReferences
CLKOUT
B8
A[0:31]
B31a
B31d
B31c
B31
B31b
CSx
B34
B34a
B34b
B32a B32d
B32c
B33a
B32
B32b
BS_A[0:3],
BS_B[0:3]
B35 B36
B35b
B35a
B33
GPL_A[0:5],
GPL_B[0:5]
Figure 17. External Bus Timing (UPM Controlled Signals)
Figure 18 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.
28
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
CLKOUT
UPWAIT
CSx
B37
B38
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 18. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing
Figure 19 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 19. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing
Figure 20 provides the timing for the synchronous external master access controlled by the GPCM.
MOTOROLA
MPC862FamilyHardwareSpecifications
29
Bus Signal TimingReferences
CLKOUT
TS
B41
B40
B42
A[0:31],
TSIZ[0:1],
R/W, BURST
B22
CSx
Figure 20. Synchronous External Master Access Timing (GPCM Handled ACS = 00)
Figure 21 provides the timing for the asynchronous external master memory access controlled by the
GPCM.
CLKOUT
B39
AS
B40
A[0:31],
TSIZ[0:1],
R/W
B22
CSx
Figure 21. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Figure 22 provides the timing for the asynchronous external master control signals negation.
AS
B43
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
Figure 22. Asynchronous External Master—Control Signals Negation Timing
30
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
Table 7 provides interrupt timing for the MPC862.
Table 7. Interrupt Timing
All Frequencies
Min Max
Num
Characteristic 1
Unit
I39 IRQx valid to CLKOUT rising edge (set 6.00
up time)
ns
I40 IRQx hold time after CLKOUT
I41 IRQx pulse width low
2.00
3.00
3.00
ns
ns
ns
—
I42 IRQx pulse width high
I43 IRQx edge-to-edge time
4xTCLOCKOUT
1
The timings I39 and I40 describe the testing conditions under which the IRQ
lines are tested when being defined as level sensitive. The IRQ lines are
synchronized internally and do not have to be asserted or negated with
reference to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the
IRQ lines detection circuitry, and has no direct relation with the total system
interrupt latency that the MPC862 is able to support.
Figure 23 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
I39
I40
IRQx
Figure 23. Interrupt Detection Timing for External Level Sensitive Lines
Figure 24 provides the interrupt detection timing for the external edge-sensitive lines.
CLKOUT
I41
I42
IRQx
I43
I43
Figure 24. Interrupt Detection Timing for External Edge Sensitive Lines
MOTOROLA
MPC862FamilyHardwareSpecifications
31
Bus Signal TimingReferences
Table 8 shows the PCMCIA timing for the MPC862.
Table 8. PCMCIA Timing
33 MHz
Min Max
40 MHz
Min Max
50 MHz
Min Max
66 MHz
Min Max
Num
Characteristic
Unit
A(0:31), REGvalid to PCMCIA Strobe 20.73
asserted. 1
—
16.75
—
13.00
—
9.36
—
ns
ns
P44
P45 A(0:31), REG valid to ALE negation.1 28.30
—
23.00
—
18.00
—
13.15
—
P46 CLKOUT to REG valid
7.58
8.58
7.58
7.58
—
15.58 6.25
7.25
14.25 5.00
6.00
13.00 3.79
4.84
11.84 ns
— ns
P47 CLKOUT to REG Invalid.
P48 CLKOUT to CE1, CE2 asserted.
P49 CLKOUT to CE1, CE2 negated.
—
—
—
15.58 6.25
15.58 6.25
14.25 5.00
14.25 5.00
13.00 3.79
13.00 3.79
11.84 ns
11.84 ns
11.00 ns
CLKOUT to PCOE, IORD, PCWE,
IOWR assert time.
11.00
—
11.00
—
11.00
—
P50
CLKOUT to PCOE, IORD, PCWE,
IOWR negate time.
2.00
11.00 2.00
11.00 2.00
11.00 2.00
11.00 ns
P51
P52 CLKOUT to ALE assert time
P53 CLKOUT to ALE negate time
7.58
—
15.58 6.25
14.25 5.00
13.00 3.79
10.04 ns
11.84 ns
15.58
—
—
14.25
—
—
13.00
—
—
PCWE, IOWR negated to D(0:31)
5.58
4.25
3.00
1.79
—
—
—
ns
ns
ns
P54
invalid.1
WAITA and WAITB valid to CLKOUT 8.00
rising edge.1
—
—
8.00
2.00
—
—
8.00
2.00
—
—
8.00
2.00
P55
P56
CLKOUT rising edge to WAITA and
WAITB invalid.1
2.00
1
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See
PCMCIA Interface in the MPC862 PowerQUICC User s Manual.
Figure 25 provides the PCMCIA access cycle timing for the external bus read.
32
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
CLKOUT
TS
P44
P45
A[0:31]
P46
P48
P47
P49
P51
P52
B19
REG
CE1/CE2
PCOE, IORD
ALE
P50
P53
P52
B18
D[0:31]
Figure 25. PCMCIA Access Cycles Timing External Bus Read
Figure 26 provides the PCMCIA access cycle timing for the external bus write.
MOTOROLA
MPC862FamilyHardwareSpecifications
33
Bus Signal TimingReferences
CLKOUT
TS
P44
P45
A[0:31]
P46
P48
P47
P49
P51
P52
B19
REG
CE1/CE2
PCOE, IOWR
ALE
P50
P53
B18
P54
P52
D[0:31]
Figure 26. PCMCIA Access Cycles Timing External Bus Write
Figure 27 provides the PCMCIA WAIT signals detection timing.
CLKOUT
P55
P56
WAITx
Figure 27. PCMCIA WAIT Signals Detection Timing
Table 9 shows the PCMCIA port timing for the MPC862.
34
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
Table 9. PCMCIA Port Timing
33 MHz
Min Max
40 MHz
Min Max
50 MHz
Min Max
66 MHz
Num
Characteristic
Unit
Min
Max
P57 CLKOUT to OPx Valid
—
19.00
—
—
19.00
—
—
19.00
—
—
19.00 ns
P58 HRESET negated to OPx drive 1
P59 IP_Xx valid to CLKOUT rising edge
P60 CLKOUT rising edge to IP_Xx invalid
25.73
5.00
1.00
21.75
5.00
1.00
18.00
5.00
1.00
14.36
5.00
1.00
—
—
—
ns
ns
ns
—
—
—
—
—
—
1
OP2 and OP3 only.
Figure 28 provides the PCMCIA output port timing for the MPC862.
CLKOUT
P57
Output
Signals
HRESET
P58
OP2, OP3
Figure 28. PCMCIA Output Port Timing
Figure 29 provides the PCMCIA output port timing for the MPC862.
CLKOUT
P59
P60
Input
Signals
Figure 29. PCMCIA Input Port Timing
Table 10 shows the debug port timing for the MPC862.
MOTOROLA
MPC862FamilyHardwareSpecifications
35
Bus Signal TimingReferences
Table 10. Debug Port Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
D61
D62
D63
D64
D65
D66
D67
DSCK cycle time
3xTCLOCKOUT
-
-
DSCK clock pulse width
DSCK rise and fall times
DSDI input data setup time
DSDI data hold time
1.25xTCLOCKOUT
0.00
8.00
5.00
0.00
0.00
3.00
ns
ns
ns
DSCK low to DSDO data valid
DSCK low to DSDO invalid
15.00 ns
2.00 ns
Figure 30 provides the input timing for the debug port clock.
DSCK
D61
D62
D61
D62
D63
D63
Figure 30. Debug Port Clock Input Timing
Figure 31 provides the timing for the debug port.
DSCK
D64
D65
DSDI
D66
D67
DSDO
Figure 31. Debug Port Timings
36
MPC862FamilyHardwareSpecifications
MOTOROLA
Bus Signal TimingReferences
Table 11 shows the reset timing for the MPC862.
Table 11. Reset Timing
33 MHz
Min Max
40 MHz
Min Max
50 MHz
Min Max
66 MHz
Min Max
Num
Characteristic
Unit
R69 CLKOUT to HRESET high impedance
R70 CLKOUT to SRESET high impedance
R71 RSTCONF pulse width
—
20.00 —
20.00 —
20.00 —
20.00 —
20.00 —
20.00 —
20.00 ns
20.00 ns
—
515.15 —
425.00 —
340.00 —
257.58 —
ns
—
ns
R72
R73
—
—
—
—
—
—
—
—
—
Configuration data to HRESET rising edge 504.55 —
set up time
425.00 —
350.00 —
277.27 —
Configuration data to RSTCONF rising
edge set up time
350.00 —
350.00 —
350.00 —
350.00 —
ns
ns
ns
R74
R75
R76
R77
R78
Configuration data hold time after
RSTCONF negation
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
Configuration data hold time after HRESET 0.00
negation
HRESET and RSTCONF asserted to data
out drive
—
—
—
25.00 —
25.00 —
25.00 —
25.00 —
25.00 —
25.00 —
25.00 —
25.00 —
25.00 —
25.00 ns
25.00 ns
25.00 ns
RSTCONF negated to data out high
impedance.
CLKOUT of last rising edge before chip
R79 three-states HRESET to data out high
impedance.
R80 DSDI, DSCK set up
90.91
0.00
—
—
75.00
0.00
—
—
60.00
0.00
—
—
45.45
0.00
—
—
ns
ns
ns
R81 DSDI, DSCK hold time
SRESET negated to CLKOUT rising edge 242.42 —
for DSDI and DSCK sample
200.00 —
160.00 —
121.21 —
R82
Figure 32 shows the reset timing for the data bus configuration.
HRESET
R71
R76
RSTCONF
R73
R74
R75
D[0:31] (IN)
Figure 32. Reset Timing—Configuration from Data Bus
MPC862FamilyHardwareSpecifications
MOTOROLA
37
IEEE 1149.1 Electrical SpecificationsReferences
Figure 33 provides the reset timing for the data bus weak drive during configuration.
CLKOUT
R69
HRESET
R79
RSTCONF
R77
R78
D[0:31] (OUT)
(Weak)
Figure 33. Reset Timing—Data Bus Weak Drive during Configuration
Figure 34 provides the reset timing for the debug port configuration.
CLKOUT
R70
R82
SRESET
R80
R80
R81
R81
DSCK, DSDI
Figure 34. Reset Timing—Debug Port Configuration
Part X IEEE 1149.1 Electrical Specifications
Table 12 provides the JTAG timings for the MPC862 shown in Figure 35 to Figure 38.
Table 12. JTAG Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
J82
TCK cycle time
100.00
40.00
0.00
—
ns
ns
10.00 ns
J83
J84
J85
J86
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
—
TMS, TDI data setup time
5.00
—
—
ns
ns
TMS, TDI data hold time
25.00
38
MPC862FamilyHardwareSpecifications
MOTOROLA
IEEE 1149.1 Electrical SpecificationsReferences
Table 12. JTAG Timing (Continued)
All Frequencies
Num
Characteristic
Unit
Min
Max
27.00 ns
ns
20.00 ns
J87
TCK low to TDO data valid
—
J88
J89
J90
J91
J92
J93
J94
J95
J96
TCK low to TDO data invalid
0.00
—
—
TCK low to TDO high impedance
TRST assert time
100.00
40.00
—
—
—
ns
ns
TRST setup time to TCK low
TCK falling edge to output valid
50.00 ns
50.00 ns
50.00 ns
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
—
—
50.00
50.00
—
—
ns
ns
TCK
J82
J83
J82
J83
J84
J84
Figure 35. JTAG Test Clock Input Timing
TCK
TMS,TDI
TDO
J85
J86
J87
J88
J89
Figure 36. JTAG Test Access Port Timing Diagram
MOTOROLA
MPC862FamilyHardwareSpecifications
39
CPM Electrical CharacteristicsPIP/PIO AC Electrical Specifications
TCK
J91
J90
TRST
Figure 37. JTAG TRST Timing Diagram
TCK
J92
J93
J94
Output
Signals
Output
Signals
J95
J96
Output
Signals
Figure 38. Boundary Scan (JTAG) Timing Diagram
Part XI CPM Electrical Characteristics
This section provides the AC and DC electrical specifications for the communications processor module
(CPM) of the MPC862.
11.1 PIP/PIO AC Electrical Specifications
Table 13 provides the PIP/PIO AC timings as shown in Figure 39 to Figure 43.
Table 13. PIP/PIO Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
21 Data-in setup time to STBI low
22 Data-In hold time to STBI high
23 STBI pulse width
0
—
ns
2.5 – t3 1
—
—
—
—
—
clk
clk
ns
1.5
24 STBO pulse width
1 clk – 5ns
25 Data-out setup time to STBO low
26 Data-out hold time from STBO high
2
5
clk
clk
40
MPC862FamilyHardwareSpecifications
MOTOROLA
CPM Electrical CharacteristicsPIP/PIO AC Electrical Specifications
Table 13. PIP/PIO Timing (Continued)
All Frequencies
Num
Characteristic
Unit
Min
Max
27 STBI low to STBO low (Rx interlock)
28 STBI low to STBO high (Tx interlock)
29 Data-in setup time to clock high
—
2
2
clk
—
—
—
25
clk
ns
ns
ns
15
7.5
—
30 Data-in hold time from clock high
31 Clock low to data-out valid (CPU writes data, control, or direction)
t3 = Specification 23
1
DATA-IN
21
22
23
STBI
27
24
STBO
Figure 39. PIP Rx (Interlock Mode) Timing Diagram
DATA-OUT
25
26
24
STBO
(Output)
28
23
STBI
(Input)
Figure 40. PIP Tx (Interlock Mode) Timing Diagram
MOTOROLA
MPC862FamilyHardwareSpecifications
41
CPM Electrical CharacteristicsPIP/PIO AC Electrical Specifications
DATA-IN
21
22
23
STBI
(Input)
24
STBO
(Output)
Figure 41. PIP Rx (Pulse Mode) Timing Diagram
DATA-OUT
25
26
24
23
STBO
(Output)
STBI
(Input)
Figure 42. PIP TX (Pulse Mode) Timing Diagram
CLKO
DATA-IN
29
30
31
DATA-OUT
Figure 43. Parallel I/O Data-In/Data-Out Timing Diagram
42
MPC862FamilyHardwareSpecifications
MOTOROLA
CPM Electrical CharacteristicsPort C Interrupt AC Electrical Specifications
11.2 Port C Interrupt AC Electrical Specifications
Table 14 provides the timings for port C interrupts.
Table 14. Port C Interrupt Timing
33.34 MHz
Num
Characteristic
Unit
Min
Max
35
36
Port C interrupt pulse width low (edge-triggered mode)
Port C interrupt minimum time between active edges
55
55
—
—
ns
ns
Figure 44 shows the port C interrupt detection timing.
36
Port C
(Input)
35
Figure 44. Port C Interrupt Detection Timing
11.3 IDMA Controller AC Electrical Specifications
Table 15 provides the IDMA controller timings as shown in Figure 45 to Figure 48.
Table 15. IDMA Controller Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
40
DREQ setup time to clock high
7
—
—
12
12
20
15
—
ns
ns
ns
ns
ns
ns
ns
41
42
43
44
45
46
DREQ hold time from clock high
3
SDACK assertion delay from clock high
SDACK negation delay from clock low
—
—
—
—
7
SDACK negation delay from TA low
SDACK negation delay from clock high
TA assertion to falling edge of the clock setup time (applies to external TA)
MOTOROLA
MPC862FamilyHardwareSpecifications
43
CPM Electrical CharacteristicsIDMA Controller AC Electrical Specifications
CLKO
(Output)
41
40
DREQ
(Input)
Figure 45. IDMA External Requests Timing Diagram
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
43
DATA
46
TA
(Input)
SDACK
Figure 46. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA
44
MPC862FamilyHardwareSpecifications
MOTOROLA
CPM Electrical CharacteristicsIDMA Controller AC Electrical Specifications
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
44
DATA
TA
(Output)
SDACK
Figure 47. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
45
DATA
TA
(Output)
SDACK
Figure 48. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA
MOTOROLA
MPC862FamilyHardwareSpecifications
45
CPM Electrical CharacteristicsBaud Rate Generator AC Electrical Specifications
11.4 Baud Rate Generator AC Electrical Specifications
Table 16 provides the baud rate generator timings as shown in Figure 49.
Table 16. Baud Rate Generator Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
10
50
BRGO rise and fall time
—
40
40
ns
51
52
BRGO duty cycle
BRGO cycle
60
—
%
ns
50
50
BRGOX
51
51
52
Figure 49. Baud Rate Generator Timing Diagram
11.5 Timer AC Electrical Specifications
Table 17 provides the general-purpose timer timings as shown in Figure 50.
Table 17. Timer Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
61
TIN/TGATE rise and fall time
TIN/TGATE low time
10
1
—
ns
clk
clk
clk
ns
62
63
64
65
—
—
—
25
TIN/TGATE high time
TIN/TGATE cycle time
CLKO low to TOUT valid
2
3
3
46
MPC862FamilyHardwareSpecifications
MOTOROLA
CPM Electrical CharacteristicsSerial Interface AC Electrical Specifications
CLKO
60
61
63
62
TIN/TGATE
(Input)
61
64
65
TOUT
(Output)
Figure 50. CPM General-Purpose Timers Timing Diagram
11.6 Serial Interface AC Electrical Specifications
Table 18 provides the serial interface timings as shown in Figure 51 to Figure 55.
Table 18. SI Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
70
L1RCLK, L1TCLK frequency (DSC = 0) 1, 2
L1RCLK, L1TCLK width low (DSC = 0) 2
—
SYNCCLK/2.5
MHz
71
P + 10
P + 10
—
—
ns
ns
ns
ns
3
71a
72
L1RCLK, L1TCLK width high (DSC = 0)
—
L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time
15.00
—
73
L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC 20.00
setup time)
74
L1CLK edge to L1RSYNC, L1TSYNC, invalid
(SYNC hold time)
35.00
—
ns
75
L1RSYNC, L1TSYNC rise/fall time
—
15.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
76
L1RXD valid to L1CLK edge (L1RXD setup time)
17.00
—
77
L1CLK edge to L1RXD invalid (L1RXD hold time) 13.00
—
4
78
L1CLK edge to L1ST(1–4) valid
10.00
10.00
10.00
10.00
10.00
0.00
45.00
78A
79
L1SYNC valid to L1ST(1–4) valid
L1CLK edge to L1ST(1–4) invalid
L1CLK edge to L1TXD valid
45.00
45.00
80
55.00
80A
81
L1TSYNC valid to L1TXD valid 4
L1CLK edge to L1TXD high impedance
L1RCLK, L1TCLK frequency (DSC =1)
L1RCLK, L1TCLK width low (DSC =1)
L1RCLK, L1TCLK width high (DSC = 1)3
55.00
42.00
82
—
16.00 or SYNCCLK/2
83
P + 10
P + 10
—
—
83a
MOTOROLA
MPC862FamilyHardwareSpecifications
47
CPM Electrical CharacteristicsSerial Interface AC Electrical Specifications
Table 18. SI Timing (Continued)
All Frequencies
Max
Num
Characteristic
Unit
Min
84
L1CLK edge to L1CLKO valid (DSC = 1)
L1RQ valid before falling edge of L1TSYNC4
L1GR setup time2
—
30.00
—
ns
85
86
87
88
1.00
42.00
42.00
—
L1TCLK
—
ns
ns
ns
L1GR hold time
—
L1CLK edge to L1SYNC valid (FSD = 00) CNT =
0000, BYT = 0, DSC = 0)
0.00
1
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
2
3
4
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
L1RCLK
(FE=0, CE=0)
(Input)
71
70
71a
72
L1RCLK
(FE=1, CE=1)
(Input)
RFSD=1
75
74
L1RSYNC
(Input)
73
77
L1RXD
(Input)
BIT0
76
78
79
L1ST(4-1)
(Output)
Figure 51. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
48
MPC862FamilyHardwareSpecifications
MOTOROLA
CPM Electrical CharacteristicsSerial Interface AC Electrical Specifications
L1RCLK
(FE=1, CE=1)
(Input)
72
83a
82
L1RCLK
(FE=0, CE=0)
(Input)
RFSD=1
75
L1RSYNC
(Input)
73
74
77
L1RXD
(Input)
BIT0
76
78
79
L1ST(4-1)
(Output)
84
L1CLKO
(Output)
Figure 52. SI Receive Timing with Double-Speed Clocking (DSC = 1)
MOTOROLA
MPC862FamilyHardwareSpecifications
49
CPM Electrical CharacteristicsSerial Interface AC Electrical Specifications
L1TCLK
(FE=0, CE=0)
(Input)
71
70
72
L1TCLK
(FE=1, CE=1)
(Input)
73
TFSD=0
75
74
L1TSYNC
(Input)
80a
BIT0
80
81
L1TXD
(Output)
79
78
L1ST(4-1)
(Output)
Figure 53. SI Transmit Timing Diagram (DSC = 0)
50
MPC862FamilyHardwareSpecifications
MOTOROLA
CPM Electrical CharacteristicsSerial Interface AC Electrical Specifications
L1RCLK
(FE=0, CE=0)
(Input)
72
83a
82
L1RCLK
(FE=1, CE=1)
(Input)
TFSD=0
75
L1RSYNC
(Input)
73
74
81
L1TXD
(Output)
BIT0
80
78a
79
L1ST(4-1)
(Output)
78
84
L1CLKO
(Output)
Figure 54. SI Transmit Timing with Double Speed Clocking (DSC = 1)
MOTOROLA
MPC862FamilyHardwareSpecifications
51
CPM Electrical CharacteristicsSerial Interface AC Electrical Specifications
Figure 55. IDL Timing
52
MPC862FamilyHardwareSpecifications
MOTOROLA
CPM Electrical CharacteristicsSCC in NMSI Mode Electrical Specifications
11.7 SCC in NMSI Mode Electrical Specifications
Table 19 provides the NMSI external clock timing.
Table 19. NMSI External Clock Timing
All Frequencies
Num
Characteristic
RCLK1 and TCLK1 width high 1
Unit
Min
Max
100
101
102
103
104
105
106
107
108
1/SYNCCLK
—
ns
ns
RCLK1 and TCLK1 width low
1/SYNCCLK +5
—
RCLK1 and TCLK1 rise/fall time
—
15.00 ns
50.00 ns
50.00 ns
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
RXD1 hold time from RCLK1 rising edge 2
CD1 setup Time to RCLK1 rising edge
0.00
0.00
5.00
5.00
5.00
5.00
—
—
—
—
ns
ns
ns
ns
1
2
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.
Also applies to CD and CTS hold time when they are used as an external sync signal.
Table 20 provides the NMSI internal clock timing.
Table 20. NMSI Internal Clock Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
100
RCLK1 and TCLK1 frequency 1
0.00
—
SYNCCLK/3 MHz
102
103
104
105
106
107
108
RCLK1 and TCLK1 rise/fall time
—
ns
ns
ns
ns
ns
ns
ns
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
RXD1 hold time from RCLK1 rising edge 2
CD1 setup time to RCLK1 rising edge
0.00
0.00
40.00
40.00
0.00
40.00
30.00
30.00
—
—
—
—
1
2
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1.
Also applies to CD and CTS hold time when they are used as an external sync signals.
Figure 56 through Figure 58 show the NMSI timings.
MOTOROLA
MPC862FamilyHardwareSpecifications
53
CPM Electrical CharacteristicsSCC in NMSI Mode Electrical Specifications
RCLK1
102
102
101
106
100
RxD1
(Input)
107
108
CD1
(Input)
107
CD1
(SYNC Input)
Figure 56. SCC NMSI Receive Timing Diagram
TCLK1
102
102
101
100
TxD1
(Output)
103
105
RTS1
(Output)
104
104
CTS1
(Input)
107
CTS1
(SYNC Input)
Figure 57. SCC NMSI Transmit Timing Diagram
54
MPC862FamilyHardwareSpecifications
MOTOROLA
CPM Electrical CharacteristicsEthernet Electrical Specifications
TCLK1
102
102
101
100
TxD1
(Output)
103
RTS1
(Output)
104
107
104
105
CTS1
(Echo Input)
Figure 58. HDLC Bus Timing Diagram
11.8 Ethernet Electrical Specifications
Table 21 provides the Ethernet timings as shown in Figure 59 to Figure 63.
Table 21. Ethernet Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
120
CLSN width high
RCLK1 rise/fall time
RCLK1 width low
RCLK1 clock period 1
RXD1 setup time
RXD1 hold time
40
—
40
80
20
5
—
15
—
ns
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
120
—
—
RENA active delay (from RCLK1 rising edge of the last data bit) 10
—
RENA width low
100
—
TCLK1 rise/fall time
—
40
99
10
10
10
10
10
15
—
TCLK1 width low
TCLK1 clock period1
101
50
50
50
50
50
TXD1 active delay (from TCLK1 rising edge)
TXD1 inactive delay (from TCLK1 rising edge)
TENA active delay (from TCLK1 rising edge)
TENA inactive delay (from TCLK1 rising edge)
RSTRT active delay (from TCLK1 falling edge)
MOTOROLA
MPC862FamilyHardwareSpecifications
55
CPM Electrical CharacteristicsEthernet Electrical Specifications
Table 21. Ethernet Timing (Continued)
All Frequencies
Min Max
Num
Characteristic
Unit
136
RSTRT inactive delay (from TCLK1 falling edge)
REJECT width low
10
1
50
—
20
20
ns
137
138
139
CLK
ns
CLKO1 low to SDACK asserted 2
CLKO1 low to SDACK negated 2
—
—
ns
1
2
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2/1.
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
CLSN(CTS1)
(Input)
120
Figure 59. Ethernet Collision Timing Diagram
RCLK1
121
121
124
123
Last Bit
RxD1
(Input)
125
126
127
RENA(CD1)
(Input)
Figure 60. Ethernet Receive Timing Diagram
56
MPC862FamilyHardwareSpecifications
MOTOROLA
CPM Electrical CharacteristicsSMC Transparent AC Electrical Specifications
TCLK1
128
128
129
131
121
TxD1
(Output)
132
133
134
TENA(RTS1)
(Input)
RENA(CD1)
(Input)
(NOTE 2)
NOTES:
1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
Figure 61. Ethernet Transmit Timing Diagram
RCLK1
RxD1
(Input)
0
1
1
BIT1
125
BIT2
136
Start Frame Delimiter
RSTRT
(Output)
Figure 62. CAM Interface Receive Start Timing Diagram
REJECT
137
Figure 63. CAM Interface REJECT Timing Diagram
11.9 SMC Transparent AC Electrical Specifications
Table 22 provides the SMC transparent timings as shown in Figure 64.
MOTOROLA
MPC862FamilyHardwareSpecifications
57
CPM Electrical CharacteristicsSPI Master AC Electrical Specifications
Table 22. SMC Transparent Timing
All Frequencies
Num
Characteristic
SMCLK clock period 1
Unit
Min
100
Max
150
—
ns
151
151A
152
153
154
155
SMCLK width low
50
50
—
10
20
5
—
—
15
50
—
—
ns
ns
ns
ns
ns
ns
SMCLK width high
SMCLK rise/fall time
SMTXD active delay (from SMCLK falling edge)
SMRXD/SMSYNC setup time
RXD1/SMSYNC hold time
1
SyncCLK must be at least twice as fast as SMCLK.
SMCLK
152
152
151
151A
150
SMTXD
(Output)
NOTE 1
154
153
155
SMSYNC
154
155
SMRXD
(Input)
NOTE:
1. This delay is equal to an integer number of character-length clocks.
Figure 64. SMC Transparent Timing Diagram
11.10SPI Master AC Electrical Specifications
Table 23 provides the SPI master timings as shown in Figure 65 and Figure 66.
58
MPC862FamilyHardwareSpecifications
MOTOROLA
CPM Electrical CharacteristicsSPI Master AC Electrical Specifications
Table 23. SPI Master Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
1024
160
MASTER cycle time
4
tcyc
161
162
163
164
165
166
167
MASTER clock (SCK) high or low time
MASTER data setup time (inputs)
Master data hold time (inputs)
Master data valid (after SCK edge)
Master data hold time (outputs)
Rise time output
2
512
—
tcyc
ns
ns
ns
ns
ns
ns
50
0
—
—
0
20
—
—
—
15
15
Fall time output
SPICLK
(CI=0)
(Output)
161
167
166
167
161
160
SPICLK
(CI=1)
(Output)
163
162
166
SPIMISO
(Input)
msb
167
Data
165
lsb
msb
164
166
SPIMOSI
(Output)
msb
Data
lsb
msb
Figure 65. SPI Master (CP = 0) Timing Diagram
MOTOROLA
MPC862FamilyHardwareSpecifications
59
CPM Electrical CharacteristicsSPI Slave AC Electrical Specifications
SPICLK
(CI=0)
(Output)
161
167
166
166
167
161
160
SPICLK
(CI=1)
(Output)
163
162
SPIMISO
(Input)
msb
167
Data
165
lsb
msb
164
166
SPIMOSI
(Output)
msb
Data
lsb
msb
Figure 66. SPI Master (CP = 1) Timing Diagram
11.11SPI Slave AC Electrical Specifications
Table 24 provides the SPI slave timings as shown in Figure 67 and Figure 68.
Table 24. SPI Slave Timing
All Frequencies
Min Max
Num
Characteristic
Unit
170
Slave cycle time
2
—
tcyc
171
172
173
174
175
176
177
Slave enable lead time
Slave enable lag time
15
15
1
—
—
—
—
—
—
50
ns
ns
Slave clock (SPICLK) high or low time
Slave sequential transfer delay (does not require deselect)
Slave data setup time (inputs)
tcyc
tcyc
ns
1
20
20
—
Slave data hold time (inputs)
ns
Slave access time
ns
60
MPC862FamilyHardwareSpecifications
MOTOROLA
CPM Electrical CharacteristicsSPI Slave AC Electrical Specifications
SPISEL
(Input)
172
171
174
SPICLK
(CI=0)
(Input)
173
182
181
173
170
SPICLK
(CI=1)
(Input)
177
181
182
180
178
Undef
SPIMISO
(Output)
msb
176
Data
lsb
msb
msb
175
179
181 182
lsb
SPIMOSI
(Input)
msb
Data
Figure 67. SPI Slave (CP = 0) Timing Diagram
SPISEL
(Input)
172
174
171
170
SPICLK
(CI=0)
(Input)
173
182
181
182
173
181
SPICLK
(CI=1)
(Input)
177
180
178
SPIMISO
(Output)
msb
msb
msb
Undef
175
Data
lsb
179
176
msb
181 182
Data
SPIMOSI
(Input)
lsb
Figure 68. SPI Slave (CP = 1) Timing Diagram
MPC862FamilyHardwareSpecifications
MOTOROLA
61
CPM Electrical CharacteristicsI2C AC Electrical Specifications
2
11.12I C AC Electrical Specifications
2
Table 25 provides the I C (SCL < 100 KHz) timings.
2
Table 25. I C Timing (SCL < 100 KHZ)
All Frequencies
Num
200
Characteristic
SCL clock frequency (slave)
Unit
KHz
Min
Max
100
0
200
202
203
204
205
206
207
208
209
210
211
SCL clock frequency (master) 1
Bus free time between transmissions
Low period of SCL
1.5
4.7
4.7
4.0
4.7
4.0
0
100
—
—
—
—
—
—
—
1
KHz
ms
ms
ms
ms
ms
ms
ns
ms
ns
ms
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
250
—
SDL/SCL rise time
SDL/SCL fall time
—
300
—
Stop condition setup time
4.7
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
2
Table 26 provides the I C (SCL > 100 KHz) timings.
2
Table 26. . I C Timing (SCL > 100 KHZ)
All Frequencies
Num
Characteristic
Expression
Unit
Min
Max
200
SCL clock frequency (slave)
SCL clock frequency (master) 1
Bus free time between transmissions
Low period of SCL
fSCL
fSCL
—
0
BRGCLK/48
Hz
200
202
203
204
205
206
207
208
209
210
211
BRGCLK/16512
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
0
BRGCLK/48
Hz
s
—
—
—
s
High period of SCL
—
—
s
Start condition setup time
Start condition hold time
Data hold time
—
—
s
—
—
s
—
—
s
Data setup time
—
1/(40 * fSCL)
—
—
s
SDL/SCL rise time
—
1/(10 * fSCL)
1/(33 * fSCL)
—
s
SDL/SCL fall time
—
—
s
Stop condition setup time
—
1/2(2.2 * fSCL)
s
1
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
62
MPC862FamilyHardwareSpecifications
MOTOROLA
UTOPIA AC Electrical SpecificationsI2C AC Electrical Specifications
2
Figure 69 shows the I C bus timing.
SDA
202
203
204
208
205
207
SCL
206
209
210
211
2
Figure 69. I C Bus Timing Diagram
Part XII UTOPIA AC Electrical Specifications
Table 27 shows the AC electrical specifications for the UTOPIA interface.
Table 27. UTOPIA AC Electrical Specifications
Num
Signal Characteristic
Direction
Min
Max
Unit
U1
UtpClk rise/fall time (Internal clock option)
Duty cycle
Output
4ns
50
ns
%
50
Frequency
50
Mhz
ns
U1a
UtpClk rise/fall time (external clock option)
Duty cycle
Input
4ns
60
40
%
Frequency
50
Mhz
ns
U2
U3
U4
U5
RxEnb and TxEnb active delay
UTPB, SOC, Rxclav and Txclav setup time
UTPB, SOC, Rxclav and Txclav hold time
Output
Input
2ns
4ns
1ns
2ns
16ns
ns
Input
ns
UTPB, SOC active delay (and PHREQ and PHSEL active
delay in MPHY mode)
Output
16ns
ns
Figure 70 shows signal timings during UTOPIA receive operations.
MOTOROLA
MPC862FamilyHardwareSpecifications
63
FEC Electrical CharacteristicsI2C AC Electrical Specifications
U1
U1
UtpClk
U5
PHREQn
U3
U4
RxClav
RxEnb
HighZ at MPHY
HighZ at MPHY
U2
UTPB
SOC
U3
U4
Figure 70. UTOPIA Receive Timing
Figure 71 shows signal timings during UTOPIA transmit operations.
U1
U1
UtpClk
U5
PHSELn
TxClav
U3
U4
HighZ at MPHY
HighZ at MPHY
U2
TxEnb
UTPB
SOC
U5
Figure 71. UTOPIA Transmit Timing
Part XIII FEC Electrical Characteristics
This section provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the
timing specifications for the MII signals are independent of system clock frequency (part speed
designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or
3.3 V.
64
MPC862FamilyHardwareSpecifications
MOTOROLA
FEC Electrical CharacteristicsMII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER,
13.1 MII Receive Signal Timing (MII_RXD[3:0],
MII_RX_DV, MII_RX_ER, MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_RX_CLK frequency - 1%.
Table 28 provides information on the MII receive signal timing.
Table 28. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
M2
M3
M4
MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
MII_RX_CLK pulse width high
5
5
—
—
ns
ns
35%
35%
65%
65%
MII_RX_CLK period
MII_RX_CLK period
MII_RX_CLK pulse width low
Figure 72 shows MII receive signal timing.
M3
MII_RX_CLK (input)
M4
MII_RXD[3:0] (inputs)
MII_RX_DV
MII_RX_ER
M1
M2
Figure 72. MII Receive Signal Timing Diagram
13.2 MII Transmit Signal Timing (MII_TXD[3:0],
MII_TX_EN, MII_TX_ER, MII_TX_CLK)
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency - 1%.
Table 29 provides information on the MII transmit signal timing,.
MOTOROLA
MPC862FamilyHardwareSpecifications
65
FEC Electrical CharacteristicsMII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 29. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
M6
M7
M8
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid 5
—
ns
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
MII_TX_CLK pulse width high
—
25
35%
35%
65%
65%
MII_TX_CLK period
MII_TX_CLK period
MII_TX_CLK pulse width low
Figure 73 shows the MII transmit signal timing diagram.
M7
MII_TX_CLK (input)
M5
M8
MII_TXD[3:0] (outputs)
MII_TX_EN
MII_TX_ER
M6
Figure 73. MII Transmit Signal Timing Diagram
13.3 MII Async Inputs Signal Timing (MII_CRS,
MII_COL)
Table 30 provides information on the MII async inputs signal timing.
Table 30. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
MII_CRS, MII_COL minimum pulse width
1.5
—
MII_TX_CLK period
Figure 74 shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 74. MII Async Inputs Timing Diagram
MPC862FamilyHardwareSpecifications
66
MOTOROLA
FEC Electrical CharacteristicsMII Serial Management Channel Timing (MII_MDIO, MII_MDC)
13.4 MII Serial Management Channel Timing
(MII_MDIO, MII_MDC)
Table 31 provides information on the MII serial management channel signal timing. The FEC functions
correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under
investigation.
Table 31. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10
MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11
M12
M13
M14
M15
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
MII_MDIO (input) to MII_MDC rising edge setup
MII_MDIO (input) to MII_MDC rising edge hold
MII_MDC pulse width high
—
25
ns
ns
ns
10
—
0
—
40%
40%
60%
60%
MII_MDC period
MII_MDC period
MII_MDC pulse width low
Figure 75 shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (output)
MII_MDIO (output)
M10
M11
MII_MDIO (input)
M12
M13
Figure 75. MII Serial Management Channel Timing Diagram
MOTOROLA
MPC862FamilyHardwareSpecifications
67
Mechanical Data and Ordering InformationMII Serial Management Channel Timing (MII_MDIO,
Part XIV Mechanical Data and Ordering
Information
Table 32 provides information on the MPC862 derivative devices.
Table 32. MPC862 Derivatives
Number
of
Cache Size
Instruction
Ethernet
Support
Multi-Channel
HDLC Support
Device
ATM Support
SCCs 1
Data
MPC862DT
MPC862DP
MPC862SR
MPC862T
Two
10/100 Mbps
10/100 Mbps
10 Mbps
Yes
Yes
4 Kbyte
16 Kbyte
4 Kbyte
4 Kbyte
16 Kbyte
4 Kbyte
8 Kbyte
4 Kbyte
4 Kbyte
8 Kbyte
Four
10/100 Mbps
10/100 Mbps
MPC862P
1
Serial communications controller (SCC)
Table 33 identifies the packages and operating frequencies available for the MPC862 derivative devices.
Table 33. MPC862 Package/Frequency Availability
Package Type
Ball grid array
Temperature (Tj)
Frequency (MHz)
Order Number
0°C to 95°C
50
XPC862DTZP50
XPC862SRZP50
XPC862TZP50
(ZP suffix)
66
80
50
66
XPC862DTZP66
XPC862SRZP66
XPC862TZP66
XPC862DTZP80
XPC862SRZP80
XPC862TZP80
Ball grid array
(CZP suffix)
-40°C to 95°C
XPC862DTCZP50
XPC862SRCZP50
XPC862TCZP50
XPC862DTCZP66
XPC862SRCZP66
XPC862TCZP66
Table 34 identifies the packages and operating frequencies available for the MPC862P.
Table 34. MPC862P Package/Frequency Availability
Package Type
Temperature (Tj)
Frequency (MHz)
Order Number
68
MPC862FamilyHardwareSpecifications
MOTOROLA
Mechanical Data and Ordering InformationPin Assignments
Table 34. MPC862P Package/Frequency Availability (Continued)
Ball grid array
(ZP suffix)
0°C to 95°C
50
66
80
50
66
XPC862DPZP50
XPC862PZP50
XPC862DPZP66
XPC862PZP66
XPC862DPZP80
XPC862PZP80
Ball grid array
(CZP suffix)
-40°C to 95°C
XPC862DPCZP50
XPC862PCZP50
XPC862DPCZP66
XPC862PCZP66
14.1 Pin Assignments
Figure 76 shows the top view pinout of the PBGA package. For additional information, see the MPC862
PowerQUICC User s Manual.
MOTOROLA
MPC862FamilyHardwareSpecifications
69
Mechanical Data and Ordering InformationPin Assignments
NOTE: This is the top view of the device.
W
V
U
T
PD10 PD8
PD14 PD13 PD9
PA0 PB14 PD15
PD3
IRQ7 D0
D4
D1
D2
D10
D11
D9
D3
D5
VDDL
D20
D6
D7
D29
DP1
DP2 CLKOUT IPA3
VSSSYN1
N/C
PD6 M_Tx_EN IRQ0 D13
D27
D23
D17
D14
D16
D15
D18
D19
D22
D24
D26
D31
D28
D30
DP3
DP0
PD4
PD5 IRQ1
D8
D21
IPA5 IPA4 IPA2
N/C VSSSYN
PA1
PC6
PC5 PC4 PD11
PA2 PB15 PD12
PD7 VDDH D12
VDDH
D25
IPA6 IPA0 IPA1 IPA7 XFC VDDSYN
R
VDDH
WAIT_B WAIT_A
VDDLRSTCONF
KAPWR
PORESET
SRESET
P
N
M
L
PA4 PB17 PA3 VDDL
PB19 PA5 PB18 PB16
GND
GND
XTAL
TEXP
HRESET
EXTCLK EXTAL
PA7
PC8
PA6
PC7
BADDR28
AS
MODCK2
OP0
BADDR29 VDDL
OP1 MODCK1
PB22 PC9
PA8 PB20
K
J
PC10 PA9 PB23 PB21
PC11 PB24 PA10 PB25
GND
BADDR30 IPB6 ALEA IRQ4
IPB5 IPB1 IPB2 ALEB
M_COL IRQ2 IPB0 IPB7
H
G
F
VDDL M_MDIO TDI
TCK
TRST TMS TDO PA11
PB26 PC12 PA12 VDDL
PB27 PC13 PA13 PB29
PB28 PC14 PA14 PC15
BR
VDDL
CS3
IRQ6 IPB4 IPB3
GND
GND
TS
BI
IRQ3 BURST
VDDH
VDDH
CS6
E
D
C
B
A
BG
BB
A8
A9
N/C
A12
A13
N/C
A16
A17
A15
A20
A21
A19
A24
A23
A25
A18 BSA0 GPLA0 N/C
CS2 GPLA5 BDIP TEA
PB30 PA15 PB31
A3
A6
A26 TSIZ1 BSA1 WE0 GPLA1 GPLA3 CS7
CS0
TA GPLA4
A0
19
A1
A4
A10
A22 TSIZ0 BSA3 M_CRS WE2 GPLA2 CS5 CE1A WR GPLB4
A2
18
A5
17
A7
16
A11
15
A14
14
A27
13
A29
12
A30
11
A28
10
A31 VDDL BSA2 WE1 WE3 CS4 CE2A CS1
9
8
7
6
5
4
3
2
1
Figure 76. Pinout of the PBGA Package
Table 35 contains a list of the MPC862 input and output signals and shows multiplexing and pin
assignments.
70
MPC862FamilyHardwareSpecifications
MOTOROLA
Mechanical Data and Ordering InformationPin Assignments
Table 35. Pin Assignments
Name
Pin Number
Type
A[0:31]
B19, B18, A18, C16, B17, A17, B16, A16, D15, C15, B15, A15, C14, Bidirectional
B14, A14, D12, C13, B13, D9, D11, C12, B12, B10, B11, C11, D10, Three-state
C10, A13, A10, A12, A11, A9
TSIZ0
REG
B9
C9
B2
F1
D2
F3
C2
Bidirectional
Three-state
TSIZ1
RD/WR
BURST
BDIP
Bidirectional
Three-state
Bidirectional
Three-state
Bidirectional
Three-state
Output
GPL_B5
TS
Bidirectional
Active Pull-up
TA
Bidirectional
Active Pull-up
TEA
BI
D1
E3
Open-drain
Bidirectional
Active Pull-up
IRQ2
RSV
H3
K1
Bidirectional
Three-state
IRQ4
KR
Bidirectional
Three-state
RETRY
SPKROUT
CR
F2
Input
IRQ3
D[0:31]
W14, W12, W11, W10, W13, W9, W7, W6, U13, T11, V11, U11, T13, Bidirectional
V13, V10, T10, U10, T12, V9, U9, V8, U8, T9, U12, V7, T8, U7, V12, Three-state
V6, W5, U6, T7
DP0
IRQ3
V3
V5
W4
V4
Bidirectional
Three-state
DP1
IRQ4
Bidirectional
Three-state
DP2
IRQ5
Bidirectional
Three-state
DP3
IRQ6
Bidirectional
Three-state
BR
BG
BB
G4
E2
E1
Bidirectional
Bidirectional
Bidirectional
Active Pull-up
MOTOROLA
MPC862FamilyHardwareSpecifications
71
Mechanical Data and Ordering InformationPin Assignments
Table 35. Pin Assignments (Continued)
Name
Pin Number
Type
Bidirectional
FRZ
IRQ6
G3
IRQ0
IRQ1
V14
U14
W15
Input
Input
Input
M_TX_CLK
IRQ7
CS[0:5]
C3, A2, D4, E4, A4, B4
D5
Output
Output
CS6
CE1_B
CS7
CE2_B
C4
C7
Output
Output
WE0
BS_B0
IORD
WE1
BS_B1
IOWR
A6
B6
A5
Output
Output
Output
WE2
BS_B2
PCOE
WE3
BS_B3
PCWE
BS_A[0:3]
D8, C8, A7, B8
D7
Output
Output
GPL_A0
GPL_B0
OE
GPL_A1
GPL_B1
C6
Output
Output
GPL_A[2:3]
GPL_B[2:3]
CS[2–3]
B5, C5
UPWAITA
GPL_A4
C1
B1
Bidirectional
Bidirectional
UPWAITB
GPL_B4
GPL_A5
PORESET
RSTCONF
HRESET
SRESET
XTAL
D3
R2
P3
N4
P2
P1
Output
Input
Input
Open-drain
Open-drain
Analog Output
72
MPC862FamilyHardwareSpecifications
MOTOROLA
Mechanical Data and Ordering InformationPin Assignments
Table 35. Pin Assignments (Continued)
Name
Pin Number
Type
EXTAL
XFC
N1
T2
Analog Input (3.3V only)
Analog Input
Output
CLKOUT
EXTCLK
TEXP
W3
N2
N3
K2
Input (3.3V only)
Output
ALE_A
Output
MII-TXD1
CE1_A
MII-TXD2
B3
A3
R3
Output
Output
Input
CE2_A
MII-TXD3
WAIT_A
SOC_Split2
WAIT_B
R4
T5
Input
Input
IP_A0
UTPB_Split02
MII-RXD3
IP_A1
T4
U3
Input
Input
UTPB_Split12
MII-RXD2
IP_A2
IOIS16_A
UTPB_Split22
MII-RXD1
IP_A3
W2
U4
U5
T6
T3
Input
Input
Input
Input
Input
UTPB_Split32
MII-RXD0
IP_A4
UTPB_Split42
MII-RXCLK
IP_A5
UTPB_Split52
MII-RXERR
IP_A6
UTPB_Split62
MII-TXERR
IP_A7
UTPB_Split72
MII-RXDV
ALE_B
DSCK/AT1
J1
Bidirectional
Three-state
IP_B[0:1]
IWP[0:1]
VFLS[0:1]
H2, J3
Bidirectional
MOTOROLA
MPC862FamilyHardwareSpecifications
73
Mechanical Data and Ordering InformationPin Assignments
Table 35. Pin Assignments (Continued)
Name
Pin Number
Type
Bidirectional
IP_B2
J2
IOIS16_B
AT2
Three-state
IP_B3
IWP2
VF2
G1
G2
J4
Bidirectional
IP_B4
LWP0
VF0
Bidirectional
Bidirectional
IP_B5
LWP1
VF1
IP_B6
DSDI
AT0
K3
H1
L4
Bidirectional
Three-state
IP_B7
PTR
AT3
Bidirectional
Three-state
OP0
Bidirectional
MII-TXD0
UtpClk_Split2
OP1
L2
L1
Output
OP2
Bidirectional
MODCK1
STS
OP3
MODCK2
DSDO
M4
K4
Bidirectional
Output
BADDR30
REG
BADDR[28:29]
AS
M3, M2
L3
Output
Input
PA15
RXD1
RXD4
C18
Bidirectional
PA14
TXD1
TXD4
D17
Bidirectional
(Optional: Open-drain)
PA13
RXD2
E17
F17
G16
Bidirectional
PA12
TXD2
Bidirectional
(Optional: Open-drain)
PA11
Bidirectional
L1TXDB
RXD3
(Optional: Open-drain)
74
MPC862FamilyHardwareSpecifications
MOTOROLA
Mechanical Data and Ordering InformationPin Assignments
Table 35. Pin Assignments (Continued)
Name
Pin Number
Type
Bidirectional
PA10
J17
L1RXDB
TXD3
(Optional: Open-drain)
PA9
K18
Bidirectional
L1TXDA
(Optional: Open-drain)
RXD4
PA8
L17
Bidirectional
L1RXDA
TXD4
(Optional: Open-drain)
PA7
M19
Bidirectional
CLK1
L1RCLKA
BRGO1
TIN1
PA6
CLK2
TOUT1
M17
N18
Bidirectional
Bidirectional
PA5
CLK3
L1TCLKA
BRGO2
TIN2
PA4
CLK4
TOUT2
P19
P17
Bidirectional
Bidirectional
PA3
CLK5
BRGO3
TIN3
PA2
CLK6
TOUT3
L1RCLKB
R18
T19
U19
Bidirectional
Bidirectional
Bidirectional
PA1
CLK7
BRGO4
TIN4
PA0
CLK8
TOUT4
L1TCLKB
PB31
SPISEL
REJECT1
C17
C19
Bidirectional
(Optional: Open-drain)
PB30
Bidirectional
SPICLK
RSTRT2
(Optional: Open-drain)
MOTOROLA
MPC862FamilyHardwareSpecifications
75
Mechanical Data and Ordering InformationPin Assignments
Table 35. Pin Assignments (Continued)
Name
Pin Number
Type
Bidirectional
PB29
E16
D19
SPIMOSI
(Optional: Open-drain)
PB28
Bidirectional
SPIMISO
BRGO4
(Optional: Open-drain)
PB27
I2CSDA
BRGO1
E19
F19
J16
J18
K17
Bidirectional
(Optional: Open-drain)
PB26
I2CSCL
BRGO2
Bidirectional
(Optional: Open-drain)
PB25
Bidirectional
(Optional: Open-drain)
RXADDR32
SMTXD1
PB24
Bidirectional
(Optional: Open-drain)
TXADDR32
SMRXD1
PB23
Bidirectional
(Optional: Open-drain)
TXADDR22
SDACK1
SMSYN1
PB22
L19
K16
Bidirectional
(Optional: Open-drain)
TXADDR42
SDACK2
SMSYN2
PB21
Bidirectional
SMTXD2
L1CLKOB
PHSEL1 1
TXADDR1 2
(Optional: Open-drain)
PB20
L16
Bidirectional
SMRXD2
L1CLKOA
PHSEL01
TXADDR02
(Optional: Open-drain)
PB19
RTS1
L1ST1
N19
N17
Bidirectional
(Optional: Open-drain)
PB18
Bidirectional
(Optional: Open-drain)
RXADDR42
RTS2
L1ST2
PB17
P18
Bidirectional
L1RQb
L1ST3
(Optional: Open-drain)
RTS3
PHREQ11
RXADDR12
76
MPC862FamilyHardwareSpecifications
MOTOROLA
Mechanical Data and Ordering InformationPin Assignments
Table 35. Pin Assignments (Continued)
Name
Pin Number
Type
Bidirectional
PB16
N16
L1RQa
L1ST4
RTS4
(Optional: Open-drain)
PHREQ01
RXADDR02
PB15
BRGO3
TxClav
R17
U18
D16
Bidirectional
Bidirectional
Bidirectional
PB14
RXADDR22
RSTRT1
PC15
DREQ0
RTS1
L1ST1
RxClav
PC14
DREQ1
RTS2
D18
E18
F18
Bidirectional
Bidirectional
Bidirectional
L1ST2
PC13
L1RQb
L1ST3
RTS3
PC12
L1RQa
L1ST4
RTS4
PC11
CTS1
J19
Bidirectional
Bidirectional
PC10
K19
CD1
TGATE1
PC9
CTS2
L18
Bidirectional
Bidirectional
PC8
M18
CD2
TGATE2
PC7
CTS3
L1TSYNCB
SDACK2
M16
R19
Bidirectional
Bidirectional
PC6
CD3
L1RSYNCB
MOTOROLA
MPC862FamilyHardwareSpecifications
77
Mechanical Data and Ordering InformationPin Assignments
Table 35. Pin Assignments (Continued)
Name
Pin Number
Type
Bidirectional
PC5
CTS4
L1TSYNCA
SDACK1
T18
PC4
CD4
L1RSYNCA
T17
U17
Bidirectional
Bidirectional
PD15
L1TSYNCA
MII-RXD3
UTPB0
PD14
V19
V18
R16
T16
W18
V17
W17
T15
V16
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
L1RSYNCA
MII-RXD2
UTPB1
PD13
L1TSYNCB
MII-RXD1
UTPB2
PD12
L1RSYNCB
MII-MDC
UTPB3
PD11
RXD3
MII-TXERR
RXENB
PD10
TXD3
MII-RXD0
TXENB
PD9
RXD4
MII-TXD0
UTPCLK
PD8
TXD4
MII-MDC
MII-RXCLK
PD7
RTS3
MII-RXERR
UTPB4
PD6
RTS4
MII-RXDV
UTPB5
78
MPC862FamilyHardwareSpecifications
MOTOROLA
Mechanical Data and Ordering InformationMechanical Dimensions of the PBGA Package
Table 35. Pin Assignments (Continued)
Name
Pin Number
Type
Bidirectional
PD5
U15
U16
W16
REJECT2
MII-TXD3
UTPB6
PD4
Bidirectional
Bidirectional
REJECT3
MII-TXD2
UTPB7
PD3
REJECT4
MII-TXD1
SOC
TMS
G18
H17
Input
Input
TDI
DSDI
TCK
H16
Input
DSCK
TRST
G19
G17
Input
TDO
Output
DSDO
M_CRS
M_MDIO
M_TXEN
M_COL
KAPWR
GND
B7
Input
H18
V15
H4
Bidirectional
Output
Input
R1
Power
Power
F6, F7, F8, F9, F10, F11, F12, F13, F14, G6, G7, G8, G9, G10,
G11, G12, G13, G14, H6, H7, H8, H9, H10, H11, H12, H13, H14,
J6, J7, J8, J9, J10, J11, J12, J13, J14, K6, K7, K8, K9, K10, K11,
K12, K13, K14, L6, L7, L8, L9, L10, L11, L12, L13, L14, M6, M7, M8,
M9, M10, M11, M12, M13, M14, N6, N7, N8, N9, N10, N11, N12,
N13, N14, P6, P7, P8, P9, P10, P11, P12, P13, P14
VDDL
VDDH
A8, M1, W8, H19, F4, F16, P4, P16
Power
Power
E5, E6, E7, E8, E9, E10, E11, E12, E13, E14, E15, F5, F15, G5,
G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P5,
P15, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, T14
N/C
D6, D13, D14, U2, V2
No-connect
1
2
Classic SAR mode only
ESAR mode only
14.2 Mechanical Dimensions of the PBGA Package
For more information on the printed circuit board layout of the PBGA package, including thermal via design
and suggested pad layout, please refer to Plastic Ball Grid Array Application Note (order number:
MOTOROLA
MPC862FamilyHardwareSpecifications
79
Mechanical Data and Ordering InformationMechanical Dimensions of the PBGA Package
AN1231/D) available from your local Motorola sales office. Figure 77 shows the mechanical dimensions of
the PBGA package.
C
0.2
4X
0.2 C
0.25 C
0.35 C
D
A
E2
E
D2
B
TOP VIEW
A2
A3
A1
A
D1
SIDE VIEW
18X e
NOTES:
W
V
U
T
1. Dimensions and tolerancing per ASME Y14.5M,
1994.
2. Dimensions in millimeters.
R
P
N
M
L
3. Dimensionbisthemaximumsolderballdiameter
measured parallel to datum C.
K
J
E1
H
G
F
MILLIMETERS
E
D
C
B
A
DIM MIN
MAX
2.05
0.70
1.35
0.90
0.90
A
A1
A2
A3
b
---
0.50
0.95
0.70
0.60
1
3
5
7
9
11 13 15 17 19
2
4 6 8 10 12 14 16 18
357X
b
BOTTOM VIEW
M
0.3
C A B
C
D
D1
25.00 BSC
22.86 BSC
M
0.15
D2 22.40
22.60
1.27 BSC
25.00 BSC
22.86 BSC
22.60
e
E
E1
E2 22.40
Case No. 1103-01
Figure 77. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package
80
MPC862FamilyHardwareSpecifications
MOTOROLA
Document Revision HistoryMechanical Dimensions of the PBGA Package
Part XV Document Revision History
Table 36 lists significant changes between revisions of this document.
Table 36. Document Revision History
Revision
Date
Substantive Changes
0
2001
Initial revision
0.1
0.2
9/2001
Change extended temperature from 95 to 105
11/2001
Revised for new template, changed Table 6 B23 max value @ 66Mhz from 2ns to 8ns
MOTOROLA
MPC862FamilyHardwareSpecifications
81
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Motorola reserves the right to make changes without further notice to any products herein. Motorola
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