SN74LS374DW [MOTOROLA]
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT; 八路透明锁存器具有三态输出;八路D型触发器具有三态输出
| 型号： | SN74LS374DW |
| 厂家： | 
MOTOROLA |
| 描述： | OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT |
| 文件： | 总7页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS373
SN54/74LS374
OCTAL TRANSPARENT LATCH
WITH 3-STATE OUTPUTS;
OCTAL D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUT
OCTAL TRANSPARENT LATCH
WITH 3-STATE OUTPUTS;
OCTAL D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUT
The SN54/74LS373 consists of eight latches with 3-state outputs for bus
organized system applications. The flip-flops appear transparent to the data
(data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is
LOW, the data that meets the setup times is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
LOW POWER SCHOTTKY
The SN54/74LS374 is a high-speed, low-power Octal D-type Flip-Flop fea-
turing separate D-type inputs for each flip-flop and 3-state outputs for bus ori-
entedapplications. Abuffered Clock (CP) and Output Enable (OE) is common
to all flip-flops. The SN54/74LS374 is manufactured using advanced Low
Power Schottky technology and is compatible with all Motorola TTL families.
J SUFFIX
CERAMIC
CASE 732-03
20
1
• Eight Latches in a Single Package
• 3-State Outputs for Bus Interfacing
• Hysteresis on Latch Enable
• Edge-Triggered D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• Hysteresis on Clock Input to Improve Noise Margin
• Input Clamp Diodes Limit High Speed Termination Effects
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
PIN NAMES
LOADING (Note a)
20
HIGH
LOW
1
D –D
0
Data Inputs
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
7
LE
Latch Enable (Active HIGH) Input
Clock (Active HIGH going edge) Input
Output Enable (Active LOW) Input
Outputs (Note b)
CP
OE
O –O
0
0.5 U.L.
0.25 U.L.
ORDERING INFORMATION
65 (25) U.L.
15 (7.5) U.L.
7
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
NOTES:
a) 1 TTL Units Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 25 U.L. for Commercial
(74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and
65 U.L. for Commercial (74) Temperature Ranges.
CONNECTION DIAGRAM DIP (TOP VIEW)
SN54/74LS374
SN54/74LS373
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
FAST AND LS TTL DATA
5-521
SN54/74LS373 • SN54/74LS374
TRUTH TABLE
LS373
LS374
D
LE
OE
L
O
D
LE
OE
L
O
n
n
n
n
H
H
H
L
H
H
H
L
X
X
L
L
L
L
L
L
Q
X
X
H
Z*
0
X
H
Z*
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
LOGIC DIAGRAMS
SN54LS/74LS373
SN54LS/74LS374
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
54
74
–55
0
25
25
125
70
°C
A
I
I
54
74
–1.0
–2.6
mA
mA
OH
54
74
12
24
OL
FAST AND LS TTL DATA
5-522
SN54/74LS373 • SN54/74LS374
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.4
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.4
2.4
= MIN, I
OH
= MAX, V = V
IN
CC
IH
OH
or V per Truth Table
IL
3.1
V
V
= V
CC
IL
MIN,
= V or V
IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
I
= 12 mA
= 24 mA
CC
IN
OL
V
OL
Output LOW Voltage
per Truth Table
OL
I
I
Output Off Current HIGH
Output Off Current LOW
20
–20
20
µA
µA
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX, V
= MAX, V
= 2.7 V
= 0.4 V
OZH
OUT
OZL
OUT
µA
= MAX, V = 2.7 V
IN
I
IH
Input HIGH Current
0.1
mA
mA
mA
mA
= MAX, V = 7.0 V
IN
I
I
I
Input LOW Current
–0.4
–130
40
= MAX, V = 0.4 V
IN
IL
Short Circuit Current (Note 1)
Power Supply Current
–30
= MAX
= MAX
OS
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C, V
CC
= 5.0 V)
A
Limits
LS373
Typ
LS374
Typ
Symbol
Parameter
Unit
Test Conditions
Min
Max
Min
35
Max
f
Maximum Clock Frequency
50
MHz
MAX
t
t
Propagation Delay,
Data to Output
12
12
18
18
PLH
PHL
ns
ns
ns
ns
C
R
= 45 pF,
= 667 Ω
L
L
t
t
Clock or Enable
to Output
20
18
30
30
15
19
28
28
PLH
PHL
t
t
15
25
28
36
20
21
28
28
PZH
PZL
Output Enable Time
Output Disable Time
t
t
12
15
20
25
12
15
20
25
PHZ
PLZ
C
= 5.0 pF
L
AC SETUP REQUIREMENTS (T = 25°C, V
CC
= 5.0 V)
A
Limits
LS373
LS374
Symbol
Parameter
Unit
Min
Max
Min
Max
t
t
t
Clock Pulse Width
Setup Time
15
5.0
20
15
20
0
ns
ns
ns
W
s
Hold Time
h
DEFINITION OF TERMS
SETUP TIME (t ) — is defined as the minimum time required
s
HOLD TIME (t ) — is defined as the minimum time following
h
for the correct logic level to be present at the logic input prior to
LEtransitionfromHIGH-to-LOWinordertoberecognizedand
transferred to the outputs.
the LE transition from HIGH-to-LOW that the logic level must
be maintained at the input in order to ensure continued
recognition.
FAST AND LS TTL DATA
5-523
SN54/74LS373
AC WAVEFORMS
Figure 1
Figure 2
Figure 3
AC LOAD CIRCUIT
SWITCH POSITIONS
SYMBOL
SW1
Open
SW2
Closed
Open
t
PZH
t
Closed
Closed
Closed
PZL
PLZ
PHZ
t
Closed
Closed
t
Ω
* Includes Jig and Probe Capacitance.
Figure 4
FAST AND LS TTL DATA
5-524
SN54/74LS374
AC WAVEFORMS
≈
Figure 6
Figure 5
≥
≈
Figure 7
AC LOAD CIRCUIT
SWITCH POSITIONS
SYMBOL
SW1
Open
SW2
t
Closed
Open
PZH
t
Closed
Closed
Closed
PZL
PLZ
PHZ
t
Closed
Closed
t
Ω
* Includes Jig and Probe Capacitance.
Figure 8
FAST AND LS TTL DATA
5-525
Case 751D-03 DW Suffix
20-Pin Plastic
SO-20 (WIDE)
-A-
20
1
11
10
-B-
P
G
R X 45°
C
-T-
M
J
F
°
°
°
°
K
D
Case 732-03 J Suffix
20-Pin Ceramic Dual In-Line
20
11
10
1
B
C
A
L
F
N
K
J
M
H
G
D
°
°
°
°
Case 738-03 N Suffix
20-Pin Plastic
-A-
20
1
11
10
B
C
L
-T-
K
E
N
M
J
G
F
D
°
°
°
°
FAST AND LS TTL DATA
5-526
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andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
SYMBOL
SW1
SW2
Closed
Open
Literature Distribution Centers:
USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
t
Open
PZH
EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan.
t
Closed
PZL
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
t
Closed
Closed
PLZ
◊
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