MTP3N120E [MOTOROLA]
TMOS POWER FET 3.0 AMPERES 1200 VOLTS RDS(on) = 5.0 OHM; TMOS功率场效应晶体管3.0安培1200伏的RDS（on ） = 5.0 OHM
| 型号： | MTP3N120E |
| 厂家： | 
MOTOROLA |
| 描述： | TMOS POWER FET 3.0 AMPERES 1200 VOLTS RDS(on) = 5.0 OHM |
| 文件： | 总8页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MTP3N120E/D
SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
3.0 AMPERES
1200 VOLTS
This advanced high–voltage TMOS E–FET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a drain–to–source diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls, and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
R
= 5.0 OHM
DS(on)
•
Avalanche Energy Capability Specified at Elevated
Temperature
•
•
Low Stored Gate Charge for Efficient Switching
Internal Source–to–Drain Diode Designed to Replace External
Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
D
•
Source–to–Drain Diode Recovery Time Comparable to
Discrete Fast Recovery Diode
G
*
See App. Note AN1327 — Very Wide Input Voltage Range;
Off–line Flyback Switching Power Supply
CASE 221A–06, Style 5
TO–220AB
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
Unit
Drain–Source Voltage
V
1200
Vdc
Vdc
DSS
Drain–Gate Voltage (R
= 1.0 MΩ)
Gate–Source Voltage — Continuous
V
DGR
1200
GS
V
± 20
± 40
Vdc
Vpk
GS
Gate–Source Voltage — Non–Repetitive (t ≤ 50 ms)
V
GSM
p
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
I
I
3.0
2.2
11
Adc
Apk
D
D
Drain Current — Single Pulse (t ≤ 10 µs)
I
p
DM
Total Power Dissipation
Derate above 25°C
P
D
125
1.0
Watts
W/°C
Operating and Storage Temperature Range
T , T
stg
– 55 to 150
101
°C
J
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (T
150°C)
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
mJ
J
(V
DD
= 100 Vdc, V = 10 Vdc, PEAK I = 4.5 Apk, L = 10 mH, R = 25 Ω)
GS L G
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
R
R
1.0
62.5
°C/W
°C
θJC
θJA
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T
260
L
E–FET and Designer’s are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
V
(BR)DSS
(V
GS
= 0 Vdc, I = 250 µAdc)
1200
—
—
1.28
—
—
Vdc
mV/°C
D
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
µAdc
DSS
(V
DS
(V
DS
= 1200 Vdc, V
= 1200 Vdc, V
= 0 Vdc)
= 0 Vdc, T = 125°C)
—
—
—
—
10
100
GS
GS
J
Gate–Body Leakage Current (V
= ± 20 Vdc, V
DS
= 0 Vdc)
I
—
—
100
nAdc
GS
GSS
ON CHARACTERISTICS (1)
Gate Threshold Voltage
V
GS(th)
(V
DS
= V , I = 250 µAdc)
2.0
—
3.0
7.1
4.0
—
Vdc
mV/°C
GS
D
Temperature Coefficient (Negative)
Static Drain–Source On–Resistance (V
= 10 Vdc, I = 1.5 Adc)
R
V
—
4.0
5.0
Ohm
Vdc
GS
D
DS(on)
Drain–Source On–Voltage (V
GS
= 10 Vdc)
DS(on)
(I = 3.0 Adc)
—
—
—
—
18.0
15.8
D
(I = 1.5 Adc, T = 125°C)
D
J
Forward Transconductance (V
DS
= 15 Vdc, I = 1.5 Adc)
g
2.5
3.1
—
mhos
pF
D
FS
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
2130
1710
932
2980
2390
1860
iss
(V
DS
= 25 Vdc, V = 0 Vdc,
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
—
—
—
—
—
—
—
—
13.6
12.6
35.8
20.7
31
30
30
70
40
40
—
—
—
ns
d(on)
(V
(V
= 600 Vdc, I = 3.0 Adc,
D
Rise Time
DD
t
r
V
= 10 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
t
d(off)
R
= 9.1 Ω)
t
f
Gate Charge
Q
T
Q
1
Q
2
Q
3
nC
8.0
= 600 Vdc, I = 3.0 Adc,
DS
D
V
GS
= 10 Vdc)
11
14
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
V
Vdc
ns
SD
(I = 3.0 Adc, V
= 0 Vdc)
= 0 Vdc, T = 125°C)
S
GS
—
—
0.80
0.65
1.0
—
(I = 3.0 Adc, V
S
GS
J
Reverse Recovery Time
t
—
—
—
—
394
118
276
2.11
—
—
—
—
rr
t
a
(I = 3.0 Adc, V
= 0 Vdc,
dI /dt = 100 A/µs)
S
GS
S
t
b
Reverse Recovery Stored Charge
Q
µC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
L
D
nH
—
—
3.5
4.5
—
—
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
—
7.5
—
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
6
5
4
3
2
1
0
6
V
= 10 V
T
= 25
°C
V
≥ 10 V
GS
J
DS
5
4
3
2
1
0
6 V
100°C
5 V
4 V
25°C
T
= –55°C
J
0
6
12
18
24
30
3.0
3.4
3.8
4.2
4.6
5.0
5.4
5.8
6.2
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V , GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
8
5.4
5.0
4.6
V
= 10 V
T = 100°C
J
T
= 25°C
GS
J
6
4
V
= 10 V
GS
25°C
15 V
2
0
4.2
3.8
–55
°C
0
1
2
3
4
5
6
0
1
2
3
4
5
6
I
, DRAIN CURRENT (AMPS)
I , DRAIN CURRENT (AMPS)
D
D
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.5
2.0
1.5
1.0
0.5
0
10,000
1,000
100
V
= 0 V
GS
V
I
= 10 V
GS
= 1.5 A
T
= 125°C
D
J
100°C
25°C
10
1
–50
–25
0
25
50
75
100
C)
125
150
0
200
400
600
800
1000
1200
T , JUNCTION TEMPERATURE (
°
V
DS
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
J
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when cal-
culating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
the drive circuit so that
) can be made from a rudimentary analysis of
G(AV)
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V remains virtually constant at a level known as
GS
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
= the gate drive resistance
GG
GG
R
G
and Q and V
GSP
are read from the gate charge curve.
2
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V
/(V
GG GG
– V
)]
GSP
d(on)
G
iss
In (V
/V
GG GSP
)
d(off)
G
iss
2800
10,000
T
= 25°C
V
= 0 V
V
= 0 V
J
DS
V
= 0 V
GS
GS
= 25°C
2400
2000
1600
T
J
C
C
iss
C
iss
1,000
rss
C
iss
1200
800
400
0
C
oss
100
10
C
oss
C
rss
C
rss
10
5
0
5
10
15
20
25
10
100
DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1000
V
V
DS
GS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
Figure 7a. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
1000
100
10
16
14
12
10
8
400
350
300
250
200
150
100
V
= 600 V
= 3 A
= 10 V
= 25°C
DD
I
V
T
D
GS
J
QT
t
t
d(off)
V
I
t
GS
f
Q2
Q1
6
4
d(on)
t
= 3 A
= 25
r
D
T
°C
J
2
0
50
0
V
DS
Q3
1
0
4
8
12
16
20
24
28
32
1
10
, GATE RESISTANCE (OHMS)
G
100
Q , TOTAL GATE CHARGE (nC)
R
g
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
3.0
V
T
= 0 V
GS
= 25
°C
2.4
1.8
1.2
J
0.6
0
0.55
0.59
0.63
0.67
0.71
0.75
0.79
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
tion temperature and a case temperature (T ) of 25°C. Peak
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (I
)
DM
) is exceeded and the transition time
(I
), the energy rating is specified at rated continuous cur-
DM
nor rated voltage (V
DSS
rent (I ), in accordance with industry custom. The energy rat-
D
(t ,t ) do not exceed 10 µs. In addition the total power aver-
r f
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
aged over a complete switching cycle must not exceed
(T
– T )/(R ).
J(MAX)
C
θJC
rents below rated continuous I can safely be assumed to
A Power MOSFET designated E–FET can be safely used
D
in switching circuits with unclamped inductive loads. For reli-
Motorola TMOS Power MOSFET Transistor Device Data
equal the values indicated.
5
SAFE OPERATING AREA
100
120
V
= 20 V
GS
SINGLE PULSE
= 25
I
= 3 A
D
100
T
°C
C
10
10
µs
80
60
40
100
µ
s
1.0
1 ms
10 ms
dc
0.1
R
LIMIT
DS(on)
20
0
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1.0
10
100
1,000
10,000
25
50
75
100
125
C)
150
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
DS
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
0.1
(pk)
0.05
0.02
0.01
R
(t) = r(t) R
JC θJC
θ
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
t
1
1
t
T
– T = P R (t)
(pk) θJC
2
J(pk)
C
DUTY CYCLE, D = t /t
1 2
SINGLE PULSE
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
1.0E+00
1.0E+01
t, TIME (s)
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
t
a
b
TIME
0.25 I
t
S
p
I
S
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
D1–D4
1N4007s
L1
H1
C1
0.1
1 kV
C4
0.1
1 kV
90VAC–
600VAC
+V
in
L1
470 k
1/2 W
R4
C6
F
450 V
+
+
H2
100
470 k
1/2 W
C3
C2
0.0047
3 kV
R3
R2
0.0047
3 kV
470 k
1/2 W
EARTH
GND
C5
F
450 V
100
470 k
1/2 W
R1
INPUT GND
Figure 15. The AC Input/Filter Circuit Section
D9
MUR430
100
20 V
F
T1
+12 V
+5 V
+
+
C11
C12
D8
MBR370
100
10 V
F
+V
in
V
aux
+
+
R16
100 k
1/2 W
R20
120
R9
R8
82 k, 1/2 W
1 nF
3 kV
C13
MUR130
D7
C14
C9
D6
R19
32.4 k
10
25 V
+
F
U2
MOC8102
R7
R6
R5
C15
1.5 nF
D10
V
aux
C10
R11
1.8 k
MUR1100
LL
C17
2.2 nF
1.3
F
7.5 k
7
MTP3N120E
R12 10
C16 R17
UC3845BN
R10
27 k
U3
TL431
D5
3.3 V
Q1
R21
2.49 k
6
3
4
1
R13
1 k
R15
680
GND
C7
220 pF
2
5
R14
1.2
1/2 W
U2
1/2
C8
1000 pF
MOC8102
INPUT GND
Figure 16. The DC/DC Converter Circuit Section
Motorola TMOS Power MOSFET Transistor Device Data
7
PACKAGE DIMENSIONS
NOTES:
SEATING
PLANE
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–T–
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
B
F
T
S
4
INCHES
MIN
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
MAX
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
–––
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
–––
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
–––
A
K
Q
Z
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
–––
1
2
3
U
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
H
L
R
V
J
G
T
U
V
D
N
CASE 221A–06
ISSUE Y
Z
0.080
2.04
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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MTP3N120E/D
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