MPC8280CZUPIE [MOTOROLA]
Micro Peripheral IC;
| 型号： | MPC8280CZUPIE |
| 厂家： | 
MOTOROLA |
| 描述： | Micro Peripheral IC |
| 文件： | 总72页 (文件大小：1234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
MPC8280EC/D
Rev.0.3, 6/2003
MPC8280
Hardware Specifications
t
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for .13µm (HiP7) members of the
PowerQUICC II™ family of integrated communications processors—the MPC8280, the
MPC8275, and the MPC8270 (collectively referred to throughout this document as the
MPC8280).
The following topics are addressed:
Topic
Page
2
Section 1.1, “Features”
Section 1.2, “Electrical and Thermal Characteristics”
Section 1.2.1, “DC Electrical Characteristics”
Section 1.2.2, “Thermal Characteristics”
Section 1.2.3, “AC Electrical Characteristics”
Section 1.3, “Clock Configuration Modes”
Section 1.3.1, “Local Bus Mode”
Section 1.3.2, “PCI Mode”
6
6
10
11
19
20
22
37
67
70
Section 1.4, “Pinout”
Section 1.5, “Package Description”
Section 1.6, “Ordering Information”
HiP7 members of the PowerQUICC II family are available in two packages—the standard ZU
package and an alternate VR package—as shown in Table 1. Note that throughout this
document references to the MPC8280 and the MPC8270 are inclusive of VR-package devices
unless otherwise specified. For more information on VR packages, contact your Motorola
sales office.
Table 1. HiP7 PowerQUICC II Device Packages
ZU
VR
(480 TBGA)
(516 PBGA)
MPC8280
MPC8270
MPC8275VR
MPC8270VR
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
Figure 1 shows the block diagram. Shaded portions are device-specific; refer to the notes below.
16 Kbytes
I-Cache
I-MMU
System Interface Unit
60x Bus
(SIU)
G2_LE Core
16 Kbytes
D-Cache
Bus Interface Unit
PCI Bus
32 bits, up to 66 MHz
60x-to-PCI
Bridge
D-MMU
or
60x-to-Local
Bridge
Local Bus
32 bits, up to 100 MHz
Communication Processor Module (CPM)
Memory Controller
Clock Counter
32 KB
Instruction
RAM
32 KB
Data
RAM
Timers
Interrupt
Controller
Serial
DMAs
Parallel I/O
32-bit RISC Microcontroller
and Program ROM
4 Virtual
IDMAs
System Functions
Baud Rate
Generators
IMA 1
Microcode
I2C
MCC11 MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4/ SMC1 SMC2
SPI
USB
1
TC Layer Hardware
Time Slot Assigner
Serial Interface
Non-Multiplexed
I/O
8 TDM Ports2
3 MII or RMII
Ports
2 UTOPIA
3
Ports
Notes:
1
MPC8280 only (not on MPC8270 nor the VR package (MPC8270VR and MPC8275VR))
MPC8280 only (4 TDMs on MPC8270 and the VR package (MPC8270VR and MPC8275VR))
MPC8280 and MPC8275VR only (not on MPC8270 nor MPC8270VR)
2
3
Figure 1. MPC8280 Block Diagram
1.1 Features
The major features of the MPC8280 are as follows:
•
Dual-issue integer (G2_LE) core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–450 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (SPEC95 benchmark at 450 MHz; 855 Dhrystones MIPS at 450 MHz)
2
MPC8280HardwareSpecifications
MOTOROLA
Features
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
•
•
Separate power supply for internal logic and for I/O
Separate PLLs for G2_LE core and for the CPM
— G2_LE core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1,
8:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios
64-bit data and 32-bit address 60x bus
•
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
•
•
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
•
PCI bridge
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming
— PCI Host Bridge or Peripheral capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the MPC8280) required by the PCI standard as well as message and
doorbell registers
— Supports the I O standard
2
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0
August 3, 1998)
MOTOROLA
MPC8280HardwareSpecifications
3
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
— Support for 66.67/83.33/100 MHz, 3.3 V specification
— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
— Makes use of the local bus signals, so there is no need for additional pins
System interface unit (SIU)
•
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
Twelve-bank memory controller
•
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
•
•
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible
support for communications protocols
— Interfaces to G2_LE core through an on-chip 32-Kbyte dual-port data RAM, an on-chip
32-Kbyte dual-port instruction RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII) or reduced media independent interface (RMII)
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5,
AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external
connections (no ATM support for the MPC8270)
– Transparent
– HDLC—Up to T3 rates (clear channel)
– FCC2 can also be connected to the TC layer (MPC8280 only)
— Two multichannel controllers (MCCs) (one MCC on the MPC8270)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split
into four subgroups of 32 channels each.
4
MPC8280HardwareSpecifications
MOTOROLA
Features
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Universal serial bus (USB) controller—supports both host and slave modes
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
2
2
— One inter-integrated circuit (I C) controller (identical to the MPC860 I C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to eight TDM interfaces (four on the MPC8270)
– Supports two groups of four TDM channels for a total of eight TDMs (one group of four on
the MPC8270)
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
•
•
Inverse multiplexing for ATM capabilities (IMA) (MPC8280 only).Supported by eight transfer
transmission convergence (TC) layers between the TDMs and FCC2.
Transmission convergence (TC) layer (MPC8280 only)
MOTOROLA
MPC8280HardwareSpecifications
5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.2 Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8280.
1.2.1 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MPC8280. Table 2 shows the maximum
electrical ratings.
1
Table 2. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
2
Core supply voltage
VDD
VCCSYN
VDDH
VIN
-0.3 – 2.25
-0.3 – 2.25
-0.3 – 4.0
V
V
2
PLL supply voltage
3
I/O supply voltage
V
4
Input voltage
GND(-0.3) – 3.6
120
V
Junction temperature
T
˚C
˚C
j
Storage temperature range
T
(-55) – (+150)
STG
1
Absolute maximum ratings are stress ratings only; functional operation (see Table 3) at the maximums is
not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during
power-on reset.
Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec.
VDDH should not exceed VDD/VCCSYN by more than 2.5 V during normal operation.
Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
2
3
4
Table 3 lists recommended operational voltage conditions.
1
Table 3. Recommended Operating Conditions
Rating
Symbol
Value
Unit
Core supply voltage
PLL supply voltage
I/O supply voltage
VDD
VCCSYN
VDDH
VIN
1.425 – 1.575
1.425 – 1.575
3.135 – 3.465
V
V
V
Input voltage
GND (-0.3) – 3.465
V
2
Junction temperature (maximum)
Ambient temperature
T
105
˚C
˚C
j
2
T
0–70
A
1
2
Caution: These are the recommended and tested operating conditions. Proper operation outside of
these conditions is not guaranteed.
Note that for extended temperature parts the range is (-40) – 105 .
T
T
j
A
NOTE: Core, PLL, and I/O Supply Voltages
VDDH, VCCSYN, and VDD must track each other and must vary in the
same direction—in the positive direction (+0.165 VDDH and +0.075 VDD
and VCCSYN) or in the negative direction (-0.165 VDDH and -0.075
VDD and VCCSYN).
6
MPC8280HardwareSpecifications
MOTOROLA
Electrical and Thermal Characteristics
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or V ).
CC
Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the
MPC8280. Note that in PCI mode the I/O interface is different.
4 V
GV + 5%
DD
V
V
GV
IH
DD
GND
GND – 0.3 V
IL
GND – 1.0 V
Not to exceed 10%
of t
SDRAM_CLK
Figure 2. Overshoot/Undershoot Voltage
Table 4 shows DC electrical characteristics.
1
Table 4. DC Electrical Characteristics
Characteristic
Symbol
Min
Max
Unit
Input high voltage, all inputs except CLKIN
Input low voltage
V
2.0
GND
2.4
GND
—
3.465
0.8
3.465
0.4
10
V
V
IH
V
IL
CLKIN input high voltage
V
V
IHC
CLKIN input low voltage
V
I
V
ILC
IN
2
Input leakage current, V = VDDH
µA
µA
µA
µA
V
IN
2
Hi-Z (off state) leakage current, V = VDDH
I
—
10
IN
OZ
Signal low input current, V = 0.8 V
I
—
1
IL
L
Signal high input current, V = 2.0 V
I
—
1
IH
H
Output high voltage, I = –2 mA
V
2.4
—
OH
OH
except UTOPIA mode, and open drain pins
3
In UTOPIA mode (UTOPIA pins only): I = -8.0mA
OH
PA[0-31]
PB[4-31]
PC[0-31]
PD[4-31]
3
In UTOPIA mode (UTOPIA pins only): I = 8.0mA
V
—
0.5
V
OL
OL
PA[0-31]
PB[4-31]
PC[0-31]
PD[4-31]
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
7
Electrical and Thermal Characteristics
Table 4. DC Electrical Characteristics (Continued)
1
Characteristic
Symbol
Min
Max
Unit
I
= 7.0mA
V
—
0.4
V
OL
OL
BR
BG
ABB/IRQ2
TS
A[0-31]
TT[0-4]
TBST
TSIZE[0–3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0-63]
DP(0)/RSRV/EXT_BR2
DP(1)/IRQ1/EXT_BG2
DP(2)/TLBISYNC/IRQ2/EXT_DBG2
DP(3)/IRQ3/EXT_BR3/CKSTP_OUT
DP(4)/IRQ4/EXT_BG3/CORE_SREST
DP(5)/TBEN/IRQ5/EXT_DBG3
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
PORESET
HRESET
SRESET
RSTCONF
QREQ
8
MPC8280HardwareSpecifications
MOTOROLA
Electrical and Thermal Characteristics
1
Table 4. DC Electrical Characteristics (Continued)
Characteristic
Symbol
Min
Max
Unit
I
= 5.3mA
V
—
0.4
V
OL
OL
CS[0-9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE[0–7]/PSDDQM[0–7]/PBS[0–7]
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM[0–3]/LBS[0–3]/PCI_CFG[0–3]
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LSDAMUX/LGPL5/PCI_MODCK
LWR
MODCK1/AP(1)/TC(0)/BNKSEL(0)
MODCK2/AP(2)/TC(1)/BNKSEL(1)
MODCK3/AP(3)/TC(2)/BNKSEL(2)
I
= 3.2mA
OL
L_A14/PAR
L_A15/FRAME/SMI
L_A16/TRDY
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTA
L_A30/REQ2
L_A31
LCL_D(0-31)/AD(0-31)
LCL_DP(0-3)/C/BE(0-3)
PA[0–31]
PB[4–31]
PC[0–31]
PD[4–31]
TDO
1
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input.To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
The leakage current is measured for nominal VDDH,VCCSYN, and VDD.
2
3
MPC8280 and MPC8275VR only.
MOTOROLA
MPC8280HardwareSpecifications
9
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.2.2 Thermal Characteristics
Table 5 describes thermal characteristics for both the packages. Refer to Table 1 for information on a given
device’s package.
Table 5. Thermal Characteristics
Value
Characteristic
Symbol
Unit
Air Flow
480 TBGA
516 PBGA
(ZU package) (VR package)
Junction to ambient—
single-layer board
16
11
12
9
27
21
19
16
11
8
Natural convection
1
θ
°C/W
°C/W
JA
1 m/s
Junction to ambient—
four-layer board
Natural convection
θ
JA
1 m/s
—
2
Junction to board
θ
6
°C/W
°C/W
JB
3
Junction to case
θ
2
—
JC
1
2
Assumes no thermal vias
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
3
1.2.2.1 Layout Practices
Each V pin should be provided with a low-impedance path to the board’s power supply. Each ground pin
CC
should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct
groups of logic on chip. The V power supply should be bypassed to ground using at least four 0.1 µF
CC
by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip V and ground should be kept to less than half an inch
CC
per capacitor lead.A four-layer board is recommended, employing two inner layers asVCC and GND planes.
All output pins on the MPC8280 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize overdamped conditions and reflections caused by these
fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V and GND circuits. Pull up all unused inputs or signals that will be inputs
CC
during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
Table 6 provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required to ensure the junction temperature does not exceed the maximum specified
value. Also note that the I/O power should be included when determining whether to use a heat sink.
10
MPC8280HardwareSpecifications
MOTOROLA
Electrical and Thermal Characteristics
1
Table 6. Estimated Power Dissipation for Various Configurations
2,3
P
(W)
INT
CPM
Multiplication
Factor
CPU
Multiplication
Factor
Bus
(MHz)
CPM
(MHz)
CPU
(MHz)
Vddl 1.5 Volts
Nominal
Maximum
66.67
66.67
66.67
66.67
83.33
83.33
83.33
100
2.5
2.5
3
166
166
200
233
250
250
292
300
300
3.5
4
233
266
266
300
333
375
417
400
450
0.8
0.85
0.9
0.85
0.9
4
0.95
1.0
3.5
3
4.5
4
0.9
1.1
1.2
3
4.5
5
1.15
1.3
1.25
1.4
3.5
3
4
1.35
1.4
1.45
1.5
100
3
4.5
1
2
3
Test temperature = 105˚ C)
= I x V Watts
Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds:
66.7 MHz = 0.35 W (nominal), 0.4 W (maximum)
P
INT
DD
DD
83.3 MHz = 0.4 W (nominal), 0.5 W (maximum)
100 MHz = 0.5 W (nominal), 0.6 W (maximum)
1.2.3 AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for 66.67/83.33/100 MHz MPC8280 devices. Note thatAC timings are based on a 50-pf load. Typical
output buffer impedances are shown in Table 7.
1
Table 7. Output Buffer Impedances
Output Buffers
Typical Impedance (Ω)
60x bus
45
45
45
45
25
Local bus
Memory controller
Parallel I/O
PCI
1
These are typical values at 65˚ C. Impedance may vary by ±25% with process and temperature.
MOTOROLA
MPC8280HardwareSpecifications
11
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.2.3.1 CPM AC Characteristics
Table 8 lists CPM output characteristics.
1
Table 8. AC Characteristics for CPM Outputs
Spec Number
Max Min
Characteristic
Value (ns)
Maximum Delay
Minimum Delay
66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz
sp36a sp37a FCC outputs—internal clock (NMSI)
sp36b sp37b FCC outputs—external clock (NMSI)
sp38a sp39a SCC/SMC/SPI/I2C outputs—internal clock (NMSI)
sp38b sp39b SCC/SMC/SPI/I2C outputs—external clock (NMSI)
sp40 sp41 TDM outputs/SI
6
5.5
12
16
16
12
11
11
5.5
12
16
16
12
11
11
1
2
1
2
1
2
14
19
19
14
14
14
1
0.5
2
0.5
2
2
5
3
3
sp42 sp43 TIMER/IDMA outputs
1
0.5
0.5
0.5
0.5
sp42a sp43a PIO outputs
0.5
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
Table 9 lists CPM input characteristics.
1
Table 9. AC Characteristics for CPM Inputs
Spec Number
Setup Hold
Characteristic
Value (ns)
Setup
Hold
66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz
sp16a sp17a FCC inputs—internal clock (NMSI)
sp16b sp17b FCC inputs—external clock (NMSI)
sp18a sp19a SCC/SMC/SPI/I2C inputs—internal clock (NMSI)
sp18b sp19b SCC/SMC/SPI/I2C inputs—external clock (NMSI)
sp20 sp21 TDM inputs/SI
10
3
8
2.5
16
4
8
2.5
16
4
0
2
0
2
0
2
20
5
0
0
0
2
2
2
7
5
5
4
3
3
sp22 sp23 PIO/TIMER/IDMA inputs
10
8
8
0.5
0.5
0.5
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings
are measured at the pin.
NOTE
Although the specifications generally reference the rising edge of the
clock, the following AC timing diagrams also apply when the falling edge
is the active edge.
12
MPC8280HardwareSpecifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 3 shows the FCC internal clock.
BRG_OUT
sp17a
sp16a
FCC input signals
sp36a/sp37a
FCC output signals
Note: When GFMR[TCI] = 0
sp36a/sp37a
FCC output signals
Note: When GFMR.[TCI] = 1
Figure 3. FCC Internal Clock Diagram
Figure 4 shows the FCC external clock.
Serial ClKin
sp17b
sp16b
FCC input signals
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 0
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 1
Figure 4. FCC External Clock Diagram
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
13
Electrical and Thermal Characteristics
2
Figure 5 shows the SCC/SMC/SPI/I C external clock.
Serial CLKin
sp19b
sp18b
SCC/SMC/SPI/I2C input signals
(See note)
sp38b/sp39b
SCC/SMC/SPI/I2C output signals
(See note)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
2
Figure 5. SCC/SMC/SPI/I C External Clock Diagram
2
Figure 6 shows the SCC/SMC/SPI/I C internal clock.
BRG_OUT
sp19a
sp18a
SCC/SMC/SPI/I2C input signals
(See note)
sp38a/sp39a
SCC/SMC/SPI/I2C output signals
(See note)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
2
Figure 6. SCC/SMC/SPI/I C Internal Clock Diagram
Figure 7 shows TDM input and output signals.
14
MPC8280HardwareSpecifications
MOTOROLA
Electrical and Thermal Characteristics
Serial CLKin
sp20
sp21
TDM input signals
sp40/sp41
TDM output signals
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 7. TDM Signal Diagram
Figure 8 shows PIO and timer signals.
Sys clk
sp23
sp22
PIO/IDMA/TIMER[TGATE assertion] input signals
(See note)
sp23
sp22
TIMER input signal [TGATE deassertion]
(See note)
sp42/sp43
IDMA output signals
sp42/sp43
sp42a/sp43a
TIMER(sp42/43)/ PIO(sp42a/sp43a)
output signals
Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
Figure 8. PIO and Timer Signal Diagram
1.2.3.2 SIU AC Characteristics
Table 10 lists SIU input characteristics.
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
15
Electrical and Thermal Characteristics
NOTE: PCI AC Timing
The MPC8280 meets the timing requirements of PCI Specification
Revision 2.2. Refer to Section 1.3.2, “PCI Mode” and “Note: Tval (Output
Hold)” to determine if a specific clock configuration is compliant.
1
Table 10. AC Characteristics for SIU Inputs
Spec Number
Setup Hold
Characteristic
Value (ns)
Setup
Hold
66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz
sp11 sp10 AACK/TA/TS/DBG/BG/BR
sp11a sp10 ARTRY/ TEA
6
6
5
8
5
5
5
4
6
4
3.5
4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
sp12 sp10 Data bus in normal mode
sp13 sp10 Data bus in ECC and PARITY modes
3.5
3.5
2.5
sp13a sp10 Pipeline mode—
Data bus in ECC and PARITY modes
sp14 sp10 DP pins
7
—
5
6
4
4
3.5
2.5
3.5
0.5
—
0.5
0.5
0.5
0.5
0.5
0.5
sp14a sp10 Pipeline mode—DP pins
sp15 sp10 All other pins
0.5
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
Table 11 lists SIU output characteristics.
1
Table 11. AC Characteristics for SIU Outputs
Spec Number
Max Min
Characteristic
Value (ns)
Maximum Delay
Minimum Delay
66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz
sp31 sp30 PSDVAL/TEA/TA
7
8
6
5.5
5.5
5.5
6.5
5.5
5.5
7
1
1
1
1
1
1
sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT
6.5
6.5
7
2
sp33a sp30 Data bus
6.5
8
0.5
1
0.5
1
0.5
1
sp33b sp30 DP
sp34 sp30 Memory controller signals/ALE
sp35 sp30 All other signals
sp35a sp30 AP
6
5.5
5.5
7
1
1
1
6
1
1
1
7
1
1
1
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.
2
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing.
16
MPC8280HardwareSpecifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 9 shows the interaction of several bus signals.
CLKin
sp10
sp10
sp10
sp11
sp11a
sp12
AACK/TA/TS/
DBG/BG/BR input signals
ARTRY/TEA input signals
DATA bus normal mode
input signal
sp10
sp30
sp15
All other input signals
sp31
PSDVAL/TEA/TA output signals
sp32
sp30
sp30
sp30
ADD/ADD_atr/BADDR/CI/
GBL/WT output signals
sp33a
DATA bus output signals
sp35
All other output signals
sp35a
(except AP)
sp30
AP signals
Figure 9. Bus Signals
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
17
Electrical and Thermal Characteristics
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
CLKin
sp10
sp13
DATA bus, ECC, and PARITY mode
input signals
sp13a
sp10
Pipeline mode—
DATA bus, ECC, and PARITY mode
input signals
sp10
sp14
DP mode input signal
sp10
sp14a
Pipeline mode—
DP mode input signal
sp33b
sp30
DP mode output signal
Figure 10. Parity Mode Diagram
Figure 11 shows signal behavior in MEMC mode.
CLKin
V_CLK
sp34/sp30
Memory controller signals
Figure 11. MEMC Mode Diagram
NOTE
Generally, all MPC8280 bus and system output signals are driven from the
rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is
divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the
rising edge, and T3 at the falling edge, of CLKin. However, the spacing of
T2 and T4 depends on the PLL clock ratio selected, as shown in Table 12.
18
MPC8280HardwareSpecifications
MOTOROLA
Clock Configuration Modes
Table 12. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T2 T3 T4
1/4 CLKin 1/2 CLKin 3/4 CLKin
PLL Clock Ratio
1:2, 1:3, 1:4, 1:5, 1:6
1:2.5
1:3.5
3/10 CLKin
4/14 CLKin
1/2 CLKin
1/2 CLKin
8/10 CLKin
11/14 CLKin
Figure 12 is a representation of the information in Table 12.
CLKin
CLKin
CLKin
for 1:2, 1:3, 1:4, 1:5, 1:6
T1
T1
T1
T2
T3
T3
T3
T4
for 1:2.5
T2
T4
for 1:3.5
T2
T4
Figure 12. Internal Tick Spacing for Memory Controller Signals
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
1.3 Clock Configuration Modes
The MPC8280 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set according
to three input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 13.
Table 13. MPC8280 Clocking Modes
Pins
PCI Clock
Frequency Range
(MHZ)
Clocking Mode
Reference
1
PCI_MODE PCI_CFG[0] PCI_MODCK
1
0
0
0
0
—
0
—
0
Local bus
PCI host
—
Table 14
Table 15
Table 16
Table 17
Table 18
50–66
25–50
50–66
25–50
0
1
1
0
PCI agent
1
1
1
Determines PCI clock frequency range. Refer to Section 1.3.2, “PCI Mode.”
MOTOROLA
MPC8280HardwareSpecifications
19
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Clock Configuration Modes
In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven
bits during the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits from
hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the
selected MPC8280 clock operation mode as described in the following sections.
1.3.1 Local Bus Mode
Table 14 lists default and full configurations for the MPC8280 in local bus mode. The frequencies listed are
for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting
configuration does not exceed the frequency rating of the user’s device.
NOTE
Clock configurations change only after POR is asserted.
1
Table 14. Clock Configurations for Local Bus Mode
3
Bus Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
2
CPM
Multiplication
CPU
Multiplication
Mode
4
5
Factor
Factor
MODCK_H-MODCK[1-3] low
high
low
high
low
high
Default Modes (MODCK_H= 0000)
0000_000
0000_001
0000_010
0000_011
0000_100
0000_101
0000_110
0000_111
62.5
50.0
62.5
50.0
50.0
50.0
50.0
41.7
133.3
133.3
100.0
100.0
167.0
167.0
160.0
160.0
3
3
187.5
150.0
250.0
200.0
100.0
100.0
125.0
104.2
400.0
400.0
400.0
400.0
334.0
334.0
400.0
400.0
4
5
250.0
250.0
250.0
250.0
125.0
150.0
125.0
125.0
533.3
666.7
400.0
500.0
417.5
501.0
400.0
480.0
4
4
4
5
2
2.5
3
2
2.5
2.5
2.5
3
Full Configuration Modes
0001_000
0001_001
0001_010
0001_011
0001_100
62.5
50.0
50.0
167.0
167.0
167.0
2
2
2
125.0
100.0
100.0
334.0
334.0
334.0
4
5
6
250.0
250.0
300.0
668.0
835.0
1002.0
Reserved
Reserved
0001_101
0001_110
1000_111
0001_111
0010_000
0010_001
62.5
50.0
45.5
41.7
133.3
133.3
133.3
133.3
3
3
3
3
187.5
400.0
400.0
400.0
400.0
4
5
250.0
250.0
250.0
250.0
533.3
666.7
733.3
800.0
150.0
136.4
125.0
5.5
6
Reserved
Reserved
20
MPC8280HardwareSpecifications
MOTOROLA
Clock Configuration Modes
1
Table 14. Clock Configurations for Local Bus Mode (Continued)
3
Bus Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
2
CPM
Multiplication
CPU
Multiplication
Mode
4
5
Factor
Factor
MODCK_H-MODCK[1-3] low
high
low
high
low
high
0010_010
0010_011
0010_100
0010_101
0010_110
62.5
50.0
41.7
35.7
31.3
100.0
100.0
100.0
100.0
100.0
4
4
4
4
4
250.0
200.0
166.7
142.9
125.0
400.0
400.0
400.0
400.0
400.0
4
5
6
7
8
250.0
250.0
250.0
250.0
250.0
400.0
500.0
600.0
700.0
800.0
0010_111
0011_000
0011_001
0011_010
0011_011
Reserved
50.0
41.7
35.7
31.3
80.0
80.0
80.0
80.0
5
5
5
5
250.0
208.3
178.6
156.3
400.0
400.0
400.0
400.0
5
6
7
8
250.0
250.0
250.0
250.0
400.0
480.0
560.0
640.0
0011_100
0011_101
0011_110
0011_111
0100_000
Reserved
Reserved
41.7
35.7
31.3
66.7
66.7
66.7
6
6
6
250.0
400.0
400.0
400.0
6
7
8
250.0
250.0
250.0
400.0
466.7
533.3
214.3
187.5
0101_101
0101_110
0101_111
0110_000
0110_001
0110_010
62.5
50.0
50.0
71.4
62.5
55.6
167.0
167.0
167.0
167.0
167.0
167.0
2
2
2
2
2
2
125.0
100.0
100.0
142.9
125.0
111.1
334.0
334.0
334.0
334.0
334.0
334.0
2
2.5
3
125.0
125.0
150.0
250.0
250.0
250.0
334.0
417.5
501.0
584.5
668.0
751.5
3.5
4
4.5
0110_011
0110_100
0110_101
0110_110
0110_111
0111_000
Reserved
50.0
41.7
71.4
62.5
55.6
160.0
160.0
160.0
160.0
160.0
2.5
2.5
2.5
2.5
2.5
125.0
104.2
178.6
156.3
138.9
400.0
400.0
400.0
400.0
400.0
2.5
3
125.0
125.0
250.0
250.0
250.0
400.0
480.0
560.0
640.0
720.0
3.5
4
4.5
0111_001
0111_010
Reserved
Reserved
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
21
Clock Configuration Modes
1
Table 14. Clock Configurations for Local Bus Mode (Continued)
3
Bus Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
2
CPM
Multiplication
CPU
Multiplication
Mode
4
5
Factor
Factor
MODCK_H-MODCK[1-3] low
high
low
high
low
high
0111_011
0111_100
0111_101
0111_110
41.7
71.4
62.5
55.6
133.3
133.3
133.3
133.3
3
3
3
3
125.0
214.3
187.5
166.7
400.0
400.0
400.0
400.0
3
125.0
250.0
250.0
250.0
400.0
466.7
533.3
600.0
3.5
4
4.5
0111_111
1000_000
1000_001
1000_010
1000_011
1000_100
1000_101
1000_110
Reserved
Reserved
Reserved
71.4
62.5
55.6
50.0
45.5
114.3
114.3
114.3
114.3
114.3
3.5
3.5
3.5
3.5
3.5
250.0
400.0
400.0
400.0
400.0
400.0
3.5
4
250.0
250.0
250.0
250.0
250.0
400.0
457.1
514.3
571.4
628.6
218.8
194.4
175.0
159.1
4.5
5
5.5
1100_000
1100_001
1100_010
Reserved
Reserved
Reserved
1101_000
Reserved
1
2
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency
guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock
mode. For modes with a CPU multiplication factor ≤ 3, the minimum CPU frequency is 125 MHz or 150 MHz, as
shown in the table. For modes with a CPU multiplication factor ≥ 3.5, the minimum CPU frequency is 250 MHz.
The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so
that the resulting configuration does not exceed the frequency rating of the user’s device.
MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual).
MODCK[1-3] = three hardware configuration pins.
3
4
5
60x and local bus frequency. Identical to CLKIN.
CPM multiplication factor = CPM clock/bus clock
CPU multiplication factor = Core PLL multiplication factor
1.3.2 PCI Mode
The following tables show the possible clock configurations for the MPC8280 in both PCI host and PCI
agent modes. In addition, note the following:
NOTE: PCI_MODCK
In PCI mode only, PCI_MODCK comes from the LGPL5 pin and
MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.
22
MPC8280HardwareSpecifications
MOTOROLA
Clock Configuration Modes
NOTE:Tval (Output Hold)
The minimum Tval = 2 when PCI_MODCK = 1, and the minimum
Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock
configurations that fit this condition to achieve PCI-compliant AC timing.
1.3.2.1 PCI Host Mode
Table 15 and Table 16 show configurations for PCI host mode. The frequencies listed are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does
not exceed the frequency rating of the user’s device.
1,2
Table 15. Clock Configurations for PCI Host Mode (PCI_MODCK=0)
4
Bus Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
PCI Clock
(MHz)
3
Mode
CPM
CPU
PCI
Multiplication
Multiplication
Division
Factor
5
6
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
Default Modes (MODCK_H=0000)
0000_000
0000_001
0000_010
0000_011
0000_100
0000_101
0000_110
0000_111
50.0 66.7
50.0 66.7
60.0 80.0
71.4 80.0
62.5 80.0
50.0 66.7
2
2
100.0 133.3
100.0 133.3
150.0 200.0
178.6 200.0
156.3 200.0
150.0 200.0
2.5
3
125.0 166.7
150.0 200.0
180.0 240.0
250.0 280.0
250.0 320.0
150.0 200.0
2
2
3
3
3
3
50.0 66.7
50.0 66.7
50.0 66.7
59.5 66.7
52.1 66.7
50.0 66.7
2.5
2.5
2.5
3
3
3.5
4
3
PCI host mode (PCI_MODCK=1) only (refer to Table 16)
62.5 66.7
3
187.5 200.0
4
250.0 266.6
3
62.5 66.7
Full Configuration Modes
0001_000
0001_001
0001_010
0001_011
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
3
3
3
3
150.0 200.0
150.0 200.0
150.0 200.0
150.0 200.0
5
6
7
8
250.0 333.3
300.0 400.0
350.0 466.6
400.0 533.3
3
3
3
3
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
0010_000
0010_001
0010_010
0010_011
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
4
4
4
4
200.0 266.6
200.0 266.6
200.0 266.6
200.0 266.6
5
6
7
8
250.0 333.3
300.0 400.0
350.0 466.6
400.0 533.3
4
4
4
4
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
0010_100
0010_101
0010_110
75.0 100.0
75.0 100.0
75.0 100.0
4
4
4
300.0 400.0
300.0 400.0
300.0 400.0
5
5.5
6
375.0 500.0
412.5 549.9
450.0 599.9
6
6
6
50.0 66.7
50.0 66.7
50.0 66.7
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
23
Clock Configuration Modes
1,2
Table 15. Clock Configurations for PCI Host Mode (PCI_MODCK=0) (Continued)
4
Bus Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
PCI Clock
(MHz)
3
Mode
CPM
CPU
PCI
Multiplication
Multiplication
Division
Factor
5
6
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
0011_000
0011_001
0011_010
0011_011
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
5
5
5
5
250.0 333.3
250.0 333.3
250.0 333.3
250.0 333.3
5
6
7
8
250.0 333.3
300.0 400.0
350.0 466.6
400.0 533.3
5
5
5
5
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
0100_000
0100_001
0100_010
0100_011
Reserved
50.0 66.7
50.0 66.7
50.0 66.7
6
6
6
300.0 400.0
300.0 400.0
300.0 400.0
6
7
8
300.0 400.0
350.0 466.6
400.0 533.3
6
6
6
50.0 66.7
50.0 66.7
50.0 66.7
0101_000
0101_001
0101_010
0101_011
0101_100
50.0 66.7
50.0 66.7
2
2
100.0 133.3
100.0 133.3
2.5
3
125.0 166.7
150.0 200.0
2
2
50.0 66.7
50.0 66.7
PCI host mode (PCI_MODCK=1) only (refer to Table 16)
62.5 66.7
55.6 66.7
2
2
125.0 133.3
111.1 133.3
4
250.0 266.6
250.0 300.0
2
2
62.5 66.7
55.6 66.7
4.5
0110_000
0110_001
0110_010
0110_011
0110_100
0110_101
0110_110
60.0 80.0
60.0 80.0
71.4 80.0
62.5 80.0
60.0 80.0
60.0 80.0
60.0 80.0
2.5
2.5
2.5
2.5
2.5
2.5
2.5
150.0 200.0
150.0 200.0
178.6 200.0
156.3 200.0
150.0 200.0
150.0 200.0
150.0 200.0
2.5
3
150.0 200.0
180.0 240.0
250.0 280.0
250.0 320.0
270.0 360.0
300.0 400.0
360.0 480.0
3
3
3
3
3
3
3
50.0 66.7
50.0 66.7
59.5 66.7
52.1 66.7
50.0 66.7
50.0 66.7
50.0 66.7
3.5
4
4.5
5
6
0111_000
0111_001
0111_010
0111_011
0111_100
Reserved
3
50.0 66.7
3
150.0 200.0
150.0 200.0
3
50.0 66.7
PCI host mode (PCI_MODCK=1) only (refer to Table 16)
62.5 66.7
55.6 66.7
3
3
187.5 200.0
166.7 200.0
4
250.0 266.6
250.0 300.0
3
3
62.5 66.7
55.6 66.7
4.5
1000_000
1000_001
1000_010
Reserved
66.7 88.9
71.4 88.9
3
3
200.0 266.6
214.3 266.6
3
200.0 266.6
250.0 311.1
4
4
50.0 66.7
53.6 66.7
3.5
24
MPC8280HardwareSpecifications
MOTOROLA
Clock Configuration Modes
1,2
Table 15. Clock Configurations for PCI Host Mode (PCI_MODCK=0) (Continued)
4
Bus Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
PCI Clock
(MHz)
3
Mode
CPM
CPU
PCI
Multiplication
Multiplication
Division
Factor
5
6
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
1000_011
1000_100
1000_101
1000_110
66.7 88.9
66.7 88.9
66.7 88.9
66.7 88.9
3
3
3
3
200.0 266.6
200.0 266.6
200.0 266.6
200.0 266.6
4
266.7 355.5
300.0 400.0
400.0 533.3
433.3 577.7
4
4
4
4
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
4.5
6
6.5
1001_000
1001_001
1001_010
1001_011
1001_100
57.1 76.2
57.1 76.2
71.4 76.2
62.5 76.2
57.1 76.2
3.5
3.5
3.5
3.5
3.5
200.0 266.6
200.0 266.6
250.0 266.6
218.8 266.6
200.0 266.6
2.5
3
142.9 190.5
171.4 228.5
250.0 266.6
250.0 304.7
257.1 342.8
4
4
4
4
4
50.0 66.7
50.0 66.7
62.5 66.7
54.7 66.7
50.0 66.7
3.5
4
4.5
1001_101
1001_110
1001_111
85.7 114.3
85.7 114.3
85.7 114.3
3.5
3.5
3.5
300.0 400.0
300.0 400.0
300.0 400.0
5
5.5
6
428.6 571.4
471.4 628.5
514.3 685.6
6
6
6
50.0 66.7
50.0 66.7
50.0 66.7
1010_000
1010_001
1010_010
1010_011
1010_100
75.0 100.0
75.0 100.0
75.0 100.0
75.0 100.0
75.0 100.0
2
2
2
2
2
150.0 200.0
150.0 200.0
150.0 200.0
150.0 200.0
150.0 200.0
2
2.5
3
150.0 200.0
187.5 250.0
225.0 300.0
262.5 350.0
300.0 400.0
3
3
3
3
3
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
3.5
4
1011_000
1011_001
1011_010
1011_011
1011_100
1011_101
Reserved
80.0 106.7
80.0 106.7
80.0 106.7
80.0 106.7
80.0 106.7
2.5
2.5
2.5
2.5
2.5
200.0 266.6
200.0 266.6
200.0 266.6
200.0 266.6
200.0 266.6
2.5
3
200.0 266.6
240.0 320.0
280.0 373.3
320.0 426.6
360.0 480.0
4
4
4
4
4
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
3.5
4
4.5
1101_000
1101_001
1101_010
1101_011
1101_100
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
2.5
2.5
2.5
2.5
2.5
250.0 333.3
250.0 333.3
250.0 333.3
250.0 333.3
250.0 333.3
3
3.5
4
300.0 400.0
350.0 466.6
400.0 533.3
450.0 599.9
500.0 666.6
5
5
5
5
5
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
4.5
5
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
25
Clock Configuration Modes
1,2
Table 15. Clock Configurations for PCI Host Mode (PCI_MODCK=0) (Continued)
4
Bus Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
PCI Clock
(MHz)
3
Mode
CPM
CPU
PCI
Multiplication
Multiplication
Division
Factor
5
6
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
1101_101
1101_110
125.0 166.7
125.0 166.7
2
2
250.0 333.3
250.0 333.3
3
4
375.0 500.0
500.0 666.6
5
5
50.0 66.7
50.0 66.7
1110_000
1110_001
1110_010
1110_011
1110_100
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
3
3
3
3
3
300.0 400.0
300.0 400.0
300.0 400.0
300.0 400.0
300.0 400.0
3.5
4
350.0 466.6
400.0 533.3
450.0 599.9
500.0 666.6
550.0 733.3
6
6
6
6
6
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
4.5
5
5.5
1100_000
1100_001
1100_010
Reserved
Reserved
Reserved
1
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency
guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock
mode. For modes with a CPU multiplication factor ≤ 3, the minimum CPU frequency is 125 MHz or 150 MHz, as
shown in the table. For modes with a CPU multiplication factor ≥ 3.5, the minimum CPU frequency is 250 MHz.
The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that
the resulting configuration does not exceed the frequency rating of the user’s device.
As shown in Table 13, PCI_MODCK determines the PCI clock frequency range. Refer to Table 16 for lower range
configurations.
MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual).
MODCK[1-3] = three hardware configuration pins.
60x and local bus frequency. Identical to CLKIN.
CPM multiplication factor = CPM clock/bus clock
CPU multiplication factor = Core PLL multiplication factor
2
3
4
5
6
1,2
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=1)
4
Bus Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
PCI Clock
(MHz)
3
Mode
CPM
CPU
PCI
Multiplication
Multiplication
Division
Factor
5
6
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
Default Modes (MODCK_H=0000)
0000_000
0000_001
0000_010
0000_011
0000_100
50.0 100.0
50.0 100.0
60.0 120.0
71.4 120.0
62.5 120.0
2
100.0 200.0
100.0 200.0
150.0 300.0
178.6 300.0
156.3 300.0
2.5
3
125.0 250.0
150.0 300.0
180.0 360.0
250.0 420.0
250.0 480.0
4
4
6
6
6
25.0 50.0
25.0 50.0
25.0 50.0
29.8 50.0
26.0 50.0
2
2.5
2.5
2.5
3
3.5
4
26
MPC8280HardwareSpecifications
MOTOROLA
Clock Configuration Modes
1,2
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=1) (Continued)
4
Bus Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
PCI Clock
(MHz)
3
Mode
CPM
CPU
PCI
Multiplication
Multiplication
Division
Factor
5
6
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
0000_101
0000_110
0000_111
50.0 100.0
71.4 100.0
62.5 100.0
3
3
3
150.0 300.0
214.3 300.0
187.5 300.0
3
3.5
4
150.0 300.0
250.0 350.0
250.0 400.0
6
6
6
25.0 50.0
35.7 50.0
31.3 50.0
Full Configuration Modes
0001_000
0001_001
0001_010
0001_011
50.0 100.0
50.0 100.0
50.0 100.0
50.0 100.0
3
3
3
3
150.0 300.0
150.0 300.0
150.0 300.0
150.0 300.0
5
6
7
8
250.0 500.0
300.0 600.0
350.0 700.0
400.0 800.0
6
6
6
6
25.0 50.0
25.0 50.0
25.0 50.0
25.0 50.0
0010_000
0010_001
0010_010
0010_011
50.0 100.0
50.0 100.0
50.0 100.0
50.0 100.0
4
4
4
4
200.0 400.0
200.0 400.0
200.0 400.0
200.0 400.0
5
6
7
8
250.0 500.0
300.0 600.0
350.0 700.0
400.0 800.0
8
8
8
8
25.0 50.0
25.0 50.0
25.0 50.0
25.0 50.0
0010_100
0010_101
0010_110
50.0 75.0
45.5 75.0
41.7 75.0
4
4
4
200.0 300.0
181.8 300.0
166.7 300.0
5
5.5
6
250.0 375.0
250.0 412.5
250.0 450.0
6
6
6
33.3 50.0
30.3 50.0
27.8 50.0
0011_000
0011_001
0011_010
0011_011
50.0 50.0
41.7 50.0
35.7 50.0
31.3 50.0
5
5
5
5
250.0 250.0
208.3 250.0
178.6 250.0
156.3 250.0
5
6
7
8
250.0 250.0
250.0 300.0
250.0 350.0
250.0 400.0
5
5
5
5
50.0 50.0
41.7 50.0
35.7 50.0
31.3 50.0
0100_000
0100_001
0100_010
0100_011
Reserved
41.7 50.0
35.7 50.0
31.3 50.0
6
6
6
250.0 300.0
214.3 300.0
187.5 300.0
6
7
8
250.0 300.0
250.0 350.0
250.0 400.0
6
6
6
41.7 50.0
35.7 50.0
31.3 50.0
0101_000
0101_001
0101_010
0101_011
0101_100
50.0 100.0
50.0 100.0
71.4 100.0
62.5 100.0
55.6 100.0
2
2
2
2
2
100.0 200.0
100.0 200.0
142.9 200.0
125.0 200.0
111.1 200.0
2.5
3
125.0 250.0
150.0 300.0
250.0 350.0
250.0 400.0
250.0 450.0
4
4
4
4
4
25.0 50.0
25.0 50.0
35.7 50.0
31.3 50.0
27.8 50.0
3.5
4
4.5
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
27
Clock Configuration Modes
1,2
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=1) (Continued)
4
Bus Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
PCI Clock
(MHz)
3
Mode
CPM
CPU
PCI
Multiplication
Multiplication
Division
Factor
5
6
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
0110_000
0110_001
0110_010
0110_011
0110_100
0110_101
0110_110
60.0 120.0
60.0 120.0
71.4 120.0
62.5 120.0
60.0 120.0
60.0 120.0
60.0 120.0
2.5
2.5
2.5
2.5
2.5
2.5
2.5
150.0 300.0
150.0 300.0
178.6 300.0
156.3 300.0
150.0 300.0
150.0 300.0
150.0 300.0
2.5
3
150.0 300.0
180.0 360.0
250.0 420.0
250.0 480.0
270.0 540.0
300.0 600.0
360.0 720.0
6
6
6
6
6
6
6
25.0 50.0
25.0 50.0
29.8 50.0
26.0 50.0
25.0 50.0
25.0 50.0
25.0 50.0
3.5
4
4.5
5
6
0111_000
0111_001
0111_010
0111_011
0111_100
Reserved
50.0 100.0
71.4 100.0
62.5 100.0
55.6 100.0
3
3
3
3
150.0 300.0
214.3 300.0
187.5 300.0
166.7 300.0
3
150.0 300.0
250.0 350.0
250.0 400.0
250.0 450.0
6
6
6
6
25.0 50.0
35.7 50.0
31.3 50.0
27.8 50.0
3.5
4
4.5
1000_000
1000_001
1000_010
1000_011
1000_100
1000_101
1000_110
Reserved
66.7 133.3
71.4 133.3
66.7 133.3
66.7 133.3
66.7 133.3
66.7 133.3
3
3
3
3
3
3
200.0 400.0
214.3 400.0
200.0 400.0
200.0 400.0
200.0 400.0
200.0 400.0
3
3.5
4
200.0 400.0
250.0 466.7
266.7 533.3
300.0 600.0
400.0 800.0
433.3 866.7
8
8
8
8
8
8
25.0 50.0
26.8 50.0
25.0 50.0
25.0 50.0
25.0 50.0
25.0 50.0
4.5
6
6.5
1001_000
1001_001
1001_010
1001_011
1001_100
Reserved
Reserved
71.4 114.3
62.5 114.3
57.1 114.3
3.5
3.5
3.5
250.0 400.0
218.8 400.0
200.0 400.0
3.5
4
250.0 400.0
250.0 457.1
257.1 514.3
8
8
8
31.3 50.0
27.3 50.0
25.0 50.0
4.5
1001_101
1001_110
1001_111
50.0 85.7
45.5 85.7
42.9 85.7
3.5
3.5
3.5
175.0 300.0
159.1 300.0
150.0 300.0
5
5.5
6
250.0 428.6
250.0 471.4
257.1 514.3
6
6
6
29.2 50.0
26.5 50.0
25.0 50.0
28
MPC8280HardwareSpecifications
MOTOROLA
Clock Configuration Modes
1,2
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=1) (Continued)
4
Bus Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
PCI Clock
(MHz)
3
Mode
CPM
CPU
PCI
Multiplication
Multiplication
Division
Factor
5
6
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
1010_000
1010_001
1010_010
1010_011
1010_100
75.0 150.0
75.0 150.0
75.0 150.0
75.0 150.0
75.0 150.0
2
2
2
2
2
150.0 300.0
150.0 300.0
150.0 300.0
150.0 300.0
150.0 300.0
2
2.5
3
150.0 300.0
187.5 375.0
225.0 450.0
262.5 525.0
300.0 600.0
6
6
6
6
6
25.0 50.0
25.0 50.0
25.0 50.0
25.0 50.0
25.0 50.0
3.5
4
1011_000
1011_001
1011_010
1011_011
1011_100
1011_101
Reserved
80.0 160.0
80.0 160.0
80.0 160.0
80.0 160.0
80.0 160.0
2.5
2.5
2.5
2.5
2.5
200.0 400.0
200.0 400.0
200.0 400.0
200.0 400.0
200.0 400.0
2.5
3
200.0 400.0
240.0 480.0
280.0 560.0
320.0 640.0
360.0 720.0
8
8
8
8
8
25.0 50.0
25.0 50.0
25.0 50.0
25.0 50.0
25.0 50.0
3.5
4
4.5
1101_000
1101_001
1101_010
1101_011
1101_100
50.0 100.0
71.4 100.0
62.5 100.0
55.6 100.0
50.0 100.0
2.5
2.5
2.5
2.5
2.5
125.0 250.0
178.6 250.0
156.3 250.0
138.9 250.0
125.0 250.0
3
3.5
4
150.0 300.0
250.0 350.0
250.0 400.0
250.0 450.0
250.0 500.0
5
5
5
5
5
25.0 50.0
35.7 50.0
31.3 50.0
27.8 50.0
25.0 50.0
4.5
5
1101_101
1101_110
62.5 125.0
62.5 125.0
2
2
125.0 250.0
125.0 250.0
3
4
187.5 375.0
250.0 500.0
5
5
25.0 50.0
25.0 50.0
1110_000
1110_001
1110_010
1110_011
1110_100
71.4 100.0
62.5 100.0
55.6 100.0
50.0 100.0
50.0 100.0
3
3
3
3
3
214.3 300.0
187.5 300.0
166.7 300.0
150.0 300.0
150.0 300.0
3.5
4
250.0 350.0
250.0 400.0
250.0 450.0
250.0 500.0
275.0 550.0
6
6
6
6
6
35.7 50.0
31.3 50.0
27.8 50.0
25.0 50.0
25.0 50.0
4.5
5
5.5
1100_000
1100_001
1100_010
Reserved
Reserved
Reserved
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
29
Clock Configuration Modes
1
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency
guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock
mode. For modes with a CPU multiplication factor ≤ 3, the minimum CPU frequency is 125 MHz or 150 MHz, as
shown in the table. For modes with a CPU multiplication factor ≥ 3.5, the minimum CPU frequency is 250 MHz.
The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that
the resulting configuration does not exceed the frequency rating of the user’s device.
As shown in Table 13, PCI_MODCK determines the PCI clock frequency range. Refer to Table 15 for higher range
configurations.
MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual).
MODCK[1-3] = three hardware configuration pins.
60x and local bus frequency. Identical to CLKIN.
CPM multiplication factor = CPM clock/bus clock
CPU multiplication factor = Core PLL multiplication factor
2
3
4
5
6
1.3.2.2 PCI Agent Mode
Table 17 and Table 18 show configurations for PCI agent mode. The frequencies listed are for the purpose
of illustration only. Users must select a mode and input bus frequency so that the resulting configuration
does not exceed the frequency rating of the user’s device.
1,2
Table 17. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)
PCI Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
Bus Clock
(MHz)
3
Mode
CPM
CPU
Bus
Multiplication
Multiplication
Division
Factor
4
5
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
Default Modes (MODCK_H=0000
0000_000
0000_001
0000_010
0000_011
0000_100
0000_101
0000_110
0000_111
50.0 66.7
50.0 66.7
50.0 66.7
62.5 66.7
50.0 66.7
59.5 66.7
53.6 66.7
50.0 66.7
2
2
3
3
3
3
4
4
100.0 133.3
100.0 133.3
150.0 200.0
187.5 200.0
150.0 200.0
178.6 200.0
214.3 266.6
200.0 266.6
2.5
3
125.0 166.7
150.0 200.0
150.0 200.0
250.0 266.6
180.0 240.0
250.0 280.0
250.0 311.1
240.0 320.0
2
2
50.0 66.7
50.0 66.7
50.0 66.7
62.5 66.7
60.0 80.0
71.4 80.0
71.4 88.9
80.0 106.7
3
3
4
3
3
2.5
2.5
3
3.5
3.5
3
2.5
Full Configuration Modes
0001_001
0001_010
0001_011
0001_100
Reserved
Reserved
Reserved
62.5 66.7
2
125.0 133.3
8
250.0 266.6
4
31.3 33.3
0010_001
0010_010
0010_011
0010_100
50.0 66.7
59.5 66.7
52.1 66.7
50.0 66.7
3
3
3
3
150.0 200.0
178.6 200.0
156.3 200.0
150.0 200.0
3
180.0 240.0
250.0 280.0
250.0 320.0
270.0 360.0
2.5
2.5
2.5
2.5
60.0 80.0
71.4 80.0
62.5 80.0
60.0 80.0
3.5
4
4.5
30
MPC8280HardwareSpecifications
MOTOROLA
Clock Configuration Modes
1,2
Table 17. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) (Continued)
PCI Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
Bus Clock
(MHz)
3
Mode
CPM
CPU
Bus
Multiplication
Multiplication
Division
Factor
4
5
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
0011_000
0011_001
0011_010
0011_011
0011_100
Reserved
Reserved
Reserved
Reserved
Reserved
0100_000
0100_001
0100_010
0100_011
0100_100
Reserved
50.0 66.7
3
150.0 200.0
3
150.0 200.0
3
50.0 66.7
Reserved
62.5 66.7
55.6 66.7
3
3
187.5 200.0
166.7 200.0
4
250.0 266.6
250.0 300.0
3
3
62.5 66.7
55.6 66.7
4.5
0101_000
0101_001
0101_010
0101_011
0101_100
0101_101
0101_110
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
5
5
5
5
5
5
5
250.0 333.3
250.0 333.3
250.0 333.3
250.0 333.3
250.0 333.3
250.0 333.3
250.0 333.3
2.5
3
250.0 333.3
300.0 400.0
350.0 466.6
400.0 533.3
450.0 599.9
500.0 666.6
550.0 733.3
2.5
2.5
2.5
2.5
2.5
2.5
2.5
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
3.5
4
4.5
5
5.5
0110_000
0110_001
0110_010
0110_011
0110_100
Reserved
50.0 66.7
53.6 66.7
50.0 66.7
50.0 66.7
4
4
4
4
200.0 266.6
214.3 266.6
200.0 266.6
200.0 266.6
3
200.0 266.6
250.0 311.1
266.7 355.5
300.0 400.0
3
3
3
3
66.7 88.9
71.4 88.9
66.7 88.9
66.7 88.9
3.5
4
4.5
0111_000
0111_001
0111_010
0111_011
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
3
3
3
3
150.0 200.0
150.0 200.0
150.0 200.0
150.0 200.0
2
150.0 200.0
187.5 250.0
225.0 300.0
262.5 350.0
2
2
2
2
75.0 100.0
75.0 100.0
75.0 100.0
75.0 100.0
2.5
3
3.5
1000_000
Reserved
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
31
Clock Configuration Modes
Table 17. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) (Continued)
1,2
PCI Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
Bus Clock
(MHz)
3
Mode
CPM
CPU
Bus
Multiplication
Multiplication
Division
Factor
4
5
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
1000_001
1000_010
1000_011
1000_100
1000_101
50.0 66.7
50.0 66.7
59.5 66.7
52.1 66.7
50.0 66.7
3
3
3
3
3
150.0 200.0
150.0 200.0
178.6 200.0
156.3 200.0
150.0 200.0
2.5
3
150.0 200.0
180.0 240.0
250.0 280.0
250.0 320.0
270.0 360.0
2.5
2.5
2.5
2.5
2.5
60.0 80.0
60.0 80.0
71.4 80.0
62.5 80.0
60.0 80.0
3.5
4
4.5
1001_000
1001_001
1001_010
1001_011
1001_100
Reserved
Reserved
Reserved
4
62.5 66.7
55.6 66.7
4
4
250.0 266.6
222.2 266.6
250.0 266.6
250.0 300.0
4
4
62.5 66.7
55.6 66.7
4.5
1010_000
1010_001
1010_010
1010_011
1010_100
Reserved
50.0 66.7
53.6 66.7
50.0 66.7
50.0 66.7
4
4
4
4
200.0 266.6
214.3 266.6
200.0 266.6
200.0 266.6
3
200.0 266.6
250.0 311.1
266.7 355.5
300.0 400.0
3
3
3
3
66.7 88.9
71.4 88.9
66.7 88.9
66.7 88.9
3.5
4
4.5
1011_000
1011_001
1011_010
1011_011
1011_100
Reserved
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
4
4
4
4
200.0 266.6
200.0 266.6
200.0 266.6
200.0 266.6
2.5
3
200.0 266.6
240.0 320.0
280.0 373.3
320.0 426.6
2.5
2.5
2.5
2.5
80.0 106.7
80.0 106.7
80.0 106.7
80.0 106.7
3.5
4
1100_101
1100_110
1100_111
1101_000
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
6
6
6
6
300.0 400.0
300.0 400.0
300.0 400.0
300.0 400.0
4
400.0 533.3
450.0 599.9
500.0 666.6
550.0 733.3
3
3
3
3
100.0 133.3
100.0 133.3
100.0 133.3
100.0 133.3
4.5
5
5.5
1101_001
1101_010
1101_011
1101_100
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
6
6
6
6
300.0 400.0
300.0 400.0
300.0 400.0
300.0 400.0
3.5
4
420.0 559.9
480.0 639.9
540.0 719.9
600.0 799.9
2.5
2.5
2.5
2.5
120.0 160.0
120.0 160.0
120.0 160.0
120.0 160.0
4.5
5
32
MPC8280HardwareSpecifications
MOTOROLA
Clock Configuration Modes
1,2
Table 17. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) (Continued)
PCI Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
Bus Clock
(MHz)
3
Mode
CPM
CPU
Bus
Multiplication
Multiplication
Division
Factor
4
5
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
1110_000
1110_001
1110_010
1110_011
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
5
5
5
5
250.0 333.3
250.0 333.3
250.0 333.3
250.0 333.3
2.5
3
312.5 416.6
375.0 500.0
437.5 583.3
500.0 666.6
2
2
2
2
125.0 166.7
125.0 166.7
125.0 166.7
125.0 166.7
3.5
4
1110_100
1110_101
1110_110
1110_111
50.0 66.7
50.0 66.7
50.0 66.7
50.0 66.7
5
5
5
5
250.0 333.3
250.0 333.3
250.0 333.3
250.0 333.3
4
333.3 444.4
375.0 500.0
416.7 555.5
458.3 611.1
3
3
3
3
83.3 111.1
83.3 111.1
83.3 111.1
83.3 111.1
4.5
5
5.5
1100_000
1100_001
1100_010
Reserved
Reserved
Reserved
1
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency
guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock
mode. For modes with a CPU multiplication factor ≤ 3, the minimum CPU frequency is 125 MHz or 150 MHz, as
shown in the table. For modes with a CPU multiplication factor ≥ 3.5, the minimum CPU frequency is 250 MHz.
The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that
the resulting configuration does not exceed the frequency rating of the user’s device.
As shown in Table 13, PCI_MODCK determines the PCI clock frequency range. Refer to Table 18 for lower range
configurations.
2
3
MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual).
MODCK[1-3] = three hardware configuration pins.
CPM multiplication factor = CPM clock/bus clock
4
5
CPU multiplication factor = Core PLL multiplication factor
1,2
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)
PCI Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
Bus Clock
(MHz)
3
Mode
CPM
CPU
Bus
Multiplication
Multiplication
Division
Factor
4
5
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
Default Modes (MODCK_H=0000)
0000_000
0000_001
0000_010
0000_011
25.0 50.0
25.0 50.0
25.0 50.0
31.3 50.0
4
4
6
6
100.0 200.0
100.0 200.0
150.0 300.0
187.5 300.0
2.5
3
125.0 250.0
150.0 300.0
150.0 300.0
250.0 400.0
2
2
3
3
50.0 100.0
50.0 100.0
50.0 100.0
62.5 100.0
3
4
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
33
Clock Configuration Modes
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) (Continued)
1,2
PCI Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
Bus Clock
(MHz)
3
Mode
CPM
CPU
Bus
Multiplication
Multiplication
Division
Factor
4
5
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
0000_100
0000_101
0000_110
0000_111
25.0 50.0
29.8 50.0
26.8 50.0
25.0 50.0
6
6
8
8
150.0 300.0
178.6 300.0
214.3 400.0
200.0 400.0
3
180.0 360.0
250.0 420.0
250.0 466.7
240.0 480.0
2.5
2.5
3
60.0 120.0
71.4 120.0
71.4 133.3
80.0 160.0
3.5
3.5
3
2.5
Full Configuration Modes
0001_001
0001_010
0001_011
0001_100
50.0 50.0
41.7 50.0
35.7 50.0
31.3 50.0
4
4
4
4
200.0 200.0
166.7 200.0
142.9 200.0
125.0 200.0
5
6
7
8
250.0 250.0
250.0 300.0
250.0 350.0
250.0 400.0
4
4
4
4
50.0 50.0
41.7 50.0
35.7 50.0
31.3 50.0
0010_001
0010_010
0010_011
0010_100
25.0 50.0
29.8 50.0
26.0 50.0
25.0 50.0
6
6
6
6
150.0 300.0
178.6 300.0
156.3 300.0
150.0 300.0
3
180.0 360.0
250.0 420.0
250.0 480.0
270.0 540.0
2.5
2.5
2.5
2.5
60.0 120.0
71.4 120.0
62.5 120.0
60.0 120.0
3.5
4
4.5
0011_000
0011_001
0011_010
0011_011
0011_100
Reserved
31.3 50.0
4
125.0 200.0
2.5
Reserved
4
104.3 166.7
3
41.7 66.7
46.9 50.0
41.7 50.0
4
4
187.5 200.0
166.7 200.0
250.0 266.7
250.0 300.0
3
3
62.5 66.7
55.6 66.7
4.5
0100_000
0100_001
0100_010
0100_011
0100_100
Reserved
25.0 50.0
35.7 50.0
31.3 50.0
27.8 50.0
6
6
6
6
150.0 300.0
214.3 300.0
187.5 300.0
166.7 300.0
3
150.0 300.0
250.0 350.0
250.0 400.0
250.0 450.0
3
3
3
3
50.0 100.0
71.4 100.0
62.5 100.0
55.6 100.0
3.5
4
4.5
0101_000
0101_001
0101_010
0101_011
0101_100
0101_101
25.0 50.0
25.0 50.0
35.7 50.0
31.3 50.0
27.8 50.0
25.0 50.0
5
5
5
5
5
5
125.0 250.0
125.0 250.0
178.6 250.0
156.3 250.0
138.9 250.0
125.0 250.0
2.5
3
125.0 250.0
150.0 300.0
250.0 350.0
250.0 400.0
250.0 450.0
250.0 500.0
2.5
2.5
2.5
2.5
2.5
2.5
50.0 100.0
50.0 100.0
71.4 100.0
62.5 100.0
55.6 100.0
50.0 100.0
3.5
4
4.5
5
34
MPC8280HardwareSpecifications
MOTOROLA
Clock Configuration Modes
1,2
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) (Continued)
PCI Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
Bus Clock
(MHz)
3
Mode
CPM
CPU
Bus
Multiplication
Multiplication
Division
Factor
4
5
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
0101_110
25.0 50.0
5
125.0 250.0
5.5
275.0 550.0
2.5
50.0 100.0
0110_000
0110_001
0110_010
0110_011
0110_100
Reserved
25.0 50.0
26.8 50.0
25.0 50.0
25.0 50.0
8
8
8
8
200.0 400.0
214.3 400.0
200.0 400.0
200.0 400.0
3
200.0 400.0
250.0 466.7
266.7 533.3
300.0 600.0
3
3
3
3
66.7 133.3
71.4 133.3
66.7 133.3
66.7 133.3
3.5
4
4.5
0111_000
0111_001
0111_010
0111_011
25.0 50.0
25.0 50.0
25.0 50.0
25.0 50.0
6
6
6
6
150.0 300.0
150.0 300.0
150.0 300.0
150.0 300.0
2
150.0 300.0
187.5 375.0
225.0 450.0
262.5 525.0
2
2
2
2
75.0 150.0
75.0 150.0
75.0 150.0
75.0 150.0
2.5
3
3.5
1000_000
1000_001
1000_010
1000_011
1000_100
1000_101
Reserved
25.0 50.0
25.0 50.0
29.8 50.0
26.0 50.0
25.0 50.0
6
6
6
6
6
150.0 300.0
150.0 300.0
178.6 300.0
156.3 300.0
150.0 300.0
2.5
3
150.0 300.0
180.0 360.0
250.0 420.0
250.0 480.0
270.0 540.0
2.5
2.5
2.5
2.5
2.5
60.0 120.0
60.0 120.0
71.4 120.0
62.5 120.0
60.0 120.0
3.5
4
4.5
1001_000
1001_001
1001_010
1001_011
1001_100
Reserved
Reserved
Reserved
4
31.3 50.0
27.8 50.0
8
8
250.0 400.0
222.2 400.0
250.0 400.0
250.0 450.0
4
4
62.5 100.0
55.6 100.0
4.5
1010_000
1010_001
1010_010
1010_011
1010_100
Reserved
25.0 50.0
26.8 50.0
25.0 50.0
25.0 50.0
8
8
8
8
200.0 400.0
214.3 400.0
200.0 400.0
200.0 400.0
3
200.0 400.0
250.0 466.7
266.7 533.3
300.0 600.0
3
3
3
3
66.7 133.3
71.4 133.3
66.7 133.3
66.7 133.3
3.5
4
4.5
1011_000
Reserved
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
35
Clock Configuration Modes
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) (Continued)
1,2
PCI Clock
(MHz)
CPM Clock
(MHz)
CPU Clock
(MHz)
Bus Clock
(MHz)
3
Mode
CPM
CPU
Bus
Multiplication
Multiplication
Division
Factor
4
5
MODCK_H-
MODCK[1-3]
Factor
Factor
low high
low high
low high
low high
1011_001
1011_010
1011_011
1011_100
25.0 50.0
25.0 50.0
25.0 50.0
25.0 50.0
8
8
8
8
200.0 400.0
200.0 400.0
200.0 400.0
200.0 400.0
2.5
3
200.0 400.0
240.0 480.0
280.0 560.0
320.0 640.0
2.5
2.5
2.5
2.5
80.0 160.0
80.0 160.0
80.0 160.0
80.0 160.0
3.5
4
1100_101
1100_110
1100_111
1101_000
31.3 50.0
27.8 50.0
25.0 50.0
25.0 50.0
6
6
6
6
187.5 300.0
166.7 300.0
150.0 300.0
150.0 300.0
4
250.0 400.0
250.0 450.0
250.0 500.0
275.0 550.0
3
3
3
3
62.5 100.0
55.6 100.0
50.0 100.0
50.0 100.0
4.5
5
5.5
1101_001
1101_010
1101_011
1101_100
29.8 50.0
26.0 50.0
25.0 50.0
25.0 50.0
6
6
6
6
178.6 300.0
156.3 300.0
150.0 300.0
150.0 300.0
3.5
4
250.0 420.0
250.0 480.0
270.0 540.0
300.0 600.0
2.5
2.5
2.5
2.5
71.4 120.0
62.5 120.0
60.0 120.0
60.0 120.0
4.5
5
1110_000
1110_001
1110_010
1110_011
25.0 50.0
25.0 50.0
28.6 50.0
25.0 50.0
5
5
5
5
125.0 250.0
125.0 250.0
142.9 250.0
125.0 250.0
2.5
3
156.3 312.5
187.5 375.0
250.0 437.5
250.0 500.0
2
2
2
2
62.5 125.0
62.5 125.0
71.4 125.0
62.5 125.0
3.5
4
1110_100
1110_101
1110_110
1110_111
37.5 50.0
33.3 50.0
30.0 50.0
27.3 50.0
5
5
5
5
187.5 250.0
166.7 250.0
150.0 250.0
136.4 250.0
4
250.0 333.3
250.0 375.0
250.0 416.7
250.0 458.3
3
3
3
3
62.5 83.3
55.6 83.3
50.0 83.3
45.5 83.3
4.5
5
5.5
1100_000
1100_001
1100_010
Reserved
Reserved
Reserved
1
2
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency
guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock
mode. For modes with a CPU multiplication factor ≤ 3, the minimum CPU frequency is 125 MHz or 150 MHz, as
shown in the table. For modes with a CPU multiplication factor ≥ 3.5, the minimum CPU frequency is 250 MHz.
The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that
the resulting configuration does not exceed the frequency rating of the user’s device.
As shown in Table 13, PCI_MODCK determines the PCI clock range. Refer to Table 17 for higher range
configurations.
36
MPC8280HardwareSpecifications
MOTOROLA
Pinout
3
MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual).
MODCK[1-3] = three hardware configuration pins.
CPM multiplication factor = CPM clock/bus clock
4
5
CPU multiplication factor = Core PLL multiplication factor
1.4 Pinout
This section provides the pin assignments and pinout lists for both HiP7 PowerQUICC II packages.
1.4.1 ZU Package—MPC8280 and MPC8270
The following figures and table represent the standard 480 TBGA package. For information on the alternate
package, refer to Section 1.4.2, “VR Package—MPC8275VR and MPC8270VR” on page 52.
1.4.1.1 ZU Pin Assignments
Figure 13 shows the pinout of the ZU package as viewed from the top surface.
MOTOROLA
MPC8280HardwareSpecifications
37
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
A
B
A
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AA
AB
AC
AD
AE
AF
AG
AH
AJ
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Not to Scale
Figure 13. Pinout of the 480 TBGA Package (View from Top)
Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view.
View
Pressure Sensitive
Copper Heat Spreader
(Oxidized for Insulation)
Adhesive
Etched
Cavity
Die
Attach
Polymide Tape
Die
Glob-Top Filled Area
Soldermask
Glob-Top Dam
Copper Traces
1.27 mm Pitch
Wire Bonds
Figure 14. Side View of the TBGA Package
MPC8280HardwareSpecifications
38
MOTOROLA
Pinout
Table 19 shows the pinout list of the MPC8280 and MPC8270. Table 20 defines conventions and acronyms
used in Table 19.
Table 19. MPC8280 and MPC8270 Pinout List
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
BR
BG
W5
F4
E2
E3
G1
H5
H2
H1
J5
ABB/IRQ2
TS
A0
A1
A2
A3
A4
A5
J4
A6
J3
A7
J2
A8
J1
A9
K4
K3
K2
K1
L5
L4
L3
L2
L1
M5
N5
N4
N3
N2
N1
P4
P3
P2
P1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
MOTOROLA
MPC8280HardwareSpecifications
39
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
A28
A29
A30
A31
TT0
TT1
TT2
TT3
TT4
TBST
TSIZ0
TSIZ1
TSIZ2
TSIZ3
AACK
ARTRY
DBG
DBB/IRQ3
D0
R1
R3
R5
R4
F1
G4
G3
G2
F2
D3
C1
E4
D2
F5
F3
E1
V1
V2
B20
A18
A16
A13
E12
D9
D1
D2
D3
D4
D5
D6
A6
D7
B5
D8
A20
E17
B15
B13
A11
E9
D9
D10
D11
D12
D13
D14
D15
B7
B4
40
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D19
D17
D15
C13
B11
A8
A5
C5
C19
C17
C15
D13
C11
B8
A4
E6
E18
B17
A15
A12
D11
C8
E7
A3
D18
A17
A14
B12
A10
D8
B6
C4
C18
E16
MOTOROLA
MPC8280HardwareSpecifications
41
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
D50
B14
C12
B10
A7
D51
D52
D53
D54
C6
D55
D5
D56
B18
B16
E14
D12
C10
E8
D57
D58
D59
D60
D61
D62
D6
D63
C2
DP0/RSRV/EXT_BR2
IRQ1/DP1/EXT_BG2
IRQ2/DP2/TLBISYNC/EXT_DBG2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
IRQ4/DP4/CORE_SRESET/EXT_BG3
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
PSDVAL
B22
A22
E21
D21
C21
B21
A21
E20
V3
TA
C22
V5
TEA
GBL/IRQ1
W1
U2
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
U3
Y4
CPU_BG/BADDR31/IRQ5
CPU_DBG
U4
R2
CPU_BR
Y3
CS0
F25
C29
CS1
42
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
CS2
E27
E28
F26
F27
F28
G25
D29
E29
F29
G28
T5
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10/BCTL1
CS11/AP0
BADDR27
BADDR28
U1
ALE
T2
BCTL0
A27
C25
E24
D24
C24
B26
A26
B25
A25
E23
B24
A24
B23
A23
D22
H28
H27
H26
G29
D27
C28
PWE0/PSDDQM0/PBS0
PWE1/PSDDQM1/PBS1
PWE2/PSDDQM2/PBS2
PWE3/PSDDQM3/PBS3
PWE4/PSDDQM4/PBS4
PWE5/PSDDQM5/PBS5
PWE6/PSDDQM6/PBS6
PWE7/PSDDQM7/PBS7
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE0/LSDDQM0/LBS0/PCI_CFG0
LWE1/LSDDQM1/LBS1/PCI_CFG1
LWE2/LSDDQM2/LBS2/PCI_CFG2
LWE3/LSDDQM3/LBS3/PCI_CFG3
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
MOTOROLA
MPC8280HardwareSpecifications
43
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LGPL5/LSDAMUX/PCI_MODCK
LWR
E26
D25
C26
B27
D28
N27
T29
R27
R26
R29
R28
W29
P28
N26
AA27
P29
AA26
N25
AA25
AB29
AB28
P25
AB27
H29
J29
L_A14/PAR
L_A15/FRAME/SMI
L_A16/TRDY
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTA
L_A30/REQ2
L_A31/DLLOUT
LCL_D0/AD0
LCL_D1/AD1
LCL_D2/AD2
J28
LCL_D3/AD3
J27
LCL_D4/AD4
J26
LCL_D5/AD5
J25
LCL_D6/AD6
K25
L29
LCL_D7/AD7
LCL_D8/AD8
L27
LCL_D9/AD9
L26
LCL_D10/AD10
L25
44
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
LCL_D11/AD11
LCL_D12/AD12
LCL_D13/AD13
LCL_D14/AD14
LCL_D15/AD15
LCL_D16/AD16
LCL_D17/AD17
LCL_D18/AD18
LCL_D19/AD19
LCL_D20/AD20
LCL_D21/AD21
LCL_D22/AD22
LCL_D23/AD23
LCL_D24/AD24
LCL_D25/AD25
LCL_D26/AD26
LCL_D27/AD27
LCL_D28/AD28
LCL_D29/AD29
LCL_D30/AD30
LCL_D31/AD31
LCL_DP0/C0/BE0
LCL_DP1/C1/BE1
LCL_DP2/C2/BE2
LCL_DP3/C3/BE3
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
TRST
M29
M28
M27
M26
N29
T25
U27
U26
U25
V29
V28
V27
V26
W27
W26
W25
Y29
Y28
Y25
AA29
AA28
L28
N28
T28
W28
T1
D1
AH3
AG5
AJ3
AE6
AF5
AB4
AG6
TCK
TMS
TDI
TDO
TRIS
PORESET
MOTOROLA
MPC8280HardwareSpecifications
45
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
HRESET
AH5
AF6
AA3
AJ4
SRESET
QREQ
RSTCONF
MODCK1/AP1/TC0/BNKSEL0
MODCK2/AP2/TC1/BNKSEL1
MODCK3/AP3/TC2/BNKSEL2
CLKIN1
W2
W3
W4
AH4
AC29
AC25
AE28
1
1
1
1
PA0/RESTART1/DREQ3
PA1/REJECT1/DONE3
PA2/CLK20/DACK3
PA3/CLK19/DACK4/L1RXD1A2
PA4/REJECT2/DONE4
PA5/RESTART2/DREQ4
FCC2_UTM_TXADDR2
FCC2_UTM_TXADDR1
FCC2_UTM_TXADDR0
FCC2_UTM_RXADDR0
FCC2_UTM_RXADDR1
AG29
AG28
AG26
1
1
FCC2_UTM_RXADDR2/FCC1_UT_RX
PRTY
1
1
PA6/FCC2_RXADDR3
PA7/SMSYN2/FCC2_TXADDR3
PA8/SMRXD2/FCC2_TXADDR4
PA9/SMTXD2
L1RSYNCA1
AE24
L1TSYNCA1/L1GNTA1
L1RXD0A1/L1RXDA1
AH25
1
AF23
AH23
1
L1TXD0A1
1
PA10/MSNUM5
FCC1_UT8_RXD0/FCC1_UT16_RXD8
FCC1_UT8_RXD1/FCC1_UT16_RXD9
AE22
1
PA11/MSNUM4
AH22
1
PA12/MSNUM3
FCC1_UT8_RXD2/
FCC1_UT16_RXD10
AJ21
AH20
AG19
1
1
PA13/MSNUM2
FCC1_UT8_RXD3/
FCC1_UT16_RXD11
PA14/FCC1_MII_HDLC_RXD3
PA15/FCC1_MII_HDLC_RXD2
FCC1_UT8_RXD4/
FCC1_UT16_RXD12
1
1
1
FCC1_UT8_RXD5/
FCC1_UT16_RXD13
AF18
AF17
PA16/FCC1_MII_HDLC_RXD1/
FCCI_RMII_RXD1
FCC1_UT8_RXD6/
FCC1_UT16_RXD14
PA17/FCC1_MII_HDLC_RXD0/
FCC1_MII_TRAN_RXD/
FCCI_RMII_RXD0
FCC1_UT8_RXD7/
FCC1_UT16_RXD15
AE16
1
PA18/FCC1_MII_HDLC_TXD0/
FCC1_MII_TRAN_TXD/
FCC1_RMII_TXD0
FCC1_UT8_TXD7/FCC1_UT16_TXD15
AJ16
46
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
1
1
PA19/FCC1_MII_HDLC_TXD1/
FCC1_RMII_TXD1
FCC1_UT8_TXD6/FCC1_UT16_TXD14
AG15
1
PA20/FCC1_MII_HDLC_TXD2
PA21/FCC1_MII_HDLC_TXD3
PA22
FCC1_UT8_TXD5/FCC1_UT16_TXD13
FCC1_UT8_TXD4/FCC1_UT16_TXD12
FCC1_UT8_TXD3/FCC1_UT16_TXD11
FCC1_UT8_TXD2/FCC1_UT16_TXD10
FCC1_UT8_TXD1/FCC1_UT16_TXD9
FCC1_UT8_TXD0/FCC1_UT16_TXD8
AJ13
AE13
1
1
AF12
PA23
AG11
1
PA24/MSNUM1
AH9
1
PA25/MSNUM0
AJ8
1
PA26/FCC1_RMII_RX_ER
FCC1_UTM_RXCLAV/
FCC1_UTS_RXCLAV
AH7
1
PA27/FCC1_MII_RX_DV/
FCC1_RMII_CRS_DV
FCC1_UT_RXSOC
AF7
1
PA28/FCC1_MII_TX_EN/
FCC1_RMII_TX_EN
FCC1_UTM_RXENB/
FCC1_UTS_RXENB
AD5
1
PA29/FCC1_MII_TX_ER
FCC1_UT_TXSOC
AF1
AD3
1
PA30/FCC1_MII_CRS/FCC1_RTS
FCC1_UTM_TXCLAV/
FCC1_UTS_TXCLAV
1
PA31/FCC1_MII_COL
FCC1_UTM_TXENB/
FCC1_UTS_TXENB
AB5
1
1
1
PB4/FCC3_MII_HDLC_TXD3/
L1RSYNCA2/FCC3_RTS
FCC2_UT8_RXD0
FCC2_UT8_RXD1
FCC2_UT8_RXD2
AD28
AD26
AD25
PB5/FCC3_MII_HDLC_TXD2/
L1TSYNCA2/L1GNTA2
PB6/FCC3_MII_HDLC_TXD1/
FCC3_RMII_TXD1/
L1RXDA2/L1RXD0A2
1
1
PB7/FCC3_MII_HDLC_TXD0/
FCC3_RMII_TXD0/
FCC3_TXD/L1TXDA2/L1TXD0A2
FCC2_UT8_RXD3
AE26
PB8/FCC3_MII_HDLC_RXD0/
FCC3_RMII_RXD0/
FCC2_UT8_TXD3/L1RSYNCD1
AH27
FCC3_RXD/TXD3
1
1
PB9/FCC3_MII_HDLC_RXD1/
FCC3_RMII_RXD1/L1TXD2A2
FCC2_UT8_TXD2/L1TSYNCD1/
L1GNTD1
AG24
PB10/FCC3_MII_HDLC_RXD2
PB11/FCC3_MII_HDLC_RXD3
PB12/FCC3_MII_CRS/TXD2
PB13/FCC3_MII_COL/L1TXD1A2
PB14/FCC3_MII_RMII_TX_EN
PB15/FCC3_MII_TX_ER/RXD2
FCC2_UT8_TXD1/L1RXDD1
FCC2_UT8_TXD0/L1TXDD1
L1CLKOB1/L1RSYNCC1
L1RQB1/L1TSYNCC1/L1GNTC1
L1RXDC1
AH24
1
AJ24
1
1
1
AG22
AH21
AG20
1
L1TXDC1
AF19
MOTOROLA
MPC8280HardwareSpecifications
47
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
1
1
PB16/FCC3_MII_RMII_RX_ER/CLK18 L1CLKOA1
AJ18
AJ17
PB17/FCC3_MII_RX_DV/CLK17/
FCC3_RMII_CRS_DV
L1RQA1
1
PB18/FCC2_MII_HDLC_RXD3/
L1CLKOD2/L1RXD2A2
FCC2_UT8_RXD4
FCC2_UT8_RXD5
FCC2_UT8_RXD6
AE14
1
PB19FCC2_MII_HDLC_RXD2/
L1RQD2/L1RXD3A2
AF13
AG12
AH11
1
1
PB20/FCC2_MII_HDLC_RMII_RXD1
/L1RSYNCD2/L1TXD1A1
PB21//FCC2_MII_HDLC_RMII_RXD0/ FCC2_UT8_RXD7/L1TXD2A1
FCC2_TRAN_RXD/L1TSYNCD2/
L1GNTD2
1
PB22/FCC2_MII_HDLC_TXD0/
FCC2_TXD/FCC2_RMII_TXD0/
L1RXDD2
FCC2_UT8_TXD7/L1RXD1A1
FCC2_UT8_TXD6/L1RXD2A1
AH16
1
PB23/FCC2_MII_HDLC_TXD1/
L1RXD2A1/L1TXDD2/
FCC2_RMII_TXD1
AE15
1
1
PB24/FCC2_MII_HDLC_TXD2/
L1RSYNCC2
FCC2_UT8_TXD5/L1RXD3A1
FCC2_UT8_TXD4/L1TXD3A1
AJ9
PB25/FCC2_MII_HDLC_TXD3/
L1TSYNCC2/L1GNTC2
AE9
1
PB26/FCC2_MII_CRS/L1RXDC2
PB27/FCC2_MII_COL/L1TXDC2
FCC2_UT8_TXD1
FCC2_UT8_TXD0
AJ7
1
AH6
1
PB28/FCC2_MII_RX_ER/
AE3
FCC2_RMII_RX_ER/FCC2_RTS/
L1TSYNCB2/L1GNTB2/TXD1
1
1
1
PB29/L1RSYNCB2/FCC2_MII_TX_EN/ FCC2_UTM_RXCLAV/
AE2
AC5
AC4
FCC2_RMII_TX_EN
FCC2_UTS_RXCLAV
PB30/FCC2_MII_RX_DV/
FCC2_UT_TXSOC
FCC2_RMII_CRS_DV/L1RXDB2
PB31/FCC2_MII_TX_ER/L1TXDB2
FCC2_UT_RXSOC
1
PC0/DREQ1/BRGO7/SMSYN2/
L1CLKOA2
AB26
1
PC1/DREQ2/BRGO6/L1RQA2/ SPISEL
PC2/FCC3_CD/DONE2
AD29
1
FCC2_UT8_TXD3
FCC2_UT8_TXD2
AE29
AE27
1
PC3/FCC3_CTS/DACK2/CTS4/
USB_RP
1
PC4/SI2_L1ST4/FCC2_CD
FCC2_UTM_RXENB/
FCC2_UTS_RXENB
AF27
48
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
1
PC5/SI2_L1ST3/FCC2_CTS
FCC2_UTM_TXCLAV/
FCC2_UTS_TXCLAV
AF24
1
1
1
PC6/FCC1_CD
L1CLKOC1/FCC1_UTM_RXADDR2/
FCC1_UTS_RXADDR2/
FCC1_UTM_RXCLAV1
AJ26
PC7/FCC1_CTS
L1RQC1/FCC1_UTM_TXADDR2/
FCC1_UTS_TXADDR2/
FCC1_UTM_TXCLAV1
AJ25
PC8/CD4/RENA4/SI2_L1ST2/CTS3/
USBRN
FCC1_UT16_TXD0
AF22
1
PC9/CTS4/CLSN4/SI2_L1ST1/
L1TSYNCA2/L1GNTA2/USB_RP
FCC1_UT16_TXD1
AE21
1
PC10/CD3/RENA3
FCC1_UT16_TXD2/SI1_L1ST4/
FCC2_UT8_RXD3
AF20
1
PC11/CTS3/CLSN3/L1TXD3A2
PC12/CD2/RENA2
L1CLKOD1/FCC2_UT8_RXD2
AE19
AE18
1
SI1_L1ST3/FCC1_UTM_RXADDR1/
FCC1_UTS_RXADDR1
1
PC13/CTS2/CLSN2
L1RQD1/FCC1_UTM_TXADDR1/
FCC1_UTS_TXADDR1
AH18
AH17
AG16
1
1
PC14/CD1/RENA1
FCC1_UTM_RXADDR0/
FCC1_UTS_RXADDR0
PC15/CTS1/CLSN1/SMTXD2
FCC1_UTM_TXADDR0/
FCC1_UTS_TXADDR0
1
PC16/CLK16/TIN4
AF15
1
PC17/CLK15/TIN3/BRGO8
PC18/CLK14/TGATE2
AJ15
1
AH14
AG13
AH12
1
1
PC19/CLK13/BRGO7/SPICLK
PC20/CLK12/TGATE1/USB_OE
PC21/CLK11/BRGO6
1
AJ11
1
PC22/CLK10/DONE1/FCC1_UT_TXPRTY
PC23/CLK9/BRGO5/DACK1
PC24/CLK8/TOUT4
AG10
1
AE10
1
FCC2_UT8_TXD3
FCC2_UT8_TXD2
AF9
AE8
1
PC25/CLK7/BRGO4
1
PC26/CLK6/TOUT3/TMCLK
AJ6
1
PC27/FCC3_TXD/FCC3_MII_TXD0/
FCC3_RMII_TXD0/CLK5/BRGO3
AG2
1
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2/
FCC2_RXADDR4
AF3
AF2
1
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
MOTOROLA
MPC8280HardwareSpecifications
49
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
1
PC30/CLK2/TOUT1
FCC2_UT8_TXD3
AE1
AD1
1
PC31/CLK1/BRGO1
PD4/BRGO8/FCC3_RTS/SMRXD2
PD5/DONE1
1
1
L1TSYNCD1/L1GNTD1
FCC1_UT16_TXD3
FCC1_UT16_TXD4
AC28
AD27
1
PD6/DACK1
AF29
AF28
1
PD7/SMSYN1/FCC1_TXCLAV2
FCC1_UTM_TXADDR3/
FCC1_UTS_TXADDR3/
FCC2_UTM_TXADDR4
FCC2_UTS_TXADDR1
1
PD8/SMRXD1/BRGO5
PD9/SMTXD1/BRGO3
PD10/L1CLKOB2/BRGO4
PD11/L1RQB2
FCC2_UT_TXPRTY
AG25
AH26
1
FCC2_UT_RXPRTY
1
FCC2_UT8_RXD1/L1RSYNCB1
AJ27
AJ23
1
FCC2_UT8_RXD0/L1TSYNCB1/
L1GNTB1
1
1
PD12
SI1_L1ST2/L1RXDB1
SI1_L1ST1/L1TXDB1
FCC1_UT16_RXD0
FCC1_UT16_RXD1
AG23
1
PD13
AJ22
AE20
PD14/L1CLKOC2/I2CSCL
PD15/L1RQC2/I2CSDA
PD16/SPIMISO
1
AJ20
1
FCC1_UT_TXPRTY/L1TSYNCC1/
L1GNTC1
AG18
1
PD17/BRGO2/SPIMOSI
PD18/SPICLK
FCC1_UT_RXPRTY
AG17
1
1
FCC1_UTM_RXADDR4/
FCC1_UTS_RXADDR4/
FCC1_UTM_RXCLAV3/
FCC2_UTM_RXADDR3/
FCC2_UTS_RXADDR0
AF16
PD19/SPISEL/BRGO1
FCC1_UTM_TXADDR4/
FCC1_UTS_TXADDR4/
FCC1_UTM_TXCLAV3/
FCC2_UTM_TXADDR3/
FCC2_UTS_TXADDR0
AH15
1
PD20/RTS4/TENA4/L1RSYNCA2/
USB_TP
FCC1_UT16_RXD2
FCC1_UT16_RXD3
FCC1_UT16_TXD5
AJ14
1
PD21/TXD4/L1RXD0A2/L1RXDA2/
USB_TN
AH13
1
1
PD22/RXD4L1TXD0A2/L1TXDA2/
USB_RXD
AJ12
PD23/RTS3/TENA3
PD24/TXD3
FCC1_UT16_RXD4/L1RSYNCD1
FCC1_UT16_RXD5/L1RXDD1
FCC1_UT16_TXD6/L1TXDD1
AE12
1
AF10
1
PD25/RXD3
AG9
50
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 19. MPC8280 and MPC8270 Pinout List (Continued)
Pin Name
Ball
MPC8280/MPC8270
MPC8280 only (UTOPIA Pins)
1
PD26/RTS2/TENA2
PD27/TXD2
FCC1_UT16_RXD6/L1RSYNCC1
FCC1_UT16_RXD7/L1RXDC1
FCC1_UT16_TXD7/L1TXDC1
AH8
AG7
1
1
PD28/RXD2
AE4
1
PD29/RTS1/TENA1
FCC1_UTM_RXADDR3/
FCC1_UTS_RXADDR3/
FCC1_UTM_RXCLAV2/
FCC2_UTM_RXADDR4/
FCC2_UTS_RXADDR1
AG1
1
1
PD30/TXD1
FCC2_UTM_TXENB/
FCC2_UTS_TXENB
AD4
PD31/RXD1
VCCSYN
VCCSYN1
CLKIN2
AD2
AB3
B9
AE11
U5
2
SPARE4
3
PCI_MODE
AF25
V4
2
SPARE6
4
THERMAL0
AA1
AG4
4
THERMAL1
I/O power
AG21, AG14, AG8, AJ1, AJ2,
AH1, AH2, AG3, AF4, AE5, AC27,
Y27, T27, P27, K26, G27, AE25,
AF26, AG27, AH28, AH29, AJ28,
AJ29, C7, C14, C16, C20, C23,
E10, A28, A29, B28, B29, C27,
D26, E25, H3, M4, T3, AA4, A1,
A2, B1, B2, C3, D4, E5
Core Power
Ground
U28, U29, K28, K29, A9, A19,
B19, M1, M2, Y1, Y2, AC1, AC2,
AH19, AJ19, AH10, AJ10, AJ5
5
6
AA5, AB1 , AB2 , AF21, AF14,
AF8, AE7, AF11, AE17, AE23,
AC26, AB25, Y26, V25, T26, R25,
P26, M25, K27, H25, G26, D7,
D10, D14, D16, D20, D23, C9,
E11, E13, E15, E19, E22, B3, G5,
H4, K5, M3, P5, T4, Y5, AA2, AC3
1
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
Must be pulled down or left floating.
If PCI is not desired, must be pulled up or left floating.
For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D).
2
3
4
MOTOROLA
MPC8280HardwareSpecifications
51
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
5
GNDSYN (AB1): This pin exists as a separate ground signal in MPC826x(A) devices; it does not exist as a
separate ground signal on the MPC8280. New designs must connect AB1 to GND and follow the suggestions
in Section 1.2.2.1, “Layout Practices.” Old designs in which the MPC8280 is used as a drop-in replacement can
leave the pin connected to GND with the noise filtering capacitors.
XFC (AB2) pin:This pin is used in MPC826x(A) devices; it is not used in MPC8280 because there is no need for
external capacitor to operate the PLL. New designs should connect AB2 (XFC) pin to GND. Old designs in
which the MPC8280 is used as a drop-in replacement can leave the pin connected to the current capacitor.
6
Symbols used in Table 19 are described in Table 20.
Table 20. Symbol Legend
Symbol
Meaning
OVERBAR
UTM
Signals with overbars, such as TA, are active low.
Indicates that a signal is part of the UTOPIA master interface.
Indicates that a signal is part of the UTOPIA slave interface.
Indicates that a signal is part of the 8-bit UTOPIA interface.
Indicates that a signal is part of the 16-bit UTOPIA interface.
Indicates that a signal is part of the media independent interface.
UTS
UT8
UT16
MII
1.4.2 VR Package—MPC8275VR and MPC8270VR
The following figures and table represent the alternate 516 PBGA package. For information on the standard
package for the MPC8280 and the MPC8270, refer to Section 1.4.1, “ZU Package—MPC8280 and
MPC8270” on page 37.
1.4.2.1 VR Pin Assignments
Figure 15 shows the pinout of the VR package as viewed from the top surface.
52
MPC8280HardwareSpecifications
MOTOROLA
Pinout
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
A
B
C
D
E
F
C
D
E
F
G
H
G
H
J
J
K
K
L
L
M
N
M
N
P
R
T
P
R
T
U
U
V
W
Y
V
W
Y
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Not to Scale
Figure 15. Pinout of the 516 PBGA Package (View from Top)
Figure 16 shows the side profile of the PBGA package to indicate the direction of the top surface view.
Wire bonds
Ball bond
Die
attach
Transfer molding compound
Plated substrate via
Screen-printed
solder mask
Cu substrate traces
BT resin glass epoxy
DIE
1 mm pitch
Figure 16. Side View of the PBGA Package Remove
Table 21 shows the pinout list of the MPC8275VR and MPC8270VR. Table 20 defines conventions and
acronyms used in Table 21.
MOTOROLA
MPC8280HardwareSpecifications
53
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
BR
C16
D2
BG
ABB/IRQ2
TS
C1
D1
A0
D5
A1
E8
A2
C4
A3
B4
A4
A4
A5
D7
A6
D8
A7
C6
A8
B5
A9
B6
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
C7
C8
A6
D9
F11
B7
B8
C9
A7
B9
E11
A8
D11
B10
C11
A9
B11
C12
D12
A10
54
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
A30
A31
TT0
TT1
TT2
TT3
TT4
TBST
TSIZ0
TSIZ1
TSIZ2
TSIZ3
AACK
ARTRY
DBG
DBB/IRQ3
D0
B12
B13
E7
B3
F8
A3
C3
F5
E3
E2
E1
E4
D3
C2
A14
C15
W4
Y1
D1
D2
V1
D3
P4
D4
N3
K5
D5
D6
J4
D7
G1
AB1
U4
U2
N6
N1
L1
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
J5
G3
AA2
W1
MOTOROLA
MPC8280HardwareSpecifications
55
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
T3
T1
M2
K2
J1
G4
U5
T5
P5
P3
M3
K3
H2
G5
AA1
V2
U1
P2
M4
K4
H3
F2
Y2
U3
T2
N2
M5
K1
H4
F1
W2
T4
R3
N4
56
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
D52
M1
J2
D53
D54
H5
D55
F3
D56
V3
D57
R5
D58
R2
D59
N5
D60
L2
D61
J3
D62
H1
D63
F4
DP0/RSRV/EXT_BR2
AB3
W5
AC2
AA3
AD1
AC1
AB2
Y3
IRQ1/DP1/EXT_BG2
IRQ2/DP2/TLBISYNC/EXT_DBG2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
IRQ4/DP4/CORE_SRESET/EXT_BG3
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
PSDVAL
D15
Y4
TA
TEA
D16
E15
D14
E14
A17
B14
F13
B17
AC6
AD6
AE6
AB7
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
CS0
CS1
CS2
CS3
MOTOROLA
MPC8280HardwareSpecifications
57
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
CS4
AF7
AC7
AD7
AF8
AE8
AD8
AC8
AB8
C13
A12
D13
AF4
AA5
AE4
AD4
AF3
AB4
AE3
AF2
AD3
AE2
AD2
AE1
AC3
W6
CS5
CS6
CS7
CS8
CS9
CS10/BCTL1
CS11/AP0
BADDR27
BADDR28
ALE
BCTL0
PWE0/PSDDQM0/PBS0
PWE1/PSDDQM1/PBS1
PWE2/PSDDQM2/PBS2
PWE3/PSDDQM3/PBS3
PWE4/PSDDQM4/PBS4
PWE5/PSDDQM5/PBS5
PWE6/PSDDQM6/PBS6
PWE7/PSDDQM7/PBS7
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE0/LSDDQM0/LBS0/PCI_CFG0
LWE1/LSDDQM1/LBS1/PCI_CFG1
LWE2/LSDDQM2/LBS2/PCI_CFG2
LWE3/LSDDQM3/LBS3/PCI_CFG3
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
AA4
AC9
AD9
AE9
AF9
AB6
AF5
AE5
AD5
58
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
LGTA/LUPMWAIT/LGPL4/LPBS
LGPL5/LSDAMUX/PCI_MODCK
LWR
AC5
AB5
AF6
L_A14/PAR
AE13
AD15
AF16
AF15
AE15
AE14
AC17
AD14
AF13
AE20
AC14
AC19
AD13
AF21
AF22
AE21
AB14
AD20
AB9
L_A15/FRAME/SMI
L_A16/TRDY
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTA
L_A30/REQ2
L_A31/DLLOUT
LCL_D0/AD0
LCL_D1/AD1
AB10
AC10
AD10
AE10
AF10
AF11
AB12
AB11
AF12
AE11
AC13
AC12
LCL_D2/AD2
LCL_D3/AD3
LCL_D4/AD4
LCL_D5/AD5
LCL_D6/AD6
LCL_D7/AD7
LCL_D8/AD8
LCL_D9/AD9
LCL_D10/AD10
LCL_D11/AD11
LCL_D12/AD12
MOTOROLA
MPC8280HardwareSpecifications
59
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
LCL_D13/AD13
LCL_D14/AD14
LCL_D15/AD15
LCL_D16/AD16
LCL_D17/AD17
LCL_D18/AD18
LCL_D19/AD19
LCL_D20/AD20
LCL_D21/AD21
LCL_D22/AD22
LCL_D23/AD23
LCL_D24/AD24
LCL_D25/AD25
LCL_D26/AD26
LCL_D27/AD27
LCL_D28/AD28
LCL_D29/AD29
LCL_D30/AD30
LCL_D31/AD31
LCL_DP0/C0/BE0
LCL_DP1/C1/BE1
LCL_DP2/C2/BE2
LCL_DP3/C3/BE3
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
TRST
AB13
AD12
AF14
AF17
AE16
AD16
AC16
AB16
AF18
AE17
AD17
AB17
AE18
AD18
AC18
AE19
AF20
AD19
AB18
AE12
AA13
AC15
AF19
A11
E5
F22
TCK
A24
TMS
C24
TDI
A25
TDO
B24
TRIS
C19
PORESET
B25
HRESET
D24
SRESET
E23
60
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
QREQ
D18
E24
RSTCONF
MODCK1/AP1/TC0/BNKSEL0
MODCK2/AP2/TC1/BNKSEL1
MODCK3/AP3/TC2/BNKSEL2
CLKIN1
B16
F16
A15
G22
AC20
AC21
1
1
PA0/RESTART1/DREQ3
PA1/REJECT1/DONE3
PA2/CLK20/DACK3
PA3/CLK19/DACK4/L1RXD1A2
PA4/REJECT2/DONE4
PA5/RESTART2/DREQ4
PA6
FCC2_UTM_TXADDR2
FCC2_UTM_TXADDR1
FCC2_UTM_TXADDR0
FCC2_UTM_RXADDR0
FCC2_UTM_RXADDR1
FCC2_UTM_RXADDR2
L1RSYNCA1
1
AF25
1
AE24
AA21
1
1
AD25
AC24
1
1
PA7/SMSYN2
L1TSYNCA1/L1GNTA1
L1RXD0A1/L1RXDA1
AA22
AA23
1
PA8/SMRXD2
1
PA9/SMTXD2
L1TXD0A1
Y26
1
PA10/MSNUM5
FCC1_UT8_RXD0/FCC1_UT16_RXD8
FCC1_UT8_RXD1/FCC1_UT16_RXD9
W22
W23
1
PA11/MSNUM4
1
PA12/MSNUM3
FCC1_UT8_RXD2/
FCC1_UT16_RXD10
V26
1
PA13/MSNUM2
FCC1_UT8_RXD3/
FCC1_UT16_RXD11
V25
1
1
1
PA14/FCC1_MII_HDLC_RXD3
PA15/FCC1_MII_HDLC_RXD2
FCC1_UT8_RXD4/
FCC1_UT16_RXD12
T22
/FCC1_UT8_RXD5/
FCC1_UT16_RXD13
T25
PA16/FCC1_MII_HDLC_RXD1/
FCC1_RMII_RXD1
FCC1_UT8_RXD6/
FCC1_UT16_RXD14
R24
1
PA17/FCC_MII_HDLC_RXD0/
FCC1_MII_TRAN_RXD/
FCCI_RMII_RXD0
FCC1_UT8_RXD7/
FCC1_UT16_RXD15
P22
N26
N23
1
1
PA18/FCC1_MII_HDLC_TXD0/
FCC1_MIITRAN_TXD/
FCC1_RMII_TXD0
FCC1_UT8_TXD7/FCC1_UT16_TXD15
FCC1_UT8_TXD6/FCC1_UT16_TXD14
PA19/FCC1_MII_HDLC_TXD1/
FCC1_RMII_TXD1
1
PA20/FCC1_MII_HDLC_TXD2
PA21/FCC1_MII_HDLC_TXD3
FCC1_UT8_TXD5/FCC1_UT16_TXD13
FCC1_UT8_TXD4/FCC1_UT16_TXD12
K26
1
L23
MOTOROLA
MPC8280HardwareSpecifications
61
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
1
PA22
FCC1_UT8_TXD3/FCC1_UT16_TXD11
FCC1_UT8_TXD2/FCC1_UT16_TXD10
FCC1_UT8_TXD1/FCC1_UT16_TXD9
FCC1_UT8_TXD0/FCC1_UT16_TXD8
K23
H26
1
PA23
1
PA24/MSNUM1
PA25/MSNUM0
PA26/FCC1_MII_RMII_RX_ER/
F25
1
D26
D25
1
1
1
FCC1_UTM_RXCLAV/
FCC1_UTS_RXCLAV
PA27/FCC1_MII_RX_DV/
FCC1_RMII_CRS_DV
FCC1_UT_RXSOC
C25
C22
PA28/FCC1_MII_TX_EN/
FCC1_RMII_TX_EN
FCC1_UTM_RXENB/
FCC1_UTS_RXENB
1
1
PA29/FCC1_MII_TX_ER
FCC1_UT_TXSOC
B21
A20
PA30/FCC1_MII_CRS/FCC1_RTS
FCC1_UTM_TXCLAV/
FCC1_UTS_TXCLAV
1
PA31/FCC1_MII_COL
FCC1_UTM_TXENB/
FCC1_UTS_TXENB
A19
1
PB4/FCC3_MII_HDLC_TXD3/
L1RSYNCA2/FCC3_RTS
FCC2_UT8_RXD0
FCC2_UT8_RXD1
FCC2_UT8_RXD2
AD21
AD22
AC22
1
1
PB5/FCC3_MII_HDLC_TXD2/
L1TSYNCA2/L1GNTA2
PB6/FCC3_MII_HDLC_TXD1/
FCC3_RMII_TXD1/
L1RXDA2/L1RXD0A2
1
1
1
PB7/FCC3_MII_HDLC_TXD0/
FCC3_RMII_TXD0/
FCC3_TXD/L1TXDA2/L1TXD0A2
FCC2_UT8_RXD3
AE26
AB23
AC26
PB8/FCC3_MII_HDLC_RXD0/
FCC3_RMII_RXD0/
FCC3_RXD/TXD3
FCC2_UT8_TXD3/L1RSYNCD1
PB9/FCC3_MII_HDLC_RXD1/
FCC3_RMII_RXD1/L1TXD2A2
FCC2_UT8_TXD2/L1TSYNCD1/
L1GNTD1
1
1
PB10/FCC3_MII_HDLC_RXD2
PB11/FCC3_MII_HDLC_RXD3
PB12/FCC3_MII_CRS/TXD2
PB13/FCC3_MII_COL/L1TXD1A2
PB14/FCC3_MII_RMII_TX_EN
PB15/FCC3_MII_TX_ER/RXD2
FCC2_UT8_TXD1/L1RXDD1
FCC2_UT8_TXD0/L1TXDD1
L1CLKOB1/L1RSYNCC1
L1RQB1/L1TSYNCC1/L1GNTC1
L1RXDC1
AB26
AA25
1
W26
W25
1
1
V24
U24
R22
R23
1
1
1
L1TXDC1
PB16/FCC3_MII_RMII_RX_ER/CLK18 L1CLKOA1
PB17/FCC3_MII_RX_DV/
L1RQA1
CLK17/FCC3_RMII_CRS_DV
62
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
1
PB18/FCC2_MII_HDLC_RXD3/
L1CLKOD2/L1RXD2A2
FCC2_UT8_RXD4
M23
1
PB19FCC2_MII_HDLC_RXD2/
L1RQD2/L1RXD3A2
FCC2_UT8_RXD5
FCC2_UT8_RXD6
L24
K24
1
PB20/FCC2_MII_HDLC_RMII_RXD1
/L1RSYNCD2/L1TXD1A1
1
PB21//FCC2_MII_HDLC_RMII_RXD0/ FCC2_UT8_RXD7/L1TXD2A1
L21
FCC2_TRAN_RXD/L1TSYNCD2/
L1GNTD2
1
PB22/FCC2_MII_HDLC_RMII_TXD0/
FCC2_TXD/FCC2_RMII_TXD0/
L1RXDD2
FCC2_UT8_TXD7/L1RXD1A1
FCC2_UT8_TXD6/L1RXD2A1
P25
N25
1
PB23/FCC2_MII_HDLC_TXD1/
L1RXD2A1/L1TXDD2/
FCC2_RMII_TXD1
1
1
PB24/FCC2_MII_HDLC_TXD2/
L1RSYNCC2
FCC2_UT8_TXD5/L1RXD3A1
FCC2_UT8_TXD4/L1TXD3A1
E26
PB25/FCC2_MII_HDLC_TXD3/
L1TSYNCC2/L1GNTC2
H23
1
PB26/FCC2_MII_CRS/L1RXDC2
PB27/FCC2_MII_COL/L1TXDC2
FCC2_UT8_TXD1
FCC2_UT8_TXD0
C26
1
B26
A22
1
PB28/FCC2_MII_RX_ER/FCC2_RMII_RX_ER/
FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1
1
1
1
PB29/L1RSYNCB2/
FCC2_MII_TX_EN/FCC2_RMII_TX_EN FCC2_UTS_RXCLAV
FCC2_UTM_RXCLAV/
A21
E20
PB30/FCC2_MII_RX_DV/L1RXDB2/
FCC2_RMII_CRS_DV
FCC2_UT_TXSOC
FCC2_UT_RXSOC
PB31/FCC2_MII_TX_ER/L1TXDB2
C20
1
PC0/DREQ1/BRGO7/SMSYN2/
L1CLKOA2
AE22
1
PC1/DREQ2/SPISEL/BRGO6/L1RQA2
PC2/FCC3_CD/DONE2
AA19
1
FCC2_UT8_TXD3
FCC2_UT8_TXD2
AF24
1
PC3/FCC3_CTS/DACK2/CTS4/
USB_RP
AE25
AB22
AC25
AB25
1
1
1
PC4/SI2_L1ST4/FCC2_CD
PC5/SI2_L1ST3/FCC2_CTS
PC6/FCC1_CD
FCC2_UTM_RXENB/
FCC2_UTS_RXENB
FCC2_UTM_TXCLAV/
FCC2_UTS_TXCLAV
L1CLKOC1/FCC1_UTM_RXADDR2/
FCC1_UTS_RXADDR2/
FCC1_UTM_RXCLAV1
MOTOROLA
MPC8280HardwareSpecifications
63
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
1
PC7/FCC1_CTS
L1RQC1/FCC1_UTM_TXADDR2/
FCC1_UTS_TXADDR2/
AA24
FCC1_UTM_TXCLAV1
1
PC8/CD4/RENA4/SI2_L1ST2/CTS3/
USB_RN
FCC1_UT16_TXD0
Y24
1
PC9/CTS4/CLSN4/SI2_L1ST1/
L1TSYNCA2/L1GNTA2/USB_RP
FCC1_UT16_TXD1
U22
1
1
PC10/CD3/RENA3
FCC1_UT16_TXD2/SI1_L1ST4/
FCC2_UT8_RXD3
V23
PC11/CTS3/CLSN3/L1TXD3A2
PC12/CD2/RENA2
L1CLKOD1/FCC2_UT8_RXD2
U23
1
SI1_L1ST3/FCC1_UTM_RXADDR1/
FCC1_UTS_RXADDR1
T26
1
PC13/CTS2/CLSN2
L1RQD1/FCC1_UTM_TXADDR1/
FCC1_UTS_TXADDR1
R26
1
1
1
PC14/CD1/RENA1
FCC1_UTM_RXADDR0/
FCC1_UTS_RXADDR0
P26
PC15/CTS1/CLSN1/SMTXD2
FCC1_UTM_TXADDR0/
FCC1_UTS_TXADDR0
P24
PC16/CLK16/TIN4
M26
1
PC17/CLK15/TIN3/BRGO8
PC18/CLK14/TGATE2
PC19/CLK13/BRGO7
PC20/CLK12/TGATE1/USB_OE
PC21/CLK11/BRGO6
PC22/CLK10/DONE1
L26
1
1
M24
1
L22
K25
1
J25
1
G26
1
1
PC23/CLK9/BRGO5/DACK1
PC24/CLK8/TOUT4
F26
FCC2_UT8_TXD3
FCC2_UT8_TXD2
G24
1
PC25/CLK7/BRGO4
E25
G23
1
PC26/CLK6/TOUT3/TMCLK
1
PC27/FCC3_TXD/FCC3_TXD0/CLK5/
BRGO3
B23
1
1
1
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
PC30/CLK2/TOUT1
E22
E21
FCC2_UT8_TXD3
D21
1
PC31/CLK1/BRGO1
B20
1
1
PD4/BRGO8/FCC3_RTS/SMRXD2
PD5/DONE1
L1TSYNCD1/L1GNTD1
FCC1_UT16_TXD3
FCC1_UT16_TXD4
AF23
AE23
AB21
1
PD6/DACK1
64
MPC8280HardwareSpecifications
MOTOROLA
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
1
1
PD7/SMSYN1/FCC1_TXCLAV2
FCC1_UTM_TXADDR3/
FCC1_UTS_TXADDR3/
FCC2_UTM_TXADDR4
FCC2_UTS_TXADDR1
AD23
PD8/SMRXD1/BRGO5
PD9/SMTXD1/BRGO3
PD10/L1CLKOB2/BRGO4
PD11/L1RQB2
FCC2_UT_TXPRTY
AD26
1
FCC2_UT_RXPRTY
Y22
1
FCC2_UT8_RXD1/L1RSYNCB1
AB24
1
FCC2_UT8_RXD0/L1TSYNCB1/
L1GNTB1
Y23
1
PD12
SI1_L1ST2/L1RXDB1
SI1_L1ST1/L1TXDB1
FCC1_UT16_RXD0
FCC1_UT16_RXD1
AA26
1
PD13
W24
1
PD14/L1CLKOC2/I2CSCL
PD15/L1RQC2/I2CSDA
PD16/SPIMISO
V22
U26
1
1
FCC1_UT_TXPRTY/L1TSYNCC1/
L1GNTC1
T23
1
PD17/BRGO2/SPIMOSI
PD18/SPICLK
FCC1_UT_RXPRTY
R25
1
FCC1_UTM_RXADDR4/
FCC1_UTS_RXADDR4/
FCC1_UTM_RXCLAV3/
FCC2_UTM_RXADDR3/
FCC2_UTS_RXADDR0
P23
1
PD19/SPISEL/BRGO1
FCC1_UTM_TXADDR4/
FCC1_UTS_TXADDR4/
FCC1_UTM_TXCLAV3/
FCC2_UTM_TXADDR3/
FCC2_UTS_TXADDR0
N22
1
PD20/RTS4/TENA4/L1RSYNCA2/
USB_TP
FCC1_UT16_RXD2
FCC1_UT16_RXD3
FCC1_UT16_TXD5
M25
1
PD21/TXD4/L1RXD0A2/L1RXDA2/
USB_TN
L25
1
PD22/RXD4L1TXD0A2/L1TXDA2/
USB_RXD
J26
1
1
PD23/RTS3/TENA3
PD24/TXD3
FCC1_UT16_RXD4/L1RSYNCD1
FCC1_UT16_RXD5/L1RXDD1
FCC1_UT16_TXD6/L1TXDD1
FCC1_UT16_RXD6/L1RSYNCC1
FCC1_UT16_RXD7/L1RXDC1
FCC1_UT16_TXD7/L1TXDC1
K22
G25
1
PD25/RXD3
H24
1
PD26/RTS2/TENA2
PD27/TXD2
F24
H22
1
1
PD28/RXD2
B22
MOTOROLA
MPC8280HardwareSpecifications
65
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 21. MPC8275VR and MPC8270VR Pinout List (Continued)
Pin Name
Ball
MPC8275VR/MPC8270VR
MPC8275VR only (UTOPIA Pins)
1
PD29/RTS1/TENA1
FCC1_UTM_RXADDR3/
FCC1_UTS_RXADDR3/
FCC1_UTM_RXCLAV2/
FCC2_UTM_RXADDR4/
FCC2_UTS_RXADDR1
D22
1
PD30/TXD1
FCC2_UTM_TXENB/
FCC2_UTS_TXENB
C21
1
PD31/RXD1
VCCSYN
VCCSYN1
CLKIN2
E19
D19
K6
K21
C14
AD24
B15
E17
C23
2
SPARE4
3
PCI_MODE
2
SPARE6
4
THERMAL0
4
THERMAL1
I/O power
E6, F6, H6, L5, L6, P6,T6, U6,V5,
Y5, AA6, AA8, AA10, AA11,
AA14, AA16, AA17, AB19, AB20,
W21, U21, T21, P21, N21, M22,
J22, H21, F21, F19, F17, E16,
F14, E13, E12, F10, E10, E9
Core Power
Ground
L3, V4, W3, AC11, AD11, AB15,
U25, T24, J24, H25, F23, B19,
D17, C17, D10, C10
5
6
B18 , A18 , A2, B1, B2, A5, C5,
C18, D4, D6, G2, L4, P1, R1, R4,
AC4, AE7, AC23, Y25, N24, J23,
A23, D23, D20, E18, A13, A16,
K10, K11, K12, K13, K14, K15,
K16, K17, L10, L11, L12, L13,
L14, L15, L16, L17, M10, M11,
M12, M13, M14, M15, M16, M17,
N10, N11, N12, N13, N14, N15,
N16, N17, P10, P11, P12, P13,
P14, P15, P16, P17, R10,
R11,R12, R13, R14, R15, R16,
R17, T10, T11, T12, T13, T14,
T15, T16, T17, U10, U11, U12,
U13, U14, U15, U16, U17
1
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
Must be pulled down or left floating.
If PCI is not desired, must be pulled up or left floating.
For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D).
2
3
4
66
MPC8280HardwareSpecifications
MOTOROLA
Package Description
5
6
GNDSYN (B18): This pin exists as a separate ground signal in MPC826x(A) devices; it does not exist as a
separate ground signal on the MPC8275VR/MPC8270VR. New designs must connect B18 to GND and follow
the suggestions in Section 1.2.2.1, “Layout Practices.” Old designs in which the MPC8275VR/MPC8270VR is
used as a drop-in replacement can leave the pin connected to GND with the noise filtering capacitors.
XFC (A18) pin: This pin is used in MPC826x(A) devices; it is not used in MPC8275VR/MPC8270VR because
there is no need for external capacitor to operate the PLL. New designs should connect A18 (XFC) pin to GND.
Old designs in which the MPC8275VR/MPC8270VR is used as a drop-in replacement can leave the pin
connected to the current capacitor.
1.5 Package Description
The following sections provide the package parameters and mechanical dimensions.
1.5.1 Package Parameters
Package parameters are provided in Table 22.
Table 22. Package Parameters
Outline
(mm)
Pitch
(mm)
Nominal Unmounted
Height (mm)
Package
Devices
Type
Interconnects
ZU
MPC8280
37.5 x 37.5
TBGA
480
1.27
1.55
MPC8270
VR
MPC8275VR
MPC8270VR
27 x 27
PBGA
516
1
2.25
MOTOROLA
MPC8280HardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
67
Package Description
1.5.2 Mechanical Dimensions
1.5.2.1 ZU Package Dimensions
Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package.
Notes:
1. Dimensions and Tolerancing per
ASME Y14.5M-1994.
2. Dimensions in millimeters.
3. Dimension b is measured at the
maximum solder ball diameter,
parallel to primary data A.
4. Primary data A and the seating
plane are defined by the spherical
crowns of the solder balls.
Millimeters
Dim
Min
Max
A
A1
A2
A3
b
1.45
0.60
0.85
0.25
0.65
1.65
0.70
0.95
—
0.85
D
37.50 BSC
D1
e
35.56 REF
1.27 BSC
37.50 BSC
35.56 REF
E
E1
Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature—480 TBGA
68
MPC8280HardwareSpecifications
MOTOROLA
Package Description
1.5.2.2 VR Package Dimensions
Figure 18 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA package.
Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA
MOTOROLA
MPC8280HardwareSpecifications
69
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Ordering Information
1.6 Ordering Information
Figure 19 provides an example of the Motorola part numbering nomenclature for the MPC8280. In addition
to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any
enhancement(s) in the part from the original production design. Each part number also contains a revision
code that refers to the die mask revision number and is specified in the part numbering scheme for
identification purposes only. For more information, contact your local Motorola sales office.
MPC 82XX C ZU XXX X
Die Revision Level
Product Code
Device Number
Processor Frequency
(CPU/CPM/Bus)
Temperature Range
Blank = 0 to 105 ˚C
C = -40 to 105 ˚C
Package
ZU = 480 TBGA
VR = 516 PBGA
Figure 19. Motorola Part Number Key
Table 23. Document Revision History
Substantive Changes
Revision
Date
0
—
—
0.1
0.2
0.3
Initial public release
11/2002 Table 21, “VR Pinout”: Addition of C18 to the Ground (GND) pin list (page 63)
6/2003 • Removal of notes stating “no local bus” on VR-package devices. The MPC8270VR and the
MPC8275VR have local bus support.
• References to “G2 core” changed to “G2_LE core.” Refer to the G2 Core Reference Manual
(G2CORERM/D).
• Addition of VCCSYN to “Note” below Table 3, and to note 2 of Table 4
• Figure 2: New
• Table 4: Addition of note 1
• Table 5: Addition of θ and θ . Modifications to ZU package values.
JB
JC
• Table 6: Addition of various configurations, Modification of values. Addition of note 3.
• Table 8: Addition of 66 MHZ and 100 MHz values. Addition of sp42a/sp43a.
• Table 9: Addition of 66 MHZ and 100 MHz values
• Table 11: sp30 values. sp33b @100 MHz value. Removal of previous note 2. Modification of
current note 2.
• Figure 5, Figure 6, Figure 7, and Figure 8: Addition of notes
• Section 1.2.3.2: Addition of note on PCI timing
• Table 14, Table 15, Table 16, Table 17, Table 18: Addition of note 1 concerning minimum
operating frequencies
• Addition of statement before clock tables about selection of clock configuration and input
frequency
• Table 19 and Table 21: Addition of note 1 to CPM pins
70
MPC8280HardwareSpecifications
MOTOROLA
Ordering Information
MOTOROLA
MPC8280HardwareSpecifications
71
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution
P.O. Box 5405, Denver, Colorado 80217
1-480-768-2130
(800) 521-6274
JAPAN:
Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu Minato-ku
Tokyo 106-8573 Japan
Information in this document is provided solely to enable system and software
implementers to use Motorola products.There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits or
integrated circuits based on the information in this document.
81-3-3440-3569
ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre, 2 Dai King Street
Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters which may be provided in Motorola data sheets
and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts.
Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which
the failure of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
TECHNICAL INFORMATION CENTER:
(800) 521-6274
HOME PAGE:
www.motorola.com/semiconductors
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark
Office. digital dna is a trademark of Motorola, Inc. The PowerPC name is a
trademark of IBM Corp. and is used under license. All other product or service
names are the property of their respective owners. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
© Motorola, Inc. 2003
MPC8280EC/D
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明