MPC8250ACZQIHBC [MOTOROLA]
32-BIT, 200MHz, RISC PROCESSOR, PBGA516, 27 X 27 MM, 1.25 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-516;
| 型号： | MPC8250ACZQIHBC |
| 厂家： | 
MOTOROLA |
| 描述： | 32-BIT, 200MHz, RISC PROCESSOR, PBGA516, 27 X 27 MM, 1.25 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-516 外围集成电路 |
| 文件： | 总73页 (文件大小：835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Technical Data
MPC8250EC/D
Rev.0.9 8/2003
MPC8250
Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC8250 PowerQUICC II™
communications processor.
The following topics are addressed:
Topic
Page
2
Section 1.1, “Features”
Section 1.2, “Electrical and Thermal Characteristics”
Section 1.2.1, “DC Electrical Characteristics”
Section 1.2.2, “Thermal Characteristics”
Section 1.2.3, “Power Considerations”
Section 1.2.4, “AC Electrical Characteristics”
Section 1.3, “Clock Configuration Modes”
Section 1.3.1, “Local Bus Mode”
Section 1.3.2, “PCI Mode”
5
5
10
10
11
19
19
22
28
53
56
Section 1.4, “Pinout”
Section 1.5, “Package Description”
Section 1.6, “Ordering Information”
The MPC8250 is available in two packages—the standard ZU package (480 TBGA) and an
alternate VR package (516 PBGA)—as described in Section 1.4, “Pinout,” and Section 1.5,
“Package Description.” For more information on VR packages, contact your Motorola sales
office. Note that throughout this document references to the MPC8250 are inclusive of its VR
version unless otherwise specified.
NOTE: Document Revision History
Changes to this document are summarized in Table 23 on
page 56.
Features
Figure 1 shows the block diagram for the MPC8250.
16 Kbytes
I-Cache
I-MMU
System Interface Unit
(SIU)
60x Bus
G2 Core
16 Kbytes
D-Cache
Bus Interface Unit
PCI Bus
32 bits, up to 66 MHz
60x-to-PCI
Bridge
D-MMU
or
60x-to-Local
Bridge
Local Bus
32 bits, up to 66 MHz
Communication Processor Module (CPM)
Memory Controller
Clock Counter
Timers
Serial
DMAs
32 Kbytes
Dual-Port RAM
Interrupt
Controller
Parallel I/O
32-bit RISC Microcontroller
and Program ROM
4 Virtual
IDMAs
System Functions
Baud Rate
Generators
I2C
MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2
SPI
Time Slot Assigner
Serial Interface
Non-Multiplexed
I/O
3 MII
Ports
4 TDM Ports
Figure 1. MPC8250 Block Diagram
1.1 Features
The major features of the MPC8250 are as follows:
•
•
Footprint-compatible with the MPC8260
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–200 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
2
MPC8250 Hardware Specifications
MOTOROLA
Features
•
•
Separate power supply for internal logic (1.8 V) and for I/O (3.3V)
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
•
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
•
•
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
•
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
•
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
•
CPU core can be disabled and the device can be used in slave mode to an external core
MOTOROLA
MPC8250 Hardware Specifications
3
Features
•
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible
support for communications protocols
— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– Transparent
– HDLC—Up to T3 rates (clear channel)
— One multichannel controller (MCC2)
– Handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four
subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
2
2
— One inter-integrated circuit (I C) controller (identical to the MPC860 I C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to four TDM interfaces
– Supports one group of four TDM channels
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
4
MPC8250 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
PCI bridge
•
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI Host Bridge or Peripheral capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the MPC8265A) required by the PCI standard as well as message and
doorbell registers
— Supports the I O standard
2
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0
August 3, 1998)
— Support for 66 MHz, 3.3 V specification
— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
— Makes use of the local bus signals, so there is no need for additional pins
1.2 Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8250.
1.2.1 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MPC8250. Table 1 shows the maximum
electrical ratings.
MOTOROLA
MPC8250 Hardware Specifications
5
Electrical and Thermal Characteristics
Table 1. Absolute Maximum Ratings
1
Rating
Symbol
Value
Unit
2
Core supply voltage
VDD
VCCSYN
VDDH
VIN
-0.3 – 2.5
-0.3 – 2.5
V
V
2
PLL supply voltage
3
I/O supply voltage
-0.3 – 4.0
V
4
Input voltage
GND(-0.3) – 3.6
120
V
Junction temperature
T
˚C
˚C
j
Storage temperature range
T
(-55) – (+150)
STG
1
2
3
4
Absolute maximum ratings are stress ratings only; functional operation (see Table 2) at the maximums is not
guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on
reset.
Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH
should not exceed VDD/VCCSYN by more than 2.5 V during normal operation.
Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
Table 2 lists recommended operational voltage conditions.
1
Table 2. Recommended Operating Conditions
Rating
Symbol
Value
Unit
2
2
3
3
4
Core supply voltage
PLL supply voltage
I/O supply voltage
VDD
VCCSYN
VDDH
VIN
1.7 – 1.9
1.7–2.1
1.9 –2.2
V
V
4
1.7 – 1.9
1.7–2.1
1.9–2.2
3.135 – 3.465
V
Input voltage
GND (-0.3) – 3.465
V
5
Junction temperature (maximum)
Ambient temperature
T
105
˚C
˚C
j
5
T
0–70
A
1
Caution: These are the recommended and tested operating conditions. Proper device operating outside of these
conditions is not guaranteed.
CPU frequency less than or equal to 200 MHz.
CPU frequency greater than 200 MHz but less than 233 MHz.
CPU frequency greater than or equal to 233 MHz.
2
3
4
5
Note that for extended temperature parts the range is (-40) – 105 .
T
T
j
A
NOTE: Core, PLL, and I/O Supply Voltages
VDDH, VCCSYN, and VDD must track each other and both must vary in
the same direction—in the positive direction (+5% and +0.1 Vdc) or in the
negative direction (-5% and -0.1 Vdc).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or V ).
CC
Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the
MPC8280. Note that in PCI mode the I/O interface is different.
6
MPC8250 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
4 V
GV + 5%
DD
V
V
GV
IH
DD
GND
GND – 0.3 V
IL
GND – 1.0 V
Not to exceed 10%
of t
SDRAM_CLK
Figure 2. Overshoot/Undershoot Voltage
Table 3 shows DC electrical characteristics.
1
Table 3. DC Electrical Characteristics
Characteristic
Symbol
Min
Max
Unit
Input high voltage, all inputs except CLKIN
Input low voltage
V
2.0
GND
2.4
GND
—
3.465
0.8
3.465
0.4
10
V
V
IH
V
IL
CLKIN input high voltage
V
V
IHC
CLKIN input low voltage
V
I
V
ILC
2
Input leakage current, V = VDDH
µA
µA
µA
µA
V
IN
IN
2
Hi-Z (off state) leakage current, V = VDDH
I
—
10
IN
OZ
Signal low input current, V = 0.8 V
I
—
1
IL
L
Signal high input current, V = 2.0 V
I
—
1
IH
H
Output high voltage, I = –2 mA
V
2.4
—
OH
OH
MOTOROLA
MPC8250 Hardware Specifications
7
Electrical and Thermal Characteristics
Table 3. DC Electrical Characteristics (Continued)
1
Characteristic
Symbol
Min
Max
Unit
I
= 7.0mA
V
—
0.4
V
OL
OL
BR
BG
ABB/IRQ2
TS
A[0-31]
TT[0-4]
TBST
TSIZE[0–3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0-63]
DP(0)/RSRV/EXT_BR2
DP(1)/IRQ1/EXT_BG2
DP(2)/TLBISYNC/IRQ2/EXT_DBG2
DP(3)/IRQ3/EXT_BR3/CKSTP_OUT
DP(4)/IRQ4/EXT_BG3/CORE_SREST
DP(5)/TBEN/IRQ5/EXT_DBG3
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
PORESET
HRESET
SRESET
RSTCONF
QREQ
8
MPC8250 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
1
Table 3. DC Electrical Characteristics (Continued)
Characteristic
Symbol
Min
Max
Unit
I
= 5.3mA
V
—
0.4
V
OL
OL
CS[0-9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE(0:7)/PSDDQM(0:7)/PBS(0:7)
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM[0:3]/LBS[0–3]/PCI_CFG[0–3
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LSDAMUX/LGPL5/PCI_MODCK
LWR
MODCK1/AP(1)/TC(0)/BNKSEL(0)
MODCK2/AP(2)/TC(1)/BNKSEL(1)
MODCK3/AP(3)/TC(2)/BNKSEL(2)
I
= 3.2mA
OL
L_A14/PAR
L_A15/FRAME/SMI
L_A16/TRDY
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTA
L_A30/REQ2
L_A31
LCL_D(0-31)/AD(0-31)
LCL_DP(0-3)/C/BE(0-3)
PA[0–31]
PB[4–31]
PC[0–31]
PD[4–31]
TDO
1
2
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input.To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
The leakage current is measured for nominal VDD, VCCSYN, and VDD.
MOTOROLA
MPC8250 Hardware Specifications
9
Electrical and Thermal Characteristics
1.2.2 Thermal Characteristics
Table 4 describes thermal characteristics.
Table 4. Thermal Characteristics
Value
Characteristic
Symbol
Unit
Air Flow
480 TBGA
516 PBGA
(ZU package) (VR package)
Junction to ambient—
single-layer board
13
10
11
8
24
18
16
13
8
Natural convection
1
1 m/s
θ
°C/W
JA
Junction to ambient—
four-layer board
Natural convection
1 m/s
—
2
Junction to board
θ
4
°C/W
°C/W
JB
3
Junction to case
θ
1.1
6
—
JC
1
2
Assumes no thermal vias
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
3
1.2.3 Power Considerations
The average chip-junction temperature, T , in °C can be obtained from the following:
J
T = T + (P x θJA)
(1)
J
A
D
where
T = ambient temperature °C
A
θJA = package thermal resistance, junction to ambient, °C/W
P = P
+ P
I/O
D
INT
P
P
= I x V Watts (chip internal power)
DD DD
INT
= power dissipation on input and output pins (determined by user)
I/O
For most applications P < 0.3 x P . If P is neglected, an approximate relationship between P and T
I/O
INT
I/O
D
J
is the following:
P = K/(T + 273° C)
(2)
D
J
Solving equations (1) and (2) for K gives:
2
K = P x (T + 273° C) + θJA x P
(3)
D
A
D
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by solving
D
A
D
J
equations (1) and (2) iteratively for any value of T .
A
10
MPC8250 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
1.2.3.1 Layout Practices
Each V pin should be provided with a low-impedance path to the board’s power supply. Each ground pin
CC
should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct
groups of logic on chip. The V power supply should be bypassed to ground using at least four 0.1 µF
CC
by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip V and ground should be kept to less than half an inch
CC
per capacitor lead.A four-layer board is recommended, employing two inner layers asVCC and GND planes.
All output pins on the MPC8250 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize overdamped conditions and reflections caused by these
fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V and GND circuits. Pull up all unused inputs or signals that will be inputs
CC
during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required for conditions above P = 3W (when the ambient temperature is 70˚ C or
D
greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that the
I/O power should be included when determining whether to use a heat sink.
1
Table 5. Estimated Power Dissipation for Various Configurations
2
P
(W)
INT
Bus
(MHz)
CPM
Core CPU
CPM
(MHz)
CPU
(MHz)
Vddl 1.8 Volts
Vddl 2.0 Volts
Multiplier Multiplier
Nominal Maximum Nominal Maximum
66.66
66.66
66.66
66.66
83.33
83.33
83.33
2
2.5
3
3
3
133
166
200
200
166
166
208
200
200
266
300
250
250
291
1.2
1.3
—
2
2.1
—
—
—
—
—
1.8
1.9
2.3
2.4
2.2
2.2
2.4
2.3
2.3
2.9
3.1
2.8
2.8
3.1
4
3
4.5
3
—
2
—
2
3
—
2.5
3.5
—
1
2
Test temperature = room temperature (25˚ C)
= I x V Watts
P
INT
DD
DD
1.2.4 AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for the 66 MHz MPC8250 device. Note that AC timings are based on a 50-pf load. Typical output
buffer impedances are shown in Table 6.
MOTOROLA
MPC8250 Hardware Specifications
11
Electrical and Thermal Characteristics
Table 6. Output Buffer Impedances
1
Output Buffers
60x bus
Typical Impedance (Ω)
40
40
40
46
25
Local bus
Memory controller
Parallel I/O
PCI
1
These are typical values at 65˚ C. The impedance may vary
by ±25% with process and temperature.
Table 7 lists CPM output characteristics.
1
Table 7. AC Characteristics for CPM Outputs
Spec Number
Max Delay (ns) Min Delay (ns)
66 MHz 83 MHz 66 MHz 83 MHz
Characteristic
Max
Min
sp36a
sp36b
sp40
sp37a
sp37b
sp41
FCC outputs—internal clock (NMSI)
FCC outputs—external clock (NMSI)
TDM outputs/SI
6
5.5
12
16
16
16
11
11
1
2
1
1
14
25
19
19
14
14
5
4
sp38a
sp38b
sp42
sp39a
sp39b
sp43
SCC/SMC/SPI/I2C outputs—internal clock (NMSI)
Ex_SCC/SMC/SPI/I2C outputs—external clock (NMSI)
TIMER/IDMA outputs
1
0.5
1
2
1
0.5
0.5
sp42a
sp43a
PIO outputs
0.5
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
Table 8 lists CPM input characteristics.
1
Table 8. AC Characteristics for CPM Inputs
Spec Number
Setup (ns)
Hold (ns)
Characteristic
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp16a
sp16b
sp20
sp17a
sp17b
sp21
FCC inputs—internal clock (NMSI)
FCC inputs—external clock (NMSI)
TDM inputs/SI
10
3
8
2.5
12
16
4
0
3
0
2
15
20
5
12
0
10
0
sp18a
sp18b
sp22
sp19a
sp19b
sp23
SCC/SMC/SPI/I2C inputs—internal clock (NMSI)
SCC/SMC/SPI/I2C inputs—external clock (NMSI)
PIO/TIMER/IDMA inputs
5
4
10
8
3
3
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
Note that although the specifications generally reference the rising edge of the clock, the following AC
timing diagrams also apply when the falling edge is the active edge.
12
MPC8250 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 3 shows the FCC external clock.
Serial ClKin
sp17b
sp16b
FCC input signals
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 0
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 1
Figure 3. FCC External Clock Diagram
Figure 4 shows the FCC internal clock.
BRG_OUT
sp17a
sp16a
FCC input signals
FCC output signals
sp36a/sp37a
Note: When GFMR.TCI = 0
sp36a/sp37a
FCC output signals
Note: When GFMR.TCI = 1
Figure 4. FCC Internal Clock Diagram
2
Figure 5 shows the SCC/SMC/SPI/I C external clock.
MOTOROLA
MPC8250 Hardware Specifications
13
Electrical and Thermal Characteristics
Serial CLKin
sp19b
sp18b
SCC/SMC/SPI/I2C input signals
(See note.)
sp38b/sp39b
SCC/SMC/SPI/I2C output signals
(See note.)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
2
Figure 5. SCC/SMC/SPI/I C External Clock Diagram
2
Figure 6 shows the SCC/SMC/SPI/I C internal clock.
BRG_OUT
sp19a
sp18a
SCC/SMC/SPI/I2C input signals
(See note.)
sp38a/sp39a
SCC/SMC/SPI/I2C output signals
(See note.)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
2
Figure 6. SCC/SMC/SPI/I C Internal Clock Diagram
Figure 7 shows TDM input and output signals.
14
MPC8250 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Serial CLKin
sp20
sp21
TDM input signals
sp40/sp41
TDM output signals
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 7. TDM Signal Diagram
Figure 8 shows PIO, timer, and DMA signals.
Sys clk
sp23
sp22
PIO/IDMA/TIMER[TGATE assertion] input signals
(See note)
sp23
sp22
TIMER input signal [TGATE deassertion]
(See note)
sp42/sp43
IDMA output signals
sp42/sp43
sp42a/sp43a
TIMER(sp42/43)/ PIO(sp42a/sp43a)
output signals
Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
Figure 8. PIO, Timer, and DMA Signal Diagram
Table 9 lists SIU input characteristics.
MOTOROLA
MPC8250 Hardware Specifications
15
Electrical and Thermal Characteristics
Table 9. AC Characteristics for SIU Inputs
1
Spec Number
Setup (ns)
Hold (ns)
Characteristic
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp11
sp12
sp13
sp14
sp15
sp10
sp10
sp10
sp10
sp10
AACK/ARTRY/TA/TS/TEA/DBG/BG/BR
Data bus in normal mode
Data bus in ECC and PARITY modes
DP pins
6
5
8
7
5
5
4
6
6
4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
All other pins
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
Table 10 lists SIU output characteristics.
1
Table 10. AC Characteristics for SIU Outputs
Spec Number
Max Delay (ns)
Min Delay (ns)
Characteristic
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp31
sp32
sp30
sp30
sp30
sp30
sp30
sp30
PSDVAL/TEA/TA
7
8
6
6.5
6.5
7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ADD/ADD_atr./BADDR/CI/GBL/WT
sp33a
sp33b
sp34
Data bus
6.5
8
DP
Memory controller signals/ALE
All other signals
6
5
sp35
6
5.5
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the
signal. Timings are measured at the pin.
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when ECC or PARITY are used. Also, sp33a
can be used as the AC specification for DP signals.
Figure 9 shows the interaction of several bus signals.
16
MPC8250 Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
CLKin
sp10
sp10
sp11
AACK/ARTRY/TA/TS/TEA/
DBG/BG/BR input signals
sp12
sp15
DATA bus normal mode
input signal
sp10
sp30
All other input signals
sp31
sp32
PSDVAL/TEA/TA output signals
sp30
sp30
sp30
ADD/ADD_atr/BADDR/CI/
GBL/WT output signals
sp33a
sp35
DATA bus output signals
All other output signals
Figure 9. Bus Signals
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
CLKin
sp10
sp13
DATA bus, ECC, and PARITY mode input signals
sp10
sp14
DP mode input signal
sp33b/sp30
DP mode output signal
Figure 10. Parity Mode Diagram
Figure 11 shows signal behavior in MEMC mode.
MOTOROLA
MPC8250 Hardware Specifications
17
Electrical and Thermal Characteristics
CLKin
V_CLK
sp34/sp30
Memory controller signals
Figure 11. MEMC Mode Diagram
NOTE
Generally, all MPC8250 bus and system output signals are driven from the
rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is
divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the
rising edge, and T3 at the falling edge, of CLKin. However, the spacing of
T2 and T4 depends on the PLL clock ratio selected, as shown in Table 11.
Table 11. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
PLL Clock Ratio
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6
1/4 CLKin
1/2 CLKin
3/4 CLKin
1:2.5
1:3.5
3/10 CLKin
4/14 CLKin
1/2 CLKin
1/2 CLKin
8/10 CLKin
11/14 CLKin
Figure 12 is a graphical representation of Table 11.
CLKin
CLKin
CLKin
for 1:2, 1:3, 1:4, 1:5, 1:6
T1
T1
T1
T2
T3
T3
T3
T4
for 1:2.5
T2
T4
for 1:3.5
T2
T4
Figure 12. Internal Tick Spacing for Memory Controller Signals
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
18
MPC8250 Hardware Specifications
MOTOROLA
Clock Configuration Modes
1.3 Clock Configuration Modes
The MPC8250 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set according
to three input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 12.
Table 12. MPC8250 Clocking Modes
Pins
PCI Clock
Frequency Range
(MHZ)
Clocking Mode
Reference
1
PCI_MODE PCI_CFG[0] PCI_MODCK
1
0
0
0
0
—
0
—
0
Local bus
PCI host
—
Table 13 and Table 14
Table 15 and Table 16
50–66
25–50
50–66
25–50
0
1
1
0
PCI agent
Table 17 and Table 18
1
1
1
Determines PCI clock frequency range. Refer to Section 1.3.2, “PCI Mode.”
In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven
bits during the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits from
hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the
selected MPC8250 clock operation mode as described in the following sections.
NOTE
Clock configurations change only after POR is asserted.
1.3.1 Local Bus Mode
Table 13 shows the eight basic clock configurations for the MPC8250. Another 49 configurations are
available by using the configuration pin (RSTCONF) and driving four pins on the data bus.
Table 13. Clock Default Configurations
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Factor
Core
Frequency
MODCK[1–3]
Frequency
Factor
000
001
010
011
100
101
110
111
33 MHz
33 MHz
33 MHz
33 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
166 MHz
166 MHz
4
5
133 MHz
166 MHz
133 MHz
166 MHz
166 MHz
200 MHz
166 MHz
200 MHz
4
4
4
5
2
2.5
3
2
2.5
2.5
2.5
3
Table 14 describes all possible clock configurations when using the hard reset configuration sequence.
Note also that basic modes are shown in boldface type. The frequencies listed are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does
not exceed the frequency rating of the user’s device.
MOTOROLA
MPC8250 Hardware Specifications
19
Clock Configuration Modes
1
Table 14. Clock Configuration Modes
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Core
Frequency
MODCK_H–MODCK[1–3]
2,3
2
2
2
2
Frequency
Factor
Factor
0001_000
0001_001
0001_010
0001_011
0001_100
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
2
2
2
2
2
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0001_101
0001_110
0001_111
0010_000
0010_001
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
3
3
3
3
3
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0010_010
0010_011
0010_100
0010_101
0010_110
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
4
4
4
4
4
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0010_111
0011_000
0011_001
0011_010
0011_011
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
5
5
5
5
5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0011_100
0011_101
0011_110
0011_111
0100_000
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
6
6
6
6
6
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
20
MPC8250 Hardware Specifications
MOTOROLA
Clock Configuration Modes
Table 14. Clock Configuration Modes (Continued)
1
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Core
Frequency
MODCK_H–MODCK[1–3]
2,3
2
2
2
2
Frequency
Factor
Factor
0100_001
0100_010
0100_011
0100_100
0100_101
0100_110
Reserved
0100_111
0101_000
0101_001
0101_010
0101_011
0101_100
Reserved
0101_101
0101_110
0101_111
0110_000
0110_001
0110_010
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2
2
2
2
2
2
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
0110_011
0110_100
0110_101
0110_110
0110_111
0111_000
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2.5
2.5
2.5
2.5
2.5
2.5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
0111_001
0111_010
0111_011
0111_100
0111_101
0111_110
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
3
3
3
3
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
MOTOROLA
MPC8250 Hardware Specifications
21
Clock Configuration Modes
Table 14. Clock Configuration Modes (Continued)
1
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Core
Frequency
MODCK_H–MODCK[1–3]
2,3
2
2
2
2
Frequency
Factor
Factor
0111_111
1000_000
1000_001
1000_010
1000_011
1000_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
3.5
3.5
3.5
3.5
3.5
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
1
2
Because of speed dependencies, not all of the possible configurations in Table 14 are applicable.
The user should choose the input clock frequency and the multiplication factors such that the frequency of the
CPU is equal to or greater than 133 MHz (150 MHz for extended temperature parts) and the CPM ranges
between 66–233 MHz.
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
the resulting configuration does not exceed the frequency rating of the user’s part.
3
1.3.2 PCI Mode
The PCI mode is selected according to three input pins, as shown in Table 12. In addition, note the
following:
NOTE: PCI_MODCK
In PCI mode only, PCI_MODCK comes from the LGPL5 pin and
MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.
NOTE:Tval (Output Hold)
The minimum Tval = 2 when PCI_MODCK = 1, and the minimum
Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock
configurations that fit this condition to achieve PCI-compliant AC timing.
NOTE
Clock configurations change only after POR is asserted.
1.3.2.1 PCI Host Mode
The frequencies listed are for the purpose of illustration only. Users must select a mode and input bus
frequency so that the resulting configuration does not exceed the frequency rating of the user’s device.
22
MPC8250 Hardware Specifications
MOTOROLA
Clock Configuration Modes
Table 15. Clock Default Configurations in PCI Host Mode (MODCK_HI = 0000)
Input Clock
MODCK[1–3] Frequency Multiplication
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
PCI Division
PCI
Frequency
1
2
2
Factor
(Bus)
Factor
000
001
010
011
100
101
110
111
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2
2
133 MHz
133 MHz
166 MHz
166 MHz
166 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
200 MHz
233 MHz
266 MHz
200 MHz
233 MHz
266 MHz
2/4
2/4
3/6
3/6
3/6
3/6
3/6
3/6
66/33 MHz
66/33 MHz
55/28 MHz
55/28 MHz
55/28 MHz
66/33 MHz
66/33 MHz
66/33 MHz
2.5
2.5
2.5
3
3
3.5
4
3
3
3.5
4
3
1
2
Assumes MODCK_HI = 0000.
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.) Refer to Table 12.
Table 16 describes all possible clock configurations when using the MPC8250’s internal PCI bridge in host
mode.
Table 16. Clock Configuration Modes in PCI Host Mode
Input Clock
Frequency
CPM
Multiplication
Factor
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
PCI Division
PCI
Frequency
MODCK_H –
MODCK[1–3]
1
2
2
Factor
(Bus)
0001_000
0001_001
0001_010
0001_011
33 MHz
33 MHz
33 MHz
33 MHz
3
3
3
3
100 MHz
100 MHz
100 MHz
100 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
3/6
3/6
3/6
3/6
33/16 MHz
33/16 MHz
33/16 MHz
33/16 MHz
0010_000
0010_001
0010_010
0010_011
33 MHz
33 MHz
33 MHz
33 MHz
4
4
4
4
133 MHz
133 MHz
133 MHz
133 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
4/8
4/8
4/8
4/8
33/16 MHz
33/16 MHz
33/16 MHz
33/16 MHz
3
0011_000
33 MHz
33 MHz
33 MHz
33 MHz
5
5
5
5
166 MHz
166 MHz
166 MHz
166 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
5
5
5
5
33 MHz
33 MHz
33 MHz
33 MHz
3
0011_001
3
0011_010
3
0011_011
3
0100_000
33 MHz
33 MHz
33 MHz
6
6
6
200 MHz
200 MHz
200 MHz
5
6
7
166 MHz
200 MHz
233 MHz
6
6
6
33 MHz
33 MHz
33 MHz
3
0100_001
3
0100_010
MOTOROLA
MPC8250 Hardware Specifications
23
Clock Configuration Modes
Table 16. Clock Configuration Modes in PCI Host Mode (Continued)
Input Clock
Frequency
CPM
Multiplication
Factor
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
PCI Division
PCI
Frequency
MODCK_H –
MODCK[1–3]
1
2
2
Factor
(Bus)
3
0100_011
33 MHz
6
200 MHz
8
266 MHz
6
33 MHz
0101_000
0101_001
0101_010
0101_011
0101_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2
2
2
2
2
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
2/4
2/4
2/4
2/4
2/4
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
3.5
4
4.5
0110_000
0110_001
0110_010
0110_011
0110_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2.5
2.5
2.5
2.5
2.5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3/6
3/6
3/6
3/6
3/6
55/28 MHz
55/28 MHz
55/28 MHz
55/28 MHz
55/28 MHz
3.5
4
4.5
0111_000
0111_001
0111_010
0111_011
0111_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
3
3
3
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3/6
3/6
3/6
3/6
3/6
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
3.5
4
4.5
1000_000
1000_001
1000_010
1000_011
1000_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
3
3
3
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
4/8
4/8
4/8
4/8
4/8
50/25 MHz
50/25 MHz
50/25 MHz
50/25 MHz
50/25 MHz
3.5
4
4.5
1001_000
1001_001
1001_010
1001_011
1001_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
3.5
3.5
3.5
3.5
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
4/8
4/8
4/8
4/8
4/8
58/29 MHz
58/29 MHz
58/29 MHz
58/29 MHz
58/29 MHz
3.5
4
4.5
1010_000
1010_001
100 MHz
100 MHz
2
2
200 MHz
200 MHz
2
200 MHz
250 MHz
3/6
3/6
66/33 MHz
66/33 MHz
2.5
24
MPC8250 Hardware Specifications
MOTOROLA
Clock Configuration Modes
Table 16. Clock Configuration Modes in PCI Host Mode (Continued)
Input Clock
Frequency
CPM
Multiplication
Factor
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
PCI Division
PCI
Frequency
MODCK_H –
MODCK[1–3]
1
2
2
Factor
(Bus)
1010_010
1010_011
1010_100
100 MHz
100 MHz
100 MHz
2
2
2
200 MHz
200 MHz
200 MHz
3
3.5
4
300 MHz
350 MHz
400 MHz
3/6
3/6
3/6
66/33 MHz
66/33 MHz
66/33 MHz
1011_000
1011_001
1011_010
1011_011
1011_100
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
2.5
2.5
2.5
2.5
2.5
250 MHz
250 MHz
250 MHz
250 MHz
250 MHz
2
2.5
3
200 MHz
250 MHz
300 MHz
350 MHz
400 MHz
4/8
4/8
4/8
4/8
4/8
62/31 MHz
62/31MHz
62/31 MHz
62/31 MHz
62/31 MHz
3.5
4
1
2
3
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so
that the resulting configuration does not exceed the frequency rating of the user’s part.
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.). Refer to Table 12
In this mode, PCI_MODCK must be “0”.
1.3.2.2 PCI Agent Mode
The frequencies listed are for the purpose of illustration only. Users must select a mode and input bus
frequency so that the resulting configuration does not exceed the frequency rating of the user’s device.
Table 17. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000)
Input Clock
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
1
MODCK[1–3] Frequency Multiplication
3
4
Factor
Frequency
2
2
(PCI)
Factor
000
001
010
011
100
101
110
111
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
2/4
2/4
3/6
3/6
3/6
3/6
4/8
4/8
133 MHz
133 MHz
200 MHz
200 MHz
200 MHz
200 MHz
266 MHz
266 MHz
2.5
3
166 MHz
200 MHz
200 MHz
266 MHz
240 MHz
280 MHz
300 MHz
300 MHz
2
2
66 MHz
66 MHz
66 MHz
66 MHz
80 MHz
80 MHz
88 MHz
100 MHz
3
3
4
3
3
2.5
2.5
3
3.5
3.5
3
2.5
1
2
Assumes MODCK_HI = 0000.
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2. Refer to Table 12
Core frequency = (60x bus frequency)(core multiplication factor)
3
4
Bus frequency = CPM frequency / bus division factor
Table 18 describes all possible clock configurations when using the MPC8250’s internal PCI bridge in agent
mode.
MOTOROLA
MPC8250 Hardware Specifications
25
Clock Configuration Modes
Table 18. Clock Configuration Modes in PCI Agent Mode
Input Clock
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
MODCK_H –
MODCK[1–3]
Frequency Multiplication
3
4
Factor
Frequency
1,2
1
(PCI)
Factor
0001_001 66/33 MHz
0001_010 66/33 MHz
0001_011 66/33 MHz
0001_100 66/33 MHz
2/4
2/4
2/4
2/4
133 MHz
133 MHz
133 MHz
133 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
4
4
4
4
33 MHz
33 MHz
33 MHz
33 MHz
0010_001 50/25 MHz
0010_010 50/25 MHz
0010_011 50/25 MHz
0010_100 50/25 MHz
3/6
3/6
3/6
3/6
150 MHz
150 MHz
150 MHz
150 MHz
3
180 MHz
210 MHz
240 MHz
270 MHz
2.5
2.5
2.5
2.5
60 MHz
60 MHz
60 MHz
60 MHz
3.5
4
4.5
0011_000 66/33 MHz
0011_001 66/33 MHz
0011_010 66/33 MHz
0011_011 66/33 MHz
0011_100 66/33 MHz
2/4
2/4
2/4
2/4
2/4
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
2.5
3
110MHz
132 MHz
154 MHz
176MHz
198 MHz
3
3
3
3
3
44 MHz
44 MHz
44 MHz
44 MHz
44 MHz
3.5
4
4.5
0100_000 66/33 MHz
0100_001 66/33 MHz
0100_010 66/33 MHz
0100_011 66/33 MHz
0100_100 66/33 MHz
3/6
3/6
3/6
3/6
3/6
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3
3
3
3
3
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
4
4.5
5
0101_000
0101_001
0101_010
0101_011
0101_100
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
5
5
5
5
5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
2.5
2.5
2.5
2.5
2.5
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
5
5
5
5
3.5
4
4.5
0110_000 50/25 MHz
0110_001 50/25 MHz
0110_010 50/25 MHz
0110_011 50/25 MHz
0110_100 50/25 MHz
4/8
4/8
4/8
4/8
4/8
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3
3
3
3
3
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
4
4.5
26
MPC8250 Hardware Specifications
MOTOROLA
Clock Configuration Modes
Bus Division 60x Bus
Table 18. Clock Configuration Modes in PCI Agent Mode (Continued)
Input Clock
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
MODCK_H –
MODCK[1–3]
Frequency Multiplication
3
4
Frequency
Factor
Frequency
1,2
1
(PCI)
Factor
0111_000 66/33 MHz
0111_001 66/33 MHz
0111_010 66/33 MHz
0111_011 66/33 MHz
3/6
3/6
3/6
3/6
200 MHz
200 MHz
200 MHz
200 MHz
2
200 MHz
250 MHz
300 MHz
350 MHz
2
2
2
2
100 MHz
100 MHz
100 MHz
100 MHz
2.5
3
3.5
1000_000 66/33 MHz
1000_001 66/33 MHz
1000_010 66/33 MHz
1000_011 66/33 MHz
1000_100 66/33 MHz
1000_101 66/33 MHz
3/6
3/6
3/6
3/6
3/6
3/6
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2
2.5
3
160 MHz
200 MHz
240 MHz
280 MHz
320 MHz
360 MHz
2.5
2.5
2.5
2.5
2.5
2.5
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
3.5
4
4.5
1001_000 66/33 MHz
1001_001 66/33 MHz
1001_010 66/33 MHz
1001_011 66/33 MHz
1001_100 66/33 MHz
4/8
4/8
4/8
4/8
4/8
266 MHz
266 MHz
266 MHz
266 MHz
266 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
4
4
4
4
4
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
4
4.5
1010_000 66/33 MHz
1010_001 66/33 MHz
1010_010 66/33 MHz
1010_011 66/33 MHz
1010_100 66/33 MHz
4/8
4/8
4/8
4/8
4/8
266 MHz
266 MHz
266 MHz
266 MHz
266 MHz
2.5
3
222 MHz
266 MHz
300 MHz
350 MHz
400 MHz
3
3
3
3
3
88 MHz
88 MHz
88 MHz
88 MHz
88 MHz
3.5
4
4.5
1011_000 66/33 MHz
1011_001 66/33 MHz
1011_010 66/33 MHz
1011_011 66/33 MHz
1011_100 66/33 MHz
4/8
4/8
4/8
4/8
4/8
266 MHz
266 MHz
266 MHz
266 MHz
266 MHz
2
2.5
3
212MHz
265 MHz
318 MHz
371 MHz
424 MHz
2.5
2.5
2.5
2.5
2.5
106 MHz
106 MHz
106 MHz
106 MHz
106 MHz
3.5
4
1
2
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency
is divided by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2. Refer to
Table 12
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so
that the resulting configuration does not exceed the frequency rating of the user’s part.
Core frequency = (60x bus frequency)(core multiplication factor)
3
4
5
Bus frequency = CPM frequency / bus division factor
In this mode, PCI_MODCK must be “1”.
MOTOROLA
MPC8250 Hardware Specifications
27
Pinout
1.4 Pinout
This section provides the pin assignments and pinout list for the MPC8250.
1.4.1 ZU Package
The following figures and table represent the standard 480 TBGA package. For information on the alternate
package, refer to Section 1.4.2, “VR Package” on page 40.
1.4.1.1 ZU Pin Assignments
Figure 13 shows the pinout of the ZU package as viewed from the top surface.
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
A
B
A
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AA
AB
AC
AD
AE
AF
AG
AH
AJ
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Not to Scale
Figure 13. Pinout of the 480 TBGA Package as Viewed from the Top Surface
28
MPC8250 Hardware Specifications
MOTOROLA
Pinout
Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view.
View
Pressure Sensitive
Adhesive
Copper Heat Spreader
(Oxidized for Insulation)
Etched
Cavity
Die
Attach
Polymide Tape
Die
Glob-Top Filled Area
Soldermask
Glob-Top Dam
Copper Traces
1.27 mm Pitch
Figure 14. Side View of the TBGA Package
Table 19 shows the pinout list of the ZU package of the MPC8250. Table 20 defines conventions and
acronyms used in Table 19.
Table 19. MPC8250 ZU Package Pinout List
Pin Name
Ball
BR
W5
F4
E2
E3
G1
H5
H2
H1
J5
BG
ABB/IRQ2
TS
A0
A1
A2
A3
A4
A5
J4
A6
J3
A7
J2
A8
J1
A9
K4
K3
K2
K1
L5
L4
L3
L2
L1
M5
A10
A11
A12
A13
A14
A15
A16
A17
A18
MOTOROLA
MPC8250 Hardware Specifications
29
Pinout
Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name
Ball
A19
N5
N4
N3
N2
N1
P4
P3
P2
P1
R1
R3
R5
R4
F1
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
TT0
TT1
G4
G3
G2
F2
TT2
TT3
TT4
TBST
TSIZ0
TSIZ1
TSIZ2
TSIZ3
AACK
ARTRY
DBG
DBB/IRQ3
D0
D3
C1
E4
D2
F5
F3
E1
V1
V2
B20
A18
A16
A13
E12
D9
A6
B5
D1
D2
D3
D4
D5
D6
D7
30
MPC8250 Hardware Specifications
MOTOROLA
Pinout
Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name
Ball
D8
A20
E17
B15
B13
A11
E9
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
B7
B4
D19
D17
D15
C13
B11
A8
A5
C5
C19
C17
C15
D13
C11
B8
A4
E6
E18
B17
A15
A12
D11
C8
E7
A3
D18
A17
A14
MOTOROLA
MPC8250 Hardware Specifications
31
Pinout
Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name
Ball
D43
B12
A10
D8
D44
D45
D46
B6
D47
C4
D48
C18
E16
B14
C12
B10
A7
D49
D50
D51
D52
D53
D54
C6
D55
D5
D56
B18
B16
E14
D12
C10
E8
D57
D58
D59
D60
D61
D62
D6
D63
C2
DP0/RSRV/EXT_BR2
IRQ1/DP1/EXT_BG2
B22
A22
E21
D21
C21
B21
A21
E20
V3
IRQ2/DP2/TLBISYNC/EXT_DBG2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
IRQ4/DP4/CORE_SRESET/EXT_BG3
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
PSDVAL
TA
C22
V5
TEA
GBL/IRQ1
W1
U2
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
U3
32
MPC8250 Hardware Specifications
MOTOROLA
Pinout
Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name
Ball
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
Y4
U4
R2
CPU_BR
Y3
CS0
F25
C29
E27
E28
F26
F27
F28
G25
D29
E29
F29
G28
T5
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10/BCTL1
CS11/AP0
BADDR27
BADDR28
U1
ALE
T2
BCTL0
A27
C25
E24
D24
C24
B26
A26
B25
A25
E23
B24
A24
B23
A23
D22
H28
PWE0/PSDDQM0/PBS0
PWE1/PSDDQM1/PBS1
PWE2/PSDDQM2/PBS2
PWE3/PSDDQM3/PBS3
PWE4/PSDDQM4/PBS4
PWE5/PSDDQM5/PBS5
PWE6/PSDDQM6/PBS6
PWE7/PSDDQM7/PBS7
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE0/LSDDQM0/LBS0/PCI_CFG0
MOTOROLA
MPC8250 Hardware Specifications
33
Pinout
Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name
Ball
LWE1/LSDDQM1/LBS1/PCI_CFG1
LWE2/LSDDQM2/LBS2/PCI_CFG2
LWE3/LSDDQM3/LBS3/PCI_CFG3
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LGPL5/LSDAMUX/PCI_MODCK
LWR
H27
H26
G29
D27
C28
E26
D25
C26
B27
D28
N27
T29
L_A14/PAR
L_A15/FRAME/SMI
L_A16/TRDY
R27
R26
R29
R28
W29
P28
N26
AA27
P29
AA26
N25
AA25
AB29
AB28
P25
AB27
H29
J29
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTA
L_A30/REQ2
L_A31/DLLOUT
LCL_D0/AD0
LCL_D1/AD1
LCL_D2/AD2
J28
LCL_D3/AD3
J27
LCL_D4/AD4
J26
LCL_D5/AD5
J25
LCL_D6/AD6
K25
34
MPC8250 Hardware Specifications
MOTOROLA
Pinout
Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name
Ball
LCL_D7/AD7
L29
L27
LCL_D8/AD8
LCL_D9/AD9
L26
LCL_D10/AD10
LCL_D11/AD11
LCL_D12/AD12
LCL_D13/AD13
LCL_D14/AD14
LCL_D15/AD15
LCL_D16/AD16
LCL_D17/AD17
LCL_D18/AD18
LCL_D19/AD19
LCL_D20/AD20
LCL_D21/AD21
LCL_D22/AD22
LCL_D23/AD23
LCL_D24/AD24
LCL_D25/AD25
LCL_D26/AD26
LCL_D27/AD27
LCL_D28/AD28
LCL_D29/AD29
LCL_D30/AD30
LCL_D31/AD31
LCL_DP0/C0/BE0
LCL_DP1/C1/BE1
LCL_DP2/C2/BE2
LCL_DP3/C3/BE3
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
TRST
L25
M29
M28
M27
M26
N29
T25
U27
U26
U25
V29
V28
V27
V26
W27
W26
W25
Y29
Y28
Y25
AA29
AA28
L28
N28
T28
W28
T1
D1
AH3
AG5
AJ3
AE6
TCK
TMS
TDI
MOTOROLA
MPC8250 Hardware Specifications
35
Pinout
Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name
Ball
TDO
AF5
AB4
AG6
AH5
AF6
AA3
AJ4
TRIS
PORESET
HRESET
SRESET
QREQ
RSTCONF
MODCK1/AP1/TC0/BNKSEL0
MODCK2/AP2/TC1/BNKSEL1
MODCK3/AP3/TC2/BNKSEL2
XFC
W2
W3
W4
AB2
AH4
AC29
AC25
AE28
CLKIN1
1
1
1
1
PA0/RESTART1/DREQ3
PA1/REJECT1/DONE3
PA2/CLK20/DACK3
PA3/CLK19/DACK4/L1RXD1A2
PA4/REJECT2/DONE4
PA5/RESTART2/DREQ4
PA6
AG29
AG28
AG26
1
1
1
AE24
1
PA7/SMSYN2
AH25
1
PA8/SMRXD2
AF23
AH23
1
PA9/SMTXD2
1
PA10/MSNUM5
AE22
1
PA11/MSNUM4
AH22
1
PA12/MSNUM3
AJ21
AH20
AG19
1
1
PA13/MSNUM2
PA14/FCC1_RXD3
PA15/FCC1_RXD2
PA16/FCC1_RXD1
PA17/FCC1_RXD0/FCC1_RXD
PA18/FCC1_TXD0/FCC1_TXD
PA19/FCC1_TXD1
PA20/FCC1_TXD2
PA21/FCC1_TXD3
PA22
1
1
1
AF18
AF17
AE16
1
AJ16
1
AG15
1
AJ13
AE13
1
1
AF12
36
MPC8250 Hardware Specifications
MOTOROLA
Pinout
Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name
Ball
1
PA23
AG11
1
PA24/MSNUM1
AH9
1
PA25/MSNUM0
AJ8
1
PA26/FCC1_MII_RX_ER
PA27/FCC1_MII_RX_DV
PA28/FCC1_MII_TX_EN
PA29/FCC1_MII_TX_ER
AH7
1
1
AF7
AD5
1
AF1
AD3
1
PA30/FCC1_MII_CRS/FCC1_RTS
PA31/FCC1_MII_COL
1
AB5
1
1
1
PB4/FCC3_TXD3/L1RSYNCA2/FCC3_RTS
PB5/FCC3_TXD2/L1TSYNCA2/L1GNTA2
PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2
PB7/FCC3_TXD0/FCC3_TXD/L1TXDA2/L1TXD0A2
PB8/FCC3_RXD0/FCC3_RXD/TXD3
PB9/FCC3_RXD1/L1TXD2A2
AD28
AD26
AD25
1
AE26
1
AH27
AG24
AH24
1
1
PB10/FCC3_RXD2
1
PB11/FCC3_RXD3
AJ24
1
1
1
PB12/FCC3_MII_CRS/TXD2
AG22
AH21
AG20
PB13/FCC3_MII_COL/L1TXD1A2
PB14/FCC3_MII_TX_EN/RXD3
1
PB15/FCC3_MII_TX_ER/RXD2
AF19
1
1
1
PB16/FCC3_MII_RX_ER/CLK18
AJ18
AJ17
PB17/FCC3_MII_RX_DV/CLK17
PB18/FCC2_RXD3/L1CLKOD2/L1RXD2A2
PB19/FCC2_RXD2/L1RQD2/L1RXD3A2
PB20/FCC2_RXD1/L1RSYNCD2/L1TXD1A1
PB21/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2
PB22/FCC2_TXD0/FCC2_TXD/L1RXDD2
PB23/FCC2_TXD1/L1TXDD2
AE14
1
AF13
AG12
AH11
AH16
1
1
1
1
AE15
1
1
PB24/FCC2_TXD2/L1RSYNCC2
AJ9
PB25/FCC2_TXD3/L1TSYNCC2/L1GNTC2
PB26/FCC2_MII_CRS/L1RXDC2
AE9
1
AJ7
1
PB27/FCC2_MII_COL/L1TXDC2
AH6
1
PB28/FCC2_MII_RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1
PB29/L1RSYNCB2/FCC2_MII_TX_EN
AE3
AE2
1
MOTOROLA
MPC8250 Hardware Specifications
37
Pinout
Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name
Ball
1
PB30/FCC2_MII_RX_DV/L1RXDB2
PB31/FCC2_MII_TX_ER/L1TXDB2
PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2
PC1/DREQ2/BRGO6/L1RQA2
PC2/FCC3_CD/DONE2
AC5
AC4
1
1
1
AB26
AD29
1
AE29
AE27
1
PC3/FCC3_CTS/DACK2/CTS4
PC4/SI2_L1ST4/FCC2_CD
PC5/SI2_L1ST3/FCC2_CTS
PC6/FCC1_CD
1
1
AF27
AF24
1
1
1
AJ26
AJ25
PC7/FCC1_CTS
PC8/CD4/RENA4/SI2_L1ST2/CTS3
PC9/CTS4/CLSN4/SI2_L1ST1/L1TSYNCA2/L1GNTA2
PC10/CD3/RENA3
AF22
AE21
1
1
AF20
1
PC11/CTS3/CLSN3/L1TXD3A2
PC12/CD2/RENA2
AE19
AE18
1
1
PC13/CTS2/CLSN2
AH18
AH17
AG16
1
1
PC14/CD1/RENA1
PC15/CTS1/CLSN1/SMTXD2
PC16/CLK16/TIN4
1
AF15
1
PC17/CLK15/TIN3/BRGO8
PC18/CLK14/TGATE2
AJ15
1
AH14
AG13
AH12
1
1
PC19/CLK13/BRGO7/SPICLK
PC20/CLK12/TGATE1
1
PC21/CLK11/BRGO6
AJ11
1
PC22/CLK10/DONE1
AG10
1
PC23/CLK9/BRGO5/DACK1
PC24/CLK8/TOUT4
AE10
1
AF9
AE8
1
PC25/CLK7/BRGO4
1
PC26/CLK6/TOUT3/TMCLK
PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
PC30/CLK2/TOUT1
AJ6
1
AG2
1
1
1
AF3
AF2
AE1
AD1
1
PC31/CLK1/BRGO1
1
PD4/BRGO8/FCC3_RTS/SMRXD2
AC28
38
MPC8250 Hardware Specifications
MOTOROLA
Pinout
Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name
Ball
1
PD5/DONE1
PD6/DACK1
AD27
1
1
1
AF29
AF28
PD7/SMSYN1FCC1_TXCLAV2
PD8/SMRXD1/BRGO5
PD9/SMTXD1/BRGO3
PD10/L1CLKOB2/BRGO4
PD11/L1RQB2
AG25
AH26
1
1
1
AJ27
AJ23
1
PD12
AG23
1
PD13
AJ22
AE20
1
PD14/L1CLKOC2/I2CSCL
PD15/L1RQC2/I2CSDA
PD16/SPIMISO
1
AJ20
1
AG18
AG17
1
PD17/BRGO2/SPIMOSI
PD18/SPICLK
1
AF16
1
PD19/SPISEL/BRGO
PD20/RTS4/TENA4/L1RSYNCA2
PD21/TXD4/L1RXD0A2/L1RXDA2
PD22/RXD4/L1TXD0A2/L1TXDA2
PD23/RTS3/TENA3
PD24/TXD3
AH15
1
AJ14
AH13
1
1
AJ12
1
AE12
1
AF10
1
PD25/RXD3
AG9
AH8
AG7
1
1
PD26/RTS2/TENA2
PD27/TXD2
1
1
PD28/RXD2
AE4
PD29/RTS1/TENA1
PD30/TXD1
AG1
AD4
AD2
1
1
PD31/RXD1
VCCSYN
AB3
B9
VCCSYN1
GNDSYN
AB1
AE11
U5
CLKIN2
2
SPARE4
3
PCI_MODE
AF25
V4
2
SPARE6
4
THERMAL0
AA1
MOTOROLA
MPC8250 Hardware Specifications
39
Pinout
Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name
Ball
4
THERMAL1
I/O power
AG4
AG21, AG14, AG8, AJ1, AJ2, AH1,
AH2, AG3, AF4, AE5, AC27, Y27,
T27, P27, K26, G27, AE25, AF26,
AG27, AH28, AH29, AJ28, AJ29,
C7, C14, C16, C20, C23, E10, A28,
A29, B28, B29, C27, D26, E25, H3,
M4, T3, AA4, A1, A2, B1, B2, C3,
D4, E5
Core Power
Ground
U28, U29, K28, K29, A9, A19, B19,
M1, M2, Y1, Y2, AC1, AC2, AH19,
AJ19, AH10, AJ10, AJ5
AA5, AF21, AF14, AF8, AE7, AF11,
AE17, AE23, AC26, AB25,Y26,V25,
T26, R25, P26, M25, K27, H25,
G26, D7, D10, D14, D16, D20, D23,
C9, E11, E13, E15, E19, E22, B3,
G5, H4, K5, M3, P5, T4, Y5, AA2,
AC3
1
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input.To prevent excessive DC
current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
Must be pulled down or left floating.
If PCI is not desired, this pin should be pulled up or left floating.
For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D)
available at www.motorola.com/semiconductors.
2
3
4
Symbols used in Table 19 are described in Table 20.
Table 20. Symbol Legend
Symbol
Meaning
OVERBAR
MII
Signals with overbars, such as TA, are active low.
Indicates that a signal is part of the media independent interface.
1.4.2 VR Package
The following figures and table represent the alternate 516 PBGA package. For information on the standard
package for the MPC8250, refer to Section 1.4.1, “ZU Package” on page 28.
1.4.2.1 VR Pin Assignments
Figure 15 shows the pinout of the VR package as viewed from the top surface.
40
MPC8250 Hardware Specifications
MOTOROLA
Pinout
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
A
B
C
D
E
F
C
D
E
F
G
H
G
H
J
J
K
K
L
L
M
N
M
N
P
R
T
P
R
T
U
U
V
W
Y
V
W
Y
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Not to Scale
Figure 15. Pinout of the 516 PBGA Package (View from Top)
Figure 16 shows the side profile of the PBGA package to indicate the direction of the top surface view.
Wire bonds
Ball bond
Die
attach
Transfer molding compound
Plated substrate via
Screen-printed
solder mask
Cu substrate traces
BT resin glass epoxy
DIE
1 mm pitch
Figure 16. Side View of the PBGA Package
Table 21 shows the pinout list of the MPC8250VR. Table 20 defines conventions and acronyms used in
Table 21.
MOTOROLA
MPC8250 Hardware Specifications
41
Pinout
Table 21. MPC8250 VR Package Pinout List
Pin Name
Ball
BR
C16
D2
BG
ABB/IRQ2
TS
C1
D1
A0
D5
A1
E8
A2
C4
A3
B4
A4
A4
A5
D7
A6
D8
A7
C6
A8
B5
A9
B6
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
C7
C8
A6
D9
F11
B7
B8
C9
A7
B9
E11
A8
D11
B10
C11
A9
B11
C12
D12
A10
B12
42
MPC8250 Hardware Specifications
MOTOROLA
Pinout
Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name
Ball
A31
TT0
TT1
TT2
TT3
TT4
TBST
TSIZ0
TSIZ1
TSIZ2
TSIZ3
AACK
ARTRY
DBG
DBB/IRQ3
D0
B13
E7
B3
F8
A3
C3
F5
E3
E2
E1
E4
D3
C2
A14
C15
W4
Y1
V1
P4
N3
K5
J4
D1
D2
D3
D4
D5
D6
D7
G1
AB1
U4
U2
N6
N1
L1
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
J5
G3
AA2
W1
T3
T1
MOTOROLA
MPC8250 Hardware Specifications
43
Pinout
Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name
Ball
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
M2
K2
J1
G4
U5
T5
P5
P3
M3
K3
H2
G5
AA1
V2
U1
P2
M4
K4
H3
F2
Y2
U3
T2
N2
M5
K1
H4
F1
W2
T4
R3
N4
M1
J2
H5
44
MPC8250 Hardware Specifications
MOTOROLA
Pinout
Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name
Ball
D55
F3
V3
D56
D57
R5
D58
R2
D59
N5
D60
L2
D61
J3
D62
H1
D63
F4
DP0/RSRV/EXT_BR2
IRQ1/DP1/EXT_BG2
AB3
W5
IRQ2/DP2/TLBISYNC/EXT_DBG2
AC2
AA3
AD1
AC1
AB2
Y3
IRQ3/DP3/CKSTP_OUT/EXT_BR3
IRQ4/DP4/CORE_SRESET/EXT_BG3
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
PSDVAL
D15
Y4
TA
TEA
D16
E15
D14
E14
A17
B14
F13
B17
AC6
AD6
AE6
AB7
AF7
AC7
AD7
AF8
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
MOTOROLA
MPC8250 Hardware Specifications
45
Pinout
Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name
Ball
CS8
AE8
AD8
AC8
AB8
C13
A12
D13
AF4
AA5
AE4
AD4
AF3
AB4
AE3
AF2
AD3
AE2
AD2
AE1
AC3
W6
CS9
CS10/BCTL1
CS11/AP0
BADDR27
BADDR28
ALE
BCTL0
PWE0/PSDDQM0/PBS0
PWE1/PSDDQM1/PBS1
PWE2/PSDDQM2/PBS2
PWE3/PSDDQM3/PBS3
PWE4/PSDDQM4/PBS4
PWE5/PSDDQM5/PBS5
PWE6/PSDDQM6/PBS6
PWE7/PSDDQM7/PBS7
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
AA4
AC9
AD9
AE9
AF9
AB6
AF5
AE5
AD5
AC5
AB5
AF6
AE13
AD15
LWE0/LSDDQM0/LBS0/PCI_CFG0
LWE1/LSDDQM1/LBS1/PCI_CFG1
LWE2/LSDDQM2/LBS2/PCI_CFG2
LWE3/LSDDQM3/LBS3/PCI_CFG3
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LGPL5/LSDAMUX/PCI_MODCK
LWR
L_A14/PAR
L_A15/FRAME/SMI
46
MPC8250 Hardware Specifications
MOTOROLA
Pinout
Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name
Ball
L_A16/TRDY
AF16
AF15
AE15
AE14
AC17
AD14
AF13
AE20
AC14
AC19
AD13
AF21
AF22
AE21
AB14
AD20
AB9
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTA
L_A30/REQ2
L_A31/DLLOUT
LCL_D0/AD0
LCL_D1/AD1
AB10
AC10
AD10
AE10
AF10
AF11
AB12
AB11
AF12
AE11
AC13
AC12
AB13
AD12
AF14
AF17
AE16
AD16
LCL_D2/AD2
LCL_D3/AD3
LCL_D4/AD4
LCL_D5/AD5
LCL_D6/AD6
LCL_D7/AD7
LCL_D8/AD8
LCL_D9/AD9
LCL_D10/AD10
LCL_D11/AD11
LCL_D12/AD12
LCL_D13/AD13
LCL_D14/AD14
LCL_D15/AD15
LCL_D16/AD16
LCL_D17/AD17
LCL_D18/AD18
MOTOROLA
MPC8250 Hardware Specifications
47
Pinout
Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name
Ball
LCL_D19/AD19
LCL_D20/AD20
LCL_D21/AD21
LCL_D22/AD22
LCL_D23/AD23
LCL_D24/AD24
LCL_D25/AD25
LCL_D26/AD26
LCL_D27/AD27
LCL_D28/AD28
LCL_D29/AD29
LCL_D30/AD30
LCL_D31/AD31
LCL_DP0/C0/BE0
LCL_DP1/C1/BE1
LCL_DP2/C2/BE2
LCL_DP3/C3/BE3
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
TRST
AC16
AB16
AF18
AE17
AD17
AB17
AE18
AD18
AC18
AE19
AF20
AD19
AB18
AE12
AA13
AC15
AF19
A11
E5
F22
TCK
A24
TMS
C24
TDI
A25
TDO
B24
TRIS
C19
PORESET
B25
HRESET
D24
SRESET
E23
QREQ
D18
RSTCONF
E24
MODCK1/AP1/TC0/BNKSEL0
MODCK2/AP2/TC1/BNKSEL1
MODCK3/AP3/TC2/BNKSEL2
XFC
B16
F16
A15
A18
CLKIN1
G22
48
MPC8250 Hardware Specifications
MOTOROLA
Pinout
Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name
Ball
1
1
PA0/RESTART1/DREQ3
PA1/REJECT1/DONE3
PA2/CLK20/DACK3
AC20
AC21
1
1
AF25
PA3/CLK19/DACK4/L1RXD1A2
PA4/REJECT2/DONE4
PA5/RESTART2/DREQ4
PA6
AE24
AA21
1
1
AD25
AC24
1
1
1
PA7/SMSYN2
AA22
AA23
PA8/SMRXD2
1
PA9/SMTXD2
Y26
1
1
PA10/MSNUM5
W22
W23
PA11/MSNUM4
1
PA12/MSNUM3
V26
V25
1
PA13/MSNUM2
1
1
1
PA14/FCC1_RXD3
T22
T25
PA15/FCC1_RXD2
PA16/FCC1_RXD1
R24
1
PA17/FCC1_RXD0/FCC1_RXD
PA18/FCC1_TXD0/FCC1_TXD
PA19/FCC1_TXD1
P22
N26
N23
1
1
1
PA20/FCC1_TXD2
K26
1
PA21/FCC1_TXD3
L23
1
PA22
K23
H26
1
PA23
1
PA24/MSNUM1
F25
1
PA25/MSNUM0
D26
D25
C25
C22
1
1
1
PA26/FCC1_MII_RX_ER
PA27/FCC1_MII_RX_DV
PA28/FCC1_MII_TX_EN
PA29/FCC1_MII_TX_ER
PA30/FCC1_MII_CRS/FCC1_RTS
PA31/FCC1_MII_COL
PB4/FCC3_TXD3/L1RSYNCA2/ FCC3_RTS
PB5/FCC3_TXD2/L1TSYNCA2/ L1GNTA2
PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2
1
1
1
B21
A20
A19
1
AD21
AD22
AC22
1
1
MOTOROLA
MPC8250 Hardware Specifications
49
Pinout
Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name
Ball
1
1
1
1
1
PB7/FCC3_TXD0/FCC3_TXD/ L1TXDA2/L1TXD0A2
PB8/FCC3_RXD0/FCC3_RXD/TXD3
PB9/FCC3_RXD1/L1TXD2A2
AE26
AB23
AC26
AB26
AA25
PB10/FCC3_RXD2
PB11/FCC3_RXD3
1
PB12/FCC3_MII_CRS/TXD2
W26
W25
1
PB13/FCC3_MII_COL/L1TXD1A2
PB14/FCC3_MII_TX_EN/RXD3
1
V24
U24
R22
R23
1
1
1
1
PB15/FCC3_MII_TX_ER/RXD2
PB16/FCC3_MII_RX_ER/CLK18
PB17/FCC3_MII_RX_DV/CLK17
PB18/FCC2_RXD3/L1CLKOD2/ L1RXD2A2
PB19FCC2_RXD2/L1RQD2/L1RXD3A2
PB20/FCC2_RXD1/L1RSYNCD2/ L1TXD1A1
PB21/FCC2_RXD0/FCC2_RXD/ L1TSYNCD2/L1GNTD2
PB22/FCC2_TXD0/FCC2_TXD/ L1RXDD2
PB23/FCC2_TXD1/L1TXDD2
M23
1
L24
K24
1
1
L21
1
P25
N25
1
1
PB24/FCC2_TXD2/L1RSYNCC2
PB25/FCC2_TXD3/L1TSYNCC2/ L1GNTC2
PB26/FCC2_MII_CRS/L1RXDC2
PB27/FCC2_MII_COL/L1TXDC2
PB28/FCC2_MII_RX_ER/FCC2_RTS/ L1TSYNCB2/L1GNTB2/TXD1
PB29/L1RSYNCB2/ FCC2_MII_TX_EN
PB30/FCC2_MII_RX_DV/L1RXDB2
PB31/FCC2_MII_TX_ER/L1TXDB2
PC0/DREQ1/BRGO7/SMSYN2/ L1CLKOA2
PC1/DREQ2/BRGO6/L1RQA2
E26
1
H23
C26
1
1
1
1
1
1
B26
A22
A21
E20
C20
AE22
AA19
1
1
1
1
PC2/FCC3_CD/DONE2
AF24
PC3/FCC3_CTS/DACK2/CTS4
AE25
AB22
AC25
AB25
AA24
1
1
1
1
PC4/SI2_L1ST4/FCC2_CD
PC5/SI2_L1ST3/FCC2_CTS
PC6/FCC1_CD
PC7/FCC1_CTS
1
PC8/CD4/RENA4/SI2_L1ST2/CTS3
PC9/CTS4/CLSN4/SI2_L1ST1/ L1TSYNCA2/L1GNTA2
Y24
1
U22
50
MPC8250 Hardware Specifications
MOTOROLA
Pinout
Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name
Ball
1
PC10/CD3/RENA3
V23
U23
1
PC11/CTS3/CLSN3/L1TXD3A2
PC12/CD2/RENA2
1
1
T26
PC13/CTS2/CLSN2
R26
1
PC14/CD1/RENA1
P26
P24
1
1
PC15/CTS1/CLSN1/SMTXD2
PC16/CLK16/TIN4
M26
1
PC17/CLK15/TIN3/BRGO8
PC18/CLK14/TGATE2
PC19/CLK13/BRGO7/SPICLK
PC20/CLK12/TGATE1
PC21/CLK11/BRGO6
PC22/CLK10/DONE1
PC23/CLK9/BRGO5/DACK1
PC24/CLK8/TOUT4
L26
1
1
M24
1
L22
K25
1
J25
1
G26
1
F26
1
G24
1
PC25/CLK7/BRGO4
E25
G23
1
PC26/CLK6/TOUT3/TMCLK
PC27/FCC3_TXD/FCC3_TXD0/CLK5/ BRGO3
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
PC30/CLK2/TOUT1
1
1
1
1
B23
E22
E21
D21
1
PC31/CLK1/BRGO1
B20
1
PD4/BRGO8/FCC3_RTS/SMRXD2
PD5/DONE1
AF23
1
AE23
AB21
1
1
PD6/DACK1
PD7/SMSYN1/FCC1_TXCLAV2
PD8/SMRXD1/BRGO5
PD9/SMTXD1/BRGO3
PD10/L1CLKOB2/BRGO4
PD11/L1RQB2
AD23
AD26
1
1
Y22
1
AB24
1
Y23
1
PD12
AA26
1
PD13
W24
1
PD14/L1CLKOC2/I2CSCL
PD15/L1RQC2/I2CSDA
PD16/SPIMISO
V22
U26
1
1
T23
MOTOROLA
MPC8250 Hardware Specifications
51
Pinout
Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name
Ball
1
PD17/BRGO2/SPIMOSI
PD18/SPICLK
R25
1
P23
N22
1
1
PD19/SPISEL/BRGO1
PD20/RTS4/TENA4/L1RSYNCA2
PD21/TXD4/L1RXD0A2/L1RXDA2
PD22/RXD4L1TXD0A2/L1TXDA2
PD23/RTS3/TENA3
PD24/TXD3
M25
1
L25
1
J26
1
1
K22
G25
1
PD25/RXD3
H24
1
PD26/RTS2/TENA2
PD27/TXD2
F24
H22
1
1
PD28/RXD2
B22
1
PD29/RTS1/TENA1
PD30/TXD1
D22
C21
1
1
PD31/RXD1
E19
VCCSYN
D19
K6
VCCSYN1
GNDSYN
B18
K21
C14
AD24
B15
E17
C23
CLKIN2
2
SPARE4
3
PCI_MODE
2
SPARE6
4
THERMAL0
4
THERMAL1
I/O power
E6, F6, H6, L5, L6, P6,T6, U6,V5,
Y5, AA6, AA8, AA10, AA11,
AA14, AA16, AA17, AB19, AB20,
W21, U21, T21, P21, N21, M22,
J22, H21, F21, F19, F17, E16,
F14, E13, E12, F10, E10, E9
52
MPC8250 Hardware Specifications
MOTOROLA
Package Description
Ball
Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name
Core Power
Ground
L3, V4, W3, AC11, AD11, AB15,
U25, T24, J24, H25, F23, B19,
D17, C17, D10, C10
A2, B1, B2, A5, C5, C18, D4, D6,
G2, L4, P1, R1, R4, AC4, AE7,
AC23, Y25, N24, J23, A23, D23,
D20, E18, A13, A16, K10, K11,
K12, K13, K14, K15, K16, K17,
L10, L11, L12, L13, L14, L15, L16,
L17, M10, M11, M12, M13, M14,
M15, M16, M17, N10, N11, N12,
N13, N14, N15, N16, N17, P10,
P11, P12, P13, P14, P15, P16,
P17, R10, R11,R12, R13, R14,
R15, R16, R17, T10, T11, T12,
T13, T14, T15, T16, T17, U10,
U11, U12, U13, U14, U15, U16,
U17
1
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
Must be pulled down or left floating.
If PCI is not desired, must be pulled up or left floating.
For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D).
2
3
4
1.5 Package Description
The following sections provide the package parameters and mechanical dimensions.
1.5.1 Package Parameters
Package parameters are provided in Table 22.
Table 22. Package Parameters
Outline
(mm)
Pitch
(mm)
Nominal Unmounted
Height (mm)
Package
Devices
Type
Interconnects
ZU
VR
MPC8250
MPC8250VR
37.5 x 37.5
27 x 27
TBGA
PBGA
480
516
1.27
1
1.55
2.25
MOTOROLA
MPC8250 Hardware Specifications
53
Package Description
1.5.2 Mechanical Dimensions
1.5.2.1 ZU Package Dimensions
Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package.
Notes:
1. Dimensions and Tolerancing per
ASME Y14.5M-1994.
2. Dimensions in millimeters.
3. Dimension b is measured at the
maximum solder ball diameter,
parallel to primary data A.
4. Primary data A and the seating
plane are defined by the spherical
crowns of the solder balls.
Millimeters
Dim
Min
Max
A
A1
A2
A3
b
1.45
0.60
0.85
0.25
0.65
1.65
0.70
0.95
—
0.85
D
37.50 BSC
D1
e
35.56 REF
1.27 BSC
37.50 BSC
35.56 REF
E
E1
Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature—480 TBGA
54
MPC8250 Hardware Specifications
MOTOROLA
Package Description
1.5.2.2 VR Package Dimensions
Figure 18 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA package.
Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA
MOTOROLA
MPC8250 Hardware Specifications
55
Ordering Information
1.6 Ordering Information
Figure 19 provides an example of the Motorola part numbering nomenclature for the MPC8250. In addition
to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any
enhancement(s) in the part from the original production design. Each part number also contains a revision
code that refers to the die mask revision number and is specified in the part numbering scheme for
identification purposes only. For more information, contact your local Motorola sales office.
MPC 8250 A C ZU XXX X
Product Code
Die Revision Level
Device Number
Processor Frequency
(CPU/CPM/Bus)
Process Technology
(A = 0.25 micron)
Package
ZU = 480 TBGA
VR = 516 PBGA
Temperature Range
(Blank = 0 to 105 ˚C
C = -40 to 105 ˚C)
Figure 19. Motorola Part Number Key
Table 23. Document Revision History
Substantive Changes
Revision
Date
0
11/2001 Initial version
0.1
2/2002 • Note 2 for Table 4 (changes in italics): “...greater than or equal to 266 MHz, 200 MHz CPM...”
• Table 18: core and bus frequency values for the following ranges of MODCK_HMODCK:
0011_000 to 0011_100 and 1011_000 to 1011_1000
• Table 19: footnotes added to pins at AE11, AF25, U5, and V4.
0.2
3/2202 • Table 19: modified notes to pins AE11 and AF25.
• Table 19: added note to pins AA1 and AG4 (Therm0 and Therm1).
0.3
0.4
3/2002 • Table 19: modified note to pin AF25.
5/2002 • Table 2: Notes 2 and 3
• Addition of note on page 8:VDDH and VDD tracking
• Table 14: Note 3
• Table 16: Note 1
• Table 18: Note 3
0.5
0.6
0.7
0.8
9/2002 Addition of VR (516 PBGA) package information. Refer to sections 1.2.2, 1.4.2, and 1.5.
10/2002 Table 21, “VR Pinout”: corrected ball assignment for the following pins—A12–A17, TA, PD5, PC2.
10/2002 Table 21, “VR Pinout”: Addition of L3 to the Core (VDDx) pin list (page 53)
11/2002 Table 21, “VR Pinout”: Addition of C18 to the Ground (GND) pin list (page 53)
56
MPC8250 Hardware Specifications
MOTOROLA
Ordering Information
Table 23. Document Revision History (Continued)
Substantive Changes
Revision
Date
0.9
8/2003 • Table 2: Modification to supply voltage ranges reflected in notes 2, 3, and 4
• Addition of VCCSYN to “Note: Core, PLL, and I/O Supply Voltages” following Table 2
• Addition of Figure 2
• Addition of note 1 to Table 3
• Table 4: Changes to θ . Addition of θ and θ
JA
JB
JC
• Table 7, Figure 8: Addition of sp42a/sp43a
• Figure 3 through Figure 8: Addition of notes or modifications
• Table 9: Change to sp10
• Table 14, Table 16, and Table 18: Removal of PLL bypass mode from clock tables
• Table 19 and Table 21: Addition of note 1
• Addition of SPICLK to PC19 in Table 19 and Table 21. It is documented correctly in the
MPC8260 PowerQUICC II™ Family Reference Manual but had previously been omitted from
Table 19 and Table 21.
MOTOROLA
MPC8250 Hardware Specifications
57
Ordering Information
THIS PAGE INTENTIONALLY LEFT BLANK
58
MPC8250 Hardware Specifications
MOTOROLA
Ordering Information
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA
MPC8250 Hardware Specifications
59
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217
1-303-675-2140 or 1-800-441-2447
JAPAN:
Motorola Japan Ltd.; SPS, Technical Information Center,
3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan
81-3-3440-3569
ASIA/PACIFIC:
Information in this document is provided solely to enable system and software
implementers to use Motorola products.There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits or
integrated circuits based on the information in this document.
Motorola Semiconductors H.K. Ltd.; Silicon Harbour
Centre, 2 Dai King Street, Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong
852-26668334
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters which may be provided in Motorola data sheets
and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts.
Motorola does not convey any license under its patent rights nor the rights of
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against all claims, costs, damages, and expenses, and reasonable attorney fees
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was negligent regarding the design or manufacture of the part.
TECHNICAL INFORMATION CENTER:
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HOME PAGE:
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Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark
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© Motorola, Inc. 2003
MPC8250EC/D
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Semiconductors
Motorola > Semiconductors > Products > Network and Communication Processors > PowerQUICC, PowerQUICC II, and PowerQUICC III Communications Processors
> MPC8250
MPC8250 : PowerQUICC II™ Integrated Communications Processor
Page Contents:
The PowerQUICC II™ integrated communications processor family delivers excellent integration of
processing power for networking and communications peripherals, providing customers with an innovative,
total system solution for building high-end communications systems. Motorola's PowerQUICC II processor
family is the next generation of Motorola's leading PowerQUICC™ line of integrated communications
processors, providing higher performance in all areas of device operation, including greater flexibility,
extended capabilities, and higher integration.
Features
Parametrics
Documentation
Tools
Applications
Motorola's leading PowerQUICC architecture integrates two processing blocks. One block is a high-
performance embedded G2 core and the second block is the Communications Processor Module (CPM).
The CPM of the MPC8250 processor can support up to three fast serial communications controllers
(FCCs), one multichannel controller (MCC), four serial communications controllers (SCCs), two serial
management controllers (SMCs), one serial peripheral interface (SPI) and one I2C interface. The
combination of the G2 core and the CPM, along with the versatility and performance of the PowerQUICC II
processor family, provides customers with enormous potential in developing networking and
communications products while significantly reducing time-to-market development stages.
Orderable Parts
Related Products
Related Links
Other Info:
FAQs
Literature Services
3rd Party Design Help
Training
Block Diagram
3rd Party Tool
Vendors
MPC8250 Features
Product Highlights
3rd Party Trainers
Rate this Page
●
●
●
●
●
●
●
●
200-300 MHz high-speed embedded G2 core
Powerful memory controller and system functions
Enhanced 32-bit RISC communications processor module
Up to three multiport 10/100 Mbps ethernet MAC
Up to 128 HDLC channels (each channel 64 Kbps, full duplex)
Up to four 10 Mbps ethernet MAC
--
-
0
+
++
Submit
Care to Comment?
Integrated PCI interface
Strong 3rd-party tools support from Motorola's Smart Networks alliance members
Typical Applications
●
●
●
●
●
●
●
Remote Access Concentrators
Regional Office Routers
Cellular Infrastructure equipment
Telecom Switching Equipment
Ethernet Switches
T1/E1-to-T3/E3 Bridges
xDSL Systems
Technical Specifications
Embedded G2 core at 200-300 MHz
●
❍
❍
❍
570 MIPS at 300 MHz (Dhrystone 2.1)
High-performance, superscalar microprocessor
Disable CPU mode
❍
❍
❍
❍
❍
❍
Supports the Motorola external L2 cache chip (MPC2605)
Improved low-power core
16 Kbyte data and 16 Kbyte instruction cache
Memory Management Unit
Floating Point Unit
Common On-chip Processor (COP)
●
System Interface Unit (SIU)
❍
❍
❍
❍
Memory controller, including two dedicated SDRAM machines
PCI up to 66 MHz
Hardware bus monitor and software watchdog timer
IEEE 1149.1 JTAG test access port
●
High-Performance CPM with operating frequency of 133 MHz
❍
❍
❍
❍
❍
Parallel I/0 registers
On-board 32 Kbytes of dual-port RAM
One multichannel controller (MCC), each supporting 128 full-duplex, 64 Kbps, HDLC lines
Virtual DMA functionality
Three FCCs supporting 10/100 Mbps Ethernet (up to three) (IEEE 802.3X with Flow
Control)
❍
❍
Three MII interfaces
Four TDM interfaces (T1/E1) supporting four T1 lines or one T3 line
●
Two bus architectures: one 64-bit 60x bus and one 32-bit PCI or local bus
Integrated PCI interface
❍
●
●
●
●
1.8V or 2.0V internal and 3.3V I/O
300 MHz power consumption: ~3 W
Package: 480 TBGA package (37.5 x 37.5 mm)
Integrated PCI capability
MPC8250ZQ/VR Features
●
●
●
●
●
●
●
●
603e core with 16K inst and 16K data caches
64-bit 60x bus, 32-bit PCI bus
Three FCCs for 10/100 Ethernet
128 HDLC channels, 4 TDMs
4 SCCs, 2 SMCs, SPI, I2C
80KB ROM, 32KB RAM
Memory controller built from SDRAM, UPM, GPCM machines
Performance
❍
❍
❍
❍
200 MHz CPU, 166 MHz CPM, 66 MHz bus
~ 1.5W @ full performance, 2.0V
Extended Temp Available ( -40°C to 105°C)
Technology
■
HIP4 .25 micron, 3.3V I/O, 2.0V Core
516 PBGA, 27x27mm, 1mm ball pitch
■
■
ZQ package has lead-bearing spheres
VR package is lead-free
■
MPC8260 Derivatives
8250
8255
8260
8264
8265
8266
Serial Communications
Controllers (SCCs)
4
4
4
4
4
4
Fast Communication
Controllers (FCCs)
3
2
3
3
3
3
I-Cache (Kbyte)
16
16
16
16
16
16
D-Cache (Kbyte)
Ethernet (10T)
16
16
16
16
16
16
Up to 4
Up to 3
0
Up to 4
Up to 2
2
Up to 4
Up to 3
2
Up to 4
Up to 3
2
Up to 4
Up to 3
2
Up to 4
Up to 3
2
Ethernet (10/100)
UTOPIA II Ports
Multi-Channel HDLC
PCI Interface
Up to 128 Up to 128 Up to 256 Up to 256 Up to 256 Up to 256
Yes -- -- -- Yes Yes
IMA Functionality
PowerQUICC II Masks and Versions
Process Family Revision Qualification Mask
--
--
--
Yes
--
Yes
IMMR[16-
31]1
Rev_Num2
PVR
A.1
B.3
XC
XC
0K26N 0x00810101 0x0011
3K23A 0x00810101 0x0023
0x0001
0x003B
0.29 µm
(HiP3)
6K23A,
C.2
XC
0x00810101 0x0024
7K23A
0x007B
MPC8260
A.0
B.1
C.0
0.0
0.1
XC
MC
MC
—
2K25A 0x80811014 0x0060
4K25A 0x80811014 0x0062
5K25A 0x80811014 0x0064
0K49M 0x80822011 0x0A00
1K49M 0x80822013 0x0A01
0x000D
0x002D
0x002D
0x0070
0x0070
0.25 µm
(HiP4)
MPC8280
0.13 µm
(HiP7)
MC
0x0C00
0K50M 0x80822013
0x0D00
MPC8272 0.0
PC
TBD
Notes:
1. The IMMR[16-31] indicates the mask number.
2. The Rev_Num located at offset 0x8AF0 in DPRAM indicates the CPM microcode revision
number.
Masks and versions table last updated on 08JAN2004.
Return to Top
MPC8250 Parametrics
Ambient
CPM
Operation
Frequency
(Max)
Core
Operating
Voltage
(Spec)
(V)
Operating
Frequency
(Max)
Power
Dissipation
(Typ)
Power
Dissipation
(Max)
I/O Operating
CPU Performance
(Max)
Operating
Temperature
(Min)
Voltage
(Max)
(V)
(MIPS)
(MHz)
(W)
(W)
(MHz)
(oC)
1.5,
2,
1.9,
2.8,
2.9,
3.1,
3.2
380,
505.4,
570
200,
266,
300
133,
166,
200
2.2,
2.3,
2.4,
2.5,
3
1.8,
2
-40,
0
3.3
Junction Operating
Temperature
(Max)
L1 Cache
Instructional
(Max)
L1 Cache
Data
(Max)
Integrated
Memory
Controller
Internal Dual-
Port RAM
(KByte)
DMA Controller
GPIO
Pins
Bus Interface
Channels
(oC)
(KByte)
(KByte)
EDO,
EPROM,
FLASH,
SDRAM,
SRAM
60x,
Local,
PCI 2.2
105
16
16
32
28
120
External
Bus
Speed
(Max)
(MHz)
Serial
Interface
Timers
Communication
Protocol
Other Peripherals
Networking Application Function
Package Description
Type
Channels
ASYNC HDLC,
AppleTalk,
BISYNC,
Ethernet,
Fast Ethernet,
GCI,
I2C,
MII,
SPI,
TDM,
UART
PBGA 516 27*27*1.25P1.0,
TBGA 480 37*37*1.7P1.27
66
4
DMA Controller
Integrated Control/Data Plane
HDLC,
SS7,
Transparent,
UART
View expanded set of parameters
Return to Top
MPC8250 Documentation
Documentation
Application Note
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
AN2059
AN2271/D
AN2290
AN2291
AN2335/D
AN2347/D
AN2349/D
AN2431
AN2431SW/D
AN2491
AN2547
AN2547SW
AN2585
AN2586
AN2587
AN2638
Hints for Debugging the CPM
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
zip
pdf
pdf
zip
pdf
pdf
pdf
pdf
25
0
7/25/1997
MOTOROLA
MOTOROLA
MPC8260 PowerQUICC II Thermal Resistor Guide
MPC8260 PowerQUICC II Design Checklist
56 0.0 3/19/2002
249
1.1 1/27/2004
Differences among PowerQUICC II Devices and Revisions MOTOROLA
187
1.4 9/30/2003
MPC8260 Dual-Bus Architecture and Performance
Considerations
MOTOROLA
10/15/2002
61
0
0
0
0
0
0
0
0
Using an MPC8260 and an MPC7410 with Shared Memory MOTOROLA
461
10/01/2002
10/01/2002
12/20/2002
12/20/2002
MOTOROLA
MPC8260 Reset and Configuration Word
90
MOTOROLA
180
PowerQUICC II PCI Example Software
MOTOROLA
726
524
PowerQUICC II PCI Example Software
MOTOROLA
Simplified Mnemonics for PowerPC Instructions
9/30/2003
6/30/2003
6/30/2003
MOTOROLA
Detecting a CPM Overload on the PowerQUICC II
80
Software Detecting CPM Overload (accompanies AN2547) MOTOROLA
288
-
MPC82xx PowerQUICC II Reset: Sources, Effects, and
Comments
MOTOROLA
MOTOROLA
84 0.1 2/26/2004
333
MPC8260 PowerQUICC II Family Power Distribution
Trends
0
1/13/2004
Software Migration from the NPe495H/L to PowerQUICC II MOTOROLA
439
299
0.1 1/28/2004
MOTOROLA
12/12/2003
0
Effects of Clock Jitter on the MPC8260 (HiP3 and HiP4)
Data Sheets
ID
Date Last
Modified
Name
Vendor ID Format Size K Rev #
MOTOROLA pdf 925 0.9
Order Availability
MPC8250EC
MPC8250 Hardware Specifications
8/15/2003
Errata - Click here for important errata information
Size Rev
Date Last
Modified
Order
Availability
ID
Name
Vendor ID Format
pdf
K
#
MPC8260CE
MPC8260 PowerQUICC II Family Device Errata MOTOROLA
470 4.4
4/29/2004
Fact Sheets
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
MPC8260FACT
MPC8260 PowerQUICC II Integrated Comm Proc Fam
MPC8260 PowerQUICC II Microcode
142
7
6/05/2003
MOTOROLA
pdf
MPC8260MFACT
51
1
3/27/2002
Packaging Information
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
PowerQUICC II MPC8250A Pb-Free Packaging
Presentation
MOTOROLA
pdf
7/11/2003
-
MPC8250PBFREEPKG
PBGAPRES
329
1923
1
MOTOROLA
pdf
8/05/2003
-
PBGA Packaging Customer Tutorial
TBGA Packaging Customer Tutorial
1
0
MOTOROLA
pdf
1784
8/05/2003
-
TBGAPRESPKG
Product Brief
Size
K
Date Last
Modified
Order
Availability
ID
Name
Vendor ID Format
Rev #
MPC8250TS
MPC8250 PowerQUICC II Technical Summary MOTOROLA
pdf
85
0.1
11/12/2001
Product Change Notices
Size Rev Date Last
Order
Availability
ID
Name
Vendor ID Format
K
11
38
12
9
#
Modified
1/30/2003
3/28/2003
8/06/2003
10/29/2003
PCN8499
PCN8663
PCN9081
PCN9322
POWERQUICC (.25UM) HIP4 SPEC CHANGES MOTOROLA htm
0
-
-
-
-
NEW TRAY FOR 37.5 X 37.5 TBGA PACKAGE
37.5 X 37.5 MM TBGA TRAY
MOTOROLA htm
MOTOROLA htm
MOTOROLA htm
0
0
0
PQII HIP4 TRANSITION PCI DEVICE
Product Numbering Scheme
Size
K
Date Last
Modified
Order
Availability
ID
Name
Vendor ID Format
Rev #
82XXPNS
MPC82xx HiP3/HiP4 Part Numbering Scheme MOTOROLA
jpg
134
2
9/30/2003
-
Reference Manual
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
G2CORERM
G2 Core Reference Manual
5948
1
6/27/2003
The Bus Interface for 32-Bit Microprocessors that MOTOROLA
Implement the PowerPC Architecture
MPC60XBUSRM
MPC8260ESS7UMAD/D
MPC8260UM
pdf
pdf
pdf
pdf
pdf
2527 0.1 1/14/2004
MOTOROLA
12/05/2002
238 0.1
Enhanced SS7 Microcode Specification
MPC8260 PowerQUICC II Family Reference
Manual
MOTOROLA
MOTOROLA
MOTOROLA
14509
1
5/29/2003
MPC8260UMAD
MPCFPE32B/AD
MPC8260 PowerQUICC II Users Manual Errata
115 1.2 4/30/2004
12/21/2001
Programming Environments Manual for 32-Bit
Implementations of the PowerPC Architecture
6909
2
Errata to MPCFPE32B, Programming
Environments Manual for 32-Bit Implementations of
the Power PC Architecture, Rev. 2
MOTOROLA
10/11/2002
MPCFPE32BAD/AD
pdf
40
0
Selector Guide
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
Network and Communications Processors Selector Guide - MOTOROLA
Quarter 2, 2004
178
4/01/2004
SG1007
pdf
0
White Paper
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
Timing Considerations when Interfacing the
PowerQUICC II to SDRAM
MOTOROLA
pdf
103
3/09/2004
MPC826XSDRAMWP
0.1
Return to Top
MPC8250 Tools
Hardware Tools
Analyzers
Logic
ID
Name
Vendor ID
Format Size K Rev #
Order Availability
TLA715/TLA721
TEKTRONIX
TLA700 Logic Analyzers
-
-
-
-
Board Testers
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
SCANPLUS
CORELIS
ScanPlus
-
-
-
-
µMaster 4031
Functional Test and Debug Solutions for boards carrying Motorola™ and
IBM® PowerPC™ processors with COP debug port (740, 750, 750DD2,
750DD3, 755, 603e, 8240, 8250A, 8255A, 8260A, 8264A, 8265A,
8266A, 7400, 7410, etc.)
4000-994020-001
INTLTEST
-
-
-
-
Emulators/Probes/Wigglers
Size Rev
Order
Availability
ID
Name
Vendor ID
Format
K
#
CWCODETEST*
METROWERKS
CodeTEST
-
-
-
-
BDI1000/BDI2000
Abatron develops and produces high-quality, high-speed BDM and
JTAG Debug Tools (BDI Family) for software development
environments from leading vendors.
BDI1000/BDI2000
ABATRON
-
-
-
-
10200A
PROBE
CORELIS
NetICE-R option 2/2M
-
-
-
-
-
-
-
-
GREENHILLS
Green Hills Probe & Slingshot
µMaster 4031
Functional Test and Debug Solutions for boards carrying
Motorola™ and IBM® PowerPC™ processors with COP debug
port (740, 750, 750DD2, 750DD3, 755, 603e, 8240, 8250A, 8255A,
8260A, 8264A, 8265A, 8266A, 7400, 7410, etc.)
4000-994020--
001
INTLTEST
-
-
-
-
IC30001
ISYS
iC3000 ActiveEmulator
iC4000 ActiveEmulator
visionICE II
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IC40000
ISYS
VISIONICE
VISIONPROBE
WPICE
WINDRIV
WINDRIV
WINDRIV
visionPROBE II
WIND®POWER ICE
Evaluation/Development Boards and Systems
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
MOTOROLA
-
MPC8260ADS_ECOM
MPC8260ADS_TCOM
MPC8266ADS_PCIAI
PQ2FADS_VR
MPC8260ADS Daughter Card for Telephony Applications (E1)
MPC8260ADS Daughter Card for Telephony Applications (T1)
MPC8266 Application Development System (Add-In Card)
MPC82xx Family Application Development System
MPC82xx Family Application Development System
-
-
MOTOROLA
-
-
-
-
-
-
-
-
-
MOTOROLA
-
MOTOROLA
-
MOTOROLA
-
PQ2FADS_ZU
RATTLER-PCI
RATTLER1
TAIPAN
ANAMIC
ANAMIC
ANAMIC
WINDRIV
Rattler-PCI
Rattler1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Taipan
SBCPQII
SBCPowerQUICCII
Models
BSDL
ID
Name
Vendor ID
Format Size K Rev # Order Availability
PowerQUICC II BSDL (HiP4)
(03/15/2004)
MPC8260BSDL4
MOTOROLA
zip
zip
10
9
1.1
1.1
-
-
MPC82XX 516-pin BSDL Model
(10/22/2003)
MPC82XX516BSDL
MOTOROLA
Full Functional Models
ID
Name
Vendor ID Format Size K Rev #
Order Availability
EP100
EUREKA
EUREKA
EUREKA
EUREKA
EUREKA
PowerPC Bus Slave
PowerPC Bus Master
PowerPC Bus Arbiter
PowerPC-PCI Bridge
PowerPC System Controller
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EP201
EP300
EP433
ES100
IBIS
ID
Size Rev
Order
Availability
Name
Vendor ID Format
K
#
PowerQUICC II Family IBIS Models
This package contains the IBIS models for the PowerQUICC II
family of communications processors. HiP3 and HiP4
processes. Local and PCI bus configurations. 480 TBGA and
516 PBGA packages. (10/30/2003)
MOTOROLA
zip
MPC82XXIBIS
81 2.7
-
Timing Models
ID
Name
Vendor ID
Format Size K Rev #
exe 176
Order Availability
GPCM Timing Generator
(05/29/2003)
PQIIGPCMTIME
MOTOROLA
1
-
Software
Application Software
Calculators
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
Power Consumption Calculator for all PowerQUICC II
Processors
MOTOROLA
zip
491
MPC8260CALC1
2.1
-
-
(04/28/2004)
CPM Performance Calculator for all PowerQUICC II and
PowerQUICC III Processors
MOTOROLA
zip
404 3.1.2
MPC8260CALC2
(12/11/2003)
Code Examples
ID
Size Rev
Order
Availability
Name
Vendor ID Format
K
#
Fast Ethernet on the FCC of the PowerQUICC II
(10/13/2003)
MOTOROLA
zip
140
MPC8260COD08
MPC8260COD09
2
-
-
Multichannel Communication Controller of the PowerQUICC II MOTOROLA
(09/04/2002)
176
614
zip
zip
0
0
Example Software for the PowerQUICC II Family: FEC Frames
Using PHYless MII
MOTOROLA
MPC8260COD11
-
(08/02/2002)
Microcode
ID
Size Rev
Order
Availability
Name
Vendor ID Format
K
#
RAM Microcode Patches for PowerQUICC II Family Device
Errata
MOTOROLA
zip
MPC8260MC05
0
4.1
-
(04/27/2004)
Board Support Packages
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
ARC-MOT-
MQXBSP
MQX Board Support Packages
BSPs for Motorola ColdFire, PowerPC, and 68K embedded processors
ARC
-
-
-
-
EP BSP
Embedded Planet Board Support Packages provide complete software
drivers for MPC 8xx and 82xx processors for Linux, VxWorks and
INTEGRITY. Embedded Planet can also develop customer specific
software for many operating systems.
EP BSP
EMDPLAN
-
-
-
-
Device Drivers
ID
Size Rev
Order
Availability
Name
Vendor ID Format
K
#
PowerQUICC II PCI Driver
For use with the MPC8266 Application Development System and
Metrowerks CodeWarrior
MOTOROLA
zip
3492
MPC8266DRV01
PCS
0
-
-
PlanetCore
PlanetCore provides a complete set of firmware device drivers for 8xx
and 82xx Motorola processors. These drivers include an application /
RTOS boot loader, flash burner and diagnostics. customer specific
drivers can also be developed.
EMDPLAN
-
-
-
Libraries
ID
Size Rev
Order
Availability
Name
Vendor ID Format
K
#
KwikPeg GUI
KADAK's KwikPeg Graphical User Interface (GUI) is derived from PEG,
a professional, high-quality graphic system created by Swell Software,
Inc. to enable you, the embedded system developer, to easily add
graphics to your products.
PN311-1
KADAK
-
-
-
-
Operating Systems
ID
Size Rev
Order
Availability
Name
Vendor ID Format
K
#
Arabella Linux for Motorola 82xx Processors
Arabella Linux for Motorola 82xx processors is a full, commercial
ARA-MOT-82XX
ARABELLA
Linux distribution for the 82xx family of processors. It includes
support for many of the on chip peripherals including Security, ATM,
PCI, USB, PCMCIA, I2C and others.
-
-
-
-
MFS
ARC-MOT-MFS
ARC-MOT-MQX
ARC
ARC
ARC
MS-DOS File System is a portable, compatible implementation of
the Microsoft MS-DOS file system
-
-
-
-
-
-
-
-
-
-
-
-
MQX Real Time Operating System
A robust, high performance, royalty-free kernel designed for deeply
embedded applications requiring a small footprint and fast response
ARC-OS Changer
Provides developers the freedom to migrate from either pSOSystem
or VxWorks to MQX RTOS while reusing an existing code base
ARC-MOT-
OSCHANGER
CMX-RTX
CMX
CMX-RTX
-
-
-
-
-
-
-
-
DPP.82XXX.KRN
ENEA
OSE Real-Time Operating System
ThreadX
RTOS. Royalty-free real-time operating system (RTOS) for
embedded applications. ThreadX is small, fast, and royalty-free
making it ideal for high-volume electronic products.
THREADX
PX382-1
EXPRESSLOG
KADAK
-
-
-
-
AMX PPC32
AMX is a full featured RTOS for the PowerPC family. AMX has been
tested on the EST SBC8260, Embedded Planet RPX Lite MPC823
and Motorola Ultra 603, MBX860, MPC860 ADS and MPC860
FADS.
-
-
-
-
VxWorks
VxWorks, the run-time component of TORNADOII for VxWorks, is
the most widely adopted real-time operating system (RTOS) in the
embedded industry, with a reputation for performance, flexibility,
compatibility and scalability.
VXWORKS 5.X
WINDRIV
-
-
-
-
Protocol Stacks
ID
Size Rev
Order
Availability
Name
Vendor ID Format
K
#
HTTP PRO
ARC-MOT-HTTPPRO
ARC-MOT-IPSHIELD
ARC-MOT-
ARC
ARC
HTTP Pro includes all of the features and benefits of HTTP plus
more
-
-
-
-
-
-
IPShield
Security product support for IPSec, IKE, SSl and SSH. Also
supports hardware accelerated encryption on processors with
Integrated Security Engine.
-
-
Network Protocols
Compact, high performance, portable embedded TCP/IP
NETWORKPROTOCOLS networking stack and a wide variety of optional networking
protocols that are tightly integrated with the MQX (tm) RTOS
ARC
ARC
-
-
-
-
-
-
-
-
POP3
ARC-MOT-POP3
ARC-MOT-RTCS
ARC-MOT-SMTP
RSTP
Enables client embedded devices to receive e-mail from any
POP3 server
RTCS
A real-time, high performance TCP/IP stack designed
specifically for embedded networking applications such as IP
phones, bridges, routers, pagers, PDAs, cellular phones, and set-
top boxes
ARC
ARC
-
-
-
-
-
-
-
-
-
-
-
-
SMTP
Consists of source code development tools and an SNMP
v1/v2/v3 Agent
AvniRSTP
Avnisoft's AvniRSTP is a completely portable ANSI C compliant
implementation of the IEEE 802.1w RSTP Algorithm and
Protocol. It includes the AvniPORT platform abstraction layer to
simplify integration with target platforms.
AVNISOFT
TCP/IP Stack
TargetTCP, is a fast, reliable, re-entrant, full-featured TCP/IP
protocol stack designed specifically for high-performance
embedded networking. The code has a small footprint and is
well suited to memory constrained environments.
TARGETTCP
CMX TCP/IP
BLUNK
CMX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CMX TCP/IP
KwikNet
The KwikNet TCP/IP Stack enables you to add networking
features to your products with a minimum of time and expense.
KwikNet is a compact, high performance stack built with
KADAK's characteristic simplicity, flexibility and reliability.
PN713-1
KADAK
LINK
INFOLINK-STACKNAME
PSQ40XXXX
INFOLink Protocol Software Family
RTXC Quadnet Networking Protocols
Full protocol suite: TCP, UDP, SLIP, ICMP, ARP, RARP,
BOOTP, DNS, IGMP v2, RIP v2 and NAT with Berkeley Sockets
API. Plus DHCP, HTTP, Mail, TFTP, FTP, Telnet, SNTP, SNMP,
PPP and more
QUADROS
Software Tools
Code Translation
ID
Name
Vendor ID
MICROAPL
MICROAPL
Format Size K Rev #
Order Availability
PA68K-PPC
PA86-PPC
PortAsm/68K for PowerPC
PortAsm/86 for PowerPC
-
-
-
-
-
-
-
-
Compilers
ID
Size Rev
Order
Availability
Name
Vendor ID
Format
K
#
CWEPPC
METROWERKS
CodeWarrior Development Studio for PowerPC ISA
-
-
-
CodeWarrior Development Studio. Linux Application Edition for
PowerPC
CWLINPPC
GNUTOOL
METROWERKS
ANAMIC
-
-
-
-
-
-
Gnu Tool set
-
-
ARC-MOT-
COMPILER
MetaWare C/C++ Compiler Tool Suite
Optimized compiler for Motorola processors
ARC
-
-
-
MULTI
COMPILER
GREENHILLS
WINDRIV
MULTI Compiler For PowerPC
Diab C/C++ Compiler
-
-
-
-
-
-
-
-
DIAB
Debuggers
ID
Size Rev
Order
Availability
Name
Vendor ID Format
K
#
ARC-MOT-
DEBUGGER
MetaWare SeeCode Debugger
C/C++ Debugger
ARC
-
-
-
-
-
-
POWERPC
DEBUGGER
GREENHILLS
MULTI Debugger
-
-
-
-
TRACE32-ICD
TRACE32-ICD for PowerQUICC II is a high performance JTAG
LA-7729
LAUBACH
debugger for C ,C++ and JAVA. A USB 2.x, LPT or ethernet interface
is available for connection to any PC or workstation. A flash
programming utility is included.
-
-
IDE (Integrated Development Environment)
ID
Name
Vendor ID
GREENHILLS
ISYS
Format
Size K Rev #
Order Availability
MULTI
IC-SW-OPR
WPIDE
MULTI
-
-
-
-
-
-
-
-
-
-
-
-
winIDEA
WINDRIV
WIND®POWER IDE
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Applications
Networking and Communications
SOHO
Regional Office Router
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Orderable Parts Information
Budgetary
Price
QTY 1000+
($US)
Application/
Qualification
Tier
Tape
and
Reel
Pb-Free
Terminations
Package
Description
Part Number
Status
Info
Order
PBGA 516
27*27*1.25P1.0
more
more
more
more
more
KMPC8250ACVRIHBC
KMPC8250ACZQIHBC
KMPC8250ACZUMHBC
KMPC8250AVRIHBC
KMPC8250AZUPIBC
No
No
No
No
No
Yes
No
No
No
No
Available
Available
Available
Available
Available
-
-
-
-
-
PBGA 516
27*27*1.25P1.0
TBGA 480
37*37*1.7P1.27
PBGA 516
27*27*1.25P1.0
TBGA 480
37*37*1.7P1.27
Not
PBGA 516
27*27*1.25P1.0
more
more
more
more
more
more
more
more
more
more
more
more
more
MPC8250ACVRIHBB
MPC8250ACVRIHBC
MPC8250ACZQIHBB
MPC8250ACZQIHBC
MPC8250ACZUMHBB
MPC8250ACZUMHBC
MPC8250AVRIHBB
MPC8250AVRIHBC
MPC8250AZQIHBB
MPC8250AZQIHBC
MPC8250AZUMHBB
MPC8250AZUMHBC
MPC8250AZUPIBB
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
No
Recommended
for New Design
-
-
-
-
-
-
-
-
-
-
-
-
-
PBGA 516
27*27*1.25P1.0
Available
Not
PBGA 516
27*27*1.25P1.0
Recommended
for New Design
-
PBGA 516
27*27*1.25P1.0
No
Available
Not
TBGA 480
37*37*1.7P1.27
No
Recommended
for New Design
TBGA 480
37*37*1.7P1.27
No
Available
Not
PBGA 516
27*27*1.25P1.0
Yes
Yes
No
Recommended
for New Design
PBGA 516
27*27*1.25P1.0
Available
Not
PBGA 516
27*27*1.25P1.0
Recommended
for New Design
-
PBGA 516
27*27*1.25P1.0
No
Available
Not
TBGA 480
37*37*1.7P1.27
No
Recommended
for New Design
TBGA 480
37*37*1.7P1.27
No
Available
Not
TBGA 480
37*37*1.7P1.27
No
Recommended
for New Design
TBGA 480
37*37*1.7P1.27
more
more
MPC8250AZUPIBC
XPC8250ACZUIFBA
No
No
No
No
Available
-
-
Not
TBGA 480
37*37*1.7P1.27
Recommended
for New Design
-
-
-
-
-
Not
TBGA 480
37*37*1.7P1.27
more
more
more
more
XPC8250ACZUMHBA
XPC8250AZUIFBA
XPC8250AZUMHBA
XPC8250AZUPHBA
No
No
No
No
No
No
No
No
Recommended
for New Design
-
-
-
-
Not
TBGA 480
37*37*1.7P1.27
Recommended
for New Design
Not
TBGA 480
37*37*1.7P1.27
Recommended
for New Design
Not
TBGA 480
37*37*1.7P1.27
Recommended
for New Design
NOTE: Are you looking for an obsolete orderable part? Click HERE to check our distributors' inventory.
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Related Products
MC33702 : MICROPROCESSOR POWER SUPPLY (3.0 A)
The 33702 is a monolithic IC providing an efficient means of obtaining power for the Motorola Power QUICC I and ...
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Related Links
Networking
PowerPC™ Processors
PowerQUICC™ Communication Processors
Security Processors
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© Copyright 1994-2004 Motorola, Inc. All Rights Reserved.
相关型号：
MPC8250ACZQNJDX
32-BIT, 291MHz, RISC PROCESSOR, PBGA516, 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-516
NXP
MPC8250ACZQPIBX
32-BIT, 300 MHz, RISC PROCESSOR, PBGA516, 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-516
NXP
MPC8250ACZUMHBC
RISC Microprocessor, 32-Bit, 266MHz, CMOS, PBGA480, 37 X 37 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, TBGA-480
MOTOROLA
MPC8250ACZUNJDX
32-BIT, 291 MHz, RISC PROCESSOR, PBGA480, 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480
NXP
MPC8250ACZUPIBX
32-BIT, 300 MHz, RISC PROCESSOR, PBGA480, 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480
NXP
MPC8250AVVLHDX
32-BIT, 250MHz, RISC PROCESSOR, PBGA480, 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-480
NXP
MPC8250AVVNJDX
32-BIT, 291MHz, RISC PROCESSOR, PBGA480, 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-480
NXP
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