MMDF4P03HD [MOTOROLA]

DUAL TMOS POWER MOSFET 30 VOLTS; 双TMOS功率MOSFET 30伏


型号：	MMDF4P03HD
厂家：	MOTOROLA
描述：	DUAL TMOS POWER MOSFET 30 VOLTS 双TMOS功率MOSFET 30伏
文件：	总10页 (文件大小：209K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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by MMDF4P03HD/D

SEMICONDUCTOR TECHNICAL DATA

Medium Power Surface Mount Products

Motorola Preferred Device

DUAL TMOS

POWER MOSFET

30 VOLTS

Dual HDTMOS devices are an advanced series of power

MOSFETs which utilize Motorola’s High Cell Density TMOS

process. Dual HDTMOS devices are designed for use in low

voltage, high speed switching applications where power efficiency

is important. Typical applications are dc–dc converters, and power

management in portable and battery powered products such as

computers, printers, cellular and cordless phones. They can also

be used for low voltage motor controls in mass storage products

such as disk drives and tape drives.

= 85 m

DS(on)

•

Low R Provides Higher Efficiency and Extends Battery Life

DS(on)

Logic Level Gate Drive — Can Be Driven by Logic ICs

Miniature SO–8 Surface Mount Package — Saves Board Space

Diode Is Characterized for Use In Bridge Circuits

Diode Exhibits High Speed, With Soft Recovery

CASE 751–05, Style 11

SO–8

Specified at Elevated Temperature

DSS

Mounting Information for SO–8 Package Provided

Drain–1

Drain–2

Source–1

Gate–1

Source–2

Gate–2

Top View

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

Rating

Drain–to–Source Voltage

Symbol

Value

Unit

Vdc

DSS

Gate–to–Source Voltage — Continuous

± 20

Drain Current — Continuous @ T = 25°C

4.0

Adc

Apk

Drain Current — Single Pulse (t ≤ 10 µs)

Source Current — Continuous @ T = 25°C

1.7

2.0

Adc

Watts

°C

(1)

Total Power Dissipation @ T = 25°C

Operating and Storage Temperature Range

T , T

stg

– 55 to 150

450

Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C

= 30 Vdc, V

= 5.0 Vdc, V

= 20 Vdc, I = 9.0 Apk, L = 10 mH, R = 25

)

Thermal Resistance — Junction–to–Ambient

62.5

260

°C/W

°C

θJA

Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 sec.

DEVICE MARKING

D4P03

(1) Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.

ORDERING INFORMATION

Device

Reel Size

Tape Width

Quantity

MMDF4P03HDR2

13″

12 mm embossed tape

2500

This document contains information on a new product. Specifications and information herein are subject to change without notice.

HDTMOS is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola TMOS Power MOSFET Transistor Device Data

Motorola, Inc. 1997

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

Vdc

(BR)DSS

= 0 Vdc, I = 0.25 mAdc)

—

Zero Gate Voltage Drain Current

µAdc

DSS

= 24 Vdc, V

= 0 Vdc)

= 0 Vdc, T = 125°C)

—

1.0

Gate–Body Leakage Current (V

= ±20 Vdc, V

= 0 Vdc)

—

100

nAdc

Vdc

GSS

(1)

ON CHARACTERISTICS

Gate Threshold Voltage

GS(th)

= V , I = 0.25 mAdc)

1.0

—

Threshold Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance

Ω

DS(on)

= 10 Vdc, I = 3.5 Adc)

—

0.075

0.125

0.085

0.16

= 4.5 Vdc, I = 2.0 Adc)

Forward Transconductance (V

= 15 Vdc, I = 3.5 Adc)

—

6.0

—

Mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

—

425

209

57.2

600

300

iss

= 24 Vdc,

= 0 Vdc,

Output Capacitance

oss

f = 1.0 MHz)

Transfer Capacitance

rss

(2)

SWITCHING CHARACTERISTICS

Turn–On Delay Time

—

11.7

15.8

167.3

102.6

14.8

1.7

23.4

31.6

334.6

205.2

29.6

—

d(on)

= 15 Vdc,

= 10 Vdc,

= 1.0 Adc,

Rise Time

Turn–Off Delay Time

Fall Time

d(off)

= 6.0 Ω)

Gate Charge

(See Figure 8)

= 10 Vdc,

= 3.5 Adc,

= 10 Vdc)

4.7

—

3.42

—

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

(I = 1.7 Adc, V

= 0 Vdc)

= 0 Vdc,

Vdc

(I = 1.7 Adc, V

—

0.9

0.7

1.2

—

T = 125°C)

Reverse Recovery Time

—

77.4

19.9

—

(I = 3.5 Adc,

= 0 Vdc,

dI /dt = 100 A/µs)

57.5

Reverse Recovery Stored Charge

0.088

µC

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.

(2) Switching characteristics are independent of operating junction temperature.

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

6.0

= 10 V

= 25°C

6.0 V

4.5 V

4.3 V

100°C

≥ 10 V

4.1 V

5.0

4.0

3.0

2.0

1.0

5.0

4.0

3.0

2.0

3.9 V

3.7 V

3.5 V

3.3 V

3.1 V

2.9 V

2.7 V

25°C

1.0

= –55°C

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

Figure 2. Transfer Characteristics

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.18

0.16

0.14

0.12

0.10

0.08

= 25°C

= 25

= 3 A

= 4.5 V

10 V

0.06

0.04

0.1

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

1.0

1.5

2.0

2.5

I , DRAIN CURRENT (AMPS)

3.0

3.5

4.0

4.5

5.0

5.5

, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 3. On–Resistance versus

Gate–To–Source Voltage

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

100

1.6

1.4

1.2

1.0

0.8

0.6

0.4

= 0 V

= 10 V

= 1.5 A

= 125°C

100°C

0.2

1.0

–50

–25

100

125

150

5.0

T , JUNCTION TEMPERATURE (

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 5. On–Resistance Variation with

Temperature

Figure 6. Drain–To–Source Leakage

Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.

The lengths of various switching intervals (∆t) are deter-

mined by how fast the FET input capacitance can be charged

by current from the generator.

The capacitance (C ) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when cal-

culating t

and is read at a voltage corresponding to the

d(on)

on–state when calculating t

d(off)

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source

lead, inside the package and in the circuit wiring which is

common to both the drain and gate current paths, produces a

voltage at the source which reduces the gate drive current.

The voltage is determined by Ldi/dt, but since di/dt is a func-

tion of drain current, the mathematical solution is complex.

The MOSFET output capacitance also complicates the

mathematics. And finally, MOSFETs have finite internal gate

resistance which effectively adds to the resistance of the

driving source, but the internal resistance is difficult to mea-

sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is

affected by the parasitic circuit elements. If the parasitics

were not present, the slope of the curves would maintain a

value of unity regardless of the switching speed. The circuit

used to obtain the data is constructed to minimize common

inductance in the drain and gate circuit loops and is believed

readily achievable with board mounted components. Most

power electronic loads are inductive; the data in the figure is

taken with a resistive load, which approximates an optimally

snubbed inductive load. Power MOSFETs may be safely op-

erated into an inductive load; however, snubbing reduces

switching losses.

The published capacitance data is difficult to use for calculat-

ing rise and fall because drain–gate capacitance varies

greatly with applied voltage. Accordingly, gate charge data is

used. In most cases, a satisfactory estimate of average input

current (I

) can be made from a rudimentary analysis of

G(AV)

the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a resis-

tive load, V remains virtually constant at a level known as

the plateau voltage, V

. Therefore, rise and fall times may

SGP

be approximated by the following:

t = Q x R /(V

– V )

GSP

t = Q x R /V

GSP

where

= the gate drive voltage, which varies from zero to V

= the gate drive resistance

and Q and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is

not constant. The simplest calculation uses appropriate val-

ues from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

= R

In [V

/(V

GG GG

– V

)]

GSP

d(on)

iss

In (V

GG GSP

)

d(off)

iss

1000

= 25°C

800

600

400

iss

oss

200

rss

–10

–5.0

5.0

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

7.0

6.0

5.0

4.0

1000

100

= 15 V

= 3 A

= 10 V

= 25°C

d(off)

3.0

2.0

d(on)

= 3 A

= 25°C

1.0

2.0

1.0

, GATE RESISTANCE (OHMS)

100

4.0

6.0

8.0

Q , TOTAL GATE CHARGE (nC)

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode

are very important in systems using it as a freewheeling or

commutating diode. Of particular interest are the reverse re-

covery characteristics which play a major role in determining

switching losses, radiated noise, EMI and RFI.

di/dts. The diode’s negative di/dt during t is directly con-

trolled by the device clearing the stored charge. However,

the positive di/dt during t is an uncontrollable diode charac-

teristic and is usually the culprit that induces current ringing.

Therefore, when comparing diodes, the ratio of t /t serves

b a

System switching losses are largely due to the nature of

the body diode itself. The body diode is a minority carrier de-

as a good indicator of recovery abruptness and thus gives a

comparative estimate of probable noise generated. A ratio of

1 is considered ideal and values less than 0.5 are considered

snappy.

Compared to Motorola standard cell density low voltage

MOSFETs, high cell density MOSFET diodes are faster

vice, therefore it has a finite reverse recovery time, t , due to

the storage of minority carrier charge, Q , as shown in the

typical reverse recovery wave form of Figure 15. It is this

stored charge that, when cleared from the diode, passes

through a potential and defines an energy loss. Obviously,

repeatedly forcing the diode through reverse recovery further

increases switching losses. Therefore, one would like a

(shorter t ), have less stored charge and a softer reverse re-

covery characteristic. The softness advantage of the high

cell density diode means they can be forced through reverse

recovery at a higher di/dt than a standard cell MOSFET

diode without increasing the current ringing or the noise gen-

erated. In addition, power dissipation incurred from switching

the diode will be less due to the shorter recovery time and

lower switching losses.

diode with short t and low Q

these losses.

specifications to minimize

The abruptness of diode reverse recovery effects the

amount of radiated noise, voltage spikes, and current ring-

ing. The mechanisms at work are finite irremovable circuit

parasitic inductances and capacitances acted upon by high

2.5

= 0 V

= 25°C

2.0

1.5

1.0

0.5

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

di/dt = 300 A/µs

Standard Cell Density

High Cell Density

t, TIME

Figure 11. Reverse Recovery Time (t )

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

averaged over a complete switching cycle must not exceed

(T – T )/(R ).

A power MOSFET designated E–FET can be safely used

the maximum simultaneous drain–to–source voltage and

drain current that a transistor can handle safely when it is for-

ward biased. Curves are based upon maximum peak junc-

J(MAX)

θJC

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-

sipated in the transistor while in avalanche must be less than

the rated limit and must be adjusted for operating conditions

differing from those specified. Although industry practice is to

rate in terms of energy, avalanche energy capability is not a

constant. The energy rating decreases non–linearly with an

increase of peak current in avalanche and peak junction tem-

perature.

tion temperature and a case temperature (T ) of 25°C. Peak

repetitive pulsed power limits are determined by using the

thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance – Gen-

eral Data and Its Use.”

Switching between the off–state and the on–state may tra-

verse any load line provided neither rated peak current (I

)

) is exceeded, and that the transition

nor rated voltage (V

DSS

time (t , t ) does not exceed 10 µs. In addition the total power

r f

100

500

= 12 V

1.0 ms

SINGLE PULSE

= 25 C

= 3 A

450

400

350

300

250

200

150

100

10 ms

1.0

0.1

LIMIT

DS(on)

THERMAL LIMIT

PACKAGE LIMIT

0.01

0.1

1.0

105

125

100

145

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

T , STARTING JUNCTION TEMPERATURE (

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

1.0

0.1

D = 0.5

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

1.0E–04

0.001

1.0E–05

1.0E–03

1.0E–02

1.0E–01

1.0E+00

1.0E+01

1.0E+02

1.0E+03

t, TIME (s)

Figure 14. Thermal Response

di/dt

TIME

0.25 I

Figure 15. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total

design. The footprint for the semiconductor packages must be

the correct size to ensure proper solder connection interface

between the board and the package. With the correct pad

geometry, the packages will self–align when subjected to a

solder reflow process.

0.060

1.52

0.275

7.0

0.155

4.0

0.024

0.6

0.050

1.270

inches

SO–8 POWER DISSIPATION

The power dissipation of the SO–8 is a function of the input

pad size. This can vary from the minimum pad size for

soldering to the pad size given for maximum power

dissipation. Power dissipation for a surface mount device is

the equation for an ambient temperature T of 25°C, one can

calculate the power dissipation of the device which in this case

is 2.0 Watts.

determined by T

, the maximum rated junction

, the thermal resistance from the

J(max)

temperature of the die, R

150°C – 25°C

= 2.0 Watts

θJA

62.5°C/W

devicejunctiontoambient;andtheoperatingtemperature,T .

Using the values provided on the data sheet for the SO–8

package, P can be calculated as follows:

The 62.5°C/W for the SO–8 package assumes the

recommended footprint on a glass epoxy printed circuit board

to achieve a power dissipation of 2.0 Watts using the footprint

shown. Another alternative would be to use a ceramic

substrate or an aluminum core board such as Thermal Clad .

Using board material such as Thermal Clad, the power

dissipation can be doubled using the same footprint.

– T

J(max)

θJA

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values into

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated

to a high temperature, failure to complete soldering within a

short time could result in device failure. Therefore, the

following items should always be observed in order to

minimize the thermal stress to which the devices are

subjected.

• Always preheat the device.

• The delta temperature between the preheat and soldering

should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering method,

the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

• When shifting from preheating to soldering, the maximum

temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and result

in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive

thermal shock and stress which can result in damage to the

device.

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control

line on the graph shows the actual temperature that might be

experienced on the surface of a test board at or near a central

solder joint. The two profiles are based on a high density and

a low density board. The Vitronics SMD310 convection/in-

frared reflow soldering system was used to generate this

profile. The type of solder used was 62/36/2 Tin Lead Silver

with a melting point between 177–189°C. When this type of

furnace is used for solder reflow work, the circuit boards and

solder joints tend to heat first. The components on the board

are then heated by conduction. The circuit board, because it

has a large surface area, absorbs the thermal energy more

efficiently, then distributes this energy to the components.

Because of this effect, the main body of a component may be

up to 30 degrees cooler than the adjacent solder joints.

settings that will give the desired heat pattern. The operator

must set temperatures for several heating zones and a figure

for belt speed. Taken together, these control settings make up

a heating “profile” for that particular circuit board. On

machines controlled by a computer, the computer remembers

these profiles from one operating session to the next. Figure

16 shows a typical heating profile for use when soldering a

surface mount device to a printed circuit board. This profile will

vary among soldering systems, but it is a good starting point.

Factors that can affect the profile include the type of soldering

system in use, density and types of components on the board,

typeofsolderused, andthetypeofboardorsubstratematerial

being used. This profile shows temperature versus time. The

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

STEP 6

VENT

STEP 7

COOLING

STEP 1

PREHEAT

ZONE 1

“RAMP”

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

STEP 2

VENT

“SOAK” ZONES 2 & 5

“RAMP”

STEP 3

HEATING

205

PEAK AT

SOLDER JOINT

° TO 219°C

200

170°C

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

160°C

150°C

150°

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

100°C

140°C

MASS OF ASSEMBLY)

100

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

50°

TIME (3 TO 7 MINUTES TOTAL)

MAX

Figure 16. Typical Solder Heating Profile

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

NOTES:

–A–

1. DIMENSIONS A AND B ARE DATUMS AND T IS A

DATUM SURFACE.

2. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

3. DIMENSIONS ARE IN MILLIMETER.

4. DIMENSION A AND B DO NOT INCLUDE MOLD

PROTRUSION.

5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

6. DIMENSION D DOES NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS

OF THE D DIMENSION AT MAXIMUM MATERIAL

CONDITION.

–B–

MILLIMETERS

DIM

MIN

4.80

3.80

1.35

0.35

0.40

MAX

5.00

4.00

1.75

0.49

1.25

–T–

SEATING

PLANE

1.27 BSC

8X D

0.18

0.10

0.25

0.25 (0.010)

5.80

0.25

6.20

0.50

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

CASE 751–05

SO–8

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

ISSUE P

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”

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ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola

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MMDF4P03HD/D

◊

Motorola TMOS Power MOSFET Transistor Device Data

MMDF4P03HD [MOTOROLA]

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