MCM67D709 [MOTOROLA]
128K x 9 Bit Synchronous Dual I/O Fast Static RAM; 128K ×9位同步双I / O快速静态RAM
| 型号： | MCM67D709 |
| 厂家： | 
MOTOROLA |
| 描述： | 128K x 9 Bit Synchronous Dual I/O Fast Static RAM |
| 文件： | 总12页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM67D709/D
SEMICONDUCTOR TECHNICAL DATA
MCM67D709
128K x 9 Bit Synchronous
Dual I/O Fast Static RAM
The MCM67D709 is a 1,179,648 bit synchronous static random access
memory organized as 131,072 words of 9 bits, fabricated using Motorola’s
high–performance silicon–gate BiCMOS technology. The device integrates a
128K x 9 SRAM core with advanced peripheral circuitry consisting of address
registers, two sets of input data registers and two sets of output latches. This
device has increased output drive capability supported by multiple power pins.
Asynchronous inputs include the processor output enable (POE) and the
system output enable (SOE).
FN PACKAGE
PLASTIC
CASE 778–02
The address inputs (A0 – A16) are synchronous and are registered on the
falling edge of clock (K). Write enable (W), processor input enable (PIE) and
system input enable (SIE) are registered on the rising edge of clock (K). Writes
to the RAM are self–timed.
PIN ASSIGNMENTS
All data inputs/outputs, PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, and SDQP
haveinputdataregisterstriggeredbytherisingedgeoftheclock. Thesepinsalso
have three–state output latches which are transparent during the high
level of the clock and latched during the low level of the clock.
7
6
5
4
3
2
1 52 51 50 49 48 47
46
A16
A15
PDQ7
8
9
10
11
PDQP
SDQP
45
44
43
V
SS
This device has a special feature which allows data to be passed through the
RAM between the system and processor ports in either direction. This streaming
is accomplished by latching in data from one port and asynchronously output
enabling the other port. It is also possible to write to the RAM while streaming.
The MCM67D709’s dual I/Os can be used in x9 separate I/O applications.
Common I/Os PDQ0 – 7, PDQP and SDQ0 – 7, SDQP can be treated as either
inputs (D) or outputs (Q) depending on the state of the control pins. In order to
dedicate PDQ0 – 7, PDQP as data (D) inputs and SDQ0 – 7, SDQP as outputs
(Q), tie SIE and POE high. SOE becomes the asynchronous G for the outputs.
PIE will need to track W for proper write/read operations.
SDQ7
PDQ6
SDQ6
V
12
13
42
41
SS
V
PDQ5
CC
14
15
16
17
18
40
39
38
37
36
PDQ4
SDQ4
PDQ2
SDQ2
SDQ5
V
CC
PDQ3
SDQ3
V
V
SS
SS
PDQ1
SDQ1
19
20
35
34
PDQ0
SDQ0
21 22 23 24 25 26 27 28 29 30 31 32 33
This device is ideally suited for pipelined systems and systems with multiple
data buses and multi–processing systems, where a local processor has a bus
isolated from a common system bus.
•
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply
88110/88410 Compatibility: –16/60 MHz, –20/50 MHz
Self–Timed Write Cycles
Clock Controlled Output Latches
Address and Data Input Registers
Common Data Inputs and Data Outputs
Dual I/O for Separate Processor and Memory Buses
Separate Output Enable Controlled Three–State Outputs
3.3 V I/O Compatible
High Board Density 52 Lead PLCC Package
Can be used as Separate I/O x9 SRAM
PIN NAMES
A0 – A16 . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
PIE . . . . . . . . . . . . . Processor Input Enable
SIE . . . . . . . . . . . . . . . System Input Enable
POE . . . . . . . . . . Processor Output Enable
SOE . . . . . . . . . . . . . System Output Enable
PDQ0 – PDQ7 . . . . . . . Processor Data I/O
PDQP . . . . . . . . . . . Processor Data Parity
SDQ0 – SDQ7 . . . . . . . . . System Data I/O
SDQP . . . . . . . . . . . . . System Data Parity
V
CC
V
SS
. . . . . . . . . . . . . . . + 5 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be
connected for proper operation of the
device.
REV2
5/95
Motorola, Inc. 1994
BLOCK DIAGRAM
POE
PDQ0 – PDQ7, PDQP
9
K
DATA
DATA
REGISTER
LATCH
A0 – A16
WRITE
DRIVER
128K x 9 ARRAY
9
SENSE
DATA
DATA
AMPLIFIER
LATCH
REGISTER
9
W
PIE
SIE
SOE
SDQ0 – SDQ7, SDQP
FUNCTIONAL TRUTH TABLE (See Notes 1 and 2)
Memory Subsystem
Cycle
PDQ0 – PDQ7,
PDQP Output
SDQ0 – SDQ7,
SDQP Output
W
PIE
1
SIE
1
POE
0
SOE
1
Mode
Read
Read
Read
Read
N/A
Notes
1
Processor Read
Copy Back
Dual Bus Read
NOP
Data Out
High–Z
High–Z
Data Out
Data Out
High–Z
3
3
3
1
1
1
1
0
1
1
1
0
0
Data Out
High–Z
1
X
0
X
0
1
1
X
X
1
X
1
NOP
High–Z
High–Z
2, 4
2, 5
2, 5
2, 6
2, 6
2, 6
2, 6
4
0
0
1
Write
Write
Write
Write
N/A
Processor Write Hit
Allocate
Data In
High–Z
0
1
0
1
1
High–Z
Data In
0
0
1
1
0
Write Through
Allocate With Stream
Cache Inhibit Write
Cache Inhibit Read
NOP
Data In
Stream Data
Data In
0
1
0
0
1
Stream Data
Data In
1
0
1
1
0
Stream Data
Data In
1
1
0
0
1
N/A
Stream Data
High–Z
0
1
1
X
0
X
0
N/A
High–Z
X
0
1
N/A
Invalid
Data In
Stream
2, 7
2, 7
2, 7
2, 7
X
0
1
0
1
N/A
Invalid
Data In
High–Z
X
X
1
0
0
0
N/A
Invalid
Stream
Data In
1
0
1
0
N/A
Invalid
High–Z
Data In
NOTES:
1. A ‘0’ represents an input voltage ≤ V and a ‘1’ represents an input voltage ≥ V . All inputs must satisfy the specified setup and hold times
IL
IH
for the falling or rising edge of K. Some entries in this truth table represent latched values. Other possible combinations of control inputs not
covered by this note or the table above are not supported and the RAMs behavior is not specified.
2. If either IE signal is sampled low on the rising edge of clock, the corresponding OE is a don’t care, and the corresponding outputs are
High–Z.
3. A read cycle is defined as a cycle where data is driven on the internal data bus by the RAM.
4. No RAM cycle is performed.
5. A write cycle is defined as a cycle where data is driven onto the internal data bus through one of the data I/O ports (PDQ0 – PDQ7 and
PDQP or SDQ0 – SDQ7 and SPDQ), and written into the RAM.
6. Data is driven on the internal data bus by one I/O port through its data input register and latched into the data output latch of the other
I/O port.
7. Data contention will occur.
MCM67D709
2
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0 V)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
Rating
Symbol
Value
Unit
Power Supply
V
CC
– 0.5 to + 7.0
V
Voltage Relative to V
for Any Pin
V , V
in out
– 0.5 to V
CC
+ 0.5
V
SS
Except V
CC
Output Current (per I/O)
Power Dissipation
I
± 30
mA
W
out
P
D
2.0
Temperature Under Bias
Operating Temperature
Storage Temperature
T
– 10 to + 85
0 to +70
°C
°C
°C
bias
T
A
T
– 55 to + 125
stg
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS (Voltages referenced to V
SS
= 0 V)
Parameter
Symbol
Min
4.75
2.2
Max
Unit
V
Supply Voltage (Operating Voltage Range)
V
CC
5.25
Input High Voltage
Input Low Voltage
V
IH
V
+ 0.3**
V
CC
V
IL
– 0.5*
—
0.8
V
Input Leakage Current (All Inputs, V = 0 to V
in CC
)
I
± 1.0
± 1.0
µA
µA
mA
lkg(I)
Output Leakage Current (POE, SOE = V
IH
)
I
—
lkg(O)
AC Supply Current (All Inputs = V or V ,V = 0.0 V and V ≥ 3.0 V,
I
CCA
IL
min)
IH IL
IH
280
260
I
= 0 mA, Cycle Time≥ t
KHKH
MCM67D709–16: t
= 16 ns
= 20 ns
—
—
out
KHKH
KHKH
MCM67D709–20: t
Output Low Voltage (I
OL
= + 8.0 mA)
= – 4.0 mA)
V
—
0.4
3.3
V
V
OL
Output High Voltage (I
OH
V
OH
2.4
*V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
IL IL
**V (max) = V
+ 0.3 V dc; V (max) = V
+ 2.0 V ac (pulse width ≤ 20 ns) for I≤ 20.0 mA.
IH CC IH CC
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Typ
Max
6
Unit
pF
Input Capacitance (All Pins Except I/Os)
C
5
6
in
Input/Output Capacitance (PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, SDQP)
C
7
pF
out
MCM67D709
3
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ CYCLE (See Note 1)
Processor Frequency
60 MHz
50 MHz
MCM67D709–16
MCM67D709–20
Parameter
Read Cycle Time Clock High to Clock High
Clock Low Pulse Width
Symbol
Min
16
5
Max
—
—
—
6
Min
20
5
Max
—
Unit Notes
t
ns
ns
ns
ns
ns
ns
ns
1, 2
KHKH
t
—
KLKH
KHKL
KHQV
Clock High Pulse Width
t
7
7
—
Clock High to Output Valid
t
—
0
—
0
7.5
—
3
Clock (K) High to Output Low Z After Write
Output Hold from Clock High
Setup Times:
t
—
—
—
KHQX1
KHQX2
t
2
3
—
3, 4
A
W
PIE
SIE
t
2
2
2
2
2
2
2
2
—
AVKL
t
WHKH
t
t
PIEHKH
SIEHKH
Hold Times:
A
W
PIE
SIE
t
t
2
2
2
2
—
2
2
2
2
—
ns
KLAX
KHWX
KHPIEX
KHSIEX
t
t
Output Enable High to Q High–Z
Output Hold from Output Enable High
Output Enable Low to Q Active
Output Enable Low to Output Valid
NOTES:
t
t
0
6
—
—
5
0
8
—
—
6
ns
ns
ns
ns
4
4
4
POEHQZ
SOEHQZ
t
t
2
5
POEHQX
SOEHQX
t
t
0
0
POELQX
SOELQX
t
t
—
—
POELQV
SOELQV
1. A read is defined by W high for the setup and hold times.
2. All read cycle timing is referenced from K, SOE, or POE.
3. K must be at a high level for outputs to transition.
4. Transition is measured± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, t
a given device.
is less than t
POELQX
for a given device, and t
is less than t
for
SOELQX
POEHQZ
SOEHQZ
AC SPEC LOADS
+ 5 V
R
= 50 Ω
480
Ω
L
OUTPUT
OUTPUT
255
Z
= 50 Ω
0
Ω
5 pF
V
= 1.5 V
L
Figure 1A
Figure 1B
MCM67D709
4
MOTOROLA FAST SRAM
READ CYCLE (See Note)
t
KHKH
t
t
KHKL
KLKH
K
t
KLAX
t
AVKL
An
An + 1
An + 2
A0 – A16
t
KHPIEX
t
PIEHKH
PIE
SIE
W
t
KHSIEX
t
SIEHKH
t
KHWX
t
WHKH
POE
t
POELQV
t
POEHQZ
t
POELQX
t
POEHQX
SOE
t
SOELQV
PDQ0 – PDQ7, PDQP
Qn
t
t
KHQX1
KHQV
SDQ0 – SDQ7, SDQP
Qn
Qn + 1
t
KHQX2
MCM67D709
MOTOROLA FAST SRAM
5
WRITE THROUGH – READ – WRITE (See Note 1)
Processor Frequency
60 MHz
50 MHz
MCM67D709–16
MCM67D709–20
Parameter
Write Cycle Times
Symbol
Min
16
5
Max
—
Min
20
5
Max
—
Unit Notes
t
ns
ns
ns
ns
1, 2
KHKH
Clock Low Pulse Width
Clock High Pulse Width
t
—
—
KLKH
KHKL
KHQZ
t
7
—
7
—
Clock High to Output High–Z (W = V and
IL
t
—
8
—
8
3, 4
SIE = PIE = V
)
IH
Setup Times:
A
W
PIE
SIE
t
2
2
2
2
2
—
—
2
2
2
2
2
—
—
ns
AVKL
t
WLKH
t
t
PIEVKH
SIEVKH
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP
t
DVKH
Hold Times:
A
W
PIE
SIE
t
2
2
2
2
2
2
2
2
2
2
ns
KLAX
t
KHWX
t
t
KHPIEX
KHSIEX
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP
t
KHDX
Write with Streaming (PIE = SOE = V or
t
—
5
6
—
7
8
ns
ns
ns
ns
ns
5
6
6
6
IL
KHQV
SIE = POE = V ) Clock High to Output Valid
IL
Output Enable High to Q High–Z
Output Hold from Output Enable High
Output Enable Low to Q Active
t
t
0
0
POEHQZ
SOEHQZ
t
t
2
—
—
5
5
—
—
6
POEHQX
SOEHQX
t
t
0
0
POELQX
SOELQX
Output Enable Low to Output Valid
NOTES:
t
t
—
—
POELQV
SOELQV
1. A write is performed with W = V for the specified setup and hold times and either PIE = V or SIE = V . If both PIE = V and SIE = V or
IL IL IL IL IL
PIE = V and SIE = V , then this is treated like a NOP and no write is performed.
IH
IH
2. All write cycle timings are referenced from K.
3. K must be at a high level for the outputs to transition.
4. Transition is measured± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
5. A write with streaming is defined as a write cycle which writes data from one data bus to the array and outputs the same data onto the
other data bus.
6. Transition is measured± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, t
a given device.
is less than t
POELQX
for a given device, and t
is less than t
for
SOELQX
POEHQZ
SOEHQZ
MCM67D709
MOTOROLA FAST SRAM
6
WRITE THROUGH — READ — WRITE
t
KHKH
t
t
KHKL
KLKH
K
t
KLAX
t
AVKL
A0 – A16
An
An + 1
An + 2
t
PIEHKH
t
KHPIEX
t
PIEVKH
t
KHPIEX
PIE
SIE
t
t
KHSIEX
SIEHKH
t
t
SIEVKH
KHSIEX
t
t
KHWX
WHKH
t
t
WLKH
KHWX
W
POE
t
POEHQZ
SOE
t
POEHQX
t
DVKH
t
KHDX
t
SOEHQZ
t
POEHQZ
t
KHDX
t
POELQV
t
DVKH
t
SOELQV
t
SOEHQX
Qn
+ 1
PDQ0 – PDQ7, PDQP
Qn – 1
Dn
Dn + 2
t
POELQX
t
KHQV
Qn
SDQ0 – SDQ7, SDQP
Qn – 1
(STREAMED)
MCM67D709
7
MOTOROLA FAST SRAM
STREAM CYCLE (See Note 1)
Processor Frequency
Symbol
60 MHz
50 MHz
MCM67D709–16
MCM67D709–20
Parameter
Min
16
5
Max
—
—
—
6
Min
20
5
Max
—
—
—
7
Unit Notes
Stream Cycle Time
Clock Low Pulse Width
Clock High Pulse Width
Stream Access Time
Setup Times:
t
ns
ns
ns
ns
ns
1, 2
KHKH
t
KLKH
KHKL
KHQV
t
7
7
t
—
—
A
W
PIE
SIE
t
2
2
2
2
2
—
2
2
2
2
2
—
AVKL
t
WHKH
t
t
PIEVKH
SIEVKH
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP
t
DVKH
Hold Times:
A
W
PIE
SIE
t
2
2
2
2
2
—
2
2
2
2
2
—
ns
KLAX
t
KHWX
t
t
KHPIEX
KHSIEX
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP
t
KHDX
Output Enable High to Q High–Z
t
t
0
6
—
5
0
8
—
6
ns
ns
ns
3
3
POEHQZ
SOEHQZ
Output Enable Low to Q Active
t
t
0
0
POELQX
SOELQX
Output Enable Low to Output Valid
NOTES:
t
t
—
—
POELQV
SOELQV
1. A stream cycle is defined as a cycle where data is passed from one data bus to the other data bus.
2. All stream cycle timing is referenced from K.
3. Transition is measured± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, t is less than t , t is less than t , for a given device.
POEHQZ
POELQX SOEHQZ SOELQX
MCM67D709
MOTOROLA FAST SRAM
8
STREAM CYCLE
t
KHKH
t
t
KHKL
KLKH
K
t
KLAX
t
AVKL
A0 – A16
An
An + 1
An + 2
t
KHPIEX
t
PIEVKH
PIE
SIE
t
KHSIEX
t
SIEVKH
t
KHWX
t
WHKH
W
POE
t
POEHQZ
SOE
t
SOEHQZ
t
DVKH
t
KHQV
t
KHDX
Qn – 1
Dn
Qn + 1 (STREAMED)
PDQ0 – PDQ7, PDQP
t
KHQV
Qn
SDQ0 – SDQ7, SDQP
Qn – 1
Dn + 1
(STREAMED)
MCM67D709
9
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM
67D709 FN
XX
Speed (16 = 16 ns (60 MHz),
20 = 20 ns (50 MHz))
Motorola Memory Prefix
Part Number
Package (FN = PLCC)
Full Part Numbers — MCM67D709FN16 MCM67D709FN20
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
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against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM67D709
10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE
52–LEAD PLCC
CASE 778–02
M
S
S
B
0.007 (0.180)
T
L –M
N
Y BRK
-N-
M
S
S
0.007 (0.180)
T
L –M
N
U
D
D
-L-
-M-
52
LEADS
ACTUAL
Z
W
(NOTE 1)
52
1
G1
X
S
S
S
0.010 (0.250)
0.007 (0.180)
T
L –M
L –M
N
V
VIEW D-D
M
S
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
T
L –M
L –M
N
N
Z
M
R
M
S
S
H
T
N
C
K1
E
K
0.004 (0.100)
(NOTE 1)
52
SEATING
-T-
G
J
PLANE
M
S
S
F
0.007 (0.180)
T
L –M
N
VIEW S
VIEW S
G1
S
S
S
0.010 (0.250)
T
L –M
N
NOTES:
1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE
REPRESENTED BY A GENERAL (SMALLER) CASE
OUTLINE DRAWING RATHER THAN SHOWING ALL 52
LEADS.
2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF
LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-,
SEATING PLANE.
4. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
20.19
20.19
4.57
A
B
C
E
0.785
0.785
0.165
0.090
0.013
0.795
0.795
0.180
0.110
0.019
19.94
19.94
4.20
2.29
2.79
F
0.33
0.48
G
H
J
K
R
U
V
W
X
Y
0.050 BSC
1.27 BSC
0.026
0.032
—
—
0.756
0.756
0.048
0.048
0.056
0.020
0.66
0.51
0.64
19.05
19.05
1.07
1.07
1.07
—
0.81
—
—
19.20
19.20
1.21
1.21
1.42
0.50
0.020
0.025
0.750
0.750
0.042
0.042
0.042
—
6. CONTROLLING DIMENSION: INCH.
7. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS
R AND U ARE DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
8. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
Z
G1
K1
2°
10
°
2°
10°
0.710
0.040
0.730
—
18.04
1.02
18.54
—
MCM67D709
11
MOTOROLA FAST SRAM
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JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
CODELINE TO BE PLACED HERE
MCM67D709/D
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