MCM20027IBBN [MOTOROLA]
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MOTOROLA |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Order this document by MCM20027/D
MCM20027
Advance Information
Color SXGA Digital Image Sensor
1.3 Megapixel
1280 x 1024 pixel progressive scan solid state image sen-
sor with integrated CDS/PGA/ADC, digital programming,
control, timing, and pixel correction features
Features:
•
SXGA resolution, active CMOS image sensor with square
pixel unit cells
•
6.0mm pitch pixels with patented pinned photodiode
architecture
•
•
Bayer-RGB color filter array with optional micro lenses
High sensitivity, quantum efficiency, and charge
conversion efficiency
•
•
•
•
•
•
Low fixed pattern noise / Wide dynamic range
Antiblooming and continuous variable speed shutter
Single master clock operation
Part Number
Description
Package
MCM20027IBBL
Color RGB sensor
with Lenslets
48 Pin CLCC
Digitally programmable via I2C interface
Integrated on-chip timing/logic circuitry
CDS sample and hold for suppression of low frequency
and correlated reset noise
MCM20027IBMN
Monochrome
sensor without
Lenslets
48 Pin CLCC
•
•
20X programmable variable gain to optimize dynamic
range and facilitate white balance and iris adjustment
10-bit, pipelined algorithmic RSD ADC (DNL +0.5 LSB, INL
+1.0 LSB)
•
•
Automatic column offset correction for noise suppression
Pixel addressability to support ‘Window of Interest’
windowing, resolution, and subsampling
Encoded data stream
10 fps full SXGA at 13.5MHz Master Clock Rate
Single 3.3V power supply
•
•
•
•
48 pin CLCC package
The MCM20027 is a fully integrated, high performance CMOS image sensor with features such as integrated timing,
control, and analog signal processing for digital imaging applications. The part provides designers a complete im-
aging solution with a monolithic image capture and processing engine thus making it a true “camera on a chip”. Sys-
tem benefits enable design of smaller, portable, low cost and low power systems. Thereby making the product
suitable for a variety of consumer applications including still/full motion imaging, security/surveillance, and automo-
tive among others.
The imaging pixels are based on active CMOS pixels using pinned photodiodes that are realized using Motorola’s
sub-micron ImageMOSTM technology. A maximum frame rate of 10 FPS at full resolution can be achieved, further
the frame rate is completely adjustable without adjusting the system clock. Each pixel on the sensor is individually
addressable allowing the user to control “Window of Interest” (WOI) panning and zooming. Control of sub-sam-
pling, resolution, exposure, gain, and other image processing features is accomplished via a two pin I2C interface.
The sensor is run by supplying a single Master Clock. The sensor output is 10 digital bits providing wide dynamic
range images.
ELECTRO STATIC DISCHARGE WARNING:
This device is sensitive to electrostatic discharge (ESD).ESD immunity meets Human Body Model (HBM) < 1500 V and Machine Model (MM) < 150
V Additional ESD data upon request. When handling this part, proper ESD precautions should be followed to avoid exposing the device to dis-
charges which may be detrimental to its immediate performance and/or reduce the parts expected lifetime..
This document contains information on a new product.Specifications and information herein are subject to change with-
out notice.
Ó MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 :
MCM20027
1
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Specifications
Image Size: 7.7mm x 6.1mm (9.82mm Diagonal, 1/2” Optic)
Resolution:1280 x 1024 pixels, available digital zoom and region of interest (ROI) windowing
Pixel Size: 6mm x 6mm
Monochrome Sensitivity: 1.8 V/Lux-sec
Min. Detectable Light Level: 3 Lux at 10FPS/F2 lens
Scan Modes: Progressive
Shutter Modes: Continuous Frame and Single Frame Rolling Shutter modes available
Readout Rate: 13.5MSPS
Frame Rate: 0-10 Full frames (1280x1024) per second
Max Master Clock Frequency: 13.5MHz
System Dynamic Range: 50dB
On Chip programmable gain: -9.5dB to 26dB
On Chip Image Correction: Column Fixed Pattern Correction
Analog to Digital Converter: 10-bit, RSD ADC (DNL +/-0.5 LSB, INL +/-1.0 LSB)
Power Dissipation: 250mW RMS, operating @13.5Mhz
Package: 48 pin ceramic LCC
Temperature Operating Range: 0-40oC
MCLK
INIT
Digital
Control
Sensor
STROBE
SYNC
1280 x 1024 pixels
(1296 x 1048 total including
Interface
SCLK
I2C Serial
Interface
dark and isolation)
SDATA
C D S
Post ADC
ADC(9:0)
HCLK
VCLK
10 Bit
ADC
Column
FRC
White
Balance
Global
Gain
Global
Offset
Offset
Control Signal
Encoding
SOF
Figure 1. MCM20027 Simplified Block Diagram
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
1296
4Dark + 4Isolation
48
44
SOF
VCLK
4Da
rk
+4Is
45
47
HCLK
olati
on 104
8
STROBE
1024
Image Sensor Pixel Array
1280
12Dark +4Isolation
2
1
1
2
Column
Sequencer
& Drivers
Column Decode, Sensing, and Muxing
1
INIT
I2C Serial
Interface
Color
Sequencer
30 SDATA
29 SCLK
Analog
Switch
6
6
6
6
43
MCLK
I2 C Register
Decode
Column
Offset
Calibration
EXT_VINR
EXT_VINS
10
11
6
6
6
6
42
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
41
40
39
38
35
10 Bit
Frame
Rate
Clamp
WB
PGA
0.88x -2.84x
Global
PGA
0.696x -7.48x
Global
Dova
Column
DOVA
RSD
Pipelined
ADC
1.5x
2.0x
10
6
7
34 ADC3
ADC2
CLRCA
CLRCB
Post ADC
Processing
Test
Monitor
Logic
32
31
ADC1
ADC0
CVREFM
Bandgap
Reference
and Bias
14
Vrefp
Vrefm
10
Analog Circuits
Digital Logic
CVREFP
EXTRES
15
Generation
Vcm
Ibias
20
19
EXTRESRTN
17
16
18 21
See “MCM20027 Pin Definitions” on page 67 for more information
Figure 2. MCM20027 Detailed Block Diagram
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Table Of Contents
MCM20027 Overview......................................................................
MCM20027 Architecture.................................................................
Pixel Architecture...........................................................................
Color Separation and Fill Factor Enhancement ..........................
Frame Capture Modes....................................................................
Continuous Frame Rolling Shutter capture mode (Default)........
Single Frame Rolling Shutter capture mode (SFRS)...................
Active Window of Interest Control ................................................
Active Window Sub-sampling Control..........................................
Frame Rate and Integration Time Control....................................
CFRS Frame Time/Rate:.................................................................
Integration Time in CFRS mode:...................................................
SFRS Frame Time/Rate:.................................................................
Integration Time in SFRS mode....................................................
1.0
2.0
7
7
2.1
2.2
7
9
3.0
10
10
11
12
12
13
13
13
14
14
3.1
3.2
4.0
5.0
6.0
6.1
6.2
6.3
6.4
6.5
Example of Frame time/rate and Integration Time in CFRS and
SFRS modes....................................................................................
Analog Signal Processing Chain Overview ...............................
Correlated Double Sampling (CDS)...............................................
Frame Rate Clamp (FRC)................................................................
Programmable Per-Column Offset ..............................................
7.0
15
15
15
16
7.1
7.2
7.3
7.4
Digitally Programmable Gain Amplifiers (DPGA) for White Bal-
ance and Exposure Gain................................................................
16
16
16
17
19
19
20
20
20
White Balance Control PGA...........................................................
Exposure Global Gain PGA............................................................
Gain Modes.....................................................................................
Global Digital Offset Voltage Adjust (DOVA)................................
Analog to Digital Converter (ADC)................................................
MCM20027 Sensor External Controls...........................................
Initialization ....................................................................................
Standby Mode...............................................................................
7.4.1
7.4.2
7.4.3
7.5
7.6
8.0
8.1
8.2
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ImageMOS
Table Of Contents
Tristate Mode..................................................................................
References CVREFP, CVREFM......................................................
Common Mode References: VAG, VAGREF and VAGRETURN.
Internal Bias Current Control.........................................................
Sensor Output/Input Signals.........................................................
Start Of Data Capture (SYNC)........................................................
Start Of Row Readout (SOF)..........................................................
Horizontal Data SYNC (VCLK)........................................................
Data Valid (HCLK)...........................................................................
Strobe Signal...................................................................................
8.3
8.4
8.5
8.6
20
20
20
21
22
22
22
22
22
24
26
26
9.0
9.1
9.2
9.3
9.4
9.5
I2C Serial Interface..........................................................................
10.0
MCM20027 I2C Bus Protocol ........................................................
START Signal..................................................................................
Slave Address Transmission.........................................................
Acknowledgment ...........................................................................
Data Transfer..................................................................................
Stop Signal......................................................................................
Repeated START Signal.................................................................
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
26
26
26
26
27
27
27
28
28
31
32
32
35
64
67
69
72
I2C Bus Clocking and Synchronization........................................
Register Write.................................................................................
Register Read..................................................................................
Suggested Software Register Changes........................................
MCM20027 Utility Programming Registers...................................
Register Reference Map ................................................................
Detailed Register Block Assignments..........................................
Electrical Characteristics ..............................................................
MCM20027 Pin Definitions.............................................................
MCM20027 Packaging Information................................................
MCM20027 Typical electrical connection.....................................
11.0
12.0
12.1
13.0
14.0
15.0
16.0
17.0
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Reference Documentation
Release
Date
No
1
Description
Name of Document
Contact/Location of Info
Digital Camera Reference
Design utilizing the MCM20027
Roadrunner
Application Note
May 4 2001
http://www.motorola.com/adc/imaging
http://www.motorola.com/adc/imaging
Information on MCM20027
Optics
Optic Application
note
2
Feb 7 2001
Strobe Timing
Application Note
http://www.motorola.com/adc/imaging
3
Information on Strobe Timing
May 30 2001
Table 1. Reference Documentation
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
1.0 MCM20027 Overview
grammable Per-Column Offset” on page 16 and “Global
Digital Offset Voltage Adjust (DOVA)” on page 19) can
be done on a per column basis and globally. This per-
column offset correction can be applied by using stored
values in the on chip registers. A 10-bit Redundant
Signed Digit (RSD) ADC converts the analog data to a
10-bit digital word stream. The fully differential analog
signal processing pipeline serves to improve noise im-
munity, signal to noise ratio, and system dynamic
range.
The MCM20027 is a solid state CMOS Active CMOS
Imager (ACITM) that integrates the functionality of a
complete analog image acquisition, digitizer, and digital
signal processing system on a single chip. The image
sensor comprises a format pixel array with 1280x1024
active elements. The image size is fully programmable
to user defined windows of interest. The pixels are on a
6.0mm pitch. High sensitivity and low noise are a char-
acteristic of the pinned “shared diffusion” photodiode ar-
chitecture utilized in the pixels. Standard microlenses
further enhance the sensitivity. The sensor is available
with Bayer patterned Color Filter Arrays (CFAs) for color
output or as a monochrome imager.
The sensor uses an industry standard two line I2C com-
plaint serial interface. (see page 26). The MCM20027
operates with a single 3.3V power supply ( see “Electri-
cal Characteristics” on page 53) with no additional bias-
es and requires only a single Master Clock for operation
upto 13.5MHz. It is housed in a 48 pin ceramic LCC
package (see “MCM20027 Packaging Information” on
page 69).
Integrated timing and programming controls allow video
or still image capture modes.Frame rates are program-
mable while keeping Master Clock frequency constant.
User programmable row and column start/stop allow
windowing to a minimum 1x1 pixel window (see “Active
Window of Interest Control” on page 12). Windowing
can also be performed by subsampling in multiple pixel
increments to allow digital zoom (see “Active Window
Sub-sampling Control” on page 12).
The MCM20027 is designed taking into consideration
interfacing requirements to standard video encoders. In
addition to the 10 bit bayer encoded data stream, the
sensor outputs the valid frame, line and pixel sync sig-
nals needed for encoding. The sensor interfaces with a
variety of commercially available video image proces-
sors to allow encoding into various standard video for-
mats.
The analog video output of the pixel array is processed
by an on chip analog signal processing pipeline. Corre-
lated Double Sampling (see “Correlated Double Sam-
pling (CDS)” on page 15) eliminates the sensor reset
noise without the need to capture and subtract a reset
frame per live video frame. The Frame Rate Clamp
(FRC) enables real time optical black level calibration
and offset correction (see “Frame Rate Clamp (FRC)”
on page 15). The programmable analog gain consists of
exposure or global gain to map the signal swing to the
ADC input range, and white balance gain to perform col-
or white balance in the analog domain. The ASP signal
chain consists of :
The MCM20027 is an elegant and extremely flexible
single chip solution that simplifies a system designer’s
tasks of image sensing, processing, digital conversion,
and digital signal processing to a high performance, low
cost, low power IC. One that supports among others a
wide range of low power, portable consumer digital im-
aging applications.
2.0 MCM20027 Architecture
2.1 Pixel Architecture
The MCM20027 ImageMOSTM (1) sensor comprises of
a 1280 x 1024 active pixel array and supports progres-
sive scan mode.
(1) Column op-amp(1.5X fixed gain)
(2) Column DOVA (1.5X fixed gain)
(3) White Balance PGA (0.88-2.82X)
(4) Global PGA (0.67X - 5.92X)
The MCM20027 utilizes the Kodak patented “Shared
Floating Diffusion” pixel design 3. This design enables
two adjacent Row pixels‘ photodiodes to share the
same floating diffusion transistor. (see Figure 2, on
page 8).
(5) Global DOVA (2.0X fixed gain)
These Digitally Programmable Amplifiers (DPGAs) al-
low real time color gain correction for Auto White Bal-
ance (see “White Balance Control PGA” on page 16) as
well as global gain adjustment (see “Exposure Global
Gain PGA” on page 16); offset calibration (see “Pro-
1. ImageMOS is a Motorola trademark
2. Patents held jointly by Motorola and Kodak
3. Kodak Patent pending
Revision 8.0 - 28 November 2001 :
MCM20027
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
The basic operation of the pixel relies on the photoelec-
tric effect where due to its physical properties silicon is
able to detect photons of light. The photons generate
electron-hole pairs in direct proportion to the intensity
and wavelength of the incident illumination. The appli-
cation of an appropriate bias allows the user to collect
the electrons and meter the charge in the form of a use-
ful parameter such as voltage.
sion and Row Select gate controls. In addition all pixels
have common supply (VDD) and ground (VSS) connec-
tions. An optimized cell architecture provides enhance-
ments such as noise reduction, fill factor maximizations,
and antiblooming. The use of pinned photodiodes (2)
and proprietary transfer gate devices in the photoele-
ments enables enhanced sensitivity in the entire visual
spectral range and a lag free operation.
The pixel architecture also requires all pixels in a row to
have common Reset , Transfer 1 and 2, Floating diffu-
SHARED
RESET
GATE
ROW SELECT
FLOATING
GATE
DIFFUSION
GATE
TRANSFER
GATE 1
TRANSFER
GATE 2
PHOTODIODE
PHOTODIODE
ROW2
ROW 1
Figure 2. Shared Floating Diffusion Pixel Architecture
TRANSFER GATE 1
TRANSFER GATE 2
RESET GATE
T
int
T
int
ROW SELECT GATE
SHARED FLOATING
DIFFUSION GATE
T
row
T
row
T=0
T=1
T=2
T=5 T=6
T=3 T=4
How it works?
At this time Photodiode 2 is held at Reset level by hav-
ing Transfer Gate 2 and the Reset Gate open (On). Af-
ter 1 Row Period [Trow], @T=2 ,Transfer Gate 2 closes
(Off). This action causes Photodiode 2 to start charging.
When the integration (charging) of Photdiode 1 has
In brief, initially during Integration @T=0, both Transfer
Gates 1 and 2 and the Reset Gate is Open (On-Active
High). Transfer Gate 1 then Closes (Off) @ T=1, there-
by allowing Photodiode 1 to charge its well capacitance.
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
neared completion, @ T=3, the Reset Gate closes (Off).
The charge off the well capacitance of Photodiode 1 is
then transfered to the Shared Floating Diffusion Gate
@ T=4 when Transfer Gate 1 opens (On). Also @T=4
the Shared Diffusion gate and the Row Select gate
opens (On). This action causes charge from the floating
diffusion to be read out as a Voltage value for that pixel
on Row 1. @T=5 the Row Select gate and the Floating
diffusion close (Off) while the Reset gate opens (On).
This is occurs in preparation of readout of Row 2.
When the integration (charging) of Photodiode 2 has
neared completion, the Reset Gate closes (Off) again.
The charge off the Well Capacitance of Photodiode 2 is
then transfered to the Shared Floating Diffusion Gate
@ T=6 when Transfer Gate 2 opens (On) and then the
same readout procedure as before occurs.
The nominal photoresponse of the MCM20027 is shown
in Figure 3
R
G
B
S
R
F
,
4 0 0 t o 1 1 0 0 n m
1
0 . 9
0 . 8
0 . 7
0 . 6
0 . 5
0 . 4
0 . 3
0 . 2
0 . 1
0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
1 0 0 0
1 1 0 0
- 0 . 1
W
a v e l e
ix e ls
n g t h , n m
R
E
D
P
ix e ls
G
r e e n - B
P
G
r e e n - B
P
ix e ls
B lu e P ix e ls
Figure 3. MCM20027 Nominal spectral response
In addition to the imaging pixels, there are additional
pixels called dark and dummy pixels at the periphery of
the imaging section (see Figure 2). The dark pixels are
covered by a light blocking shield rendering the pixels
underneath insensitive to photons. These pixels provide
the sensor means to measure the dark level offset
which is used downstream in the signal processing
chain to perform auto black level calibration. The dum-
my pixels are provided at the array’s periphery to elimi-
nate inexact measurements due to light piping into the
dark pixels adjacent to active pixels. The output of these
pixels should be discarded.
atary color filter technology result in CFAs with superior
spectral and transmission properties. The standard op-
tion is a primary (RGB) “Bayer” pattern (see Figure 4),
however, facility to produce customized CFAs including
complementary (CMYG) mosaics also exists.
Applications requiring higher sensitivity can benefit from
the optional micro-lens arrays shown in Figure 5. The
lenslet arrays can improve the fill factor (aperture ratio)
of the sensor by 1.5-2x depending on the F number of
the main lens used in the camera system. Microlenses
yield greatest benefits when the main lens has a high F
number. As a caution, telecentric optical design is a re-
quirement due to the limited optical acceptance angle of
the lenslit. The optical acceptance angle is approxi-
mately 15 degrees (see figure 5a). Due to the lenslits
being placed in the same area/position over all the pho-
todiodes on the sensor, hence, care should be taken
when taking into consideration the telecentric design for
especially the outermost pixels.The fill factor of the pix-
els without microlenses is 32%. With Microlens the fill
factor improves to approximately 45% to 50%.
Electronic shuttering, also known as electronic expo-
sure timing in photographic terms, is a standard feature.
The pixel integration time can be widely varied from a
small fraction of a given frame readout time to the entire
frame time.
2.2 Color Separation and Fill Factor Enhancement
The MCM20027 family is offered with the option of
monolithic polymer color filter arrays (CFAs). The com-
bination of an extremely planarized process and propri-
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ImageMOS
3.1 Continuous Frame Rolling Shutter capture
(CFRS) [Default]
G1
B
R
G2
R
G1
B
R
G2
R
The default mode of image capture is the “Continuous
Frame Rolling Shutter” capture mode (CFRS). This
mode will yield frame rates up to 10fps at 13.5 MHz
MCLK. In this mode the image integration and row read-
out take place in parallel. While a row of pixels is being
read out, another row(s) are being integrated. Readout
of each row follows the Integration of that row. There-
fore the Integration of the rows are staggered out due to
the Readout of sequential rows occurring one after the
other (see “Integration Time in CFRS mode:” on
page 13).
G1
G1
B
G2
G2
B
Figure 4. On-chip Bayer CFA
In CFRS, after one frame has completed integrating,
the first row of the second frame automatically begins
integrating. The readout of the rows also follow the
same routine. The waveforms depicting the CFRS out-
put data stream refer to Figure 6, on page 11 and Figure
7, on page 12.
A
o
o
15
15
3.1.1 CFRS Video Encoded Data stream
The Pixel Data Stream Signal Control Register, (Table
53), on page 62 allows the user to select how the output
pixel data stream in Continuous Frame Rolling Shutter
mode is encoded/formatted. In default mode, internally
generated signals SOF, VCLK, HCLK etc. drive the in-
tegration and readout of the pixel data frames but only
the valid pixel data is readout of the sensor. When a “1”
is written to bit 5 of the Pixel Data Stream Signal Control
Register, (Table 53), on page 62, it causes the output
pixel data to be encoded with SOF, VCLK and End Of
Frame signals. It accomplishes this by attaching the pix-
el data with certain predefined signal data. The Video
Encoded Signal Definitions, (Table 2), on page 10 de-
fines the data that represents the SOF, VCLK and End
of Frame signals.
B
Iris
microlenses
Figure 5. a) 15 degrees acceptance angle
b)Improvement in pixel sensitivity results from fo-
cusing incident light on photo sensitive portions of
the pixel by using microlenses
Signal
SOF
Description
Data
Start of Row read-
out (i.e.. Readout of
Row 1)
3FF3FF3FF3FF
VCLK
Start of Row read-
out of Rows 2+
3FF3FF000000
000000000000
3.0 Frame Capture Modes
There exists two frame capture modes:
End Of Readout of last Row
Frame complete
1) Continuous Frame Rolling Shutter mode (CFRS)
2) Single Frame Rolling Shutter mode (SFRS)
Table 2. Video Encoded Signal Definitions
The sensor can be put into either one of the aforemen-
tioned modes by writing either “1” or “0” to Bit 6 of Cap-
ture Mode Control Register, (Table 29), on page 48.
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
3.2 Single Frame Rolling Shutter capture mode
(SFRS)
mode” on page 14). This process continues until all
Rows have been integrated and readout. Once readout
of the entire frame is complete, the sensor awaits a new
SYNC signal before it starts integration and readout of
another frame.
This mode of capture refers to non-interlaced or se-
quential row by row scanning of the entire sensor in a
single pass for the purpose of capturing a single frame.
The start of Integration in this mode is triggered by the
SYNC signal. Similar to the CFRS capture mode, Read-
out of each row follows the Integration of that row.
Therefore the Integration of the rows are staggered out
as well due to the Readout of the sequential rows occur-
ring one after the other (see “Integration Time in SFRS
The waveforms depicting the SFRS output data stream
refer to Figure 8, on page 12
NOTE!! The faster the clock speed , the closer the se-
quential Integration start times are.
Frame Time = 1064 row times
Row Time = 1338 MCLKs
WOI = 1280 Columns x 1024 Rows
starting at row 16, column 8
SOF
VCLK
HCLK
BLANK
Figure 6. CFRS Default Frame Waveform
MCLK
SOF
Row Time = vcwd + 39
VCLK
HCLK
row 16
row 17
Pixel Array Values
ADC[9:0]
Valid Pixel Data
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Figure 7. CFRS Default Line Waveform
SYNC
T = (cintd + 1) * Row Time
SOF
VCLK
HCLK
Standard Frame
Timing (Figure 18)
Figure 8. SFRS Waveform
5.0 Active Window Sub-sampling Control
4.0 Active Window of Interest Control
The pixel data to be read out of the device is defined as
a ‘Window of Interest’ (WOI). The window of interest
can be defined anywhere on the pixel array at any size.
The user provides the upper-left pixel location and the
size in both row and column depth to define the WOI.
The WOI is defined using the WOI Pointer, WOI Depth,
and WOI Width registers, (Table 32 on page 51 through
Table 39 on page 53). Please refer to Figure 9 for a pic-
torial representation of the WOI within the active pixel
array.
The user can further control the size of the Active Win-
dow that is read out by sub sampling the already de-
fined Active Window Of Interest (See “Active Window of
Interest Control” on page 12). Subsampling enables the
pixel data to be readout in 1 pixel or 2 pixel increments
depending if you are subsampling in either mono-
chrome (1 pixel) or bayer pixel (2 pixel) space in four dif-
ferent sampling rates in each direction: full, 1/2, 1/4, or
1/8. The user controls the subsampling via the Sub-
sample Control Register, (Table 30), on page 49.
An example of Bayer space sub-sampling is shown in
Figure 10.
G R G R G R G R G R G R
B G B G B G B G B G B G
G R G R G R G R G R G R
B G B G B G B G B G B G
G R G R G R G R G R G R
B G B G B G B G B G B G
G R G R G R G R G R G R
0
1295
0
ACTIVE PIXEL ARRAY
WOI Pointer (wcp,wrp)
B G B G B G B G B G B G
Sub-sample Control Register =
G R G R G R G R G R G R
B G B G B G B G B G B G
x0010101b
=
Progressive Scan
Bayer Pattern
G R G R G
R G R G R G R
Read 1 Pattern, Skip 1 Pattern
in both directions
Window of Interest (WOI)
B G B G B G B G B G B G
Figure 10. Bayer Space Sub-sampling Example
WOI Column Width (wcw)
1047
Figure 9. WOI Definition
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ImageMOS
6.0 Frame Rate and Integration Time Control
6.2 Integration Time in CFRS mode:
In Continuous Frame Rolling Shutter capture mode, the
Integration time is defined as:
In addition to the minimum time required to readout the
selected resolution and WOI, the user has the ability to
control the frame rates while operating in either Contin-
uous Frame Rolling Shutter capture mode (CFRS) and
Single Frame Rolling Shutter (SFRS).
Integration Time=Tint = (cintd + 1) * Trow
where cintd is the number of virtual row times desired
for integration time. Therefore, the integration time in
CFRS mode can be adjusted in steps of virtual frame
row times.The user controls cintd via the Integration
Time MSB Register, (Table 40), on page 54 and Inte-
gration Time LSB Register, (Table 41), on page 55.
The frame rate can be defined as the time required to
readout an entire frame of data plus the required bound-
ary timing. This is done by varying the size of a number
of parameters identified in later sections, the main one
being the Virtual Frame surrounding the WOI.
Row Time (Trow) is the length of time required to read
one row of the virtual frame and can be defined as:
Please refer to Figure 11 for a pictorial description of the
Virtual Frame and its relationship to the WOI
Trow = (vcwd + shsd + shrd + 19) * MCLKperiod
where vcwd defines the number of columns in the virtu-
al frame and shsd and shrd are internal timing control
registers.
.
0
vcw[13:0]
0
The user controls vcwd via the CFRS Virtual Frame
Column Width registers (Table 44 on page 56 and Table
45 on page 56).
WOI Pointer (wcp,wrp)
The user controls the shsd and shrd values via the In-
ternal Timing Control Register 1 (shs time definition);
Table 50 and Table 51, “Internal Timing Control Regis-
ter 2 (shr time definition),” on page 60.
Window of Interest (WOI)
WOI Column Width (wcw)
Virtual Frame
vrd[13:0]
NOTE!! In Continuous Frame Rolling Shutter
(CFRS) capture mode, the Integration time upper
limit is bounded by the Frame time (see “CFRS
Frame Time/Rate:” on page 13).
Figure 11. Virtual Frame Definition
6.1 CFRS Frame Time/Rate:
i.e.. Tint < Tframe
In Continuous Frame Rolling Shutter capture mode, the
Frame time is completely defined by the size of the Vir-
tual Frame and can be expressed as:
Frame Time = Tframe = (vrdd + 1) * Trow
where vrdd defines the number of rows in the virtual
frame. The user controls vrdd via the Virtual Frame Row
Depth registers (Table 42 on page 55 and Table 43 on
page 55).
Frame Rate = (Frame time)-1
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ImageMOS
6.3 SFRS Frame Time/Rate:
In Single Frame Rolling Shutter capture mode the Frame
time is defined as:
NOTE!! vcwd and cintd are typically varied frame to
frame
Frame time = Tframe= Integration time+Readout time
Calculations:
Readout time is the amount of time to readout the data af-
ter integration of the row has been completed. It is defined
as follows:
Row Time =Trow = (vcwd + shsd + shrd + 19)
= (1290 + 10 + 10 + 19) / 13.5e6
= 98.44ms
Readout time = (vrdd + 1) * Trow
where vrdd defines the number of rows in the virtual
frame. The user controls vrdd via the CFRS Virtual Frame
Row Depth registers (Table 42 on page 55 and Table 43
on page 55).
Integration Time = (cintd + 1) * Trow
=(350+1)*98.44ms
Trow = (vcwd + shsd + shrd + 19) * MCLKperiod
=34.5ms
For Integration time see “Integration Time in SFRS
mode” on page 14
Readout time = (vrdd + 1) * Trow
= Frame time in CFRS mode
Frame Time in CFRS mode = (vrdd + 1) * Trow
Tframe =(1034 + 1)* 98.44
= 101.34 ms
6.3.1 Integration Time in SFRS mode
The Integration time in Single Frame Rolling Shutter cap-
ture mode is the same as in Rolling Shutter Capture
Mode. For further information, see “Integration Time in
CFRS mode:” on page 13. The only difference is that
in this mode the Integration time is NOT bounded by
the Frame time
Frame Time in SFRS mode =
Tframe = Integration time+Readout time
= 34.5ms + 101.34ms
= 135.84ms
6.4 Example of Frame time/rate and Integration Time
in CFRS and SFRS modes
The following illustrates how to determine the Frame time/
rate and Integration time in both capture modes:
Results
Assumptions:
1) Active Window of Interest = 1280 x 1024
i.e.. (wcwd)=1279
Tint
Tframe
Capture Mode
(wrdd)=1023
CFRS
SFRS
34.5ms
34.5ms
101.34 ms
135.84ms
2) Virtual Column Width (vcwd)= 1290
3) Virtual Row Depth (vrdd) = 1034
4) Sample & hold time (shsd) = 10
5) Sample & hold time (shrd) = 10
6) Integration Time (cintd)= 350
7) MCLK = 13.5 Mhz
NOTE!! CFRS Integration time = 34.5ms because:
Tint < Tframe = (vrdd + 1) * Trow
(see “Integration Time in CFRS mode:” on page 13)
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ImageMOS
7.0 Analog Signal Processing Chain Overview
begins a new frame. The MCM20027 uses optical black
(dark) pixels to aid in establishing this reference.
The MCM20027’s analog signal processing (ASP)
chain incorporates Correlated Double Sampling (CDS),
Frame Rate Clamp (FRC), two Digitally Programmable
Gain Amplifiers (DPGA), Offset Correction (DOVA), and
a 10-bit Analog to Digital Converter (ADC).
Cap
LRCA
0.1mf
CLRCA
LRCLMP
LRCLMP
V
cm
FRC
-
1X
To see a pictorial depiction of this chain refer to “Speci-
fications” on page 2
LRCLMP
BUF
+
Previous
Stage
+
V+
V-
Diff
V
cm
Amp
7.1 Correlated Double Sampling (CDS)
-
The uncertainty associated with the reset action of a ca-
pacitive node results in a reset noise which is equal to
kTC; C being the capacitance of the node, T the temper-
ature and k the Boltzmann constant. A common way of
eliminating this noise source in all image sensors is to
use Correlated Double Sampling. The output signal is
sampled twice, once for its reset (reference) level and
once for the actual video signal. These values are sam-
pled and held while a difference amplifier subtracts the
reference level from the signal output. Double sampling
of the signal eliminates correlated noise sources (see
.“Conceptual block diagram of CDS implementation.”
on page 15)
+
BUF
-
LRCLMP
1X
V
LRCLMP
LRCLMP
cm
CLRCB
Cap
0.1mf
LRCB
Figure 13. FRC Conceptual Block Diagram
On the MCM20027, dark pixel input signals should be
sampled for a minimum of 137ms to allow the two 0.1mF
capacitors at the CLRCA and CLRCB pins sufficient
time to charge for 10-bit accuracy. This guarantees that
the FRC’s “droop” will be maintained at <750 mV, thus
assuring the specified ADC 10-bit accuracy at +0.5
LSB. Therefore, at maximum operational frequency
(13.5 MHz), the imager would require a number of
frames to establish the dark pixel reference for subse-
quent active pixel processing. The dark pixel sample
period is automatically controlled internally and it is set
to skip the first 3 dark rows and then sample the next 2
dark rows. When “dark clamping” is active, each dark
pixel is processed and held to establish pixel reference
level at the CLRCA and CLRCB pins. During this period,
the FRC’s differential outputs (V+ and V- on the Diff
Amp, Figure 13) are clamped to Vcm. Together, these
actions help to eliminate the dark level offset, simulta-
neously establishing the desired zero code at the ADC
output.
CDSP1
S/H1
V+
AVIN
AMP
V-
CDSP2
S/H2
Figure 12. Conceptual block diagram of CDS
implementation.
7.2 Frame Rate Clamp (FRC)
The FRC (Figure 13) is designed to provide a feed for-
ward dark level subtract reference level measurement.
In the automatic FRC mode, the optical black level ref-
erence is re-established each time the image sensor
Care should be exercised in choosing the capacitors for
the CLRCA, B pins to reflect different frame rates.
The user can disable this function via the FRC Definition
Register; Table 54 and the Power Configuration Regis-
ter, (Table 19), on page 41 (Check this - should be re-
ferring o FRC clamp ON/OFF) which will allow the ASP
chain to drift in offset Per-Column Digital Offset Voltage
Adjust (DOVA), and controls the number of rows to
clamp on.
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ImageMOS
7.3 Programmable Per-Column Offset
sten, and halogen to cover a wide gamut of illumination
conditions.
A programmable per-column offset adjustment is avail-
able on the MCM20027. In order to reduce the risk and
have the ability to cover any mode of repetitive column
Fixed Pattern Noise (FPN), there exists 64 registers that
can be programmed with a DC offset that is added to all
columns. (Mod64 Column Offset registers; Table 27).
Each register is 6 bits, (5 bits plus 1 sign bit), providing+/
- 32 register values. The DC register values is added to
each of the 64 columns registers to provide the total off-
set value. This set of 64 values is then repeatedly ap-
plied to each bank of 64 in the sensor via the column
DOVA stage of the ASP chain.
Both DPGA designs use switched capacitors to mini-
mize accumulated offset and improve measurement ac-
curacy and dynamic range. The white balance gain
registers are 6-bits and can be programmed to allow
gain of 0.696x to 2.74x in varying steps.
The user programs the individual gain coefficients into
the MCM20027 via the Color Gain Registers (Table 8
through Table 11). For the default Bayer configuration
of the color filter array; Figure 4, the Color Gain Register
addresses are as follows: Reg (00h): green pixel of a
green-red row; Reg (01h): red pixel; Reg (02h): blue pix-
el; and Reg (03h): green pixel of a blue-green row.
The Column DOVA DC Register; Table 26, is used to
set the initial offset of the pixel output in a range that will
facilitate per-column offset data generation for varying
operational conditions. In most operational scenarios,
this register can be left in its default state of 00h. This is
a pre-image processing gain in comparison to the Glo-
bal DOVA Register (see section )which is a post image
processing chain gain (pre A2D gain)
The MCM20027 is presently available with only a Bayer
CFA, however, it is designed to support other novel col-
or configurations. This is accomplished via the Color
Tile Configuration Register, (Table 12), on page 37 and
the Color Tile Row Definition registers (Table 13
through Table 16).
7.4 Digitally Programmable Gain Amplifiers (DPGA)
for White Balance and Exposure Gain
6
Two DPGAs are available in the analog signal process-
ing chain. These are used to perform white balance and
exposure gain functions.
Green (0)
6
Red (1)
6
DPGA
6
0.7x-27x
Blue (2)
7.4.1 White Balance Control PGA
6
The sensor produces three primary color outputs, Red,
Green and Blue. These are monochrome signals that
represent luminance values in each of the primary col-
ors. When added in equal amounts they mix to make
neutral color. White balancing is a technique where the
gain coefficients of the green(0), red, blue, and green(3)
pixels comprising the Bayer pattern (see Figure 14.) are
set so as to equalize their outputs for neutral color
scenes. Since the sensitivity of the two green pixels in
the Bayer pattern may not be equal, an individual color
gain register is provided for each component of the Bay-
er pattern.
Green (3)
R(1)
G(0)
B(2) G(3)
Figure 14. Color Gain Register Selection
7.4.2 Exposure Global Gain PGA
The global gain DPGA provides a 0.67x to 7.5x (approx)
programmable gain adjustment for dynamic range. The
gain of the amplifier is linearly programmable using a six
bit gain coefficients on 2 6-bit PGA gain registers in
varying steps depending on which exposure gain mode
Once all color gain registers are loaded with the desired
gain coefficients ,according to which gain mode (see
“Gain Modes” on page 17) has been set, white balance
is then achieved in real time and in analog space. These
gain coefficient values are then selected and applied to
the pixel output via a high speed path, the delay of
which is much shorter than the pixel clock rate. Real
time updates can be performed to any of the gain regis-
ters. However, latency associated with the I2C interface
should be taken into consideration before changes oc-
cur. In most applications, users will be able to assign
predefined settings such as daylight, fluorescent, tung-
it is set at i.e. RAW or LIN or LIN2
(PGA Gain Mode,
(Table 25), on page 45). The user programs the global
gain via the Exposure PGA Global Gain Register A, (Ta-
ble 23), on page 44.
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ImageMOS
7.4.3 Gain Modes
There are two different Gain modes for White Balance
and there are three different Gain modes for the Expo-
sure gain refer to White Balance Gain modes and Gain
Formulas; Table 3 and Exposure Gain modes and Gain
Formulas; Table 4 for more info.
There exists different gain modes that are available
when the sensor is performing White Balance and Ex-
posure gain. The Gain mode utilized for White balance
and Exposure gain can be selected by the user writing
different values to the register described in Table 25,
“PGA Gain Mode,” on page 45.
Register
No
Gain
Modes
Gain
Steps
Gain
Range
Register Name
Variable
Gain Formula
00h
01h
02h
03h
DPGA Color 1 Gain
Register; Table 8
cg1
RAW
0-32
33-63
0-47
0.6956 + (0.02174* cg1d)
1.391+ (0.0434* (cg1d-32)
0.6956 +(0.0434 x cg1d)
0.6956 + (0.02174* cg2d)
1.391+ (0.0434* (cg2d-32)
0.6956 +(0.0434 x cg2d)
0.6956 + (0.02174* cg3d)
1.391+ (0.0434* (cg3d-32)
0.6956 +(0.0434 x cg3d)
0.6956 + (0.02174* cg4d)
1.391+ (0.0434* (cg4d-32)
0.6956 +(0.0434 x cg4d)
0.69-1.39
1.39-2.74
0.69-2.74
0.69-1.39
1.39-2.74
0.69-2.74
0.69-1.39
1.39-2.74
0.69-2.74
0.69-1.39
1.39-2.74
0.69-2.74
LINEAR
RAW
DPGA Color 2 Gain
Register; Table 9
cg2
cg3
cg4
0-32
33-63
0-47
LINEAR
RAW
DPGA Color 3 Gain
Register; Table 10
0-32
33-63
0-47
LINEAR
RAW
DPGA Color 4 Gain
Register; Table 11
0-32
33-63
0-47
LINEAR
Table 3. White Balance Gain modes and Gain Formulas
Green-RedPixel
Red Pixel Data
Data
DPGA Color 1 Gain
DPGA Color 2 Gain
Register
Register
Blue Pixel Data
Green-Blue
Pixel Data
DPGA Color 3 Gain
Register
DPGA Color 4 Gain
Register
NOTE!! The Diagrams above illustrates how the Color Gain Registers apply the gain onto each individual
color pixel data:
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Register
Gain
Modes
Gain
Steps
Gain
Register Name
Variable
Gain Formula
No
Range
0.69-1.39
1.39-2.74
0.69-2.74
0.69-3.60
0.69-1.39
1.39-2.74
0.69-2.74
0.69-3.60
10h
Exposure PGA Global
Gain Register A; Table
23
gg1
RAW
0-32
33-63
0-47
0-67
0-32
33-63
0-47
0-67
0.6956 + (0.02174* gg1d)
1.391+ (0.0434* (gg1d-32)
0.6956 +(0.0434 x gg1d)
0.6956 + (0.0434 * gg2d)
0.6956 + (0.02174* cg2d)
1.391+ (0.0434* (cg2d-32)
0.6956 +(0.0434 x cg2d)
0.6956 + (0.0434 * gg2d)
LINEAR
LINEAR 2
RAW
21h
Exposure PGA Global
Gain Register B; Table
24
gg2
LINEAR
LINEAR 2
Table 4. Exposure Gain modes and Gain Formulas
The Diagram below illustrates how the Exposure Gain Registers apply the gain onto the pixel data:
Pixel Data
Exposure PGA Gain
Register A
Exposure PGA Gain
Register B
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ImageMOS
7.5 Global Digital Offset Voltage Adjust (DOVA)
A programmable global offset adjustment is available
on the MCM20027. A user defined offset value is loaded
via a 6-bit signed magnitude programming code via the
Global DOVA Register, (Table 28), on page 47.
7.6 Analog to Digital Converter (ADC)
The ADC is a fully differential, low power circuit. A pipe-
lined, Redundant Signed Digit (RSD) algorithmic tech-
nique is used to yield an ADC with superior
characteristics for imaging applications.
Offset correction allows fine-tuning of the signal to re-
move any additional residual error which may have ac-
cumulated in the analog signal path. This function is
performed directly before analog to digital conversion
and introduces a fixed gain of 2.0X. This feature is use-
ful in applications that need to insert a desired offset to
adjust for a known system noise floor relative to AVSS
and offsets of amplifiers in the analog chain.
Integral Noise Linearity (INL) and Differential Noise Lin-
earity (DNL) performance is specified at +1.0 and +0.5,
respectively, with no missing codes. The input voltage
resolution is 2.44 mV with a full-scale 2.5 Vpp input (2.5
Vpp/210). The input dynamic range of the ADC is pro-
grammed via a Programmable Voltage Reference Gen-
erator. The positive reference voltage (VREFP) and
negative reference voltages (VREFM) can be pro-
grammed from 2.5V to 1.25V and 0V to 1.25V respec-
tively in steps of 5mV via the Reference Voltage
Registers (Table 17 and Table 18). This feature is used
independently or in conjunction with the DPGAs to max-
imize the system dynamic range based on incident illu-
mination. The default input range for the ADC is 1.9V for
VREFP and 0.6V for VREFM hence allowing a 10 bit
digitization of a 1.3V peak to peak signal.
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ImageMOS
8.0 Sensor External Controls (Additional
Operational Conditions)
8.3 Tristate Mode
The sensors HCLK, SOF, VCLK, SYNC and STROBE
output signals as well as the pixel output data can be
tristated via the Tristate Control Register, (Table 21), on
page 42.
The MCM20027 includes initialization, standby modes,
and external reference voltage outputs to afford the
user additional applications flexibility.
8.4 References CVREFP, CVREFM
8.1 Initialization
The MCM20027 contains all internally generated refer-
ences and biases on-chip for system simplification. An
internally generated differential bandgap regulator de-
rives all the ADC and other analog signal processing re-
quired references. The user should connect 0.1mF
capacitors to the CVREFP and CVREFM pins (#15 and
#14 respectively) to accurately hold the biases.
The INIT input pin (#42) controls reinitialization of the
MCM20027. This serves to assure controlled chip and
system startup. Control is asserted via a logic high in-
put. (i.e.. Asserting a Logic high “1” initializes all the
Registers, while asserting a Logic low “0” returns the
sensor to normal operation). This state must be held a
minimum of 1 ms and a 1 ms “wait period” should be al-
lowed before chip processing to ensure that the start-up
routines within the MCM20027 have run to completion,
and to guarantee that all holding and bypass capacitors,
etc. have achieved their required steady state values.
8.5 Common Mode References: VAG, VAGREF and
VAGRETURN
Tasks which are accomplished during startup include:
reset of the utility programming registers and initializa-
tion to their default values (please refer to previous sec-
tion for settings), reset of all internal counters and
latches, and setup of the analog signal processing
chain.
The MCM20027 holds the Common Mode Reference
Voltages on the chip to a stable value. In order to
achieve this stable value, the VAG (pin #16),
VAGREF(pin #18 ) and VAGRETURN (pin #17) have to
be connected to two 0.1mF capacitors in the manner de-
scribed in the diagram below:
Another method of saving power consumption is to ap-
plying an active high signal to the INIT pin (#42) but
Note - Doing this will also cause initialization of the chip
.
VAG
(pin #16)
0.1mF
8.2 Standby Mode
The standby mode option is implemented to allow the
user to reduce system power consumption during peri-
ods which do not require operation of the MCM20027.
This feature allows the user to extend battery life in low
power applications.
VAGRETURN
(pin #17)
0.1mF
VAGREF
(pin #18)
By utilizing this mode, the user may reduce dynamic
power consumption from 250mW RMS nominal
@13.5MHz to <100 uW in the standby mode.
The standby mode is activated by writing a “1” to bit 0 of
“Power Configuration Register” on page 41. Writing a
“0” restores normal operation.
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
8.6 Internal Bias Current Control
The ASP chain has internally generated bias currents
that result in an operating power consumption of nearly
400mW approx. (Accurate value will be given upon sen-
sor testing). By attaching a resistor between pin 20, EX-
TRES; and Pin19, the user can reduce the power
consumption of the device. This feature is enabled by
writing a 1b to bit res of the Power Configuration Regis-
ter. Additional power savings can be achieved at lower
clock rates. Note - The External Bias resistor Input pin
(EXTRESP - pin #20) should be connected to the
ETRESRTN (pin#19) in the manner described in the di-
agram below.
EXTRESP
(pin #20)
Resistor
EXTRESRTN
(pin #19)
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
9.0 Sensor Output/Input Signals
9.3 Horizontal Data SYNC (VCLK)
This signal triggers the Readout of the sequential rows
of the frame. This signal is an Output and can be read
via Pin # 44 of the sensor (see Figure 20, on page 67).
The VCLK signal delay in relation to SOF, as well as its
length can be set by the user via VCLK Delay Register,
(Table 47), on page 57 and SOF & VCLK Signal Length
Control Register, (Table 48), on page 57. For timing di-
agrams depicting the use of the VCLK signal refer toFig-
ure 15, on page 22, Figure 6, on page 11, Figure 7, on
page 12 ,Figure 8, on page 12 and Figure 16, on
page 24.
9.1 Start Of Data Capture (SYNC)
This signal is utilized by the sensor to indicate the start
of integration (data capture) in Single Frame Rolling
Shutter capture mode (SFRS). For more info refer to
Figure 15, on page 22, Figure 8, on page 12 and Figure
16, on page 24. This signal can be generated internally
by the sensor or be driven via Pin # 46 of the sensor
(see Figure 20, on page 67). To set whether the signal
is generated internally or externally, as well as other
settings to this signal, refer to Sync and Strobe Control
register, (Table 31), on page 50.
9.4 Data Valid (HCLK)
9.2 Start Of Row Readout (SOF)
This signal triggers/indicates a single active pixel data
has been readout (eg Column 5 of Row 10 data has
been read out). This signal is an Output and can be
read via Pin # 45 of the sensor (see Figure 20, on
page 67). The HCLK signal delay can be set by the user
via HCLK Delay Register, (Table 52), on page 60. For
timing diagrams depicting the use of the HCLK signal
refer to Figure 15, on page 22, Figure 6, on page 11,
Figure 7, on page 12 ,and Figure 8, on page 12.
This signal triggers/indicates the start of Row Readout
of the frame. This signal is an Output and can be read
via Pin # 48 of the sensor (see Figure 20, on page 67).
The SOF signal delay as well as its length can be set by
the user via SOF Delay Register, (Table 46), on page
57 and SOF & VCLK Signal Length Control Register,
(Table 48), on page 57. For timing diagrams depicting
the use of the SOF signal refer to Figure 15, on
page 22, Figure 6, on page 11, Figure 7, on page 12
,Figure 8, on page 12 and Figure 16, on page 24.
MCLK
thsync
tsusync
SYNC
tdsof
SOF
tdvclk
VCLK
tdfhclk
tdrhclk
HCLK
tdadc
ADC[9:0]
Figure 15. Pixel Data Bus Iinterface Timing Specifications (see Table Below)
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
PIXEL DATA BUS INTERFACE TIMING SPECIFICATIONS (see Figure 15)
Symbol
Characteristic
Min
Typ
Max
Unit
f
MCLK maximum frequency
SYNC hold time w.r.t MCLK
1
11.5
13.5
MHz
max
t
3.5
3.0
8
-
-
9
ns
ns
ns
ns
ns
ns
ns
ns
hsync
t
SYNC setup time w.r.t MCLK
8.5
susync
t
MCLK to SOF delay time
13
13.5
13
5
21.5
22
dsof
t
MCLK to VCLK delay time
8.5
7.5
3
dvclk
t
Rising edge of MCLK to rising edge of HCLK delay time
Falling edge of MCLK to falling edge of HCLK delay time
MCLK to ADC[9:0] delay time
22
drhclk
t
10.5
21.5
21.5
dfhclk
t
8
13
13
dadc
t
MCLK to STROBE delay time
8
strobe
Revision 8.0 - 28 November 2001 :
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
9.5 Strobe Signal
last Row begins to Integrate. (see 3“Frame Rate and In-
tegration Time Control” on page 13). The start of the
strobe signal can also be set by the user. In default
mode, when the strobe is activated, the signal fires 2
Row Periods (Trow) before the first Row begins to Read-
out and last for a length of 1 Trow .A sample timing dia-
gram for the Strobe signal can be seen in Figure 16, on
page 24:
The Strobe signal is a output pin on the MCM20027
sensor that can be used to activate ‘Flash/Strobe illumi-
nation modules”. It can be activated by writing a “1” to
bit 3 of “Sync and Strobe Control register” on page 50
while in SFRS mode. When activated, the Strobe signal
goes high (Active) when all Rows are Integrating simul-
taneously, and ends one Row period (Trow) before the
T
frame
SYNC
1st ROW OF
INTEGRATION
T
int
2nd ROW OF
INTEGRATION
T
int
3rd ROW OF
INTEGRATION
T
int
LAST ROW OF
INTEGRATION
T
int
SOF
VCLK
STROBE
Trow Trow
Trow TrowTrow Trow Trow
Trow
T
strobe2
Tstrobe1
Figure 16. Strobe Timing Diagram in SFRS capture mode
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
To ensure that Strobe signal fires, the integration time
must be large enough to ensure that all rows are inte-
Variables:
Integration Time (cintmin) is the main variable used to control
the time of the Strobe signals.
grating simulanteously for at least 2 Row periods (Trow
)
(see “Frame Rate and Integration Time Control” on
page 13)
Tintmin=(cintmin+1)*Trow
where Trow = (vcwd + shsd + shrd + 19)
Calculations:
To accomplish this - ensure that the Integration time
(cintd) greater than 2 Row periods (Trow) larger than
the active Window of Interest Row depth.
Row Time =Trow = (vcwd + shsd + shrd + 19)
= (1290 + 10 + 10 + 19) / 13.5e6
= 98.44ms
Min. Integration time =Tintmin=(cintmin+1)*Trow
cintmin=wrdd+x where x > 2
Tintmin=(cintmin+1)*Trow
cintmin=wrdd+x where x > 2
where wrdd is the Window Of Interest Row depth.
Tstrobe1= Trow
Tstrobe2= Tintmin- (wrdd+1)*Trow
Let cintmin= wrdd+x where x > 2
= 1023 + 4 = 1029
Therefore,
where x=4
Tintmin= 101.39
Tstrobe1= 98.44ms
Tstrobe2= Tintmin- (wrdd+2)*Trow
= 3 * Trow
EXAMPLE: Below you will find an example of how to
ensure that the strobe signal will fire and to determine
the length of the STROBE signal in default mode:
(Refer to Figure 16, on page 24 for timing analysis)
= 295us
Goal (For example purpose):
Strobe Signal that lasts for at least 250us, which is the
length of a typical strobe/flash event.
Results:
Signal
Trow
Value
98us
Assumptions:
1) Active Window of Interest = 1280 x 1024
ie. (wcwd)=1279
Tint
101ms
98us
Tstrobe1
Tstrobe2
Tframe
(wrdd)=1023
295us
202ms
2) Virtual Column Width (vcwd)= 1290
3) Virtual Row Depth (vrdd) = 1034
4) Sample & hold time (shsd) = 10
5) Sample & hold time (shrd) = 10
6) MCLK = 13 Mhz
NOTE!! Refer to Figure 16, on page 24 for timing
analysis
Revision 8.0 - 28 November 2001 :
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
10.0 I2C Serial Interface
The first byte of a data transfer, immediately after the
START signal, is the slave address transmitted by the
master. This is a 7-bit calling address followed by a R/
W bit. The seven-bit address for the MCM20027, start-
ing with the MSB (AD7) is 0110011b. The transmitted
calling address on the SDATA line may only be
changed while SCLK is low as shown in Figure 17. The
data on the SDATA line is valid on the High to Low sig-
nal transition on the SCLK line. The R/W bit following
the 7-bit tells the slave the desired direction of data
transfer:
The I2C is an industry standard which is also compatible
with the Motorola bus (called M-Bus) that is available on
many microprocessor products. The I2C contains a se-
rial two-wire half-duplex interface that features bidirec-
tional operation, master or slave modes, and multi-
master environment support. The clock frequency on
the system is governed by the slowest device on the
board. The SDATA and SCLK are the bidirectional data
and clock pins, respectively. These pins are open drain
and will require a pull-up resistor to VDD of 1.5 kW to 10
kW (see page 66).
•
•
1 = Read transfer, the slave transitions to a slave
transmitter and sends the data to the master
0 = Write transfer, the master transmits data to the
slave
The I2C is used to write the required user system data
into the Program Control Registers in the MCM20027.
The I2C bus can also read the data in the Program Con-
trol Register for verification or test considerations. The
MCM20027 is a slave only device that supports a max-
imum clock rate (SCLK) of 100 kHz while reading or
10.4 Acknowledgment
Only the slave with a calling address that matches the
one transmitted by the master will respond by sending
back an acknowledge bit. This is done by pulling the
SDATA line low at the 9th clock (see Figure 17). If a
transmitted slave address is acknowledged, successful
slave addressing is said to have been achieved. No two
slaves in the system may have the same address. The
MCM20027 is configured to be a slave only.
2
writing only one register address per I C start/stop cy-
cle. The following sections will be limited to the methods
for writing and reading data into the MCM20027 regis-
ter.
For a complete reference to I2C, see “The I2C Bus from
Theory to Practice” by Dominique Paret and Carll-
Fenger, published by John Wiley & Sons, ISBN
0471962686.
10.5 Data Transfer
Once successful slave addressing is achieved, data
transfer can proceed between the master and the se-
lected slave in a direction specified by the R/W bit sent
by the calling master. Note that for the first byte after a
start signal (in Figure 17 and Figure 18), the R/W bit is
always a “0” designating a write transfer. This is re-
quired since the next data transfer will contain the reg-
ister address to be read or written.
2
10.1 MCM20027 I C Bus Protocol
2
The MCM20027 uses the I C bus to write or read one
2
register byte per start/stop I C cycle as shown in Figure
17 and Figure 18. These figures will be used to describe
2
the various parts of the I C protocol communications as
it applies to the MCM20027.
2
MCM20027 I C bus communication is basically com-
All transfers that come after a calling address cycle are
referred to as data transfers, even if they carry sub-ad-
dress information for the slave device.
posed of following parts: START signal, MCM20027
slave address (0110011b) transmission followed by a R/
W bit, an acknowledgment signal from the slave, 8 bit
data transfer followed by another acknowledgment sig-
nal, STOP signal, Repeated START signal, and clock
synchronization.
Each data byte is 8 bits long. Data may be changed only
while SCLK is low and must be held stable while SCLK
is high as shown in Figure 17. There is one clock pulse
on SCLK for each data bit, the MSB being transferred
first.
10.2 START Signal
When the bus is free, i.e. no master device is engaging
the bus (both SCLK and SDATA lines are at logical “1”),
a master may initiate communication by sending a
START signal. As shown in Figure 17, a START signal
is defined as a high-to-low transition of SDATA while
SCLK is high. This signal denotes the beginning of a
new data transfer and wakes up all the slaves on the
bus.
Each data byte has to be followed by an acknowledge
bit, which is signalled from the receiving device by pull-
ing the SDATA low at the ninth clock. So one complete
data byte transfer needs nine clock pulses. If the slave
receiver does not acknowledge the master, the SDATA
line must be left high by the slave. The master can then
generate a stop signal to abort the data transfer or a
start signal (repeated start) to commence a new calling.
10.3 Slave Address Transmission
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
If the master receiver does not acknowledge the slave
transmitter after a byte transmission, it means 'end of
data' to the slave, so the slave releases the SDATA line
for the master to generate STOP or START signal.
10.7 Repeated START Signal
A Repeated START signal is a START signal generated
without first generating a STOP signal to terminate the
communication. This is used by the master to commu-
nicate with another slave or with the same slave in a dif-
ferent mode (transmit/receive mode) without releasing
the bus.
10.6 Stop Signal
The master can terminate the communication by gener-
ating a STOP signal to free the bus. However, the mas-
ter may generate a START signal followed by a calling
command without generating a STOP signal first. This
is called a Repeated START. A STOP signal is defined
as a low-to-high transition of SDATA while SCLK is at
logical “1” (see Figure 17).
As shown in Figure 18, a Repeated START signal is be-
ing used during the read cycle and to redirect the data
transfer from a write cycle (master transmits the register
address to the slave) to a read cycle (slave transmits
the data from the designated register to the slave).
The master can generate a STOP even if the slave has
generated an acknowledge bit at which point the slave
must release the bus.
MSB
1
LSB
7
MSB
LSB
8
SCLK
2
3
4
5
6
8
9
1
2
3
4
5
6
7
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1
“0” “1” “1” “0” “0” “1” “1”
D7 D6 D5 D4 D3 D2 D1 D0
MCM20027 Register Address
SDATA
2
MCM20027 I C Bus Address
Ack
Bit
from
Start
Signal
Ack
Bit
from
Write
MCM20027
MCM20027
MSB
LSB
1
2
3
4
5
6
7
8
9
SCLK
SDATA
D7 D6 D5 D4 D3 D2 D1 D0
Data to write MCM20027 Register
Ack
Bit
Stop
Signal
from
MCM20027
2
Figure 17. WRITE Cycle using I C Bus
2
10.8 I C Bus Clocking and Synchronization
Open drain outputs are used on the SCLK outputs of all
master and slave devices so that the clock can be syn-
chronized and stretched using wire-AND logic. This
means that the slowest device will keep the bus from
going faster than it is capable of receiving or transmit-
ting data.
signal Low period is stretched. Therefore, synchronized
clocking occurs since the SCLK is held low by the de-
vice with the longest Low period. Also, this method can
be used by the slaves to slow down the bit rate of a
transfer. The master controls the length of time that the
SCLK line is in the High state. The data on the SDATline
is valid when the master switches the SCLK line from a
High to a Low.
After the master has driven SCLK from High to Low, all
the slaves drive SCLK Low for the required period that
is needed by each slave device and then releases the
SCLK bus. If the slave SCLK Low period is greater than
the master SCLK Low period, the resulting SCLK bus
Slave devices may hold the SCLK low after completion
of one byte transfer (9 bits). In such case, it halts the bus
clock and forces the master clock into wait states until
the slave releases the SCLK line.
Revision 8.0 - 28 November 2001 :
MCM20027
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
10.9 Register Write
ously received from the master; MCM20027 transi-
tions to slave-receiver
Master does not send an acknowledgment (NAK)
Master transmits STOP to end the read cycle
Writing the MCM20027 registers is accomplished with
•
•
2
the following I C transactions (see Figure 17):
•
•
Master transmits a START
Master transmits the MCM20027 Slave Calling Ad-
dress with “WRITE” indicated (BYTE=66h, 102d,
01100110b)
•
MCM20027 slave sends acknowledgment by forc-
ing the SDATA Low during the 9th clock, if the Call-
ing Address was received
•
•
Master transmits the MCM20027 Register Address
MCM20027 slave sends acknowledgment by forc-
ing the SDATA Low during the 9th clock after re-
ceiving the Register Address
•
•
Master transmits the data to be written into the reg-
ister at the previously received Register Address
MCM20027 slave sends acknowledgment by forc-
ing the SDATA Low during the 9th clock after re-
ceiving the data to be written into the Register
Address
•
Master transmits STOP to end the write cycle
10.10 Register Read
Reading the MCM20027 registers is accomplished with
2
the following I C transactions (see Figure 18):
•
•
Master transmits a START
Master transmits the MCM20027 Slave Calling Ad-
dress with “WRITE” indicated (BYTE=66h, 102d,
01100110b)
•
MCM20027 slave sends acknowledgment by forc-
ing the SData Low during the 9th clock, if the Calling
Address was received
•
•
Master transmits the MCM20027 Register Address
MCM20027 slave sends acknowledgment by forc-
ing the SData Low during the 9th clock after receiv-
ing the Register Address
•
•
Master transmits a Repeated START
Master transmits the MCM20027 Slave Calling Ad-
dress with “READ” indicated (BYTE = 67h, 103d,
01100111b)
•
MCM20027 slave sends acknowledgment by forc-
ing the SDATA Low during the 9th clock, if the Call-
ing Address was received
•
•
At this point, the MCM20027 transitions from a
“Slave-Receiver” to a “Slave-Transmitter”
MCM20027 sends the SCLK and the Register Data
contained in the Register Address that was previ-
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MCM20027
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
SCLK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
MSB
LSB
MSB
LSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1
“0” “1” “1” “0” “0” “1” “1”
XX
D7 D6 D5 D4 D3 D2 D1 D0
MCM20027 Register Address
SDATA
2
MCM20027 I C Bus Address
Ack
Start
Signal
Ack
Bit
from
Write
Repeated
Start
Signal
Bit
from
MCM20027
MCM20014
SCLK
At this point the MCM20027
transitions from a “SLAVE-receiver”
to a “SLAVE- transmitter”
1
2
3
4
5
6
7
8
9
MSB
LSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1
“0” “1” “1” “0” “0” “1” “1”
SDATA
2
MCM20027 I C Bus Address
Read Ack Bit fromMCM20027
SCLK
1
2
3
4
5
6
7
8
9
The MCM20027
transitions from a “SLAVE-transmitter”
LSB
MSB
to a “SLAVE-receiver” after the
register data is sent
SDATA D7 D6 D5 D4 D3 D2 D1 D0
Data from MCM20027 Register
No Ack. Bit from MASTER terminates the transfer
Stop
Signal from MASTER
Single Byte Transfer to Master
2
Figure 18. READ Cycle using I C Bus
Revision 8.0 - 28 November 2001 :
MCM20027
MOTOROLA
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
I2C SERIAL INTERFACE6 TIMING SPECIFICATIONS (see Figure 19)
Symbol
Characteristic
Min
Max
Unit
f
SCLK maximum frequency
50
400
KHz
max
7
M1
M2
M3
M4
Start condition SCLK hold time
4
8
-
-
-
T
T
T
MCLK
T
SCLK low period
MCLK
8
SCLK/SDATA rise time [from V = (0.2)*VDD to V = (.8)*VDD]
.3
-
IL
IH
ms
7
SDATA hold time
4
MCLK
8
M5
M6
M7
M8
M9
SCLK/SDATA fall time (from Vh = 2.4V to Vl = 0.5V)
SCLK high period
-
.3
-
ms
T
4
4
MCLK
7
SDATA setup time
-
MCLK
T
Start / Repeated Start condition SCLK setup time
Stop condition SCLK setup time
4
4
-
-
MCLK
T
MCLK
C
Capacitive for each I/O pin
-
10
200
10
pF
I
Cbus
Rp
Capacitive bus load for SCLK and SDATA
Pull-up Resistor on SCLK and SDATA
-
pF
9
1.5
kW
6
7
8
9
2
I C is a proprietary Phillips interface bus
The unit T is the period of the input master clock; The frequency of MCLK is assumed 13.5 MHz
MCLK
The capacitive load is 200 pF
A pull-up resistor to VDD is required on each of the SCLK and SDATA lines; for a maximum bus capacitive load of 200 pf, the minimum
value of Rp should be selected in order to meet specifications
M2
M6
M5
M3
VIH
VIL
SCLK
M1
M4
M7
M8
M9
M8
SDATA
Figure 19. I2C SERIAL INTERFACE6 TIMING SPECIFICATIONS
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
11.0 Suggested Software Register Programming
Reference
NOTE!! These are only suggested value changes. De-
pending on the application, there might exist more or
less registers whose default values require modifica-
tions.
There are number of registers whose default values we
have been changed to make the sensor operational with
a Digital Still Camera. The registers, there suggested
new values (changes) and reason for there change are
detailed in Suggested Register Default Value Changes,
(Table 5), on page 31
Register
No
Default
Values
New
Register Name
Comment
Values
Power Configuration
Register; Table 19
Switching External Resistor On for Lower
active power consumption
0Ch
00h
08h
White Balance switched from Raw to Linear
gain mode .
Exposure Gain switched from Raw to Linear
2 gain mode
22h
00h
06h
PGA Gain Mode; Table 25
23h
42h
56h
Global DOVA Register;
Table 28
00h
02h
0Eh
27h
00h
09h
Negative Offset for Analog Signal Process-
ing chain
Sync and Strobe Control
register; Table 31
Necessary for switch to SFRS capture mode
in addition to Capture Mode Control Register
SOF & VCLK Signal
Length Control Register;
Table 48
new SOF = 64 MCLKs
new VCLK = 8 MCLKs
5Fh
60h
Internal Timing Control
Register 1 (shs time defi-
nition); Table 50
0Ah
0Ah
00h
00h
new shs=64 MCLKs
increase sample time to sweep all available
charge from pixel
Internal Timing Control
Register 2 (shr time defini-
tion); Table 51
new shr=64 MCLKs
increased reset timesweep all available
charge from pixel
Table 5. Suggested Register Default Value Changes
Revision 8.0 - 28 November 2001 :
MCM20027
MOTOROLA
31
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
12.0 MCM20027 Utility Programming Registers
Address Range
00h - 2Fh
Block Name
Analog Register Interface
Sensor Interface
12.1 Register Reference Map
The I2C addressing is broken up into groups of 16 and
assigned to a specific digital block. The designated
block is responsible for driving the internal control bus,
when the assigned range of addresses are present on
the internal address bus. The grouping designation and
assigned range are listed in Table 6. Each block con-
tains registers which are loaded and read by the digital
and analog blocks to provide configuration control via
the I2C serial interface.
40h - 7Fh
80h - BFh
Column Offset coeff.
Table 6. I2C Address Range Assignments
face. If the register is shadowed, the sensor interface
will only be updated upon frame boundaries, thereby
eliminating intraframe artifacts resulting from register
changes.
Table 7 contains all the I2C address assignments. The
table includes a column indicating whether the register
values are shadowed with respect to the sensor inter-
Hex
Defa
ult
Ref.
Table
Shadow
ed?
Register Function
Address
00h
DPGA Color 1 Gain Register (Green of Green-Red
Row)
0Eh
Table 8, page 35
Yes
01h
02h
03h
DPGA Color 2 Gain Register (Red)
DPGA Color 3 Gain Register (Blue)
0Eh
0Eh
0Eh
Table 9, page 35
Table 10, page 36
Table 11, page 36
Yes
Yes
Yes
DPGA Color 4 Gain Register (Green of Blue-Green
Row)
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Unused
Color Tile Configuration Register
Color Tile Row 1 Definition Register
Color Tile Row 2 Definition Register
Color Tile Row 3 Definition Register
Color Tile Row 4 Definition Register
Negative Voltage Reference Code Register
Positive Voltage Reference Code Register
Power Configuration Register
05h
44h
EEh
00h
00h
76h
80h
00h
FUO
00h
50h
Table 12, page 37
Table 13, page 38
Table 14, page 38
Table 15, page 39
Table 16, page 39
Table 17, page 40
Table 18, page 40
Table 19, page 41
FUO
No
No
No
No
No
No
No
No
FUO
No
No
Factory Use Only
Reset Control Register
Table 20, page 42
Device Identification (read only)
Table 7. I2C Address Assignments
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Hex
Defa
ult
Ref.
Table
Shadow
ed?
Register Function
Address
10h
11h
12h
13h
Exposure PGA Global Gain Register A
Unused
0Eh
Table 23, page 44
Yes
Tristate Control Register; Table 21
Programable Bias Generator Control register
03h
00h
Table 21, page 42
Table 22, page 43
14-1F
Unused
20h
Column DOVA DC Register
00h
0Eh
00h
00h
Table 26, page 46
Table 24, page 45
Table 25, page 45
Table 28, page 47
No
Yes
No
21h
22h
Exposure PGA Global Gain Register B
PGA Gain Mode
23h
Global DOVA Register
No
24 - 3Fh
40h
Unused
Capture Mode Control Register
Sub-sample Control Register
Sync and Strobe Control register
Unused
2Ah
10h
02h
Table 29, page 48
Table 30, page 49
Table 31, page 50
Yes
Yes
Yes
41h
42h
43h - 44h
45h
WOI Row Pointer MSB Register
WOI Row Pointer LSB Register
WOI Row Depth MSB Register
WOI Row Depth LSB Register
WOI Column Pointer MSB Register
WOI Column Pointer LSB Register
WOI Column Width MSB Register
WOI Column Width LSB Register
Factory Use Only
00h
10h
03h
FFh
00h
08h
04h
FFh
Table 32, page 51
Table 33, page 51
Table 34, page 51
Table 35, page 52
Table 36, page 52
Table 37, page 53
Table 38, page 53
Table 39, page 53
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
Integration Time MSB Register
Integration Time LSB Register
Virtual Frame Row Depth MSB Register
Virtual Frame Row Depth LSB Register
04h
FFh
04h
27h
Table 40, page 54
Table 41, page 55
Table 42, page 55
Table 43, page 55
Yes
Yes
Yes
Yes
4Fh
50h
51h
Table 7. I2C Address Assignments (Continued)
Revision 8.0 - 28 November 2001 :
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MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Hex
Defa
ult
Ref.
Table
Shadow
ed?
Register Function
Address
52h
53h
Virtual Frame Column Width MSB Register
Virtual Frame Column Width LSB Register
SOF Delay Register
05h
13h
4Ch
02h
0Eh
04h
Table 44, page 56
Table 45, page 56
Table 46, page 57
Table 47, page 57
Table 47, page 57
Table 49, page 58
Yes
Yes
No
54h
55h
VCLK Delay Register
No
56h
SOF & VCLK Signal Length Control Register
Greycode and Readout Control Register
Unused
No
57h
No
58h - 5Eh
5Fh
Internal Timing Control Register 1 (shs time definition)
Internal Timing Control Register 2 (shr time definition)
Factory Use Only
0Ah
0Ah
Table 50, page 59
Table 51, page 60
Yes
Yes
60h
61h-63h
64h
HCLK Delay Register
5Ch
00h
Table 52, page 60
Table 53, page 62
Yes
65h
Pixel Data Stream Signal Control Register
Factory Use Only
66h
67h
FRC Definition Register
24h
00h
Table 54, page 63
Table 27, page 47
68h
Factory Use Only
69h - 7Fh
80-BF
C0h -FF h
Unused
Mod64 Column Offset registers
Unused
Table 7. I2C Address Assignments (Continued)
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ImageMOS
13.0 Detailed Register Block Assignments
The four Color Gain Registers, Color Tile Configuration
Register, and four Color Tile Row definitions define how
white balance is achieved on the device. Six-bit gain
codes can be selected for four separate colors: Table 8,
Table 9, Table 10, and Table 11. Gain for each individ-
ual color register is programmable given the gain func-
tion defined in the table. The gain function used
depends on what Gain mode (White balance gain
mode) the sensor is set (PGA Gain Mode; Table
25).The user programs these registers to account for
changing light conditions to assure a white balanced
output. The default value in each register is provides for
a unity gain. In addition, the default CFA pattern color is
listed in the title of each register.
This section describes in further detail the functional op-
eration of the various MCM20027 programmable regis-
ters. The registers are subdivided into various blocks for
ease of addressability and use (see Table 6).
In each table where a suffix code is used; h = hex, b =
binary, and d = decimal.
13.1 Analog Register Interface Block
The address range for this block is 00h to BFh.
13.1.1 Analog Color Configuration
Address
00h
Default
0Eh
DPGA Color 1 Gain Code
Green of Green-Red Row
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
cg1[5]
cg1[4]
cg1[3]
cg1[2]
cg1[1]
cg1[0]
Bit
Number
Function
Description
Reset
State
7 - 6
5 - 0
Unused
Gain
Unused
xx
PGA Gain Mode
001110b
Raw Gain Mode [cg1d= 0-32d] ---> Gain = 0.6956 + (0.02174* cg1d)
Raw Gain Mode [cg1d= 33-63d] --> Gain = 1.391+ (0.0434* (cg1d-32)
(Range 0.696 - 2.736)
Linear Gain Mode -----> Gain = 0.6956 +(0.0434 x cg1d)
(Range 0.696 - 2.736)
Table 8. DPGA Color 1 Gain Register
Address
01h
Default
0Eh
DPGA Color 2 Gain Code
Red
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
cg2[5]
cg2[4]
cg2[3]
cg2[2]
cg2[1]
cg2[0]
Bit
Number
Function
Description
Reset
State
7 - 6
Unused
Unused
xx
Table 9. DPGA Color 2 Gain Register
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ImageMOS
Address
01h
Default
0Eh
DPGA Color 2 Gain Code
Red
msb (7)
x
6
x
5
4
3
2
1
lsb (0)
cg2[0]
001110b
cg2[5]
cg2[4]
cg2[3]
cg2[2]
cg2[1]
5 - 0
Gain
PGA Gain Mode
Raw Gain Mode [cg2d= 0-32d] ---> Gain = 0.6956 + (0.02174* cg2d)
Raw Gain Mode [cg2d= 33-63d] --> Gain = 1.391+ (0.0434* (cg2d-32)
(Range 0.696 - 2.736)
Linear Gain Mode -----> Gain = 0.6956 +(0.0434 x cg2d)
(Range 0.696 - 2.736)
Table 9. DPGA Color 2 Gain Register
Address
02h
Default
0Eh
DPGA Color 3 Gain Code
Blue
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
cg3[5]
cg3[4]
cg3[3]
cg3[2]
cg3[1]
cg3[0]
Bit
Number
Function
Description
Reset
State
7 - 6
5 - 0
Unused
Gain
Unused
xx
PGA Gain Mode
001110b
Raw Gain Mode [cg3d= 0-32d] ---> Gain = 0.6956 + (0.02174* cg3d)
Raw Gain Mode [cg3d= 33-63d] --> Gain = 1.391+ (0.0434* (cg3d-32)
(Range 0.696 - 2.736)
Linear Gain Mode -----> Gain = 0.6956 +(0.0434 x cg3d)
(Range 0.696 - 2.736)
Table 10. DPGA Color 3 Gain Register
Address
03h
Default
0Eh
DPGA Color 4 Gain Code
Green of Blue-Green Row
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
cg4[5]
cg4[4]
cg4[3]
cg4[2]
cg4[1]
cg4[0]
Bit
Number
Function
Description
Reset
State
7 - 6
Unused
Unused
xx
Table 11. DPGA Color 4 Gain Register
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ImageMOS
Address
03h
Default
0Eh
DPGA Color 4 Gain Code
Green of Blue-Green Row
msb (7)
x
6
x
5
4
3
2
1
lsb (0)
cg4[0]
001110b
cg4[5]
cg4[4]
cg4[3]
cg4[2]
cg4[1]
5 - 0
Gain
PGA Gain Mode
Raw Gain Mode [cg4d= 0-32d] ---> Gain = 0.6956 + (0.02174* cg4d)
Raw Gain Mode [cg4d= 33-63d] --> Gain = 1.391+ (0.0434* (cg4d-32)
(Range 0.696 - 2.736)
Linear Gain Mode -----> Gain = 0.6956 +(0.0434 x cg4d)
(Range 0.696 - 2.736)
Table 11. DPGA Color 4 Gain Register
The Color Tile Configuration Register; Table 12, defines
the maximum number of lines and the maximum num-
ber of colors per line. A maximum of four row and four
column definitions are permitted. The Color Tile Config-
uration Register defaults to two lines and two colors per
line. The user should leave this register in default unless
a unique CFA option has been ordered.
This register can be configured to any pattern combina-
tion of 1, 2, or 4 rows and 1, 2, or 4 columns.
Address
05h
Default
Color Tile Configuration
05h
lsb (0)
nr[0]
msb (7)
6
x
5
4
3
2
1
x
x
x
nc[1]
nc[0]
nr[1]
Bit
Number
Function
Description
Reset
State
7 - 4
3 - 2
Unused
Unused
xxxx
01b
Columns
00b = 1 Column in tile.
01b = 2 Columns in tile.
1xb = 4 Columns in tile.
1 - 0
Rows
00b = 1 Row in tile.
01b = 2 Rows in tile.
1xb = 4 Rows in tile.
01b
Table 12. Color Tile Configuration Register
The Color Tile Row Definition registers; Table 13, Table
14, Table 15, and Table 16 define the sequence of col-
ors for each respective line. Each byte wide line defini-
tion allows a maximum of four unique color definitions
using 2 bits per color in a given line. Gain programming
for each color was described earlier in this section. The
default line definitions are colors 00b, 01b, 00b, 01b for
row 1 and 10b, 11b, 10b, 11b for row 2 which supports a
Bayer pattern as defined in section 2.2. The user should
leave these registers in default unless a unique CFA op-
tion has been ordered.
For the default Bayer configuration of the color filter ar-
ray; Figure 4, the Color Gain Register addresses are as
follows: Reg (01h): green pixel of a green-red row; Reg
(00h): red pixel; Reg (03h): blue pixel; and Reg
(02h):green pixel of a blue-green row. The predefined
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ImageMOS
gain values programmed in the respective registers are
applied to pixel outputs as they are being read.
Address
06h
Default
44h
Color Tile Row 1 Definition
Green - Red Row
msb (7)
6
5
4
3
2
1
lsb (0)
r1c4[1]
r1c4[0]
Function
r1c3[1]
r1c3[0]
r1c2[1]
r1c2[0]
r1c1[1]
r1c1[0]
Bit
Number
Description
Reset
State
7 - 6
5 - 4
3 - 2
1 - 0
Color 4
Color 3
Color 2
Color 1
Fourth Color in Row 1(Green)
Third Color in Row 1 (Red)
Second Color in Row 1 (Green)
First Color in Row 1 (Red)
01b
00b
01b
00b
Table 13. Color Tile Row 1 Definition Register
Address
07h
Default
EEh
Color Tile Row 2 Definition
Blue - Green Row
msb (7)
6
5
4
3
2
1
lsb (0)
r2c4[1]
r2c4[0]
Function
r2c3[1]
r2c3[0]
r2c2[1]
r2c2[0]
r2c1[1]
r2c1[0]
Bit
Number
Description
Reset
State
7 - 6
5 - 4
3 - 2
1 - 0
Color 4
Color 3
Color 2
Color 1
Fourth Color in Row 2 (Blue)
11b
10b
11b
10b
Third Color in Row 2 (Green)
Second Color in Row 2 (Blue)
First Color in Row 2 (Green)
Table 14. Color Tile Row 2 Definition Register
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
08h
Default
00h
Color Tile Row 3 Definition
Unused
msb (7)
6
5
4
3
2
1
lsb (0)
r3c4[1]
r3c4[0]
Function
r3c3[1]
r3c3[0]
r3c2[1]
r3c2[0]
r3c1[1]
r3c1[0]
Bit
Number
Description
Reset
State
7 - 6
5 - 4
3 - 2
1 - 0
Color 4
Color 3
Color 2
Color 1
Fourth Color in Row 3
Third Color in Row 3
Second Color in Row 3
First Color in Row 3
00b
00b
00b
00b
Table 15. Color Tile Row 3 Definition Register
Address
09h
Default
00h
Color Tile Row 4 Definition
Unused
msb (7)
6
5
4
3
2
1
lsb (0)
r4c4[1]
r4c4[0]
Function
r4c3[1]
r4c3[0]
r4c2[1]
r4c2[0]
r4c1[1]
r4c1[0]
Bit
Number
Description
Reset
State
7 - 6
5 - 4
3 - 2
1 - 0
Color 4
Color 3
Color 2
Color 1
Fourth Color in Row 4
Third Color in Row 4
Second Color in Row 4
First Color in Row 4
00b
00b
00b
00b
Table 16. Color Tile Row 4 Definition Register
13.1.2 Reference Voltage Adjust Registers
The analog register block allows programming the input
voltage range of the analog to digital converter to match
the saturation voltage of the pixel array. The voltage ref-
erence generator can be programmed via two registers;
nrv (0 to 1.25V) Table 17, prv (2.5V to 1.25V) Table 18,
in 5mV steps. A 00h value in the prv register represents
a reference output voltage of 2.5V. A 00h value in the
nrv register represents output voltage of 0V. The de-
fault settings for the two registers produce a 1.9V refer-
ence on prv and 0.6V on nrv outputs. When adjusting
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
these values, the user should keep the voltage range
centered around 1.25V.
Address
Default
76h
Voltage Reference “Negative” Code
0Ah
msb (7)
nrv[7]
6
5
4
3
2
1
lsb (0)
nrv[6]
nrv[5]
nrv[4]
nrv[3]
nrv[2]
nrv[1]
nrv[0]
Bit
Number
Function
Description
Reset
State
7 - 0
Reference Voltage = 0.0 + (5mV * nrcd)
01110110b
(0.6V)
Table 17. Negative Voltage Reference Code Register
Address
0Bh
Default
80h
Voltage Reference “Positive” Code
msb (7)
6
5
4
3
2
1
lsb (0)
prv[7]
prv[6]
prv[5]
prv[4]
prv[3]
prv[2]
prv[1]
prv[0]
Bit
Number
Function
Description
Reset
State
7 - 0
Reference Voltage = 2.5 - (5mV * prvd)
10000000b
(1.9V)
Table 18. Positive Voltage Reference Code Register
13.1.3 Analog Control Registers
sistor at a specific clock rate. Power is further reduced
at lower clock rates.
The Analog Register Block also contains a Power Con-
figuration Register; Table 19, and a Reset Control Reg-
ister; Table 20.
The pbg bit of the Power Configuration Register; Table
19, is used to enable/disable the “Programmable Bias
Generator”. When this bit is enabled, the user can vary
the power consumption of the White Balance PGA
(PGAWB), Exposure gain PGA A (PGAEXPa), Expo-
sure gain PGA B (PGEXPb), Frame Rate Clamp (FRC),
Column Offset DOVA (COL_DOVA), Global offset
DOVA (DOVE) and/or the Analog to Digital converter
(A2D) between half an full current (power) consumption.
in the Programable Bias Generator Control register; Ta-
ble 22.
The Power Configuration Register controls the internal
analog functionality that directly effect power consump-
tion of the device. An external precision resistor pin is
available on the MCM20027 that may be used to more
accurately regulate the internal current sources. This
serves to minimize variations in power consumption that
are caused by variations in internal resistor values as
well as offer a method to reduce the power consumption
of the device. The default for this control uses the inter-
nally provided resistor which is nominally 12.5kW. This
feature is enabled by setting the res bit of the Power
Configuration Register and placing a resistor between
the pin; EXTRES, and ground. Figure 11 depicts the
power savings that can be achieved with an external re-
When this bit is disabled, it will use the power config-
ured by the internal or external resistor (bit 3).
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ImageMOS
The MCM20027 is put into a standby mode via the I2C
interface by setting the sby bit of the Power Configura-
tion Register.
Address
Default
Power Configuration
0Ch
msb (7)
x
00h
lsb (0)
sby
6
x
5
4
3
2
1
x
pbg
res
ssc
sc
Bit
Number
Function
Description
Reset
State
7-5
4
Unused
Unused
x
Prog Bias
Gen
0b = Prog Bias Gen Disabled
1b = Prog Bias Gen Enabled
0
3
2
Int/Ext
Resistor
0b = Internal Resistor
1b = External Resistor
0b
0b
Select
Software
Clamp
0b = Select internal Clamp
1b = Select software Clamp
1
0
Software
Clamp
0b = Clamp Off
0b
0b
1b = Clamp On (if ssc = 1)
Software
Standby
0b = Soft Standby inactive
1b = Soft Standby active
Table 19. Power Configuration Register
Additional control of the MCM20027 can be had using
the Reset Control Register; Reset Control Register; Ta-
ble 20.
Setting the sit bit allows the user to completely reset the
MCM20027 to the default state via the serial control In-
terface. For both reset bits, ssr and sit, the user must
return those bits to 0 to enable continued operation
Setting the sir bit of this register will reset all the non
programmable Sensor interface registers to a known re-
set state.
Setting the par bit of this register will reset all the Sen-
sors non programmable Post ADC registers to a known
reset state.
Setting the asp bit of this register will reset all the sen-
sors registers in the ASP processing chain to a known
reset state.
Setting the ssr bit of this register will reset all the non-
user programmable registers to a known reset state.
This is useful in situations when control of the
MCM20027 has been lost due to system interrupts and
the device needs only to be restarted using the earlier
user programmed values.
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
.
Address
0Eh
Default
Reset Control
00h
lsb (0)
sit
msb (7)
6
x
5
4
3
2
1
x
x
asr
par
sir
ssr
Bit
Number
Function
Description
Reset
State
7 - 5
4
Unused
Unused
xxx
0b
ASP (A2D) 0b = Normal Mode
Reset
1b = Reset registers in the A2D to 0
3
2
Post ADC
Reset
0b = Normal Mode
1b = Reset non-programmable Post ADC Registers to Reset state.
0b
0b
Sensor
Interface
Reset
0b = Normal Mode
1b = Reset non-programmable Sensor Interface resgisters to Reset
state.
1
0
State
Reset
0b = Normal Mode
1b = Reset all non-programmable registers to the Reset state
0b
0b
Soft Reset 0b = Normal Mode
1b = Reset all registers. (Same functions as setting the INIT pin)
Table 20. Reset Control Register
The Tristate Control Register; Table 21 is used to set
signals into Tristate mode. When the tsctl bit is reset
(i.e.. “0”) the HCLK, SOF, VCLK, SYNC and STROBE
output signals are set to Tristate mode. When the tspix
bit is reset (i.e. “0”) the pixel output data is set to Tristate
mode.
Address
Default
03h
Tristate Control B
12h
msb (7)
FUO
6
5
4
3
2
1
lsb (0)
FUO
FUO
FUO
FUO
FUO
tsctl
tspix
Bit
Number
Function
Description
Reset
State
7 - 3
1
FUO
tsctl
Factory Use Only
000000b
1b
0 - Outputs in Tristate
1 - Outputs driving
Table 21. Tristate Control Register
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
12h
Default
03h
Tristate Control B
msb (7)
FUO
0
6
5
4
3
2
1
lsb (0)
tspix
1b
FUO
tspix
FUO
FUO
FUO
FUO
tsctl
0 - Outputs in Tristate
1 - Outputs driving
Table 21. Tristate Control Register
The Programable Bias Generator Control register; Ta-
ble 22 can be used by the user to vary the power con-
sumption of the White Balance PGA (PGAWB),
Exposure gain PGA A (PGAEXPa), Exposure gain PGA
B (PGEXPb), Frame Rate Clamp (FRC), Column Offset
DOVA (COL_DOVA), Global offset DOVA (DOVE) and/
or the Analog to Digital converter (A2D) between half an
full current (power) consumption.
In order for this Register to be used, the pbg bit of the
Power Configuration Register; Table 19 has to be en-
abled.
Address
Default
00h
Programable Bias Generator Control
13h
msb (7)
x
6
5
4
3
2
1
lsb (0)
adp
gdp
egb
ega
wbp
cdp
fcp
Bit
Number
Function
Description
Reset
State
7
6
Unused
Unused
xb
0b
A to D
Converter
(A2D)
1b = Full Current (Power) consumption [80/100]
0b = Half Current (Power) consumption [40/50]
5
4
3
2
1
Global
Dova
1b = Full Current (Power) consumption [80/100]
0b = Half Current (Power) consumption [40/50]
0b
0b
0b
0b
0b
PGA Exp.
Gain B
1b = Full Current (Power) consumption [80/100]
0b = Half Current (Power) consumption [40/50]
PGA Exp.
Gain A
1b = Full Current (Power) consumption [80/100]
0b = Half Current (Power) consumption [40/50]
PGA White 1b = Full Current (Power) consumption [80/100]
Balance
0b = Half Current (Power) consumption [40/50]
Col_Dova
1b = Full Current (Power) consumption [80/100]
0b = Half Current (Power) consumption [40/50]
Table 22. Programable Bias Generator Control register
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
Default
00h
Programable Bias Generator Control
13h
msb (7)
6
5
4
3
2
1
lsb (0)
fcp
0b
x
adp
gdp
egb
ega
wbp
cdp
0
Frame
Rate
Clamp
1b = Full Current (Power) consumption [80/100]
0b = Half Current (Power) consumption [40/50]
Table 22. Programable Bias Generator Control register
13.2 Gain Calibration Block
The Exposure gain mode is set at either Raw or Linear,
then Exposure PGA Global Gain Register A; Table 23
and Exposure PGA Global Gain Register B; Table 24
are both utilized. But if it is set at Linear 2 gain mode,
then only Exposure PGA Global Gain Register A; Table
23 is used.
The Exposure PGA Global Gain Register A; Table 23
and the Exposure PGA Global Gain Register B; Table
24, allows the user to set a global gain via two 6 bit reg-
ister which are applied universally to all the pixel out-
puts. This enables the user to account for varying light
conditions.The Gain range depends on what the Expo-
sure Gain Mode (PGA Gain Mode; Table 25)is set. If
(
Address
Default
0Eh
Exposure PGA Global Gain A
10h
msb (7)
x
6
x
5
4
3
2
1
lsb (0)
gg1[5]
gg1[4]
gg1[3]
gg1[2]
gg1[1]
gg1[0]
Bit
Number
Function
Description
Reset
State
7 - 6
5 - 0
Unused
Gain
Unused
xx
PGA Gain Mode
001110
Raw Gain Mode [gg1d= 0-32d] ---> Gain = 0.6956 + (0.02174* gg1d)
Raw Gain Mode [gg1d= 33-63d] --> Gain = 1.391+ (0.0434* (gg1d-
32)
(Range 0.696 - 2.736)
Linear Gain Mode -----> Gain = 0.6956 + (0.0434 * gg1d)
(Range 0.696 - 2.736)
Linear 2 Gain Mode ----> Gain = 0.484 +(0.12 x gg1d)
(Range 0.484 - 7.488)
Table 23. Exposure PGA Global Gain Register A
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ImageMOS
Address
Default
0Eh
Exposure PGA Global Gain B
21h
msb (7)
x
6
x
5
4
3
2
1
lsb (0)
gg2[5]
gg2[4]
gg2[3]
gg2[2]
gg2[1]
gg2[0]
Bit
Number
Function
Description
Reset
State
7 - 6
5 - 0
Unused
Gain
Unused
xxb
PGA Gain Mode
001110
Raw Gain Mode [gg2d= 0-32d] ---> Gain = 0.6956 + (0.02174* gg2d)
Raw Gain Mode [gg2d= 33-63d] --> Gain = 1.391+ (0.0434* (gg2d-
32)
(Range 0.696 - 2.736)
Linear Gain Mode -----> Gain = 0.6956 + (0.0434 * gg2d)
(Range 0.696 - 2.736)
Table 24. Exposure PGA Global Gain Register B
The PGA Gain Mode; Table 25, is the register where the
PGA Gain modes for the White Balance and Exposure
gains can be selected. There are two different Gain
modes for White Balance and there are three different
Gain modes for the Exposure gain.
i.e. PGA Global Gain A Register= Raw gain mode
PGA Global Gain B Register= Raw gain mode
2) Linear gain mode - 48 steps @ 0.04340/step
i.e. PGA Global Gain A Register= Linear gain mode
PGAGlobal Gain B Register= Linear gain mode
3) Linear 2 gain mode - 64 steps @ ~ 0.12/step
i.e. PGA Global Gain A Register= Linear 2 gain mode
PGA Global Gain B Register= Not used
White Balance Gain modes:
1) Raw gain mode - 32 steps @ 0.02174/step
- 32 steps @ 0.04340/step
2) Linear gain mode - 48 steps @ 0.04340/step
Exposure Gain Modes:
The wbm bit sets the White Balance mode. While the
egm[d] bit sets the Exposure gain mode
1) Raw gain mode - 32 steps @ 0.02174/step
- 32 steps @ 0.04340/step
Address
22h
Default
00h
PGA Gain Mode
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
x
x
x
wbm
egm[1]
egm[0]
Bit
Number
Function
Description
Reset
State
Table 25. PGA Gain Mode
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
22h
Default
00h
PGA Gain Mode
msb (7)
6
x
5
x
4
3
2
1
lsb (0)
x
x
x
wbm
egm[1]
egm[0]
7 - 3
2
Unused
Unused
xxxx
0b
White Bal- 0b = Raw gain mode
ance Gain
Mode
1b = Linear gain mode
1 - 0
Exposure
Gain Mode
00b = Raw gain mode
01b = Linear gain mode
1xb = Linear 2 gain mode
00b
Table 25. PGA Gain Mode
13.3 Offset Calibration Block
this register can be left in its default state of 00h. This is
a pre-image processing gain in comparison to the Glo-
bal DOVA Register which is a post image processing
chain gain (pre A2D gain).
Offset adjustments for the MCM20027 are done in sep-
arate sections of the ASP to facilitate FPN removal and
final image black level set.
The Column DOVA DC Register; Table 26, is used to
set the initial offset of the pixel output in a range that will
facilitate per-column offset data generation for varying
operational conditions. In most operational scenarios,
This register can also be used to apply a global offset
adjust. In this case, the user must take into account the
Color Gain and Global Gain registers to determine the
resulting offset at the output.
Address
Default
00h
Column DOVA DC
20h
msb (7)
x
6
x
5
4
3
2
1
lsb (0)
cdd[5]
cdd[4]
cdd[3]
cdd[2]
cdd[1]
cdd[0]
Bit
Number
Function
Description
Reset
State
7 - 6
5
Unused
Sign
Unused
xx
0b
0b = Positive Offset
1b = Negative Offset
4 - 0
Column
Offset = 2.6 * cddd (64 steps @ 2.6mV /Step)
00000b
DC Offset
Table 26. Column DOVA DC Register
The Mod64 Column Offset registers; Table 27 are used
in conjunction with the Column DOVA DC Register; Ta-
ble 26 to reduce/eliminate fixed pattern noise (FPN).
There are 64 registers that can be programmed with in-
dividual offset values. They will be applied to all the col-
umns on a single image frame on a Modular 64
basis.i.e. Register 80h Column offset will be applied to
Column 0 , Register 81h Column offset will be applied to
Column 1, Register BFh Column offset will be applied to
Column 63, Register 80h Column offset will be applied
to Column 0..etc..
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
Default
00h
Mod64 Column Offset
80-BFh
msb (7)
x
6
x
5
4
3
2
1
lsb (0)
mdd[5]
mdd[4]
mdd[3]
mdd[2]
mdd[1]
mdd[0]
Bit
Number
Function
Description
Reset
State
7 - 6
5
Unused
Sign
Unused
xx
0b
0b = Positive Offset
1b = Negative Offset
4 - 0
Mod 64
Column
Offset = 2.6 * mddd (64 steps @ 2.6mV /Step)
00000b
DC Offset
Table 27. Mod64 Column Offset registers
The Global DOVA Register; Table 28 performs a final
offset adjustment in analog space prior to the ADC. The
6-bit register uses its MSB to indicate positive or nega-
tive offset. Each bit value changes the offset value by 4
LSB code levels hence giving an offset range of +/-124
LSB. As an example, to program an offset of +92 LSB,
the binary representation of +23d i.e. 010111b should
be loaded.
Address
Default
00h
Global DOVA
23h
msb (7)
x
6
x
5
4
3
2
1
lsb (0)
gd[5]
gd[4]
gd[3]
gd[2]
gd[1]
gd[0]
Bit
Number
Function
Description
Reset
State
7 - 6
5
Unused
Sign
Unused
xx
0b
0b = Positive Offset
1b = Negative Offset
4 - 0
Offset
Offset = 12 * gdd (64 steps @ 12mV /Step)
00000b
Table 28. Global DOVA Register
13.4 Sensor Interface Block
13.4.1 Sensor Output Control
The sensor output control registers define how the win-
dow of interest is captured and what data is output from
the MCM20027.
Setting the cms bit will stop the current output data
stream at the end of the current frame. Unsetting this bit
(cms = 0b) will resume the output of the frame stream.
The MCM20027 is in CFRS in default. The user may
use this bit to capture data in the CFRS mode and/or
SFRS while using the SYNC pin. The SYNC pin triggers
a single frame of data to be output from the device in the
The Capture Mode Control Register; Table 29, defines
how the data is captured and how the data is to be pro-
vided at the output..
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
SFRS mode. Please refer to Figure 14, on page 20 for
a timing diagram of this mode.
The he bit is used to determine whether HCLK is output
continuously or for the WOI pixels only. The default is
WOI only.
The sp bit is used to define whether SOF is active high
or low. SOF is active high in default.
The hp bit is used to define whether HCLK is active high
or low. HCLK is active high in default.
The ve bit is used to determine whether VCLK is output
at the beginning of all the rows including virtual frame
rows or for the WOI rows only. The default is WOI only.
The hm bit is used to define HCLK is toggled or wheth-
erwhether it is continuously output.
The vp bit is used to define whether VCLK is active high
or low. VCLK is active high in default.
Address
Default
2Ah
Capture Mode Control
40h
msb (7)
FUO
6
5
4
3
vp
2
1
lsb (0)
cms
sp
ve
he
hp
hm
Bit
Number
Function
Description
Reset
State
7
6
FUO
Factory Use Only
0b
0b
Capture
Mode
0b = Continuos Frame Rolling Shutter
1b = Single Frame Rolling Shutter
5
4
3
2
1
0
SOF
Phase
1b = SOF active high
0b = SOF active low
1b
0b
1b
0b
1b
0b
VCLK
Enable
1b = All virtual frame rows
0b = Window of Interest rows only
VCLK
Phase
1b = Active high
0b = Active low
HCLK
Enable
1b = Continuous
0b = Window of Interest Pixels only
HCLK
Phase
1b = Active high
0b = Active low
HCLK
Mode
1b = Continuous - envelope
0b = Toggles - like MCLK
Table 29. Capture Mode Control Register
The Sub-sample Control Register; Table 30, is used to
define what pixels of the WOI are read and the method
they are read.
(monochrome) or in color tiles of pixels (Bayer pattern).
The pixels will be read in monochrome mode in default.
The row sub sampling rate is defined by rf[1:0] while the
column sub sampling rate is defined by cf[1:0]. The pix-
el array is fully sampled in default.
Using the cm bit, the user can sample the pixel array in
either monochrome or Bayer pattern color space. This
means that when sampling the rows or columns, the set
of pixels read will be gathered as individual pixels
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
Default
Sub-sample Control
41h
msb (7)
x
10h
lsb (0)
cf[0]
6
5
4
3
2
1
FUO
FUO
cm
rf[1]
rf[0]
cf[1]
Bit
Number
Function
Description
Reset
State
7
6-5
4
Unused
FUO
Unused
x
Factory Use Only
FUO
1b
Color
Mode
1b = Bayer Pattern Sampling
0b = Monochrome Pattern Sampling
3 - 2
Row Fre-
quency
11b = read one row pattern, skip 7 (1/8 sampled)
10b = read one row pattern, skip 3 (1/4 sampled)
01b = read one row pattern, skip one (1/2 sampled)
00b = full sampling
00b
1 - 0
Column
Frequency
11b = read one column pattern, skip 7 (1/8 sampled)
10b = read one column pattern, skip 3 (1/4 sampled)
01b = read one column pattern, skip one (1/2 sampled)
00b = full sampling
00b
Table 30. Sub-sample Control Register
The Sync and Strobe Control register; Table 31 is used
to control the sync and strobe signals.
the bit is set to 0 (Setting 0), causes the STROBE signal
to on for a duration of 1 Row time (TROW) from the time
all Rows are integrating
The sr bit when enabled causes the SYNC signal to go
high for exactly one clock cycle, and then returns to a
low. It remains low until the sr bit is enabled again.
The sso bit ,when enabled, forces the STROBE signal
and thereby the STROBE Pin high until it is reset back
to 0. When this bit is set high - the sae and saw bit set-
tings become negligible.
The sa bit when enabled causes the SYNC signal high
until this bit is disabled. This causes continuous frame
processing.
The se bit when enabled will allow for an external signal
to drive the SYNC signal via the SYNC pin on the chip.
NOTE! Please refer to Figure 15, on page 14 for Strobe
Signal timing diagram.
The sae bit when enabled will enable the STROBE sig-
nal to be generated automatically by the sensor.This will
only work in SFRS (Single Frame Rolling Shutter). The
STROBE signal is goes high when all the Rows in the
Frame are integrating together.
The saw bit allows the user to select how long the
STROBE signal is going to be on. If the bit is set to 1
(Setting 1), causes the STROBE Signal to be on from
the time all the Rows are integrating to 1 Row time
(TROW) before Read-Out of the first Row commences. If
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
Default
SYNC and STROBE Control
42h
msb (7)
x
02h
lsb (0)
sr
6
x
5
4
3
2
1
sso
saw
sae
se
sa
Bit
Number
Function
Description
Reset
State
7-6
5
Unused
Unused
xx
0b
Strobe
Enable
1b = Strobe On
0b = Disabled
4
Strobe
Auto Width
Definition
1b = Maximum time (Entire time during which all active rows are inte
grating)
0b = 1 line
0b
3
2
Strobe
Auto
Enabled
1b = Enabled during integration
0b = Disabled
0b
0b
Exernal
SYNC
Enabled
1b = Enabled
0b = Disabled
1
0
SYNC
Always
1b = Enabled
0b = Disabled
1b
0b
SYNC
Request
1b = Enabled (Self clearing - will always read “0”)
0b = Disabled
Table 31. Sync and Strobe Control register
13.4.2 Programmable “Window of Interest”
The WOI Row Depth; wrd[10:0] (Table 32 and Table
33), and the WOI Column Depth; wcd[10:0] (Table 36
and Table 37), indicate the size of the WOI.
The WOI is defined by a set of registers that indicate the
upper-left starting point for the window and another set
of registers that define the size of the window. Please
refer to Figure 9, on page 12 for a pictorial representa-
tion of the WOI within the active pixel array.
The WOI Row Depth; wrd[10:0], has a range of 0d to
1047d whereas the WOI Column Depth; wcd[10:0], has
a range of 0d to 1295d.
The WOI Row Pointer; wrp[10:0] (Table 32 and Table
33), and the WOI Column Pointer; wcp[10:0] (Table 36
and Table 37), mark the upper-left starting point for the
WOI.
The user should be careful to create a WOI that con-
tains active pixels only. There is no logic in the sensor
The WOI Row Pointer; wrp[10:0], has a range of 0d to
1047d whereas the WOI Column Pointer; wcp[10:0] has
a usable range of 0d to 1295d. The pointer can be
placed anywhere within the active pixel array.
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
interface to prevent the user from defining an WOI that
addresses non-existent pixels.
Address
Default
00h
WOI Row Pointer MSB
45h
msb (7)
x
6
x
5
4
3
2
1
lsb (0)
x
x
x
wrp[10]
wrp[9]
wrp[8]
Bit
Number
Function
Description
Reset
State
7 - 3
2 - 0
Unused
Unused
xxxxx
000b
WOI Row
Pointer
In conjunction with the WOI Row Pointer LSB Register (Table 33),
forms the 11-bit WOI Row Pointer wrp[10:0]
Table 32. WOI Row Pointer MSB Register
WOI Row Pointer LSB
Address
46h
Default
10h
msb (7)
6
5
4
3
2
1
lsb (0)
wrp[7]
wrp[6]
Function
wrp[5]
wrp[4]
wrp[3]
wrp[2]
wrp[1]
wrp[0]
Bit
Number
Description
Reset
State
7 - 0
WOI Row
Pointer
In conjunction with the WOI Row Pointer MSB Register (Table 32),
forms the 11-bit WOI Row Pointer wrp[10:0]
00010000b
(row 16)
Table 33. WOI Row Pointer LSB Register
Address
47h
Default
03h
WOI Row Depth MSB
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
x
x
x
wrd[10]
wrd[9]
wrd[8]
Bit
Number
Function
Description
Reset
State
7 - 3
Unused
Unused
xxxxx
Table 34. WOI Row Depth MSB Register
Revision 8.0 - 28 November 2001 :
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
Default
03h
WOI Row Depth MSB
47h
msb (7)
x
6
5
4
3
2
1
lsb (0)
wrd[8]
011b
x
x
x
x
wrd[10]
wrd[9]
2-0
WOI Row
Depth
In conjunction with the WOI Row Depth LSB Register (Table 35),
forms the 11-bit WOI Row Depth wrd[10:0].
Table 34. WOI Row Depth MSB Register
WOI Row Depth LSB
Address
48h
Default
FFh
msb (7)
6
5
4
3
2
1
lsb (0)
wrd[7]
wrd[6]
Function
wrd[5]
wrd[4]
wrd[3]
wrd[2]
wrd[1]
wrd[0]
Bit
Number
Description
Reset
State
7 - 0
WOI Row
Pointer
In conjunction with the WOI Row Depth MSB Register (Table 34),
forms the 11-bit WOI Row Depth wrd[10:0].
Desired = wrdd + 1.
11111111b
(1024
rows)
Table 35. WOI Row Depth LSB Register
Address
49h
Default
00h
WOI Column Pointer MSB
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
x
x
x
wcp[10]
wcp[9]
wcp[8]
Bit
Number
Function
Description
Reset
State
7 - 3
2 - 0
Unused
Unused
xxxxx
000b
WOI Col.
Pointer
In conjunction with the WOI Column Pointer LSB Register (Table
37), forms the 11-bit WOI Column Pointer wcp[10:0]
Table 36. WOI Column Pointer MSB Register
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
Default
08h
WOI Column Pointer LSB
4Ah
msb (7)
wcp[7]
6
5
4
3
2
1
lsb (0)
wcp[6]
Function
wcp5]
wcp[4]
wcp[3]
wcp[2]
wcp[1]
wcp[0]
Bit
Number
Description
Reset
State
7 - 0
WOI Col.
Pointer
In conjunction with the WOI Column Pointer MSB Register (Table
36), forms the 11-bit WOI Column Pointer wcp[10:0]
00001000b
(col. 8)
Table 37. WOI Column Pointer LSB Register
Address
4Bh
Default
04h
WOI Column Width MSB
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
x
x
x
wcw[10]
wcw[9]
wcw[8]
Bit
Number
Function
Description
Reset
State
7 - 3
2 - 0
Unused
Unused
xxxxx
100b
WOI Col.
Width
In conjunction with the WOI Column Width LSB Register (Table 39),
forms the 11-bit WOI Column Width wcw[10:0].
Table 38. WOI Column Width MSB Register
WOI Column Width LSB
Address
4Ch
Default
FFh
msb (7)
6
5
4
3
2
1
lsb (0)
wcw[7]
wcw[6]
Function
wcw[5]
wcw[4]
wcw[3]
wcw[2]
wcw[1]
wcw[0]
Bit
Number
Description
Reset
State
7 - 0
WOI Row
Pointer
In conjunction with the WOI Column Width MSB Register (Table 38),
forms the 11-bit WOI Column Width wcw[10:0].
Desired = wcwd + 1.
11111111b
(1280 col.)
Table 39. WOI Column Width LSB Register
Ó MOTOROLA, INC. 2001
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MCM20027
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
13.4.3 Integration Time Control
data stream. By adding additional rows or columns as
‘blanking’ to the WOI to form the Virtual Frame, the user
can control the amount of blanking in both horizontal
and vertical space.(Table 42, “Virtual Frame Row Depth
MSB Register,” on page 55 Table 43, “Virtual Frame
Row Depth LSB Register,” on page 55Table 44, “Virtual
Frame Column Width MSB Register,” on
The Integration Time registers; Table 41, Table 40, and
Table 41, control the integration time for the pixel array.
Integration time for CFRS and SFRS; cint[13:0], is
measured in Virtual Row times. Please refer to Figure
11 for a pictorial description of the Virtual Frame and its
relationship to the WOI.
page 56Table 45, “Virtual Frame Column Width LSB
Register,” on page 56)
NOTE!! The upd bit of the Integration Time MSB Reg-
ister; Table 40 is used to indicate a change to cint[13:0].
Since multiple I2C writes may be needed to complete
desired frame to frame integration time changes, the
upd bit signals that all desired programming has been
completed, and to apply these changes to the next
frame captured. This prevents undesirable changes in
integration time that may result from I2C writes that
span the “End of Frame” boundary. This upd bit has to
be toggled from its previous state in order for the new
value of cint[13:0] to be accepted/updated by the sen-
sor and take effect. i.e. If its previous state is “0”, when
writing a new cint value, first write cint[7:0] to the Inte-
gration Time LSB Register; Table 41, then write both
cint [13:8] and “1” to the upd bit to the Integration Time
MSB Register; Table 40.
The user should be careful to create a Virtual Frame
that is larger than the WOI. There is no logic in the sen-
sor interface to prevent the user from defining a Virtual
Frame smaller than the WOI. Therefore, pixel data may
be lost.
The Virtual Frame must be at least 1 row and 6 columns
larger than the WOI.
The Virtual Frame completely defines the integration
time in CFRS. Any changes to the WOI or how the WOI
is sampled has no effect on integration time.
A virtual frame is the mechanism by which the user con-
trols the integration time and frame time for the output
Address
Default
04h
Integration Time MSB
4Eh
msb (7)
FUO
6
5
4
3
2
1
lsb (0)
upd
cint[13]
cint[12]
cint[11]
cint[10]
cint[9]
cint[8]
Bit
Number
Function
Description
Reset
State
7
6
FUO
Factory Use Only
Integration This bit has to change from its previous state everytime a new value
0
Time
Update
Switch
is written to Integration Time ISB and the Integration Time LSB.
5 - 0
Integration In conjunction with the Integration Time LSB (Table 41) Register,
000100b
Time
forms the 14-bit Integration Time cint[13:0].
Table 40. Integration Time MSB Register
Ó MOTOROLA, INC. 2001
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MCM20027
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
Default
FFh
Integration Time LSB
4Fh
msb (7)
cint[7]
6
5
4
3
2
1
lsb (0)
cint[6]
Function
cint[5]
cint[4]
cint[3]
cint[2]
cint[1]
cint[0]
Bit
Number
Description
Reset
State
7 - 0
Integration In conjunction with the Integration Time ISB (Table 40) Register,
11111111b
Time
forms the 14-bit Integration Time cint[13:0].
Integration Time = (cintd + 1) * Trow
CFRS and
SFRS:
1280
Rows)
Table 41. Integration Time LSB Register
Virtual Frame Row Depth MSB
Address
50h
Default
04h
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
vrd[13]
vrd[12]
vrd[11]
vrd[10]
vrd[9]
vrd[8]
Bit
Number
Function
Description
Reset
State
7 - 6
5 - 0
Unused
Unused
xx
VirtualRow In conjunction with the CFRS and SFRS Virtual Frame Row Depth
000100b
Depth
LSB (Table 43) Register, forms the 14-bit Virtual Frame Row Depth
vrd[13:0].
Table 42. Virtual Frame Row Depth MSB Register
Address
51h
Default
27h
Virtual Frame Row Depth LSB
msb (7)
6
5
4
3
2
1
lsb (0)
vrd[7]
vrd[6]
vrd[5]
vrd[4]
vrd[3]
vrd[2]
vrd[1]
vrd[0]
Bit
Number
Function
Description
Reset
State
Table 43. Virtual Frame Row Depth LSB Register
Ó MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 :
MCM20027
55
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
Default
27h
Virtual Frame Row Depth LSB
51h
msb (7)
vrd[7]
7 - 0
6
5
4
3
2
1
lsb (0)
vrd[0]
vrd[6]
vrd[5]
vrd[4]
vrd[3]
vrd[2]
vrd[1]
VirtualRow In conjunction with the CFRS and SFRS Virtual Frame Row Depth
00100111b
Depth
MSB (Table 42) Register, forms the 14-bit Virtual Frame Row Depth
vrd[13:0].
(1064
rows)
WOI is always top-left justified in Virtual Frame.
vrdd minimum = wrdd + 1
Table 43. Virtual Frame Row Depth LSB Register
Address
52h
Default
05h
Virtual Frame Column Width MSB
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
vcw[13]
vcw[12]
vcw[11]
vcw[10]
vcw[9]
vcw[8]
Bit
Number
Function
Description
Reset
State
7 - 6
5 - 0
Unused
Unused
xx
Virtual Col- In conjunction with the CFRS and SFRS Virtual Frame Column
umn Width Width LSB (Table 45) Register, forms the 14-bit Virtual Frame Col-
umn Width vcw[13:0].
000101b
Table 44. Virtual Frame Column Width MSB Register
Address
53h
Default
13h
Virtual Frame Column Width LSB
msb (7)
6
5
4
3
2
1
lsb (0)
vcw[7]
vcw[6]
Function
vcw[5]
vcw[4]
vcw[3]
vcw[2]
vcw[1]
vcw[0]
Bit
Number
Description
Reset
State
7 - 0
Virtual Col- In conjunction with the CFRS and SFRS Virtual Frame Column
umn Width Width MSB (Table 44) Register, forms the 14-bit Virtual Frame Col-
umn Width vcw[13:0]. WOI is always top-left justified in Virtual
Frame.
00010011b
(1300 col.)
vcwd minimum = wcwd + 11
Table 45. Virtual Frame Column Width LSB Register
Ó MOTOROLA, INC. 2001
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MCM20027
56
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
is a parameter that cannot be easily identified by the
common user). The VCLK Delay is defined as the time
after the SOF signal is first initialized. The SOF & VCLK
Signal Length Control Register, Table 48 , is used to de-
fine the size of the SOF and VCLK signals. In default,
SOF is one row wide while VLCK is 64 MCLKs wide
The SOF Delay Register; Table 46 and VCLK Delay
Register; Table 47 are used to determine the time
(clock) delay for the start of the two signals respectively.
The SOF Delay is measured as the time after the start
of the change of row address (Change of row address
Address
Default
4Ch
SOF Delay
54h
msb (7)
6
5
4
3
2
1
lsb (0)
sofd[7]
sofd[6]
Function
sof[d5]
sofd[4]
sofd[3]
sofd[2]
sofd[1]
sofd[0]
Bit
Number
Description
Reset
State
1001100b
7 - 0
SOF Delay Delay= sofd[d] x 0.5 MCLKs
(Note - Delay is relative to Internal Pixel Transfer Control)
Table 46. SOF Delay Register
Address
55h
Default
02h
VCLK Delay
msb (7)
6
5
4
3
2
1
lsb (0)
vckd[7]
vckd[6]
Function
vckd[5]
vckd[4]
vckd[3]
vckd[2]
vckd[1]
vckd[0]
Bit
Number
Description
Reset
State
7 - 0
VCLK
Delay
Delay = vckd[d] x 0.5 MCLKs
(Note - Delay is relative to Start Of Frame {SOF} signal)
00000010b
Table 47. VCLK Delay Register
Address
56h
Default
Eh
SOF and VCLK Signal Length Control
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
x
x
sofc[3]
sofc[2]
vckc[1]
vckc[0]
Bit
Number
Function
Description
Reset
State
3 - 2
SOF Con-
trol
sof[3:2] = 00b = 1 MCLK Wide
sof[3:2] = 01b = 8 MCLKs Wide
sof[3:2] = 10b = 64 MCLKs Wide
sof[3:2] = 11b = Full Row Wide
11b
Table 48. SOF & VCLK Signal Length Control Register
Ó MOTOROLA, INC. 2001
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MCM20027
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
Default
SOF and VCLK Signal Length Control
56h
Eh
msb (7)
x
6
5
4
3
2
1
lsb (0)
vckc[0]
10b
x
x
x
sofc[3]
sofc[2]
vckc[1]
1 - 0
VCLK Con- vck[1:0] = 00b = 1 MCLK Wide
trol
vck[1:0] = 01b = 8 MCLKs Wide
vck[1:0] = 10b = 64 MCLKs Wide
vck[1:0] = 11b = Full Row Wide
Table 48. SOF & VCLK Signal Length Control Register
The Greycode and Readout Control Register; Table 49 allows the user to choose if the column and row addresses
are to utilize Greycode address format or not. It also allows the user to select the user to select the direction of the
row and column readout.
The rrc when enabled causes the column data to be readout in the reverse direction as compared to the normal
readout direction.
The rrr when enabled causes the row data to be readout in the reverse direction as compared to the normal readout
direction.
The gcc bit when enabled causes the column addresses to be Greycoded.
The gcr bit when enabled causes the column addresses to be Greycoded.
Address
57h
Default
04h
Greycode and Readout Control
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
x
x
gcr
gcc
rrr
rrc
Bit
Number
Function
Description
Reset
State
7-4
3
Unused
Unused
Row Grey- 1b = Greycode addressing Enabled
code
Address
0b
1b
0b = Binary Addressing
2
Column
Greycode
Address
Enable
1b = Greycode addressing Enabled
0b = Binary Addressing
Table 49. Greycode and Readout Control Register
Ó MOTOROLA, INC. 2001
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MCM20027
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
Default
04h
Greycode and Readout Control
57h
msb (7)
6
5
4
3
2
1
lsb (0)
rrc
0b
x
x
x
x
gcr
gcc
rrr
1
Row Read- 1b = Reverse Readout (Top to Bottom)
out
0b = Normal Readout (Bottom to Top)
0
Column
Readout
1b = Reverse Readout (Right to Left)
0b = Normal Readout (Left to Right
0b
Table 49. Greycode and Readout Control Register
The Internal Timing Control Register 1 (shs time definition); Table 50 and ,Internal Timing Control Register 2 (shr
time definition); Table 51 are used to define the size of internal timing pulse widths. In default, both shs and shr are
6 MCLK’s wide. A maximum of 64 MCLK‘s can be programmed for the shs delay and another 64 MCLK‘s for the shr
delay, for a total 0f 128 MCLK‘s. Note! writing 00h to either of these Registers will write a maximum timing delay of
64 MCLK‘s. i.e. 00 = 64 MCLK
Address
5Fh
Default
0Ah
Internal Timing Control
msb (7)
6
x
5
4
3
2
1
lsb (0)
x
shs[5]
shs[4]
shs[3]
shs[2]
shs[1]
shs[0]
Bit
Number
Function
Description
Reset
State
xx
7-6
Unused
shs
Unused
001010b
5 - 0
shs[5:0] = 000000b = 64 MCLKs Wide
shs[5:0] = 000001b = 1d MCLKs Wide
shs[5:0] = 000010b = 2d MCLKs Wide
shs[5:0] = 000011b = 3d MCLKs Wide
|
|
shs[5:0] = 111111b = 63d MCLKs Wide
Table 50. Internal Timing Control Register 1 (shs time definition)
Ó MOTOROLA, INC. 2001
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
Default
0Ah
Internal Timing Control
60h
msb (7)
x
6
x
5
4
3
2
1
lsb (0)
shr[5]
shr[4]
shr[3]
shr[2]
shr[1]
shr[0]
Bit
Number
Function
Description
Reset
State
xx
7-6
Unused
shr
Unused
001010b
5 - 0
shr[5:0] = 000000b = 64 MCLKs Wide
shr[5:0] = 000001b = 1d MCLKs Wide
shr[5:0] = 000010b = 2d MCLKs Wide
shr[5:0] = 000011b = 3d MCLKs Wide
|
|
shr[5:0] = 111111b = 63d MCLKs Wide
Table 51. Internal Timing Control Register 2 (shr time definition)
The HCLK Delay Register; Table 52 allows the user to program the delay for the start of the HCLK signal. The delay
is calculated in accordance to the result of inserting the value of the register into the following formula:
Delay = ((hckd[d]-4)x 0.5) - 16 MCLKs
Address
64h
Default
5Ch
HCLK Control
msb (7)
6
5
4
3
2
1
lsb (0)
x
FUO
FUO
FUO
FUO
hckd[2]
hckd[1]
hckd[0]
Bit
Number
Function
Description
Reset
State
7
Unused
FUO
Unused
x
6 - 3
Factory Use Only
Table 52. HCLK Delay Register
Ó MOTOROLA, INC. 2001
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
64h
Default
5Ch
HCLK Control
msb (7)
x
6
5
4
3
2
1
lsb (0)
hckd[0]
100b
FUO
FUO
FUO
FUO
hckd[2]
hckd[1]
2 - 0
HCLK
Delay
Delay = ((hckd[d]-4)x 0.5) - 16 MCLKs
Table 52. HCLK Delay Register
The Pixel Data Stream Control Register allows the user to select how the output pixel data stream is encoded/for-
matted.
The vcb bit allows the user to force all the Blanking data coming out of the A2D to be 0.
The vcg bit allows the user to choose between encoded pixel data output stream or non-encoded pixel data output
stream.
The vcc bit allows the user to clip the output active pixel data to lie between 001 and 3FE
The default mode (Normal Mode) has the SOF, HCLK, VCLK etc. signals being utilised to indicate the start of data
and the end of data. (Figure 2, on page 7 and Figure 14, on page 20)
Register Value = 00h
Another mode, Video Mode is a mode where the SOF and Row start/end signals are encoded (contained) in the
Active Pixel data stream. In addition, all data that is not a SOF, Row start/end, or Active pixel data are forced to 0.
i.e. all Blanking data from the A2D are forced to 0. The following sequence identifies the signals below: (see Figure
, on page 30)
a) SOF (1st Row of Pixel Data) - “3FF x 4)
b) Start of all other Rows - “3FF x 2” then “000 x 2”
Ó MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 :
MCM20027
61
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Register Value = 70
Address
Default
Pixel Data Stream Signal Control Register
65h
msb (7)
x
00h
lsb (0)
FUO
6
5
4
3
2
1
vcb
vsg
vcc
FUO
FUO
FUO
Bit
Number
Function
Description
Reset
State
x
7
6
Unused
Unused
Vcode
Blanking
1b = All blanking data will be forced to 0
0b = Blanking of Data
0b
5
Vcode
Sync Gen-
eration
1b = Prefixes 3FF x 4 to beginning of active pixel data to indicate
0b
start of Row 1(SOF signal). Prefixes 3FF x 2 and then 000 x 2 to
indicate start of all following Rows of data (VCLK) [Encoded data
stream]
0b = Use of SOF, HCLK etc. signals for sync generation (No
coded data stream)
4
Vcode
Clipping
1b = Will clip output data stream to values 001b to 3FEb
0b = No clipping of output data stream
0b
3 - 0
FUO
Factory Use Only
0000b
Table 53. Pixel Data Stream Signal Control Register
The FRC Definition Register; Table 54 allows the user to define the size of the dark rows to use as Clamping rows.
The frcs bit identifies the starting position of the Clamping rows. i.e. If 4d is written to this register, the first clamped
dark row would be the 4th row.
The frcd bit identifies the FRC row depth. Allows the user to select the number of dark rows to clamp on.
NOTE! Since there exists ONLY 11 dark rows the addition of FRC Row Depth + FRC Row Start should not be great-
er than 11, otherwise light rows would be clamped in the process.
Ó MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 :
MCM20027
62
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Address
67h
Default
24h
FRC Definition
msb (7)
6
5
4
3
2
1
lsb (0)
x
FUO
frcd[1]
frcd[0]
frcs[3]
frcs[2]
frcs[1]
frcs[0]
Bit
Number
Function
Description
Reset
State
7
6
Unused
FUO
Unused
x
Factory Use Only
5 - 4
FRC Row
Depth
Defines the number of Clamping Rows.
NOTE!! The addition of FRC Row Depth + FRC Row Start should
10b
not be greater than 11d.
3 - 0
FRC Row
Start
Defines the first Clamping row. Defines the FRC starting point.
0100
Table 54. FRC Definition Register
Ó MOTOROLA, INC. 2001
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MCM20027
63
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
14.0 Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS1 (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
V
DC Supply Voltage
DC Input Voltage
-0.5 to 3.8
V
V
DD
V
0.5 to V + 0.5
in
DD
V
-0.5 to V + 0.5
DC Output Voltage
V
out
DD
I
I
DC Current Drain per Pin, Any Single Input or Output
DC Current Drain, V and V Pins
±50
±100
mA
mA
°C
°C
DD
SS
T
Storage Temperature Range
-65 to +150
300
STG
T
Lead Temperature (10 second soldering)
L
1
Maximum Ratings are those values beyond which damage to the device may occur.
V
V
= AV = DV = V
(DV = V of Digital circuit, AV = V of Analog Circuit)
SS
DD
SS
SS
SSO SS SS SS SS
= AV = DV = V
(DV = V of Digital circuit, AV = V of Analog Circuit)
DD DD DD DD
DD
DD
DDO
RECOMMENDED OPERATING CONDITIONS (to guarantee functionality; voltage referenced to VSS)
Symbol
Parameter
Min.
3.0
0
Max
3.6
40
Unit
V
V
DC Supply Voltage, V = 3.3V (Nominal)
DD
DD
T
Commercial Operating Temperature
Junction Temperature
°C
°C
A
T
0
55
J
Notes:
- All parameters are characterized for DC conditions after thermal equilibrium has been established.
- Unused inputs must always be tied to an appropriate logic level, e.g., either V or V
.
DD
SS
- This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedance circuit.
- For proper operation it is recommended that V and V be constrained to the range V < (V or V ) < V .
DD
in
out
SS
in
out
DC ELECTRICAL CHARACTERISTICS (VDD = 3.3V ± 0.3V; VDD referenced to VSS; Ta = 0°C to 40°C)
T
= 0°C to 40°C
A
Symbol
Characteristic
Input High Voltage
Condition
Min.
2.0
-0.3
-5
Max
V +0.3
DD
Unit
V
V
IH
V
Input Low Voltage
0.8
V
IL
I
V
= V or V
SS
Input Leakage Current, No Pull-up Resistor
5
mA
in
in
DD
Ó MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 :
MCM20027
64
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
I
V
= Min., V Min. = 0.8 * V
DD OH DD
Output High Current
Output Low Current
-3
mA
mA
V
OH
I
V
= Min., V Max = 0.4 V
3
OL
DD
OL
V
V
= Min., I = -100mA
V - 0.2
DD
Output High Voltage
OH
DD
OH
V
I
V
= Min., I = 100mA
Output Low Voltage
0.2
10
V
OL
DD
OL
Output = High Impedance, V = V or V
SS
3-State Output Leakage Current
Maximum Standby Supply Current
-10
0
mA
mA
OZ
DD
out
DD
I
I
= 0mA, V = V or V
SS
15.0
out
in
DD
POWER DISSIPATION (VDD = 3.0V, VDD referenced to VSS; At = 25°C)
Symbol
Parameter
Condition
Typ
100
250
Unit
P
Standby Power
Average Power
INIT Pin Logic High
13.5 MHz Operation
uW
STDBY
P
mW
AVG
MCM20027 MONOCHROME CMOS IMAGE SENSOR ELECTRO-OPTICAL CHARACTERISTICS
Symbol
Parameter
Typ
Unit
Notes
1
2
E
Saturation Exposure
0.14
mJ/cm
sat
QE
Peak Quantum Efficiency (@550nm)
Photoresponse Non-uniformity
18
12
%
2
3
PRNU
% pk-pk
Notes:
1.For l = 550 nm wavelength.
2.Refer to typical values from Figure 3, MCM20027 nominal spectral response.
3.For a 100 x 100 pixel region under uniform illumination with output signal equal to 80% of saturation signal.
MCM20027 COLOR CMOS IMAGE SENSOR ELECTRO-OPTICAL CHARACTERISTICS
Symbol
Parameter
Typ
0.3
12
11
8
Unit
Notes
2
E
Saturation Exposure
1
2
2
2
mJ/cm
%
sat
QE
Red Peak Quantum Efficiency @ l = 650 nm
Green Peak Quantum Efficiency @ l = 550 nm
Blue Peak Quantum Efficiency @ l = 450 nm
r
QE
%
g
QE
%
b
Notes:
1.For l = 550 nm wavelength.
2.Refer to typical values from Figure 3, MCM20027 nominal spectral response.
CMOS IMAGE SENSOR CHARACTERISTICS
Symbol
Parameter
Typ
1.8
Unit
Notes
Sensitivity
V/lux-sec
2
I
Photodiode Dark Current
0.2
nA/cm
d
DSNU
CTE
Dark Signal Non-Uniformity (Entire Field)
Pixel Charge Transfer Efficiency
Horizontal Imager Frequency
0.4
% rms
%
0.9995
11.5
1
4
f
MHz
H
X
Blooming Margin - shuttered light
200
2,3
ab
Ó MOTOROLA, INC. 2001
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MCM20027
65
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Notes:
1. Transfer efficiency of photosite
2. X represents the increase above the saturation-irradiance level (H ) that the device can be exposed to before blooming of the pixel will
ab
sat
occur.
3. No column streaking
4. At 30fps VGA
GENERAL
Symbol
Parameter
Typ
70
Unit
Notes
1
-
n -
Total System (equivalent) Noise Floor
System Dynamic Range
e rms
e
total
DR
Notes:
50
dB
1.Includes amplifier noise, dark pattern noise and dark current shot noise at 13.5 MHz data rates.
ANALOG SIGNAL PROCESSOR CHARACTERISTICS
Analog to Digital Converter (ADC)
Symbol
Parameter
Resolution
Min
Typ
10
Max
Units
bits
8
V
2.5
Vpp
LSB
LSB
MHz
IN
Input Dynamic Range
INL
Integral Non-Linearity
Differential Non-Linearity
ADC Clock Rate
+1.0
+0.5
DNL
f
13.5
max
Notes:
8
Effective differential signal dynamic range
9. INL & DNL test limits are adjusted to compensate for the effects of the LRC, DOVA and DPGA stages between teh EXT_VINS input and the
input of the ADC.
Ó MOTOROLA, INC. 2001
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MCM20027
66
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
15.0 MCM20027 Pin Definitions
note: pins 1 & 46 should
be pulled down when not in use
MCLK
VCLK
SDATA
SCLK
Legend:
P = V
HCLK
SYNC
DVDD
DVSS
DD
G = V
SS
VSS_PIX
VDD_PIX
BIAS_IN
STROBE
SOF
Connect to VDD
I = Input
Top-View
O = Output
D = Digital
A = Analog
INIT
DVDD
AVDD
AVSS
CVBG
See Section 8.6 for more
information
DVSS
AVSS
EXTRESP
AVDD
EXTRESR
TN
CLRCA
See Section 8.4 for
more information
See Section 8.5 for
more information
Figure 20. MCM20027 Pin Definitions
Ó MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 :
MCM20027
67
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
Pin Pin
No. Name
Pin
Type
Pin Pin
No. Name
Pin
Type
Description
Sensor Initialize
Power
Description
Power
1
2
3
4
5
6
7
8
9
INIT
I
25 VDD_PIX Pixel power
26 VSS_PIX Pixel ground
DVDD
DVSS
Digital Power
P
G
G
P
O
O
O
O
I
D
D
A
A
Digital Ground
27 DVSS
28 DVDD
29 SCLK
30 SDATA
Digital Ground
Digital Power
G
P
D
D
AVSS
Analog Ground
AVDD
CLRCA
CLRCB
TST_VR
TST_VS
Analog Power
I2C Serial Clock
I2C Serial Data
I/O
I/O
O
O
O
O
O
P
Line Rate Clamp Output
Line Rate Clamp Output
Analog test reference Output
Analog test signal Output
31 PIX_OUT0 Output bit 0 = 1 Weight
32 PIX_OUT1 Output bit 1 = 2 Weight
33 PIX_OUT2 Output bit 2 = 4 Weight
34 PIX_OUT3 Output bit 3 = 8 Weight
35 PIX_OUT4 Output bit 4 = 16 Weight
10 EXT_VINR Analog test reference Input
11 EXT_VINS Analog test signal Input
I
12 AVSS
13 AVDD
Analog Ground
Analog Power
G
P
O
O
I
A
A
36 DVDD
37 DVSS
Digital Power
Digital Ground
D
D
G
O
O
O
O
O
14 CVREFM Bias Reference Bottom Output
15 CVREFP Bias Reference Top Output
38 PIX_OUT5 Output bit 5 = 32 Weight
39 PIX_OUT6 Output bit 6 = 64 Weight
40 PIX_OUT7 Output bit 7 = 128 Weight
41 PIX_OUT8 Output bit 8 = 256 Weight
42 PIX_OUT9 Output bit 9 = 512 Weight
16 VAG
Common Mode Cap Input
17 VAGRETN Common Mode Cap Return
18 VAGREF Common Mode Caps Input
EXTRESR
A
A
I
I
19
EXTRES Return
43 MCLK
Master Clock
I
TN
20 EXTRES External Bias Resistor Input
44 VCLK
45 HCLK
46 SYNC
Line Sync
O
O
I
21 CVBG
22 AVSS
23 AVDD
24 BIAS_IN
Bandgap Voltage Testpoint
Analog Ground
Pixel Sync
G
P
I
A
A
Sensor Sync Signal
Analog Power
47 STROBE Strobe signal
48 SOF Start Of Frame
O
O
Pixel row 1046/7 inj Bias in
Table 55. MCM20027 Pin Definitions
I
P
INPUT
POWER
G
O
D
GROUND
OUTPUT
DIGITAL
A
ANALOG
I/O
BIDIRECTIONAL
Ó MOTOROLA, INC. 2001
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MCM20027
68
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
16.0 MCM20027 Packaging Information
Figure 21. 48 Terminal ceramic leadless chip carrier (bottom view)
Dim
A
Min(Inches)
0.555
Max(Inches)
0.572
B
0.525
---
0.545
0.09362
0.024
C
D
0.016
0.054
0.075
E
0.068
F
0.095
G
H
0.040 BSC
0.033
0.555
0.525
0.047
0.572
0.545
J
K
R
0.0075 (Radius)
0.0075 (Radius)
R1
Ó MOTOROLA, INC. 2001
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PIX_OUT7
PIX_OUT3
VDD PIX_OUT4
PIX_OUT5
PIX_OUT6
PIX_OUT1
PIX_OUT9
PIX_OUT8
VSS
PIX_OUT2
PIX_OUT0
42
41
40 39 38 37
36 35 34
33
32
31
MOT
M
1
SDATA
INC.
30
3
4
5
6
7
8 9
10
11
12
13 14
2
MCLK
43
60
15
16
SCLK
VDD
29
28
VCLK
HCLK
44
45
46
59
58
17
18
57
56
19
20
VSS
27
26
25
SYNC
X-Offset:
+52µm (~2mil)
VSS_PIX
STROBE
SOF
47
48
21
22
23
55
54
VDD_PIX
Y-Offset:
+400µm (~16mil)
INIT
BIAS_IN
VDDA
24
23
22
Pin
1
2
Die Placement
positional tolerance
200um (+/- 4 mil)
53
52
24
25
VDD
51
50
VSS
3
4
VSSA
26
27
49
48
VSSA
CVBG
21
20
28
29
VDDA
5
6
EXTRESP
47
46
30
45
44
43 42
41
40
39 38
37 36
35
34
33
32
31
VSSA
CLRCA
19
K06K
7
8
9
10
11 12
13 14 15 16
VDDA CVREFM CVREFP VAG
17
VSSA
18
VAGREF
CLRCB TST_VR TST_VS EXT_VINR EXT_VINS VSSA
Figure 23. Center of the focal plane array with respect to the die cavity (top view)
Notes:
1. Dimensions are in inches.
2. Interpret dimensions and tolerances per
ASME Y14.5-1994
Ó MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 :
MCM20027
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
A
F - Lid Seal thickness
G
H
B
J
D
C - Die
E - Die Attach thickness
Metric (mm)
min
English (inches)
Dimension
Description
Glass (Thickness)
Cavity (Depth)
Die - Si (Thickness)
Bottom Layer (Thickness)
Die Attach - bondline (Thickness)
Glass Attach - bondline (Thickness)
Imager to Lid - outer surface (d)
Imager to Lid - inner surface (d)
Imager to seating plane - of pkg
Pkg (Th - total)
Nominal
max
Nominal
min
max
A
B
C
D
E
F
G
H
J
0.55000
1.11760
0.72500
0.43180
0.02540
0.02540
0.94260
0.39260
1.18220
2.12480
1.54940
0.50000
0.99060
0.70500
0.38100
0.01270
0.00635
0.67575
0.17575
1.09870
1.87795
1.70180
0.60000
1.24460
0.74500
0.48260
0.07620
0.05080
1.17770
0.57770
1.30380
2.37800
1.39700
0.02165
0.04400
0.02854
0.01700
0.00100
0.00100
0.03711
0.01546
0.04654
0.08365
0.06100
0.01969
0.03900
0.02776
0.01500
0.00050
0.00025
0.02660
0.00692
0.04326
0.07393
0.06700
0.02362
0.04900
0.02933
0.01900
0.00300
0.00200
0.04637
0.02274
0.05133
0.09362
0.05500
Base (Th)
Note: The package sketch is representative and does not necessarily reflect exact scale and relative feature sizes.
Reference Notes:
1mil = 25.4um
1mm = 39.37mil
Figure 22. 48 Terminal ceramic leadless chip carrier (z-direction view)
Ó MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 :
MCM20027
71
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
17.0 MCM20027 Typical Connection
Below you will find a schematic illustrating a typical connection of an MCM20027 CMOS sensor. One can use this
as a reference when connecting the sensor with another external device such as an image processor, SDRAM
etc.This schematic also illustrates the connection of the required passives on the sensor.
43
47
1
31
32
33
34
35
38
39
40
41
42
MASTER CLOCK
STROBE
INITIALIZE
PIXEL DATA 0
PIXEL DATA 1
PIXEL DATA 2
PIXEL DATA 3
PIXEL DATA 4
PIXEL DATA 5
PIXEL DATA 6
PIXEL DATA 7
PIXEL DATA 8
PIXEL DATA 9
MCLK
STROBE
INIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
46
START DATA CAPTURE
SYNC
30
29
I2C_DATA
I2C_CLK
SDATA
SCLK
21
10
11
CVBG
EXT_VINR
EXT_VINS
.1uf
.1uf
45
44
48
6
DATA VALID
HORIZONTAL SYNC
START OF FRAME
HCLK
VCLK
SOF
CLRCA
CLRCB
18
17
16
VAGREF
VAGRETN
VAG
7
9
8
14
15
20
19
TST_VS
TST_VR
CVREFM
CVREFP
EXTRES
EXTRESGND
27K
25
23
5
VDD_PIX
AVDD
AVDD
DVDD
2
28
36
24
13
+3.3V
BEAD
DVDD
DVDD
DVDD
BIAS_IN
AVDD
4.7/25
.01uf .01uf .01uf .01uf
26
22
12
4
VSS_PIX
AVSS
AVSS
3
37
27
DVSS
DVSS
DVSS
AVSS
M20027IB
AGND
GND
GND
.1uf
.1uf
GND
GND
.1uf
.1uf
AVDD
+3.3V
BEAD
.01uf
.01uf
.01uf .01uf
4.7/25
GND
AGND
AGND
AGND AGND AGND
Ó MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 :
MCM20027
72
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ImageMOS
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equa
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ELECTRO STATIC DISCHARGE WARNING:
This device is sensitive to electrostatic discharge (ESD).ESD immunity meets Human Body Model (HBM) < 1500 V and Machine Model (MM) < 150
V Additional ESD data upon request. When handling this part, proper ESD precautions should be followed to avoid exposing the device to dis-
charges which may be detrimental to its immediate performance and/or reduce the parts expected lifetime..
Ó MOTOROLA, INC. 2001
Revision 8.0 - 28 November 2001 :
MCM20027
73
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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