MC74HC51N [MOTOROLA]
2-Wide, 2-Input/2-Wide, 3-Input AND-NOR Gates; 2 ，宽， 2输入/ 2 -宽， 3输入与或非门
| 型号： | MC74HC51N |
| 厂家： | 
MOTOROLA |
| 描述： | 2-Wide, 2-Input/2-Wide, 3-Input AND-NOR Gates |
| 文件： | 总4页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
14
The MC74HC51 is identical in pinout to the LS51. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
ORDERING INFORMATION
MC74HCXXN
MC74HCXXD
Plastic
SOIC
•
Chip Complexity: 42 FETs or 10.5 Equivalent Gates
PIN ASSIGNMENT
A1
A2
1
2
14
13
V
CC
LOGIC DIAGRAM
C1
1
B2
C2
3
4
12
11
B1
F1
A1
12
B1
13
D2
Y2
5
6
10
9
E1
D1
C1
D1
E1
F1
8
Y1
9
10
11
Y1 = (A1•B1•C1) + (D1•E1•F1)
GND
7
8
Y1
2
3
A2
B2
FUNCTION TABLES
Inputs
6
Y2
Output
Y1
4
5
Y2 = (A2•B2) + (C2•D2)
C2
D2
A1 B1 C1 D1 E1 F1
H
X
H
X
H
X
X
H
X
H
X
H
L
L
All other combinations
H
PIN 14 = V
CC
PIN 7 = GND
Inputs
Output
Y2
A2
B2
C2
D2
H
X
H
X
X
H
X
H
L
L
All other combinations
H
10/95
REV 6
Motorola, Inc. 1995
MC74HC51
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 1.5 to V
+ 1.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
CC
and GND Pins
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
IL
out
CC
|I
|
20 µA
out
V
|I
= V or V
IH IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
OH
Minimum High–Level Output
Voltage
in
out
|
20 µA
V
in
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
IH
IL out
out
V
|I
= V or V
IH
out
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
Maximum Low–Level Output
Voltage
V
in
IL
|
20 µA
V
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
in
in
IH IL out
out
I
Maximum Input Leakage Current
V
V
= V
= V
or GND
6.0
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
or GND
2
20
40
CC
in
CC
I
= 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
MC74HC51
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
,
Maximum Propagation Delay, Any Input to Output Y
(Figures 1 and 2)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
PLH
PHL
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
TLH
THL
C
Maximum Input Capacitance
—
10
10
10
pF
in
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Section)*
pF
23
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V . For load considerations, see Chapter 2 of the
CC CC
PD CC
t
t
f
r
TEST POINT
V
CC
90%
50%
10%
INPUT
OUTPUT
DEVICE
UNDER
GND
t
PLH
t
PHL
C *
90%
50%
10%
L
TEST
OUTPUT Y
t t
THL
t
TLH
* Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
1
A1
12
B1
13
C1
8
Y1
9
D1
10
E1
11
F1
2
A2
3
B2
6
Y2
4
C2
5
D2
PIN 14 = V
PIN 7 = GND
CC
3
MOTOROLA
MC74HC51
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
ISSUE L
14
1
8
7
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
C
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
0
10
0
10
0.015
0.039
0.39
1.01
H
G
D
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE F
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
P 7 PL
–B–
M
M
0.25 (0.010)
B
7
MILLIMETERS
INCHES
G
F
R X 45°
DIM
A
B
C
D
F
G
J
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
C
0.337
0.150
0.054
0.014
0.016
J
M
SEATING
PLANE
K
D 14 PL
0.25 (0.010)
1.27 BSC
0.050 BSC
0.19
0.10
0.25
0.25
0.008
0.004
0.009
0.009
M
S
S
T
B
A
K
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.228
0.010
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
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CODELINE
MC74HC51/D
◊
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