MC74HC112ND [MOTOROLA]
HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16;
| 型号： | MC74HC112ND |
| 厂家： | 
MOTOROLA |
| 描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 触发器 |
| 文件： | 总6页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
The MC74HC112 is identical in pinout to the LS112. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
1
Each flip–flop is negative–edge clocked and has active–low asynchro-
nous Set and Reset inputs.
The HC112 is identical in function to the HC76, but has a different pinout.
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
16
Low Input Current: 1 µA
1
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
ORDERING INFORMATION
•
•
Similar in Function to the LS112 Except When Set and Reset are Low
Simultaneously
Chip Complexity: 100 FETs or 25 Equivalent Gates
MC74HCXXXN
MC74HCXXXD
MC74HCXXXDT
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
LOGIC DIAGRAM
CLOCK 1
1
2
16
15
V
CC
K1
J1
RESET 1
4
SET 1
3
4
14
13
RESET 2
CLOCK 2
2
1
5
6
SET 1
Q1
K1
Q1
Q1
5
6
12
11
K2
J2
CLOCK 1
Q1
3
J1
Q2
7
8
10
9
SET 2
Q2
15
RESET 1
GND
10
FUNCTION TABLE
Inputs
SET 2
Outputs
12
13
9
K2
Q2
Q2
Set Reset Clock
J
K
Q
Q
CLOCK 2
L
H
L
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
X
X
X
X
X
X
L
X
X
X
L
H
L
L
H
11
14
7
J2
L*
L*
No Change
RESET 2
L
H
L
H
X
X
X
L
H
H
L
H
H
X
X
X
Toggle
PIN 16 = V
CC
PIN 8 = GND
L
H
No Change
No Change
No Change
* Both outputs will remain low as long as Set and
Reset are low, but the output states are unpre-
dictable if Set and Reset go high simultaneously.
10/95
REV 6
Motorola, Inc. 1995
MC74HC112
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 1.5 to V
+ 1.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
DC Supply Current, V
CC
and GND Pins
range GND (V or V
)
V
CC
.
CC
in out
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP)
L
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V , V
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
0
V
V
C
in out
CC
T
A
– 55 + 125
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
Test Conditions
25 C
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
IL
out
CC
|I
|
20 µA
out
V
|I
= V or V
IH IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
OH
Minimum High–Level Output
Voltage
in
out
|
20 µA
V
in
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
IH
IL out
out
V
|I
= V or V
IH
out
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
Maximum Low–Level Output
Voltage
V
in
IL
|
20 µA
V
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
in
in
IH IL out
out
I
Maximum Input Leakage Current
V
V
= V
= V
or GND
6.0
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
or GND
4
40
80
CC
in
CC
I
= 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
MC74HC112
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
max
t
t
t
t
,
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
ns
ns
ns
pF
PLH
t
PHL
,
Maximum Propagation Delay, Reset to Q or Q
(Figures 2 and 4)
2.0
4.5
6.0
155
31
26
195
39
33
235
47
40
PLH
t
PHL
,
Maximum Propagation Delay, Set to Q or Q
(Figures 2 and 4)
2.0
4.5
6.0
165
33
28
205
41
35
250
50
43
PLH
t
PHL
,
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
TLH
t
THL
C
Maximum Input Capacitance
—
10
10
10
in
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Flip–Flop)*
pF
35
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
su
Minimum Setup Time, J or K to Clock
(Figure 3)
2 0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
Minimum Hold Time, Clock to J or K
(Figure 3)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
ns
ns
ns
ns
h
t
Minimum Recovery Time, Set or Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
rec
t
t
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
w
Minimum Pulse Width, Set or Reset
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
w
t , t
r f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
3
MOTOROLA
MC74HC112
SWITCHING WAVEFORMS
t
t
t
w
f
r
V
V
CC
90%
CC
50%
50%
SET OR
RESET
CLOCK
10%
GND
GND
t
PHL
t
w
1/f
PLH
max
50%
Q OR Q
t
t
PHL
90%
50%
10%
t
PLH
Q or Q
50%
Q OR Q
CLOCK
t
rec
t
t
THL
TLH
V
CC
Figure 1.
50%
GND
Figure 2.
VALID
V
TEST POINT
CC
50%
J OR K
GND
OUTPUT
t
t
h
su
DEVICE
UNDER
TEST
V
CC
50%
C *
CLOCK
L
GND
Figure 3.
* Includes all probe and jig capacitance
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
15, 14
3, 11
RESET
5, 9
Q
CL
CL
J
CL
CL
CL
2,12
1, 13
4, 10
CL
K
CL
CL
CL
CL
CL
CLOCK
SET
CL
CL
6, 7
Q
CL
MOTOROLA
4
MC74HC112
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
F
C
L
0.740
0.250
0.145
0.015
0.040
S
0.070
1.77
SEATING
–T
–
PLANE
0.100 BSC
0.050 BSC
0.015
0.130
0.305
2.54 BSC
1.27 BSC
0.38
3.30
7.74
M
K
0.008
0.110
0.295
0.21
2.80
7.50
H
J
G
D 16 PL
M
S
0°
10°
0°
10°
M
M
0.25 (0.010)
T
A
0.020
0.040
0.51
1.01
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
0.050 BSC
0.008
0.004
F
K
R X 45°
C
1.25
1.27 BSC
–T
0.19
0.10
0.25
0.25
0.009
0.009
J
SEAT
–
ING
M
K
PLANE
D 16 PL
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.229
0.010
M
S
S
0.25 (0.010)
T
B
A
5
MOTOROLA
MC74HC112
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X KREF
0.10 (0.004)
M
S
S
T
U
V
NOTES:
S
0.15 (0.006) T
U
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
B
–U–
SECTION N–N
L
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T
U
A
M
MILLIMETERS
INCHES
–V–
DIM
A
B
C
D
MIN
4.90
4.30
–––
0.05
0.50
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
0.193
0.169
–––
0.002
0.020
F
F
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
DETAIL E
H
SEATING
PLANE
–T–
D
G
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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CODELINE
MC74HC112/D
◊
相关型号：
MC74HC113N
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP14, PLASTIC, DIP-14
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