MC74HC109D [MOTOROLA]
Dual J-K Flip-Flop with Set and Reset; 双J- K触发器具有置位和复位
| 型号： | MC74HC109D |
| 厂家： | 
MOTOROLA |
| 描述： | Dual J-K Flip-Flop with Set and Reset |
| 文件： | 总5页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
High–Performance Silicon–Gate CMOS
16
The MC74HC109 is identical in pinout to the LS109. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
1
This device consists of two J–K flip–flops with individual set, reset, and
clock inputs. Changes at the inputs are reflected at the outputs with the next
low–to–high transition of the clock. Both Q and Q outputs are available from
each flip–flop.
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
PIN ASSIGNMENT
•
Chip Complexity: 148 FETs or 37 Equivalent Gates
RESET 1
J1
1
2
16
15
V
CC
RESET 2
K1
3
4
14
13
J2
LOGIC DIAGRAM
CLOCK 1
K2
SET 1
5
6
12
11
CLOCK 2
SET 2
5
SET 1
Q1
Q1
3
4
6
7
K1
Q1
Q1
7
8
10
9
Q2
Q2
CLOCK 1
GND
2
1
J1
FUNCTION TABLE
Inputs
RESET 1
Outputs
Set Reset Clock
J
K
Q
Q
11
SET 2
L
H
L
H
L
L
X
X
X
X
X
X
L
H
L
X
X
X
L
H
L
H*
L
L
H
H*
H
13
12
10
9
K2
Q2
Q2
H
H
H
H
H
H
H
H
H
H
CLOCK 2
L
Toggle
No Change
H
14
15
H
H
X
J2
H
X
L
L
No Change
RESET 2
* Both outputs will remain high as long as Set and
Reset are low, but the output states are unpre-
dictable if Set and Reset go high simultaneously.
PIN 16 = V
CC
PIN 8 = GND
10/95
REV 6
Motorola, Inc. 1995
MC74HC109
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 1.5 to V
+ 1.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
CC
and GND Pins
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
|I
|
20 µA
out
V
in
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
IH IL out
out
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IH IL
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
|I
|
20 µA
out
V
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
in
in
IH IL out
out
I
Maximum Input Leakage Current
V
V
= V
= V
or GND
6.0
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
or GND
4
40
80
CC
in
CC
I
= 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
MC74HC109
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
max
t
t
t
,
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
ns
ns
pF
PLH
t
PHL
,
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
PLH
t
PHL
,
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
TLH
t
THL
C
Maximum Input Capacitance
—
10
10
10
in
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Flip–Flop)*
pF
40
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
su
Minimum Setup Time, J or K to Clock
(Figure 3)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
Minimum Hold Time, Clock to J or K
(Figure 3)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
ns
ns
ns
ns
h
t
Minimum Recovery Time, Set or Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
rec
t
Minimum Pulse Width, Set or Reset
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
w
w
t
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
t , t
r f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
3
MOTOROLA
MC74HC109
SWITCHING WAVEFORMS
t
w
t
t
V
r
f
CC
V
SET OR
RESET
50%
CC
90%
GND
CLOCK
50%
t
10%
GND
PHL
t
w
Q OR Q
50%
t
1/f
max
t
t
PHL
PLH
PLH
90%
50%
50%
10%
Q OR Q
CLOCK
Q or Q
t
rec
t
t
THL
TLH
V
CC
50%
Figure 1.
GND
Figure 2.
TEST POINT
VALID
V
CC
J or K
50%
t
OUTPUT
GND
DEVICE
UNDER
TEST
t
su
h
C *
V
L
CC
50%
CLOCK
GND
Figure 3.
* Includes all probe and jig capacitance
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
5, 11
SET
6, 10
Q
4, 12
CLOCK
2, 14
J
7, 9
Q
3, 13
K
1, 15
RESET
MOTOROLA
4
MC74HC109
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
F
C
L
0.740
0.250
0.145
0.015
0.040
S
0.070
1.77
SEATING
–T
–
PLANE
0.100 BSC
0.050 BSC
0.015
0.130
0.305
2.54 BSC
1.27 BSC
0.38
3.30
7.74
M
K
0.008
0.110
0.295
0.21
2.80
7.50
H
J
G
D 16 PL
M
S
0°
10°
0°
10°
M
M
0.25 (0.010)
T
A
0.020
0.040
0.51
1.01
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
F
K
R X 45°
C
1.25
1.27 BSC
0.050 BSC
–T
0.19
0.10
0.25
0.25
0.008
0.004
0.009
0.009
J
SEAT
–
ING
M
K
PLANE
D 16 PL
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.229
0.010
M
S
S
0.25 (0.010)
T
B
A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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CODELINE
MC74HC109/D
◊
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