MC68HSC705C8ACP [MOTOROLA]
M68HC05 MICROCONTROLLERS; M68HC05微控制器
| 型号： | MC68HSC705C8ACP |
| 厂家： | 
MOTOROLA |
| 描述： | M68HC05 MICROCONTROLLERS |
| 文件： | 总222页 (文件大小：2263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC705C8A
MC68HSC705C8A
Technical Data
M68HC05
Microcontrollers
MC68HC705C8A/D
Rev. 3, 3/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS
MC68HC705C8A
MC68HSC705C8A
Technical Data
To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.motorola.com/semiconductors/
The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
© Motorola, Inc., 2002
Technical Data
Revision History
Revision
Level
Page
Number(s)
Date
Description
1.7 Pin Functions — Added description of programming voltage
29
(V ) pin 1.7.2 V
PP
PP
May, 2001
March, 2002
2.1
Removed note following 1.7.11 Port D I/O Pins (PD7 and
PD5–PD0)
33
14.2 Introduction — Updated Motorola contact information
192
195
14.7 44-Pin Quad Flat Pack (QFP) — Corrected case outline
drawing from Case #824E to Case #824A
3
Technical Data — MC68HC705C8A
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .21
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . .43
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . .69
Section 7. Parallel Input/Output (I/O). . . . . . . . . . . . . . . .77
Section 8. Capture/Compare Timer . . . . . . . . . . . . . . . . .89
Section 9. EPROM/OTPROM (PROM) . . . . . . . . . . . . . .103
Section 10. Serial Communications Interface (SCI). . .121
Section 11. Serial Peripheral Interface (SPI). . . . . . . . .139
Section 12. Instruction Set. . . . . . . . . . . . . . . . . . . . . . .153
Section 13. Electrical Specifications . . . . . . . . . . . . . .171
Section 14. Mechanical Specifications . . . . . . . . . . . . .191
Section 15. Ordering Information . . . . . . . . . . . . . . . . .199
Appendix A. MC68HSC705C8A . . . . . . . . . . . . . . . . . . .201
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
MC68HC705C8A — Rev. 3
Technical Data
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List of Sections
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List of Sections
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Technical Data — MC68HC705C8A
Table of Contents
Section 1. General Description
1.1
1.2
1.3
1.4
1.5
1.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.7
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
External Reset Pin (RESET) . . . . . . . . . . . . . . . . . . . . . . . .32
External Interrupt Request Pin (IRQ) . . . . . . . . . . . . . . . . . .32
Input Capture Pin (TCAP) . . . . . . . . . . . . . . . . . . . . . . . . . .32
Output Compare Pin (TCMP). . . . . . . . . . . . . . . . . . . . . . . .33
Port A I/O Pins (PA7–PA0). . . . . . . . . . . . . . . . . . . . . . . . . .33
Port B I/O Pins (PB7–PB0). . . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.1
1.7.2
1.7.3
1.7.4
1.7.5
1.7.6
1.7.7
1.7.8
1.7.9
1.7.10 Port C I/O Pins (PC7–PC0) . . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.11 Port D I/O Pins (PD7 and PD5–PD0). . . . . . . . . . . . . . . . . .33
Section 2. Memory
2.1
2.2
2.3
2.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
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Table of Contents
2.5
2.6
2.7
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Bootloader ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Section 3. Central Processor Unit (CPU)
3.1
3.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Section 4. Interrupts
4.1
4.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Capture/Compare Timer Interrupts . . . . . . . . . . . . . . . . . . .55
SCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Section 5. Resets
5.1
5.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
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5.3
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Programmable and Non-Programmable
5.3.1
5.3.2
5.3.3
COP Watchdog Resets . . . . . . . . . . . . . . . . . . . . . . . . . .62
Clock Monitor Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.3.4
Section 6. Low-Power Modes
6.1
6.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
SCI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
SPI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Programmable COP Watchdog in Stop Mode . . . . . . . . . . .71
Non-Programmable COP Watchdog in Stop Mode . . . . . . .73
6.3.1
6.3.2
6.3.3
6.3.4
6.4
6.4.1
6.4.2
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Programmable COP Watchdog in Wait Mode . . . . . . . . . . .75
Non-Programmable COP Watchdog in Wait Mode . . . . . . .75
6.5
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Section 7. Parallel Input/Output (I/O)
7.1
7.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .79
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.3.1
7.3.2
7.3.3
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .82
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.4.1
7.4.2
7.4.3
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7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . .86
Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.5.1
7.5.2
7.5.3
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Section 8. Capture/Compare Timer
8.1
8.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.3
8.3.1
8.3.2
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.4
Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .98
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . .100
Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . .101
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
Section 9. EPROM/OTPROM (PROM)
9.1
9.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
9.3
9.3.1
9.3.2
EPROM/OTPROM (PROM) Programming. . . . . . . . . . . . . . .104
Program Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Preprogramming Steps . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.4
PROM Programming Routines . . . . . . . . . . . . . . . . . . . . . . . .111
Program and Verify PROM. . . . . . . . . . . . . . . . . . . . . . . . .111
Verify PROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Secure PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Secure PROM and Verify. . . . . . . . . . . . . . . . . . . . . . . . . .113
Secure PROM and Dump. . . . . . . . . . . . . . . . . . . . . . . . . .113
Load Program into RAM and Execute . . . . . . . . . . . . . . . .114
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
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9.4.7
9.4.8
Execute Program in RAM. . . . . . . . . . . . . . . . . . . . . . . . . .115
Dump PROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.5
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Mask Option Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.5.1
9.5.2
9.5.3
9.6
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Section 10. Serial Communications Interface (SCI)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.4 SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.5 SCI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
10.6 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.6.1 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.6.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.6.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
10.6.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.6.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Section 11. Serial Peripheral Interface (SPI)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
11.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
11.4.1 Pin Functions in Master Mode . . . . . . . . . . . . . . . . . . . . . .143
11.4.2 Pin Functions in Slave Mode . . . . . . . . . . . . . . . . . . . . . . .144
11.5 Multiple-SPI Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
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11.6 Serial Clock Polarity and Phase . . . . . . . . . . . . . . . . . . . . . . .146
11.7 SPI Error Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.1 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.2 Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.3 Overrun Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.8 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.9 SPI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.9.1 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
11.9.2 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
11.9.3 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Section 12. Instruction Set
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .158
12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .159
12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .160
12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .162
12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
12.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
12.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Technical Data
12
MC68HC705C8A — Rev. 3
Table of Contents
MOTOROLA
Table of Contents
Section 13. Electrical Specifications
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
13.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .173
13.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
13.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.7 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .175
13.8 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .176
13.9 5.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
13.10 3.3-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . .185
13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . .187
Section 14. Mechanical Specifications
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
14.3 40-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . .192
14.4 40-Pin Ceramic Dual In-Line Package (Cerdip) . . . . . . . . . . .193
14.5 44-Lead Plastic-Leaded Chip Carrier (PLCC) . . . . . . . . . . . .194
14.6 44-Lead Ceramic-Leaded Chip Carrier (CLCC) . . . . . . . . . . .195
14.7 44-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . .196
14.8 42-Pin Shrink Dual In-Line Package (SDIP). . . . . . . . . . . . . .197
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Table of Contents
13
Table of Contents
Section 15. Ordering Information
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Appendix A. MC68HSC705C8A
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
5.0-Volt High-Speed DC Electrical Characteristics. . . . . . . . .202
3.3-Volt High-Speed DC Electrical Characteristics . . . . . . . .203
5.0-Volt High-Speed Control Timing. . . . . . . . . . . . . . . . . . . .204
3.3-Volt High-Speed Control Timing. . . . . . . . . . . . . . . . . . . .204
5.0-Volt High-Speed SPI Timing . . . . . . . . . . . . . . . . . . . . . .205
3.3-Volt High-Speed SPI Timing. . . . . . . . . . . . . . . . . . . . . . .207
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Index
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Technical Data
14
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Table of Contents
MOTOROLA
Technical Data — MC68HC705C8A
List of Figures
Figure
Title
Page
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
Option Register (Option) . . . . . . . . . . . . . . . . . . . . . . . . . . .23
MC68HC705C8A Block Diagram . . . . . . . . . . . . . . . . . . . . .25
40-Pin PDIP/Cerdip Pin Assignments . . . . . . . . . . . . . . . . .26
44-Lead PLCC/CLCC Pin Assignments. . . . . . . . . . . . . . . .27
44-Pin QFP Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . .27
42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .28
Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . .29
Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . .31
3-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . .31
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3-1
3-2
3-3
3-4
3-5
3-6
Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .044
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .045
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .045
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .046
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .046
Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . .047
4-1
4-2
4-3
4-4
4-5
External Interrupt Internal Function Diagram . . . . . . . . . . . .52
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Interrupt Stacking Order. . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Reset and Interrupt Processing Flowchart . . . . . . . . . . . . . .59
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
List of Figures
15
List of Figures
Figure
Title
Page
5-1
5-2
5-3
5-4
6-1
6-2
Programmable COP Watchdog Diagram . . . . . . . . . . . . . . .63
Programmable COP Reset Register (COPRST) . . . . . . . . .64
Programmable COP Control Register (COPCR) . . . . . . . . .64
Non-Programmable COP Watchdog Diagram . . . . . . . . . . .67
Stop/Wait Mode Function Flowchart . . . . . . . . . . . . . . . . . .70
Programmable COP Watchdog
in Stop Mode (PCOPE = 1) Flowchart. . . . . . . . . . . . . . .72
Non-Programmable COP Watchdog
6-3
in Stop Mode (NCOPE = 1) Flowchart . . . . . . . . . . . . . .74
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . .78
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .79
Port A I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . .81
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .82
Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . .85
Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . .86
Port C I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Port D Fixed Input Register (PORTD) . . . . . . . . . . . . . . . . .88
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-10
8-9
8-11
8-12
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Timer I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .91
Input Capture Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Output Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . .93
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .94
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .96
Timer Registers (TRH and TRL) . . . . . . . . . . . . . . . . . . . . .97
Timer Register Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Alternate Timer Register Reads. . . . . . . . . . . . . . . . . . . . . .99
Alternate Timer Registers (ATRH and ATRL) . . . . . . . . . . .99
Input Capture Registers (ICRH and ICRL). . . . . . . . . . . . .100
Output Compare Registers (OCRH and OCRL). . . . . . . . .101
9-1
9-2
EPROM/OTPROM Programming Flowchart . . . . . . . . . . .105
PROM Programming Circuit. . . . . . . . . . . . . . . . . . . . . . . .106
Technical Data
16
MC68HC705C8A — Rev. 3
List of Figures
MOTOROLA
List of Figures
Figure
Title
Page
9-3
9-4
9-5
9-6
Program Register (PROG) . . . . . . . . . . . . . . . . . . . . . . . . .109
Option Register (Option) . . . . . . . . . . . . . . . . . . . . . . . . . .116
Mask Option Register 1 (MOR1) . . . . . . . . . . . . . . . . . . . .117
Mask Option Register 2 (MOR2) . . . . . . . . . . . . . . . . . . . .118
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
SCI Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . .125
SCI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . .129
SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . .130
SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . .131
SCI Status Register (SCSR) . . . . . . . . . . . . . . . . . . . . . . .133
Baud Rate Register (Baud) . . . . . . . . . . . . . . . . . . . . . . . .136
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
SPI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .142
Master/Slave Connections . . . . . . . . . . . . . . . . . . . . . . . . .143
One Master and Three Slaves Block Diagram. . . . . . . . . .145
Two Master/Slaves and Three Slaves Block Diagram . . . .146
SPI Clock/Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . .149
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . .149
SPI Status Register (SPSR). . . . . . . . . . . . . . . . . . . . . . . .151
13-1
13-2
13-3
Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Typical Voltage Compared to Current . . . . . . . . . . . . . . . .177
Typical Current versus Internal
Frequency for Run and Wait Modes . . . . . . . . . . . . . . .179
Total Current Drain versus Frequency . . . . . . . . . . . . . . . .180
Timer Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . .183
Power-On Reset and External Reset Timing Diagram. . . .184
SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
13-4
13-5
13-6
13-7
13-8
13-9
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
List of Figures
17
List of Figures
Figure
14-1
14-2
14-3
14-4
14-5
14-6
Title
Page
MC68HC705C8AP Package Dimensions
(Case #711). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
MC68HC705C8AS Package Dimensions
(Case #734A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
MC68HC705C8AFN Package Dimensions
(Case #777). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
MC68HC705C8AFS Package Dimensions
(Case #777B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
MC68HC705C8AFB Package Dimensions
(Case #824A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
MC68HC705C8AB Package Dimensions
(Case #858). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Technical Data
18
MC68HC705C8A — Rev. 3
List of Figures
MOTOROLA
Technical Data — MC68HC705C8A
List of Tables
Table
Title
Page
2-1
4-1
5-1
Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . .57
Programmable COP Timeout Period Selection . . . . . . . . . . .66
7-1
7-2
7-3
Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9-1
9-2
MC68HC05PGMR PCB Reference Designators . . . . . . . . .104
PROM Programming Routines. . . . . . . . . . . . . . . . . . . . . . .108
10-1
10-2
10-3
Baud Rate Generator Clock Prescaling . . . . . . . . . . . . . . . .136
Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . . .138
11-1
SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .150
12-1
12-2
12-3
12-4
12-5
12-6
12-7
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .158
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .159
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .161
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . .162
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
15-1
MC68HC705C8A Order Numbers . . . . . . . . . . . . . . . . . . . .199
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
List of Tables
19
List of Tables
Table
Title
Page
A-1 Programmable COP Timeout Period Selection . . . . . . . . . . .202
A-2 MC68HSC705C8A Order Numbers . . . . . . . . . . . . . . . . . . . .209
Technical Data
20
MC68HC705C8A — Rev. 3
List of Tables
MOTOROLA
Technical Data — MC68HC705C8A
Section 1. General Description
1.1 Contents
1.2
1.3
1.4
1.5
1.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.7
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.7.1
1.7.2
1.7.3
1.7.3.1
1.7.3.2
1.7.3.3
1.7.4
1.7.5
1.7.6
1.7.7
1.7.8
1.7.9
VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
External Clock Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . .32
External Reset Pin (RESET) . . . . . . . . . . . . . . . . . . . . . . . .32
External Interrupt Request Pin (IRQ) . . . . . . . . . . . . . . . . . .32
Input Capture Pin (TCAP) . . . . . . . . . . . . . . . . . . . . . . . . . .32
Output Compare Pin (TCMP). . . . . . . . . . . . . . . . . . . . . . . .33
Port A I/O Pins (PA7–PA0). . . . . . . . . . . . . . . . . . . . . . . . . .33
Port B I/O Pins (PB7–PB0). . . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.10 Port C I/O Pins (PC7–PC0) . . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.11 Port D I/O Pins (PD7 and PD5–PD0). . . . . . . . . . . . . . . . . .33
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
General Description
21
General Description
1.2 Introduction
The MC68HC705C8A, an enhanced version of the MC68HC705C8, is a
member of the low-cost, high-performance M68HC05 Family of 8-bit
microcontroller units (MCU). The MC68HSC705C8A, introduced in
Appendix A. MC68HSC705C8A, is an enhanced, high-speed version of
the MC68HC705C8A. The M68HC05 Family is based on the
customer-specified integrated circuit (CSIC) design strategy. All MCUs
in the family use the M68HC05 central processor unit (CPU) and are
available with a variety of subsystems, memory sizes and types, and
package types.
1.3 Features
Features of the MC68HC705C8A include:
•
•
•
•
•
M68HC05 central processor unit (CPU)
On-chip oscillator with crystal/ceramic resonator
Memory-mapped input/output (I/O)
Selectable memory configurations
Selectable programmable and/or non-programmable computer
operating properly (COP) watchdog timers
•
•
•
•
•
•
•
•
•
•
Selectable port B external interrupt capability
Clock monitor
High current drive on pin C7 (PC7)
24 bidirectional I/O lines and 7 input-only lines
Serial communications interface (SCI) system
Serial peripheral interface (SPI) system
Bootstrap capability
Power-saving stop, wait, and data-retention modes
Single 3.0-volt to 5.5-volt supply (2-volt data-retention mode)
Fully static operation
Technical Data
22
MC68HC705C8A — Rev. 3
General Description
MOTOROLA
General Description
Programmable Options
•
•
Software-programmable external interrupt sensitivity
Bidirectional RESET pin
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low. Any reference to voltage,
current, or frequency specified in this document will refer to the nominal
values. The exact values and their tolerance or limits are specified in
Section 13. Electrical Specifications.
1.4 Programmable Options
These options are programmable in the mask option registers:
•
Enabling of port B pullup devices (see 9.5.2 Mask Option
Register 1)
•
Enabling of non-programmable COP watchdog (see 9.5.3 Mask
Option Register 2)
These options are programmable in the option register (see Figure 1-1):
•
•
•
One of four selectable memory configurations
Programmable read-only memory (PROM) security1
External interrupt sensitivity
Address: $1FDF
Bit 7
6
RAM1
0
5
0
0
4
0
0
3
SEC*
*
2
1
IRQ
1
Bit 0
0
Read:
RAM0
Write:
Reset:
0
U
0
*Implemented as an EPROM cell
= Unimplemented
U = Unaffected
Figure 1-1. Option Register (Option)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the PROM difficult for unauthorized users.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
General Description
23
General Description
RAM0 — Random-Access Memory Control Bit 0
1 = Maps 32 bytes of RAM into page zero starting at address
$0030. Addresses from $0020 to $002F are reserved. This bit
can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 48 bytes of PROM at location $0020–$005F.
RAM1 — Random-Access Memory Control Bit 1
1 = Maps 96 bytes of RAM into page one starting at address $0100.
This bit can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 96 bytes of PROM at location $0100.
SEC — Security Bit
This bit is implemented as an erasable, programmable read-only
memory (EPROM) cell and is not affected by reset.
1 = Bootloader disabled; MCU operates only in single-chip mode
0 = Security off; bootloader can be enabled
IRQ — Interrupt Request Pin Sensitivity Bit
IRQ is set only by reset, but can be cleared by software. This bit can
be written only once.
1 = IRQ pin is both negative edge- and level-sensitive.
0 = IRQ pin is negative edge-sensitive only.
Bits 5, 4, and 0 — Not used; always read 0
Bit 2 — Unaffected by reset; reads either 1 or 0
1.5 Block Diagram
Figure 1-2 shows the structure of the MC68HC705C8A.
Technical Data
24
MC68HC705C8A — Rev. 3
General Description
MOTOROLA
General Description
Block Diagram
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
EPROM PROGRAMMING
CONTROL
PROGRAM REGISTER
V
PP
EPROM/OTPROM — 7744 BYTES
(144 BYTES CONFIGURABLE)
OPTION
REGISTER
PB0*
PB1*
PB2*
PB3*
PB4*
PB5*
PB6*
PB7*
RAM — 176 BYTES
(304 BYTES MAXIMUM)
BOOT ROM — 240 BYTES
RESET
IRQ
ARITHMETIC
LOGIC UNIT
CPU
CONTROL
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7†
M68HC05 CPU
CPU REGISTERS
ACCUMULATOR
INDEX REGISTER
1
STACK POINTER
0
0
0
0
0
1
PROGRAM COUNTER
PD7
1
1
1
H
I
N Z C
CONDITION CODE REGISTER
RDI (PD0)
TDO (PD1)
MISO (PD2)
MOSI (PD3)
SCK (PD4)
SS (PD5)
SCI
SPI
OSC2
OSC1
INTERNAL
PROCESSOR
CLOCK
÷ 2
OSCILLATOR
COP WATCHDOG
AND
CLOCK MONITOR
BAUD RATE
GENERATOR
V
DD
TCMP
TCAP
POWER
16-BIT
CAPTURE/COMPARE
TIMER SYSTEM
V
SS
* Port B pins also function as external interrupts.
† PC7 has a high current sink and source capability.
Figure 1-2. MC68HC705C8A Block Diagram
MC68HC705C8A — Rev. 3
Technical Data
25
MOTOROLA
General Description
General Description
1.6 Pin Assignments
The MC68HC705C8A is available in six packages:
•
40-pin plastic dual in-line package (PDIP)
40-pin ceramic dual in-line package (cerdip)
44-lead plastic-leaded chip carrier (PLCC)
44-lead ceramic-leaded chip carrier (CLCC)
44-pin quad flat pack (QFP)
•
•
•
•
•
42-pin shrink dual in-line package (SDIP)
The pin assignments for these packages are shown in Figure 1-3,
Figure 1-4, Figure 1-5, and Figure 1-6.
1
2
40
39
38
37
36
35
34
VDD
RESET
IRQ
OSC1
OSC2
TCAP
PD7
3
V
PP
4
PA7
PA6
PA5
PA4
PA3
5
6
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
7
8
33
32
9
PA2
PA1
10
11
12
13
14
15
16
31
30
29
28
27
26
25
24
23
22
PA0
PB0
PB1
PB2
PB3
PC1
PC2
PC3
PB4
PB5
PB6
PC4
17
18
PC5
PC6
PB7
19
20
V
21
PC7
SS
Figure 1-3. 40-Pin PDIP/Cerdip Pin Assignments
Technical Data
26
MC68HC705C8A — Rev. 3
MOTOROLA
General Description
General Description
Pin Assignments
39
38
37
36
35
34
33
32
31
30
29
PD7
PA5
PA4
7
8
9
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
PA3
PA2
PA1
PA0
PB0
PB1
10
11
12
13
14
PB2 15
16
17
PB3
PB4
PC1
PC2
Figure 1-4. 44-Lead PLCC/CLCC Pin Assignments
33 32 31 30 29 28 27 26 25 24 23
PD7
TCAP
OSC2
OSC1
34
35
36
37
38
22 NC
21 PC4
20 PC5
19 PC6
18 PC7
V
DD
NC 39
NC 40
17
V
SS
16 NC
15 PB7
14 PB6
13 PB5
12 PB4
RESET 41
IRQ 42
V
43
PP
44
1
PA7
2
3
4
5
6
7
8
9
10 11
Figure 1-5. 44-Pin QFP Pin Assignments
MC68HC705C8A — Rev. 3
Technical Data
27
MOTOROLA
General Description
General Description
1
2
3
4
5
6
7
8
9
42
V
DD
RESET
IRQ
41 OSC1
40 OSC2
39 TCAP
38 PD7
V
PP
PA7
PA6
PA5
PA4
PA3
PA2
37 TCMP
36 PD5/SS
35 PD4/SCK
34 PD3/MOSI
33 PD2/MISO
32 PD1/TDO
31 PD0/RDI
30 PC0
PA1 10
PA0 11
PB0 12
PB1 13
PB2 14
PB3 15
NC 16
PB4 17
PB5 18
29 PC1
28 PC2
27 NC
26 PC3
25 PC4
PB6
PB7
19
20
21
24 PC5
23
22
PC6
PC7
V
SS
Figure 1-6. 42-Pin SDIP Pin Assignments
Technical Data
28
MC68HC705C8A — Rev. 3
MOTOROLA
General Description
General Description
Pin Functions
1.7 Pin Functions
This subsection describes the MC68HC705C8A signals. Reference is
made, where applicable, to other sections that contain more detail about
the function being performed.
1.7.1 VDD and VSS
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
V+
Very fast signal transitions occur
on the MCU pins, placing high
V
DD
short-duration current demands
on the power supply. To prevent
noise problems, take special care
to provide good power supply
bypassing at the MCU. Place
bypass capacitors as close to the
MCU as possible, as shown in
Figure 1-7.
+
C2
MCU
C1
V
SS
Figure 1-7. Bypassing Layout
Recommendation
1.7.2 VPP
This pin provides the programming voltage to the EPROM array. For
normal operation, VPP shuld be tied to VDD
.
NOTE: Connecting the VPP pin (programming voltage) to VSS (ground) could
result in damage to the MCU.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
29
General Description
General Description
1.7.3 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the 2-pin
on-chip oscillator. The oscillator can be driven by:
•
•
•
Crystal resonator
Ceramic resonator
External clock signal
NOTE: The frequency of the internal oscillator is fOSC. The MCU divides the
internal oscillator output by two to produce the internal clock with a
frequency of fOP.
1.7.3.1 Crystal Resonator
The circuit in Figure 1-8 shows a
crystal oscillator circuit for an AT-cut,
parallel resonant crystal. Follow the
crystal supplier’s recommendations,
because the crystal parameters
determine the external component
values required to provide reliable
startup and maximum stability. The
load capacitance values used in the
oscillator circuit design should
account for all stray layout
MCU
OSC2
OSC1
10 MΩ
XTAL
2 MHz
22 pF
22 pF
Starting value only. Follow crystal supplier’s
recommendations regarding component
values that will provide reliable startup and
maximum stability.
capacitances. To minimize output
distortion, mount the crystal and
capacitors as close as possible to the
pins.
Figure 1-8. Crystal
Connections
NOTE: Use an AT-cut crystal and not a strip or tuning fork crystal. The MCU
might overdrive or have the incorrect characteristic impedance for a strip
or tuning fork crystal.
Technical Data
30
MC68HC705C8A — Rev. 3
General Description
MOTOROLA
General Description
Pin Functions
1.7.3.2 Ceramic Resonator
To reduce cost, use a ceramic
MCU
resonator instead of a crystal. Use the
circuit shown in Figure 1-9 for a 2-pin
ceramic resonator or the circuit shown
in Figure 1-10 for a 3-pin ceramic
resonator, and follow the resonator
manufacturer’s recommendations.
OSC2
OSC1
R
CERAMIC
RESONATOR
C
C
The external component values
required for maximum stability and
reliable starting depend upon the
resonator parameters. The load
Figure 1-9. 2-Pin Ceramic
Resonator Connections
.
capacitance values used in the oscillator circuit design should include all
stray layout capacitances. To minimize output distortion, mount the
resonator and capacitors as close as possible to the pins.
MCU
OSC1
OSC2
CERAMIC
RESONATOR
Figure 1-10. 3-Pin
Ceramic Resonator
Connections
NOTE: The bus frequency (fOP) is one-half the external or crystal frequency
(fOSC), while the processor clock cycle (tCYC) is two times the fOSC
period.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
31
General Description
General Description
1.7.3.3 External Clock Signal
An external clock from another
MCU
CMOS-compatible device can drive the
OSC1 input, with the OSC2 pin
unconnected, as Figure 1-11 shows.
EXTERNAL
CMOS CLOCK
Figure 1-11. External
Clock
NOTE: The bus frequency (fOP) is one-half the external frequency (fOSC) while
the processor clock cycle is two times the fOSC period.
1.7.4 External Reset Pin (RESET)
A logic 0 on the bidirectional RESET pin forces the MCU to a known
startup state. The RESET pin contains an internal Schmitt trigger as part
of its input to improve noise immunity. See Section 5. Resets.
1.7.5 External Interrupt Request Pin (IRQ)
The IRQ pin is an asynchronous external interrupt pin. The IRQ pin
contains an internal Schmitt trigger as part of its input to improve noise
immunity. See 4.3.2 External Interrupt (IRQ).
1.7.6 Input Capture Pin (TCAP)
The TCAP pin is the input capture pin for the on-chip capture/compare
timer. The TCAP pin contains an internal Schmitt trigger as part of its
input to improve noise immunity. See Section 8. Capture/Compare
Timer.
Technical Data
32
MC68HC705C8A — Rev. 3
General Description
MOTOROLA
General Description
Pin Functions
1.7.7 Output Compare Pin (TCMP)
The TCMP pin is the output compare pin for the on-chip
capture/compare timer. See Section 8. Capture/Compare Timer.
1.7.8 Port A I/O Pins (PA7–PA0)
These eight I/O lines comprise port A, a general-purpose, bidirectional
I/O port. The pins are programmable as either inputs or outputs under
software control of the data direction registers. See 7.3 Port A.
1.7.9 Port B I/O Pins (PB7–PB0)
These eight I/O pins comprise port B, a general-purpose, bidirectional
I/O port. The pins are programmable as either inputs or outputs under
software control of the data direction registers. Port B pins also can be
configured to function as external interrupts. See 7.4 Port B.
1.7.10 Port C I/O Pins (PC7–PC0)
These eight I/O pins comprise port C, a general-purpose, bidirectional
I/O port. The pins are programmable as either inputs or outputs under
software control of the data direction registers. PC7 has a high current
sink and source capability. See 7.5 Port C.
1.7.11 Port D I/O Pins (PD7 and PD5–PD0)
These seven lines comprise port D, a fixed input port. All special
functions that are enabled (SPI and SCI) affect this port. See 7.6 Port D.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
General Description
33
General Description
Technical Data
34
MC68HC705C8A — Rev. 3
General Description
MOTOROLA
Technical Data — MC68HC705C8A
Section 2. Memory
2.1 Contents
2.2
2.3
2.4
2.5
2.6
2.7
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Bootloader ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.2 Introduction
2.3 Memory Map
This section describes the organization of the on-chip memory.
The central processor unit (CPU) can address eight Kbytes of memory
and input/output (I/O) registers. The program counter typically advances
one address at a time through memory, reading the program instructions
and data. The programmable read-only memory (PROM) portion of
memory — either one-time programmable read-only memory
(OTPROM) or erasable, programmable read-only memory
(EPROM) — holds the program instructions, fixed data, user-defined
vectors, and interrupt service routines. The random-access memory
(RAM) portion of memory holds variable data.
I/O registers are memory-mapped so that the CPU can access their
locations in the same way that it accesses all other memory locations.
The shared stack area is used during processing of an interrupt or
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Memory
35
Memory
subroutine call to save the CPU state. The stack pointer decrements
during pushes and increments during pulls.
Figure 2-1 is a memory map of the MCU. Addresses $0000–$001F,
shown in Figure 2-2, contain most of the control, status, and data
registers. Additional I/O registers have these addresses:
•
•
•
$1FDF, option register
$1FF0, mask option register 1 (MOR1)
$1FF1, mask option register 2 (MOR2)
2.4 Input/Output (I/O)
The first 32 addresses of memory space, from $0000 to $001F, are the
I/O section. These are the addresses of the I/O control registers, status
registers, and data registers. See Figure 2-2 for more information.
2.5 RAM
One of four selectable memory configurations is selected by the state of
the RAM1 and RAM0 bits in the option register located at $1FDF. Reset
or power-on reset (POR) clears these bits, automatically selecting the
first memory configuration as shown in Table 2-1. See 9.5.1 Option
Register.
Table 2-1. Memory Configurations
RAM0
RAM1
RAM Bytes
176
PROM Bytes
7744
0
1
0
1
0
0
1
1
208
7696
272
7648
304
7600
NOTE: Be careful when using nested subroutines or multiple interrupt levels.
The CPU can overwrite data in the stack RAM during a subroutine or
during the interrupt stacking operation.
Technical Data
36
MC68HC705C8A — Rev. 3
Memory
MOTOROLA
Memory
EPROM/OTPROM (PROM)
2.6 EPROM/OTPROM (PROM)
An MCU with a quartz window has a maximum of 7744 bytes of EPROM.
The quartz window allows the EPROM erasure with ultraviolet light. In
an MCU without a quartz window, the EPROM cannot be erased and
serves a maximum 7744 bytes of OTPROM (see Table 2-1). See
Section 9. EPROM/OTPROM (PROM).
2.7 Bootloader ROM
The 240 bytes at addresses $1F00–$1FEF are reserved ROM
addresses that contain the instructions for the bootloader functions. See
Section 9. EPROM/OTPROM (PROM).
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Memory
37
Memory
$0000
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
PORT D FIXED INPUT PORT
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
UNUSED
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
I/O REGISTERS
32 BYTES
$001F
$0020
UNUSED
16 BYTES
$002F
$0030
USER PROM
48 BYTES
RAM
32 BYTES
UNUSED
$004F
$0050
RAM0 = 1(1)
RAM0 = 0(1)
UNUSED
SPI CONTROL REGISTER
SPI STATUS REGISTER
$00BF
$00C0
RAM
176 BYTES
SPI DATA REGISTER
SCI BAUD RATE REGISTER
SCI CONTROL REGISTER 1
SCI CONTROL REGISTER 2
SCI STATUS REGISTER
STACK
64 BYTES
$00FF
$0100
SCI DATA REGISTER
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE REGISTER (HIGH)
INPUT CAPTURE REGISTER (LOW)
OUTPUT COMPARE REGISTER (HIGH)
OUTPUT COMPARE REGISTER (LOW)
TIMER REGISTER (HIGH)
TIMER REGISTER (LOW)
ALTERNATE TIMER REGISTER (HIGH)
ALTERNATE TIMER REGISTER (LOW)
EPROM PROGRAM REGISTER
COP RESET REGISTER
USER PROM
96 BYTES
RAM
96 BYTES
$015F
$0160
RAM1 = 0(1)
RAM1 = 1(1)
USER PROM
7584 BYTES
$1EFF
$1F00
BOOTLOADER ROM
240 BYTES
$1FDE
$1FDF
$1FE0
COP CONTROL REGISTER
UNUSED
OPTION REGISTER
BOOT ROM VECTORS
16 BYTES
$1FEF
$1FF0
RESERVED
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
MASK OPTION REGISTER 1
MASK OPTION REGISTER 2
RESERVED
SPI INTERRUPT VECTOR (HIGH)
SPI INTERRUPT VECTOR (LOW)
SCI INTERRUPT VECTOR (HIGH)
SCI INTERRUPT VECTOR (LOW)
TIMER INTERRUPT VECTOR (HIGH)
TIMER INTERRUPT VECTOR (LOW)
EXTERNAL INTERRUPT VECTOR (HIGH)
EXTERNAL INTERRUPT VECTOR (LOW)
$1FF1
$1FF2
USER PROM VECTORS
12 BYTES
$1FFF
(1) See 9.5.1 Option Register for information.
SOFTWARE INTERRUPT VECTOR (HIGH) $1FFC
SOFTWARE INTERRUPT VECTOR (LOW)
RESET VECTOR (HIGH)
$1FFD
$1FFE
$1FFF
RESET VECTOR (LOW)
Figure 2-1. Memory Map
Technical Data
38
MC68HC705C8A — Rev. 3
Memory
MOTOROLA
Memory
Bootloader ROM
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Port A Data Register
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
$0000
(PORTA) Write:
See page 78.
Reset:
Read:
Unaffected by reset
PB4 PB3
Unaffected by reset
PC4 PC3
Port B Data Register
PB7
PC7
PB6
PC6
PB5
PB2
PB1
PB0
$0001
$0002
$0003
$0004
$0005
$0006
(PORTB) Write:
See page 81.
Reset:
Read:
Port C Data Register
PC5
SS
PC2
PC1
PC0
RDI
(PORTC) Write:
See page 85.
Reset:
Unaffected by reset
SCK MOSI
Read: PD7
MISO
TDO
Port D Fixed Input Register
(PORTD) Write:
See page 88.
Reset:
Read:
Unaffected by reset
Port A Data Direction
DDRA7 DDRA6 DDRA5 DDRA4
DDRA3
DDRA2 DDRA1 DDRA0
Register (DDRA) Write:
See page 79.
Reset:
0
0
0
0
0
DDRB3
0
0
0
0
Read:
Port B Data Direction
DDRB7 DDRB6 DDRB5 DDRB4
DDRB2 DDRB1 DDRB0
Register (DDRB) Write:
See page 82.
Reset:
0
0
0
0
0
0
0
Read:
Port C Data Direction
DDRC7 DDRC6 DDRC5 DDRC4
DDRC3
0
DDRC2 DDRC1 DDRC0
(DDRC) Write:
See page 86.
Reset:
0
0
0
0
0
0
0
$0007
$0008
$0009
Unimplemented
Unimplemented
Unimplemented
= Unimplemented
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 1 of 4)
MC68HC705C8A — Rev. 3
Technical Data
39
MOTOROLA
Memory
Memory
Addr.
Register Name
Bit 7
SPIE
0
6
5
4
3
CPOL
U
2
CPHA
U
1
SPR1
U
Bit 0
SPR0
U
Read:
SPI Control Register
SPE
MSTR
$000A
(SPCR) Write:
See page 149.
Reset:
0
0
Read: SPIF
WCOL
MODF
SPI Status Register
(SPSR) Write:
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
See page 151.
Reset:
Read:
0
0
0
SPI Data Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
BIt 2
Bit 1
Bit 0
(SPDR) Write:
See page 149.
Reset:
Read:
Unaffected by reset
SCP0
Baud Rate Register
SCP1
0
SCR2
U
SCR1
U
SCR0
U
(Baud) Write:
See page 136.
Reset:
Read:
U
R8
U
U
T8
0
M
U
WAKE
U
SCI Control Register 1
(SCCR1) Write:
See page 130.
Reset:
Read:
U
U
SCI Control Register 2
TIE
0
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
(SCCR2) Write:
See page 131.
Reset:
0
0
0
0
0
0
Read: TDRE
TC
RDRF
IDLE
OR
NF
FE
SCI Status Register
(SCSR) Write:
See page 133.
Reset:
Read:
1
1
0
0
0
0
0
U
SCI Data Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(SCDR) Write:
See page 129.
Reset:
Read:
Unaffected by reset
Timer Control Register
ICIE
0
OCIE
0
TOIE
0
0
0
0
0
0
IEDG
U
OLVL
0
(TCR) Write:
See page 94.
Reset:
0
= Unimplemented
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 2 of 4)
Technical Data
40
MC68HC705C8A — Rev. 3
Memory
MOTOROLA
Memory
Bootloader ROM
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: ICF
OCF
TOF
0
0
0
0
0
Timer Status Register
$0013
(TSR) Write:
See page 96.
Reset:
U
U
U
0
0
0
0
0
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Input Capture Register
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
High (ICRH) Write:
See page 100.
Reset:
Unaffected by reset
Bit 4 Bit 3
Read: Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
Input Capture Register
Low (ICRL) Write:
See page 100.
Reset:
Unaffected by reset
Bit 12 Bit 11
Unaffected by reset
Bit 4 Bit 3
Read:
Bit 15
Write:
Output Compare Register
High (OCRH)
Bit 14
Bit 13
Bit 10
See page 101.
Reset:
Read:
Bit 7
Output Compare Register
Bit 6
Bit 5
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
Low (OCRL) Write:
See page 101.
Reset:
Unaffected by reset
Bit 12 Bit 11
Read: Bit 15
Bit 14
Bit 13
Bit 10
Timer Register High
(TRH) Write:
See page 97.
Reset:
Reset initializes TRH to $FF
Bit 4 Bit 3
Read: Bit 7
Bit 6
Bit 14
Bit 6
Bit 5
Bit 13
Bit 5
Bit 2
Bit 10
Bit 2
Bit 1
Bit 9
Bit 1
Bit 0
Bit 8
Bit 0
Timer Register Low
(TRL) Write:
See page 97.
Reset:
Reset initializes TRL to $FC
Bit 12 Bit 11
Read: Bit 15
Alternate Timer Register
High (ATRH) Write:
See page 99.
Reset:
Reset initializes ATRH to $FF
Bit 4 Bit 3
Read: Bit 7
Alternate Timer Register
Low (ATRL) Write:
See page 99.
Reset:
Reset initializes ATRL to $FC
U = Unaffected
= Unimplemented
Figure 2-2. I/O Register Summary (Sheet 3 of 4)
MC68HC705C8A — Rev. 3
Technical Data
41
MOTOROLA
Memory
Memory
Addr.
Register Name
Bit 7
6
0
0
5
0
0
4
0
0
3
0
0
2
LAT
0
1
0
0
Bit 0
PGM
0
Read:
EPROM Programming
0
0
$001C
Register (PROG) Write:
See page 109.
Reset:
Read:
Programmable COP Reset
$001D
Register (COPRST) Write: Bit 7
See page 64.
Bit 6
U
Bit 5
U
Bit 4
U
Bit 3
U
Bit 2
U
Bit 1
U
Bit 0
U
Reset:
U
Read:
0
0
0
COPF
Programmable COP Control
CME
0
PCOPE
0
CM1
0
CM0
0
$001E
$001F
Register (COPCR) Write:
See page 64.
Reset:
0
0
0
U
Unimplemented
Read:
Option Register
RAM0
0
RAM1
0
0
0
0
0
SEC*
IRQ
1
0
0
$1FDF
(Option) Write:
See page 116.
Reset:
*
U
*Implemented as an EPROM cell
Mask Option Register 1
Read:
PBPU0/
COPC
PBPU7 PBPU6 PBPU5 PBPU4
PBPU3
PBPU2 PBPU1
$1FF0
(MOR1) Write:
See page 117.
Reset:
Read:
Unaffected by reset
Mask Option Register 2
NCOPE
$1FF1
(MOR2) Write:
See page 118.
Reset:
Unaffected by reset
U = Unaffected
= Unimplemented
Figure 2-2. I/O Register Summary (Sheet 4 of 4)
Technical Data
42
MC68HC705C8A — Rev. 3
Memory
MOTOROLA
Technical Data — MC68HC705C8A
Section 3. Central Processor Unit (CPU)
3.1 Contents
3.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.2 Introduction
This section describes the central processor unit (CPU) registers.
MC68HC705C8A — Rev. 3
Technical Data
43
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
3.3 CPU Registers
Figure 3-1 shows the five CPU registers. These are hard-wired registers
within the CPU and are not part of the memory map.
Bit 7
Bit 7
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
ACCUMULATOR (A)
INDEX REGISTER (X)
Bit 12 11 10
9
0
8
0
7
1
6
1
0
0
0
STACK POINTER (SP)
Bit 12 11 10
9
8
7
6
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
Bit 7
1
6
1
5
1
4
3
I
2
1
Bit 0
C
H
N
Z
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 3-1. Programming Model
Technical Data
44
MC68HC705C8A — Rev. 3
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
CPU Registers
3.3.1 Accumulator
The accumulator (A) shown in Figure 3-2 is a general-purpose 8-bit
register. The CPU uses the accumulator to hold operands and results of
arithmetic and non-arithmetic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-2. Accumulator (A)
3.3.2 Index Register
In the indexed addressing modes, the CPU uses the byte in the index
register (X) shown in Figure 3-3 to determine the conditional address of
the operand. See 12.3.5 Indexed, No Offset, 12.3.6 Indexed, 8-Bit
Offset, and 12.3.7 Indexed, 16-Bit Offset for more information on
indexed addressing.
The 8-bit index register also can serve as a temporary data storage
location.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-3. Index Register (X)
MC68HC705C8A — Rev. 3
Technical Data
45
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
3.3.3 Stack Pointer
The stack pointer (SP) shown in Figure 3-4 is a 13-bit register that
contains the address of the next free location on the stack. During a reset
or after the reset stack pointer (RSP) instruction, the stack pointer
initializes to $00FF. The address in the stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
The seven most significant bits of the stack pointer are fixed
permanently at 0000011, so the stack pointer produces addresses from
$00C0 to $00FF. If subroutines and interrupts use more than 64 stack
locations, the stack pointer wraps around to address $00FF and begins
writing over the previously stored data. A subroutine uses two stack
locations. An interrupt uses five locations.
Bit 12
0
11
0
10
0
9
0
8
0
7
1
6
1
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
0
0
0
0
0
1
1
1
1
1
1
1
1
= Unimplemented
Figure 3-4. Stack Pointer (SP)
3.3.4 Program Counter
The program counter (PC) shown in Figure 3-5 is a 13-bit register that
contains the address of the next instruction or operand to be fetched.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Bit 12
Read:
11
10
9
8
7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Loaded with reset vector from $1FFE and $1FFF
Figure 3-5. Program Counter (PC)
Technical Data
46
MC68HC705C8A — Rev. 3
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
CPU Registers
3.3.5 Condition Code Register
The condition code register (CCR) shown in Figure 3-6 is an 8-bit
register whose three most significant bits are permanently fixed at 111.
The condition code register contains the interrupt mask and four bits that
indicate the results of prior instructions.
Bit 7
1
6
1
5
1
4
3
I
2
1
Bit 0
C
Read:
Write:
Reset:
H
U
N
U
Z
U
1
1
1
1
U
= Unimplemented
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
H — Half-Carry Bit
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry bit is required for
binary-coded decimal (BCD) arithmetic operations. Reset has no
affect on the half-carry flag.
I — Interrupt Mask Bit
Setting the interrupt mask (I) disables interrupts. If an interrupt
request occurs while the interrupt mask is a logic 0, the CPU saves
the CPU registers on the stack, sets the interrupt mask, and then
fetches the interrupt vector. If an interrupt request occurs while the
interrupt mask is set, the interrupt request is latched. The CPU
processes the latched interrupt as soon as the interrupt mask is
cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a CLI,
STOP, or WAIT instruction.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Central Processor Unit (CPU)
47
Central Processor Unit (CPU)
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result (bit 7 in the
results is a logic 1). Reset has no effect on the negative flag.
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00. Reset has
no effect on the zero flag.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow bit. Reset
has no effect on the carry/borrow flag.
3.4 Arithmetic/Logic Unit (ALU)
The arithmetic/logic unit (ALU) performs the arithmetic and logical
operations defined by the instruction set. The binary arithmetic circuits
decode instructions and set up the ALU for the selected operation. Most
binary arithmetic is based on the addition algorithm, carrying out
subtraction as negative addition. Multiplication is not performed as a
discrete operation but as a chain of addition and shift operations within
the ALU. The multiply instruction requires 11 internal clock cycles to
complete this chain of operations.
Technical Data
48
MC68HC705C8A — Rev. 3
Central Processor Unit (CPU)
MOTOROLA
Technical Data — MC68HC705C8A
Section 4. Interrupts
4.1 Contents
4.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Capture/Compare Timer Interrupts . . . . . . . . . . . . . . . . . . .55
SCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.2 Introduction
This section describes how interrupts temporarily change the normal
processing sequence.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Interrupts
49
Interrupts
4.3 Interrupt Sources
These sources can generate interrupts:
•
•
•
•
Software instructions (SWI)
External interrupt pin (IRQ)
Port B pins
Serial communications interface (SCI):
– SCI transmit data register empty
– SCI transmission complete
– SCI receive data register full
– SCI receiver overrun
– SCI receiver input idle
Serial peripheral interface (SPI):
– SPI transmission complete
– SPI mode fault
•
– SPI overrun
The IRQ pin, port B pins, SCI, and SPI can be masked (disabled) by
setting the I bit of the condition code register (CCR). The software
interrupt (SWI) instruction is non-maskable.
An interrupt temporarily changes the program sequence to process a
particular event. An interrupt does not stop the execution of the
instruction in progress but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
central processor unit (CPU) registers on the stack and loads the
program counter with a user-defined vector address.
4.3.1 Software Interrupt
The software interrupt instruction (SWI) causes a non-maskable
interrupt.
Technical Data
50
MC68HC705C8A — Rev. 3
MOTOROLA
Interrupts
Interrupts
Interrupt Sources
4.3.2 External Interrupt (IRQ)
An interrupt signal on the IRQ pin latches an external interrupt request.
After completing the current instruction, the CPU tests these bits:
•
•
IRQ latch
I bit in the CCR
Setting the I bit in the CCR disables external interrupts.
If the IRQ latch is set and the I bit is clear, the CPU then begins the
interrupt sequence. The CPU clears the IRQ latch while it fetches the
interrupt vector, so that another external interrupt request can be latched
during the interrupt service routine. As soon as the I bit is cleared during
the return-from-interrupt (RTI) instruction, the CPU can recognize the
new interrupt request. Figure 4-1 shows the logic for external interrupts.
Figure 4-1 shows an external interrupt functional diagram. Figure 4-2
shows an external interrupt timing diagram for the interrupt line. The
timing diagram illustrates two treatments of the interrupt line to the
processor.
1. Two single pulses on the interrupt line are spaced far enough
apart to be serviced. The minimum time between pulses is a
function of the length of the interrupt service.
Once a pulse occurs, the next pulse normally should not occur
until an RTI occurs. This time (tILIL) is obtained by adding 19
instruction cycles to the total number of cycles needed to complete
the service routine (not including the RTI instruction).
2. Many interrupt lines are “wire-ORed” to the IRQ line. If the interrupt
line remains low after servicing an interrupt, then the CPU
continues to recognize an interrupt.
NOTE: The internal interrupt latch is cleared in the first part of the interrupt
service routine. Therefore, a new external interrupt pulse could be
latched and serviced as soon as the I bit is cleared.
If the IRQ pin is not in use, connect it to the VDD pin.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
51
Interrupts
Interrupts
EDGE- AND LEVEL-SENSITIVE TRIGGER
OPTION REGISTER
V
DD
EXTERNAL
INTERRUPT
REQUEST
D
Q
I BIT (CCR)
IRQ LATCH
INTERRUPT PIN
C
Q
POR
R
INTERNAL RESET (COP)
EXTERNAL RESET
EXTERNAL INTERRUPT BEING SERVICED
(VECTOR FETCH)
Figure 4-1. External Interrupt Internal Function Diagram
tILIL
t
IRQ PIN
ILIH
a. Edge-Sensitive Trigger Condition. The minimum pulse width (t ) is either 125 ns (f = 2.1 MHz)
ILIH
OP
or 250 ns (f = 1 MHz). The period t
should not be less than the number of t cycles it takes to
OP
ILIL
CYC
execute the interrupt service routine plus 19 t
cycles.
CYC
tILIH
IRQ1
.
.
.
NORMALLY
USED WITH
WIRED-OR
IRQn
CONNECTION
IRQ
(INTERNAL)
b. Level-Sensitive Trigger Condition. If the interrupt line remains low after servicing an interrupt, then the
CPU continues to recognize an interrupt.
Figure 4-2. External Interrupt Timing
Technical Data
52
MC68HC705C8A — Rev. 3
MOTOROLA
Interrupts
Interrupts
Interrupt Sources
4.3.3 Port B Interrupts
When these three conditions are true, a port B pin (PBx) acts as an
external interrupt pin:
•
•
•
The corresponding port B pullup bit (PBPUx) in mask option
register 1 (MOR1) is programmed to a logic 1.
The corresponding port B data direction bit (DDRBx) in data
direction register B (DDRB) is a logic 0.
The clear interrupt mask (CLI) instruction has cleared the I bit in
the CCR.
MOR1 is an erasable, programmable read-only memory (EPROM)
register that enables the port B pullup device. Data from MOR1 is
latched on the rising edge of the voltage on the RESET pin. See 9.5.2
Mask Option Register 1.
Port B external interrupt pins can be falling-edge sensitive only or both
falling-edge and low-level sensitive, depending on the state of the IRQ
bit in the option register at location $1FDF.
When the IRQ bit is a logic 1, a falling edge or a low level on a port B
external interrupt pin latches an external interrupt request. As long as
any port B external interrupt pin is low, an external interrupt request is
present, and the CPU continues to execute the interrupt service routine.
When the IRQ bit is a logic 0, a falling-edge only on a port B external
interrupt pin latches an external interrupt request. A subsequent port B
external interrupt request can be latched only after the voltage level of
the previous port B external interrupt signal returns to a logic 1 and then
falls again to a logic 0.
Figure 4-3 shows the port B input/output (I/O) logic.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Interrupts
53
Interrupts
V
DD
PBPU7
FROM MOR1
READ $0005
WRITE $0005
RESET
DATA DIRECTION
REGISTER B
BIT DDRB7
PORT B DATA
REGISTER
BIT PB7
WRITE $0001
PB7
READ $0001
IRQ
FROM OPTION
REGISTER
VDD
EXTERNAL
INTERRUPT
REQUEST
D
Q
Q
FROM OTHER
PORT B PINS
C
R
I BIT
FROM CCR
IRQ
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Figure 4-3. Port B I/O Logic
Technical Data
54
MC68HC705C8A — Rev. 3
Interrupts
MOTOROLA
Interrupts
Interrupt Sources
4.3.4 Capture/Compare Timer Interrupts
Setting the I bit in the CCR disables all interrupts except for SWI.
4.3.5 SCI Interrupts
The serial communications interface (SCI) can generate these
interrupts:
•
•
•
•
•
Transmit data register empty interrupt
Transmission complete interrupt
Receive data register full interrupt
Receiver overrun interrupt
Receiver input idle interrupt
Setting the I bit in the CCR disables all SCI interrupts.
• SCI Transmit Data Register Empty Interrupt — The transmit
data register empty bit (TDRE) indicates that the SCI data register
is ready to receive a byte for transmission. TDRE becomes set
when data in the SCI data register transfers to the transmit shift
register. TDRE generates an interrupt request if the transmit
interrupt enable bit (TIE) is set also.
• SCI Transmission Complete Interrupt — The transmission
complete bit (TC) indicates the completion of an SCI transmission.
TC becomes set when the TDRE bit becomes set and no data,
preamble, or break character is being transmitted. TC generates
an interrupt request if the transmission complete interrupt enable
bit (TCIE) is set also.
• SCI Receive Data Register Full Interrupt — The receive data
register full bit (RDRF) indicates that a byte is ready to be read in
the SCI data register. RDRF becomes set when the data in the
receive shift register transfers to the SCI data register. RDRF
generates an interrupt request if the receive interrupt enable bit
(RIE) is set also.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Interrupts
55
Interrupts
• SCI Receiver Overrun Interrupt — The overrun bit (OR)
indicates that a received byte is lost because software has not
read the previously received byte. OR becomes set when a byte
shifts into the receive shift register before software reads the word
already in the SCI data register. OR generates an interrupt
request if the receive interrupt enable bit (RIE) is set also.
• SCI Receiver Input Idle Interrupt — The receiver input idle bit
(IDLE) indicates that the SCI receiver input is not receiving data.
IDLE becomes set when 10 or 11 consecutive logic 1s appear on
the receiver input. IDLE generates an interrupt request if the idle
line interrupt enable bit (ILIE) is set also.
4.3.6 SPI Interrupts
The serial peripheral interrupt (SPI) can generate these interrupts:
•
•
SPI transmission complete interrupt
SPI mode fault interrupt
Setting the I bit in the CCR disables all SPI interrupts.
• SPI Transmission Complete Interrupt — The SPI flag bit (SPIF)
in the SPI status register indicates the completion of an SPI
transmission. SPIF becomes set when a byte shifts into or out of
the SPI data register. SPIF generates an interrupt request if the
SPIE bit is set also.
• SPI Mode Fault Interrupt — The mode fault bit (MODF) in the SPI
status register indicates an SPI mode error. MODF becomes set
when a logic 0 occurs on the PD5/SS pin while the master bit
(MSTR) in the SPI control register is set. MODF generates an
interrupt request if the SPIE bit is set also.
Technical Data
56
MC68HC705C8A — Rev. 3
Interrupts
MOTOROLA
Interrupts
Interrupt Processing
4.4 Interrupt Processing
The CPU takes these actions to begin servicing an interrupt:
1. Stores the CPU registers on the stack in the order shown in
Figure 4-4
2. Sets the I bit in the CCR to prevent further interrupts
3. Loads the program counter with the contents of the appropriate
interrupt vector locations as shown in Table 4-1.
Table 4-1. Reset/Interrupt Vector Addresses
Local
Mask
Global
Mask
Priority
(1 = Highest)
Function
Source
Vector Address
Power-on
logic
Reset
None
None
1
$1FFE–$1FFF
RESET pin
Software
interrupt
(SWI)
Same priority
as any
instruction
User code
None
None
None
I bit
$1FFC–$1FFD
$1FFA–$1FFB
IRQ pin
Port B pins
ICF bit
External
interrupt
2
3
ICIE bit
OCIE bit
TOIE bit
Timer
interrupts
OCF bit
TOF bit
I bit
$1FF8–$1FF9
TDRE bit
TC bit
TCIE bit
SCI
interrupts
RDRF bit
OR bit
I bit
I bit
4
5
$1FF6–$1FF7
$1FF4–$1FF5
RIE bit
ILIE bit
SPIE
IDLE bit
SPIF bit
MODF bit
SPI
interrupts
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-4.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Interrupts
57
Interrupts
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
•
•
•
•
•
•
UNSTACKING
ORDER
5
4
3
2
1
1
2
3
4
5
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
•
•
STACKING
ORDER
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 4-4. Interrupt Stacking Order
NOTE: If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit. See Table 4-1 for a priority
listing.
Figure 4-5 shows the sequence of events caused by an interrupt.
Technical Data
58
MC68HC705C8A — Rev. 3
Interrupts
MOTOROLA
Interrupts
Interrupt Processing
FROM
RESET
I BIT IN
CCR REGISTER
SET?
YES
NO
EXTERNAL
IRQ
INTERRUPT?
YES
YES
CLEAR IRQ REQUEST LATCH
NO
TIMER
INTERRUPT?
NO
YES
YES
SCI
INTERRUPT?
NO
SPI
INTERRUPT?
NO
1. STACK PC, X, A, CCR
2. SET I BIT
3. LOAD PC WITH VECTOR
SWI: $1FFC–$1FFD
IRQ: $1FFA–$1FFB
TIMER: $1FF8–$1FF9
SCI: $1FF6–$1FF7
SPI: $1FF4–$1FF5
FETCH NEXT
INSTRUCTION
YES
YES
SWI
INSTRUCTION?
NO
RTI
INSTRUCTION?
RESTORE REGISTERS FROM STACK:
CCR, A, X, PC
NO
EXECUTE INSTRUCTION
Figure 4-5. Reset and Interrupt Processing Flowchart
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
59
Interrupts
Interrupts
Technical Data
60
MC68HC705C8A — Rev. 3
Interrupts
MOTOROLA
Technical Data — MC68HC705C8A
Section 5. Resets
5.1 Contents
5.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.3
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Programmable and Non-Programmable
5.3.1
5.3.2
5.3.3
COP Watchdog Resets . . . . . . . . . . . . . . . . . . . . . . . . . .62
Programmable COP Watchdog Reset . . . . . . . . . . . . . . .63
Non-Programmable COP Watchdog . . . . . . . . . . . . . . . .66
Clock Monitor Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.3.3.1
5.3.3.2
5.3.4
5.2 Introduction
This section describes how resets initialize the microcontroller unit
(MCU).
5.3 Reset Sources
A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user-defined reset vector address. These conditions produce a
reset:
•
•
•
Power-on reset (POR) — Initial power-up
External reset — A logic 0 applied to the RESET pin
Internal programmable computer operating properly (COP)
watchdog timer reset
•
•
Internal non-programmable COP watchdog timer reset
Internal clock monitor reset
MC68HC705C8A — Rev. 3
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Resets
Resets
5.3.1 Power-On Reset (POR)
A positive transition on the VDD pin generates a power-on reset (POR).
The POR is strictly for the power-up condition and cannot be used to
detect drops in power supply voltage.
A 4064 tCYC (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at
logic 0 at the end of 4064 tCYC, the MCU remains in the reset condition
until the signal on the RESET pin goes to logic 1.
5.3.2 External Reset
The minimum time required for the MCU to recognize a reset is 1 1/2
tCYC. However, to guarantee that the MCU recognizes an external reset
as an external reset and not as a COP or clock monitor reset, the RESET
pin must be low for eight tCYC. After six tCYC, the input on the RESET pin
is sampled. If the pin is still low, an external reset has occurred. If the
input is high, then the MCU assumes that the reset was initiated
internally by either the COP watchdog timer or by the clock monitor. This
method of differentiating between external and internal reset conditions
assumes that the RESET pin will rise to a logic 1 less than two tCYC after
its release and that an externally generated reset should stay active for
at least eight tCYC
.
5.3.3 Programmable and Non-Programmable COP Watchdog Resets
A timeout of a COP watchdog generates a COP reset. A COP watchdog,
once enabled, is part of a software error detection system and must be
cleared periodically to start a new timeout period.
The MC68HC705C8A has two different COP watchdogs for compatibility
with devices such as the MC68HC705C8 and the MC68HC05C4A:
1. Programmable COP watchdog reset
2. Non-programmable COP watchdog
One COP has four programmable timeout periods and the other has a
fixed non-programmable timeout period.
Technical Data
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MC68HC705C8A — Rev. 3
Resets
MOTOROLA
Resets
Reset Sources
5.3.3.1 Programmable COP Watchdog Reset
A timeout of the 18-stage ripple counter in the programmable COP
watchdog generates a reset. Figure 5-1 is a diagram of the
programmable COP watchdog. Two registers control and monitor
operation of the programmable COP watchdog:
•
•
COP reset register (COPRST), $001D
COP control register (COPCR), $001E
To clear the programmable COP watchdog and begin a new timeout
period, write these values to the COP reset register (COPRST).
See Figure 5-2.
1. $55
2. $AA
The $55 write must precede the $AA write. Instructions may be executed
between the write operations provided that the COP watchdog does not
time out before the second write.
PROGRAMMABLE COP WATCHDOG (MC68HC705C8 TYPE)
INTERNAL
CLOCK
÷4
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
(fOP
)
213
CM0
CM1
215
217
219
221
RESET
PCOPE
÷ 4
÷ 2 ÷ 2
÷ 2 ÷ 2
÷ 2 ÷ 2
COPRST
Figure 5-1. Programmable COP Watchdog Diagram
MC68HC705C8A — Rev. 3
Technical Data
63
MOTOROLA
Resets
Resets
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Bit 7
U
6
5
4
3
2
1
Bit 0
U
Reset:
U
U
U
U
U
U
= Unimplemented
U = Unaffected
Figure 5-2. Programmable COP Reset Register (COPRST)
The programmable COP control register (COPCR) shown in Figure 5-3
does these functions:
•
•
•
•
Flags programmable COP watchdog resets
Enables the clock monitor
Enables the programmable COP watchdog
Controls the timeout period of the programmable COP watchdog
Address: $001E
Bit 7
6
0
5
0
4
3
2
1
Bit 0
CM0
Read:
Write:
Reset:
0
COPF
CME
PCOPE
CM1
0
0
0
U
0
0
0
0
= Unimplemented
U = Unaffected
Figure 5-3. Programmable COP Control Register (COPCR)
COPF — COP Flag
This read-only bit is set when a timeout of the programmable COP
watchdog occurs or when the clock monitor detects a slow or absent
internal clock. Clear the COPF bit by reading the COP control register.
Reset has no effect on the COPF bit.
1 = COP timeout or internal clock failure
0 = No COP timeout and no internal clock failure
Technical Data
64
MC68HC705C8A — Rev. 3
Resets
MOTOROLA
Resets
Reset Sources
CME — Clock Monitor Enable Bit
This read/write bit enables the clock monitor. The clock monitor sets
the COPF bit and generates a reset if it detects an absent internal
clock for a period of from 5 µs to 100 µs. CME is readable and writable
at any time. Reset clears the CME bit.
1 = Clock monitor enabled
0 = Clock monitor disabled
NOTE: Do not enable the clock monitor in applications with an internal clock
frequency of 200 kHz or less.
If the clock monitor detects a slow clock, it drives the bidirectional
RESET pin low for four clock cycles. If the clock monitor detects an
absent clock, it drives the RESET pin low until the clock recovers.
PCOPE — Programmable COP Enable Bit
This read/write bit enables the programmable COP watchdog.
PCOPE is readable at any time but can be written only once after
reset. Reset clears the PCOPE bit.
1 = Programmable COP watchdog enabled
0 = Programmable COP watchdog disabled
NOTE: Programming the non-programmable COP enable bit (NCOPE) in mask
option register 2 (MOR2) to logic 1 enables the non-programmable COP
watchdog. Setting the PCOPE bit while the NCOPE bit is programmed
to logic 1 enables both COP watchdogs to operate at the same time.
(See 9.5.3 Mask Option Register 2.)
CM1 and CM0 — COP Mode Bits
These read/write bits select the timeout period of the programmable
COP watchdog. (See Table 5-1.) CM1 and CM0 can be read anytime
but can be written only once. They can be cleared only by reset.
Bits 7–5 — Unused
Bits 7–5 always read as logic 0s. Reset clears bits 7–5.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
65
Resets
Resets
Table 5-1. Programmable COP Timeout Period Selection
Programmable COP Timeout Period
COP
CM1:CM0
f
= 4.0 MHz
= 2.0 MHz
f
= 3.5795 MHz
= 1.7897 MHz
f
= 2.0 MHz
= 1.0 MHz
f
= 1.0 MHz
= 0.5 MHz
Timeout Rate
OSC
OSC
OSC
OSC
f
f
f
f
OP
OP
OP
OP
15
00
01
10
11
16.38 ms
65.54 ms
262.14 ms
1.048 s
18.31 ms
73.24 ms
292.95 ms
1.172 s
32.77 ms
131.07 ms
524.29 ms
2.097 s
65.54 ms
262.14 ms
1.048 s
f
f
f
f
÷ 2
÷ 2
÷ 2
÷ 2
OP
OP
OP
OP
17
19
21
4.194 s
5.3.3.2 Non-Programmable COP Watchdog
A timeout of the 18-stage ripple counter in the non-programmable COP
watchdog generates a reset. The timeout period is 65.536 ms when
fOSC = 4 MHz. The timeout period for the non-programmable COP timer
is a direct function of the crystal frequency. The equation is:
262,144
Timeout period =
fOSC
Two memory locations control operation of the non-programmable COP
watchdog:
1. Non-programmable COP enable bit (NCOPE) in mask option
register 2 (MOR2)
Programming the NCOPE bit in MOR2 to a logic 1 enables the
non-programmable COP watchdog. See 9.5.3 Mask Option
Register 2.
NOTE: Writing a logic 1 to the programmable COP enable bit (PCOPE) in the
COP control register enables the programmable COP watchdog. Setting
the PCOPE bit while the NCOPE bit is programmed to logic 1 enables
both COP watchdogs to operate at the same time.
Technical Data
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MC68HC705C8A — Rev. 3
Resets
MOTOROLA
Resets
Reset Sources
2. COP clear bit (COPC) at address $1FF0
To clear the non-programmable COP watchdog and start a new
COP timeout period, write a logic 0 to bit 0 of address $1FF0.
Reading address $1FF0 returns the mask option register 1
(MOR1) data at that location. See 9.5.2 Mask Option Register 1.
NOTE: The non-programmable watchdog COP is disabled in bootloader mode,
even if the NCOPE bit is programmed.
Figure 5-4 is a diagram of the non-programmable COP.
NON-PROGRAMMABLE COP WATCHDOG (MC68HC05C4A TYPE)
NCOPE
÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2
÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2
Figure 5-4. Non-Programmable COP Watchdog Diagram
5.3.4 Clock Monitor Reset
When the CME bit in the COP control register is set, the clock monitor
detects the absence of the internal bus clock for a certain period of time.
The timeout period depends on processing parameters and varies from
5 µs to 100 µs, which implies that systems using a bus clock rate of
200 kHz or less should not use the clock monitor function.
If a slow or absent clock is detected, the clock monitor causes a system
reset. The reset is issued to the external system for four bus cycles using
the bidirectional RESET pin.
Special consideration is required when using the STOP instruction with
the clock monitor. Since STOP causes the system clocks to halt, the
clock monitor issues a system reset when STOP is executed.
MC68HC705C8A — Rev. 3
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Resets
67
Resets
The clock monitor is a useful backup to the COP watchdog system.
Because the watchdog timer requires a clock to function, it cannot
indicate a system clock failure. The clock monitor would detect such a
condition and force the MCU to a reset state. Clocks are not required for
the MCU to reach a reset condition. They are, however, required to bring
the MCU through the reset sequence and back to run condition.
Technical Data
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MC68HC705C8A — Rev. 3
Resets
MOTOROLA
Technical Data — MC68HC705C8A
Section 6. Low-Power Modes
6.1 Contents
6.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
SCI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
SPI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Programmable COP Watchdog in Stop Mode . . . . . . . . . . .71
Non-Programmable COP Watchdog in Stop Mode . . . . . . .73
6.3.1
6.3.2
6.3.3
6.3.4
6.4
6.4.1
6.4.2
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Programmable COP Watchdog in Wait Mode . . . . . . . . . . .75
Non-Programmable COP Watchdog in Wait Mode . . . . . . .75
6.5
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.2 Introduction
This section describes the three low-power modes:
•
•
•
Stop mode
Wait mode
Data-retention mode
6.3 Stop Mode
The STOP instruction places the microcontroller unit (MCU) in its lowest
power consumption mode. In stop mode, the internal oscillator is turned
off, halting all internal processing including timer, serial communications
interface (SCI), and master mode serial peripheral interface (SPI)
operation. See Figure 6-1.
MC68HC705C8A — Rev. 3
Technical Data
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Low-Power Modes
69
Low-Power Modes
STOP
WAIT
OSCILLATOR ACTIVE
TIMER, SCI, AND SPI
CLOCKS ACTIVE
CPU CLOCKS STOPPED
CLEAR I BIT
STOP OSCILLATOR
AND ALL CLOCKS
CLEAR I BIT
NO
NO
RESET
YES
RESET
YES
EXTERNAL
INTERRUPT
(IRQ)
NO
EXTERNAL
INTERRUPT
(IRQ)
NO
YES
YES
INTERNAL TIMER
INTERRUPT
YES
NO
TURN ON OSCILLATOR
WAIT FOR TIME
DELAY TO STABILIZE
RESTART CPU CLOCK
YES
INTERNAL SCI
INTERRUPT
NO
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. STACK
b. SET I BIT
c. VECTOR TO
INTERRUPT ROUTINE
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. STACK
NO
YES
INTERNAL SPI
INTERRUPT
b. SET I BIT
c. VECTOR TO
INTERRUPT ROUTINE
Figure 6-1. Stop/Wait Mode Function Flowchart
During stop mode, the I bit in the condition code register (CCR) is
cleared to enable external interrupts. All other registers and memory
remain unaltered. All input/output (I/O) lines remain unchanged. The
processor can be brought out of stop mode only by an external interrupt
or reset.
Technical Data
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MC68HC705C8A — Rev. 3
Low-Power Modes
MOTOROLA
Low-Power Modes
Stop Mode
6.3.1 SCI During Stop Mode
When the MCU enters stop mode, the baud rate generator stops, halting
all SCI activity. If the STOP instruction is executed during a transmitter
transfer, that transfer is halted. If a low input to the IRQ pin is used to exit
stop mode, the transfer resumes.
If the SCI receiver is receiving data and stop mode is entered, received
data sampling stops because the baud rate generator stops, and all
subsequent data is lost. Therefore, all SCI transfers should be in the idle
state when the STOP instruction is executed.
6.3.2 SPI During Stop Mode
When the MCU enters stop mode, the baud rate generator stops,
terminating all master mode SPI operations. If the STOP instruction is
executed during an SPI transfer, that transfer halts until the MCU exits
stop mode by a low signal on the IRQ pin. If reset is used to exit stop
mode, the SPI control and status bits are cleared, and the SPI is
disabled.
If the MCU is in slave mode when the STOP instruction is executed, the
slave SPI continues to operate and can still accept data and clock
information in addition to transmitting its own data back to a master
device. At the end of a possible transmission with a slave SPI in stop
mode, no flags are set until a low on the IRQ pin wakes up the MCU.
NOTE: Although a slave SPI in stop mode can exchange data with a master SPI,
the status bits of a slave SPI are inactive in stop mode.
6.3.3 Programmable COP Watchdog in Stop Mode
The STOP instruction turns off the internal oscillator and suspends the
computer operating properly (COP) watchdog counter. If the RESET pin
brings the MCU out of stop mode, the reset function clears and disables
the COP watchdog.
If the IRQ pin brings the MCU out of stop mode, the COP counter
resumes counting from its suspended value after the 4064-tCYC clock
stabilization delay. See Figure 6-2.
MC68HC705C8A — Rev. 3
Technical Data
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Low-Power Modes
Low-Power Modes
NOTE: If the clock monitor is enabled (CME = 1), the STOP instruction causes
the clock monitor to time out and reset the MCU.
STOP
CLEAR I BIT IN CCR
TURN OFF INTERNAL OSCILLATOR
SUSPEND COP COUNTER
YES
EXTERNAL
RESET?
NO
NO
EXTERNAL
INTERRUPT?
TURN ON INTERNAL OSCILLATOR
CLEAR COP COUNTER
CLEAR PCOPE BIT IN COPCR
YES
TURN ON INTERNAL OSCILLATOR
END OF
STABILIZATION
DELAY?
YES
NO
YES
END OF
STABILIZATION
DELAY?
NO
TURN ON INTERNAL CLOCK
TURN ON INTERNAL CLOCK
RESUME COP WATCHDOG COUNT
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
Figure 6-2. Programmable COP Watchdog
in Stop Mode (PCOPE = 1) Flowchart
Technical Data
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MC68HC705C8A — Rev. 3
MOTOROLA
Low-Power Modes
Low-Power Modes
Wait Mode
6.3.4 Non-Programmable COP Watchdog in Stop Mode
The STOP instruction has these effects on the non-programmable COP
watchdog:
•
•
Turns off the oscillator and the COP watchdog counter
Clears the COP watchdog counter
If the RESET pin brings the MCU out of stop mode, the COP watchdog
begins counting immediately. The reset function clears the COP counter
again after the 4064-tCYC clock stabilization delay.
If the IRQ pin brings the MCU out of stop mode, the COP watchdog
begins counting immediately. The IRQ function does not clear the
COP counter again after the 4064-tCYC clock stabilization delay. See
Figure 6-3.
NOTE: If the clock monitor is enabled (CME = 1), the STOP instruction causes
it to time out and reset the MCU.
6.4 Wait Mode
The WAIT instruction places the MCU in an intermediate power
consumption mode. All central processor unit (CPU) activity is
suspended, but the oscillator, capture/compare timer, SCI, and SPI
remain active. Any interrupt or reset brings the MCU out of wait mode.
See Figure 6-1.
The WAIT instruction has these effects on the CPU:
•
•
Clears the I bit in the condition code register, enabling interrupts
Stops the CPU clock, but allows the internal clock to drive the
capture/compare timer, SCI, and SPI
The WAIT instruction does not affect any other registers or I/O lines. The
capture/compare timer, SCI, and SPI can be enabled to allow a periodic
exit from wait mode.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Low-Power Modes
73
Low-Power Modes
STOP
CLEAR I BIT IN CCR
CLEAR COP COUNTER
TURN OFF INTERNAL OSCILLATOR
TURN OFF COP COUNTER
YES
EXTERNAL
RESET?
NO
NO
EXTERNAL
INTERRUPT?
TURN ON INTERNAL OSCILLATOR
TURN ON COP WATCHDOG
YES
TURN ON INTERNAL OSCILLATOR
TURN ON COP WATCHDOG
END OF
STABILIZATION
DELAY?
YES
NO
YES
END OF
STABILIZATION
DELAY?
NO
CLEAR COP COUNTER
TURN ON INTERNAL CLOCK
TURN ON INTERNAL CLOCK
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
Figure 6-3. Non-Programmable COP Watchdog
in Stop Mode (NCOPE = 1) Flowchart
Technical Data
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MC68HC705C8A — Rev. 3
MOTOROLA
Low-Power Modes
Low-Power Modes
Data-Retention Mode
6.4.1 Programmable COP Watchdog in Wait Mode
The programmable COP watchdog is active during wait mode. Software
must periodically bring the MCU out of wait mode to clear the
programmable COP watchdog.
6.4.2 Non-Programmable COP Watchdog in Wait Mode
The non-programmable COP watchdog is active during wait mode.
Software must periodically bring the MCU out of wait mode to clear the
non-programmable COP watchdog.
6.5 Data-Retention Mode
In data-retention mode, the MCU retains random-access memory (RAM)
contents and CPU register contents at VDD voltages as low as 2.0 Vdc.
The data-retention feature allows the MCU to remain in a low
power-consumption state during which it retains data, but the CPU
cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic 0.
2. Lower VDD voltage. The RESET pin must remain low continuously
during data-retention mode.
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to logic 1.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Low-Power Modes
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Low-Power Modes
Technical Data
76
MC68HC705C8A — Rev. 3
Low-Power Modes
MOTOROLA
Technical Data — MC68HC705C8A
Section 7. Parallel Input/Output (I/O)
7.1 Contents
7.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .79
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.3.1
7.3.2
7.3.3
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .82
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.4.1
7.4.2
7.4.3
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . .86
Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.5.1
7.5.2
7.5.3
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.2 Introduction
This section describes the programming of ports A, B, C, and D.
MC68HC705C8A — Rev. 3
Technical Data
77
MOTOROLA
Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
7.3 Port A
Port A is an 8-bit, general-purpose, bidirectional input/output (I/O) port.
7.3.1 Port A Data Register
The port A data register (PORTA) shown in Figure 7-1 contains a data
latch for each of the eight port A pins. When a port A pin is programmed
to be an output, the state of its data register bit determines the state of
the output pin. When a port A pin is programmed to be an input, reading
the port A data register returns the logic state of the pin.
Address: $0000
Bit 7
6
5
4
3
2
1
Bit 0
PA0
Read:
Write:
Reset:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
Unaffected by reset
Figure 7-1. Port A Data Register (PORTA)
PA7–PA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register A. Reset has no effect on port A data.
Technical Data
78
MC68HC705C8A — Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
Port A
7.3.2 Data Direction Register A
The contents of data direction register A (DDRA) shown in Figure 7-2
determine whether each port A pin is an input or an output. Writing a
logic 1 to a DDRA bit enables the output buffer for the associated port A
pin; a logic 0 disables the output buffer. A reset clears all DDRA bits,
configuring all port A pins as inputs.
Address: $0004
Bit 7
DDRA7
0
6
DDRA6
0
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
DDRA2
0
1
DDRA1
0
Bit 0
DDRA0
0
Read:
Write:
Reset:
Figure 7-2. Data Direction Register A (DDRA)
DDRA7–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears bits
DDRA7–DDRA0.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing DDRA bits from logic 0 to logic 1.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
79
Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
7.3.3 Port A Logic
Figure 7-3 is a diagram of the port A I/O logic.
READ $0004
WRITE $0004
DATA DIRECTION
REGISTER A
BIT DDRAx
RESET
PORT A DATA
REGISTER
BIT PAx
WRITE $0000
READ $0000
PAx
Figure 7-3. Port A I/O Logic
When a port A pin is programmed to be an output, the state of its data
register bit determines the state of the output pin. When a port A pin is
programmed to be an input, reading the port A data register returns the
logic state of the pin.
The data latch can always be written, regardless of the state of its DDRA
bit. Table 7-1 summarizes the operation of the port A pins.
Table 7-1. Port A Pin Functions
Accesses to DDRA
Read/Write
Accesses to PORTA
DDRA Bit
I/O Pin Mode
Read
Pin
Write
(1)
(2)
0
1
DDRA7–DDRA0
DDRA7–DDRA0
Input, Hi-Z
PA7–PA0
Output
PA7–PA0
PA7–PA0
1. Hi-Z = high impedance
2. Writing affects data register but does not affect input.
NOTE: To avoid excessive current draw, tie all unused input pins to VDD or VSS,
or change I/O pins to outputs by writing to DDRA in user code as early
as possible.
Technical Data
80
MC68HC705C8A — Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
Port B
7.4 Port B
Port B is an 8-bit, general-purpose, bidirectional I/O port. Port B pins can
also be configured to function as external interrupts. The port B pullup
devices are enabled in mask option register 1 (MOR1). See 9.5.2 Mask
Option Register 1 and 4.3.3 Port B Interrupts.
7.4.1 Port B Data Register
The port B data register (PORTB) shown in Figure 7-4 contains a data
latch for each of the eight port B pins.
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
PB0
Read:
Write:
Reset:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
Unaffected by reset
Figure 7-4. Port B Data Register (PORTB)
PB7–PB0 — Port B Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register B. Reset has no effect on port B data.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Parallel Input/Output (I/O)
81
Parallel Input/Output (I/O)
7.4.2 Data Direction Register B
The contents of data direction register B (DDRB) shown in Figure 7-5
determine whether each port B pin is an input or an output. Writing a
logic 1 to a DDRB bit enables the output buffer for the associated port B
pin; a logic 0 disables the output buffer. A reset clears all DDRB bits,
configuring all port B pins as inputs. If the pullup devices are enabled by
mask option, setting a DDRB bit to a logic 1 turns off the pullup device
for that pin.
Address: $0005
Bit 7
DDRB7
0
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Write:
Reset:
Figure 7-5. Data Direction Register B (DDRB)
DDRB7–DDRB0 — Port B Data Direction Bits
These read/write bits control port B data direction. Reset clears bits
DDRB7–DDRB0.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
Technical Data
82
MC68HC705C8A — Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
Port B
7.4.3 Port B Logic
Figure 7-6 shows the port B I/O logic.
V
DD
PBPU7
FROM MOR1
READ $0005
WRITE $0005
RESET
DATA DIRECTION
REGISTER B
BIT DDRB7
PORT B DATA
REGISTER
BIT PB7
WRITE $0001
READ $0001
PB7
IRQ
FROM OPTION
REGISTER
V
DD
EXTERNAL
INTERRUPT
REQUEST
D
IRQ
LATCH
Q
FROM OTHER
PORT B PINS
C
Q
R
I BIT
FROM CCR
IRQ
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Figure 7-6. Port B I/O Logic
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
83
Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
When a port B pin is programmed as an output, reading the port bit reads
the value of the data latch and not the voltage on the pin itself. When a
port B pin is programmed as an input, reading the port bit reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its DDRB bit.
Table 7-2. Port B Pin Functions
Accesses to DDRB
Read/Write
Accesses to PORTB
DDRB Bit
I/O Pin Mode
Read
Pin
Write
(1)
(2)
0
1
DDRB7–DDRB0
DDRB7–DDRB0
Input, Hi-Z
PB7–PB0
Output
PB7–PB0
PB7–PB0
1. Hi-Z = high impedance
2. Writing affects data register but does not affect input.
NOTE: To avoid excessive current draw, tie all unused input pins to VDD or VSS,
or for I/O pins change to outputs by writing to DDRB in user code as early
as possible.
Technical Data
84
MC68HC705C8A — Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
Port C
7.5 Port C
Port C is an 8-bit, general-purpose, bidirectional I/O port. PC7 has a high
current sink and source capability.
7.5.1 Port C Data Register
The port C data register (PORTC) shown in Figure 7-7 contains a data
latch for each of the eight port C pins. When a port C pin is programmed
to be an output, the state of its data register bit determines the state of
the output pin. When a port C pin is programmed to be an input, reading
the port C data register returns the logic state of the pin.
Address: $0002
Bit 7
6
5
4
3
2
1
Bit 0
PC0
Read:
Write:
Reset:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
Unaffected by reset
Figure 7-7. Port C Data Register (PORTC)
PC7–PC0 — Port C Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register C. PC7 has a high current sink and source capability. Reset
has no effect on port C data.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Parallel Input/Output (I/O)
85
Parallel Input/Output (I/O)
7.5.2 Data Direction Register C
The contents of data direction register C (DDRC) shown in Figure 7-8
determine whether each port C pin is an input or an output. Writing a
logic 1 to a DDRC bit enables the output buffer for the associated port C
pin; a logic 0 disables the output buffer. A reset clears all DDRC bits,
configuring all port C pins as inputs.
Address: $0006
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
0
0
0
0
0
0
0
0
Figure 7-8. Data Direction Register C (DDRC)
DDRC7–DDRC0 — Port C Data Direction Bits
These read/write bits control port C data direction. Reset clears bits
DDRC7–DDRC0.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing DDRC bits from logic 0 to logic 1.
Technical Data
86
MC68HC705C8A — Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
Port C
7.5.3 Port C Logic
Figure 7-9 shows port C I/O logic.
READ $0006
WRITE $0006
DATA DIRECTION
REGISTER C
RESET
BIT DDRCx
PORT C DATA
REGISTER
BIT PCx
WRITE $0002
PCx
READ $0002
Figure 7-9. Port C I/O Logic
When a port C pin is programmed as an output, reading the port bit reads
the value of the data latch and not the voltage on the pin. When a port C
pin is programmed as an input, reading the port bit reads the voltage
level on the pin. The data latch can always be written, regardless of the
state of its DDRC bit. Table 7-3 summarizes the operation of the port C
pins.
Table 7-3. Port C Pin Functions
Accesses to DDRC
Read/Write
Accesses to PORTC
DDRC Bit
I/O Pin Mode
Read
Pin
Write
(1)
(2)
0
1
DDRC7–DDRC0
DDRC7–DDRC0
Input, Hi-Z
PC7–PC0
Output
PC7–PC0
PC7–PC0
1. Hi-Z = high impedance
2. Writing affects data register but does not affect input.
NOTE: To avoid excessive current draw, tie all unused input pins to VDD or VSS
or change I/O pins to outputs by writing to DDRC in user code as early
as possible.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
87
Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
7.6 Port D
Port D is a 7-bit, special-purpose, input-only port that has no data
register. Reading address $0003 returns the logic states of the port D
pins.
Port D shares pins PD5–PD2 with the serial peripheral interface module
(SPI). When the SPI is enabled, PD5–PD2 read as logic 0s. When the
SPI is disabled, reading address $0003 returns the logic states of the
PD5–PD2 pins.
Port D shares pins PD1 and PD0 with the SCI module. When the SCI is
enabled, PD1 and PD0 read as logic 0s. When the SCI is disabled,
reading address $0003 returns the logic states of the PD1 and PD0 pins.
Address: $0003
Bit 7
PD7
6
5
4
3
2
1
Bit 0
RDI
Read:
Write:
Reset:
SS
SCK
MOSI
MISO
TDO
Unaffected by reset
= Unimplemented
Figure 7-10. Port D Fixed Input Register (PORTD)
Technical Data
88
MC68HC705C8A — Rev. 3
Parallel Input/Output (I/O)
MOTOROLA
Technical Data — MC68HC705C8A
Section 8. Capture/Compare Timer
8.1 Contents
8.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.3
8.3.1
8.3.2
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.4
Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .98
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . .100
Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . .101
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.2 Introduction
This section describes the operation of the 16-bit capture/compare timer.
Figure 8-1 shows the structure of the timer module. Figure 8-2 is a
summary of the timer input/output (I/O) registers.
8.3 Timer Operation
The core of the capture/compare timer is a 16-bit free-running counter.
The counter is the timing reference for the input capture and output
compare functions. The input capture and output compare functions can
latch the times at which external events occur, measure input
waveforms, and generate output waveforms and timing delays. Software
can read the value in the counter at any time without affecting the
counter sequence.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Capture/Compare Timer
89
Capture/Compare Timer
EDGE
SELECT/
TCAP
ICRH ($0014)
TRH ($0018)
ICRL ($0015)
TRL ($0019)
DETECT
LOGIC
ATRH ($001A)
ATRL ($001B)
÷ 4
INTERNAL CLOCK (XTAL ÷ 2)
16-BIT COUNTER
PIN
CONTROL
LOGIC
16-BIT COMPARATOR
TCMP
OCRH ($0016)
OCRL ($0017)
TIMER
INTERRUPT
REQUEST
$0012
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
$0013
INTERNAL DATA BUS
Figure 8-1. Timer Block Diagram
Technical Data
90
MC68HC705C8A — Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer Operation
Addr.
Register Name
Bit 7
ICIE
0
6
5
4
3
2
1
Bit 0
Read:
Timer Control Register
OCIE
TOIE
0
0
0
IEDG
OLVL
$0012
(TCR) Write:
See page 94.
Reset:
0
0
0
0
0
0
0
0
U
0
0
0
Read: ICF
OCF
TOF
Timer Status Register
(TSR) Write:
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
See page 96.
Reset:
U
U
U
0
0
0
0
0
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Input Capture Register
High (ICRH) Write:
See page 100.
Reset:
Unaffected by reset
Bit 4 Bit 3
Read: Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
Input Capture Register
Low (ICRL) Write:
See page 100.
Reset:
Unaffected by reset
Bit 12 Bit 11
Unaffected by reset
Bit 4 Bit 3
Output Compare Register Read:
Bit 15
Bit 7
Bit 14
Bit 13
Bit 10
High (OCRH)
See page 101.
Write:
Reset:
Read:
Output Compare Register
Bit 6
Bit 5
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
Low (OCRL) Write:
See page 101.
Reset:
Unaffected by reset
Bit 12 Bit 11
Read: Bit 15
Bit 14
Bit 13
Bit 10
Timer Register High
(TRH) Write:
See page 97.
Reset:
Reset initializes TRH to $FF
Bit 4 Bit 3
Read: Bit 7
Bit 6
Bit 14
Bit 6
Bit 5
Bit 13
Bit 5
Bit 2
Bit 10
Bit 2
Bit 1
Bit 9
Bit 1
Bit 0
Bit 8
Bit 0
Timer Register Low
(TRL) Write:
See page 97.
Reset:
Reset initializes TRL to $FC
Bit 12 Bit 11
Read: Bit 15
Alternate Timer Register
High (ATRH) Write:
See page 99.
Reset:
Reset initializes ATRH to $FF
Bit 4 Bit 3
Read: Bit 7
Alternate Timer Register
Low (ATRL) Write:
See page 99.
Reset:
Reset initializes ATRL to $FC
U = Unaffected
= Unimplemented
Figure 8-2. Timer I/O Register Summary
MC68HC705C8A — Rev. 3
Technical Data
91
MOTOROLA
Capture/Compare Timer
Capture/Compare Timer
Because of the 16-bit timer architecture, the I/O registers for the input
capture and output compare functions are pairs of 8-bit registers.
Because the counter is 16 bits long and preceded by a fixed
divide-by-four prescaler, the counter rolls over every 262,144 internal
clock cycles. Timer resolution with a 4-MHz crystal is 2 µs.
8.3.1 Input Capture
The input capture function can record the time at which an external event
occurs. When the input capture circuitry detects an active edge on the
input capture pin (TCAP), it latches the contents of the timer registers
into the input capture registers. The polarity of the active edge is
programmable.
Latching values into the input capture registers at successive edges of
the same polarity measures the period of the input signal on the TCAP
pin. Latching the counter values at successive edges of opposite polarity
measures the pulse width of the signal. Figure 8-3 shows the logic of the
input capture function.
15
$0019
0
$0018
8
7
TIMER REGISTER HIGH
TIMER REGISTER LOW
8
7
0
15
LATCH
EDGE
INPUT CAPTURE REGISTER HIGH
$0014
INPUT CAPTURE REGISTER LOW
$0015
TCAP
SELECT/DETECT
LOGIC
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REGISTER
$0012
TIMER STATUS REGISTER
$0013
Figure 8-3. Input Capture Operation
Technical Data
92
MC68HC705C8A — Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer Operation
8.3.2 Output Compare
The output compare function can generate an output signal when the
16-bit counter reaches a selected value. Software writes the selected
value into the output compare registers. On every fourth internal clock
cycle the output compare circuitry compares the value of the counter to
the value written in the output compare registers. When a match occurs,
the timer transfers the programmable output level bit (OLVL) from the
timer control register to the output compare pin (TCMP).
Software can use the output compare register to measure time periods,
to generate timing delays, or to generate a pulse of specific duration or
a pulse train of specific frequency and duty cycle on the TCMP pin.
Figure 8-4 shows the logic of the output compare function.
15
0
COUNTER LOW BYTE
COUNTER HIGH BYTE
PIN
CONTROL
LOGIC
16-BIT COMPARATOR
TCMP
8
0
7
15
OUTPUT COMPARE REGISTER HIGH
$0016
OUTPUT COMPARE REGISTER LOW
$0017
TIMER
INTERRUPT
REQUEST
TIMER STATUS REGISTER
$0013
TIMER STATUS REGISTER
$0012
Figure 8-4. Output Compare Operation
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
93
Capture/Compare Timer
Capture/Compare Timer
8.4 Timer I/O Registers
These registers control and monitor the timer operation:
•
•
•
•
•
•
Timer control register (TCR)
Timer status register (TSR)
Timer registers (TRH and TRL)
Alternate timer registers (ATRH and ATRL)
Input capture registers (ICRH and ICRL)
Output compare registers (OCRH and OCRL)
8.4.1 Timer Control Register
The timer control register (TCR) as shown in Figure 8-5 performs these
functions:
•
•
•
•
•
Enables input capture interrupts
Enables output compare interrupts
Enables timer overflow interrupts
Controls the active edge polarity of the TCAP signal
Controls the active level of the TCMP output
Address: $0012
Bit 7
6
OCIE
0
5
TOIE
0
4
0
0
3
0
0
2
0
0
1
IEDG
U
Bit 0
OLVL
0
Read:
ICIE
Write:
Reset:
0
U = Unaffected
Figure 8-5. Timer Control Register (TCR)
Technical Data
94
MC68HC705C8A — Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer I/O Registers
ICIE — Input Capture Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Reset clears the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Reset clears the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables interrupts caused by a timer overflow.
Reset clears the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Edge Bit
The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture registers. Reset has no effect
on the IEDG bit.
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
OLVL — Output Level Bit
The state of this read/write bit determines whether a logic 1 or a
logic 0 appears on the TCMP pin when a successful output compare
occurs. Reset clears the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
Bits 4–2 — Not used; these bits always read 0
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Capture/Compare Timer
95
Capture/Compare Timer
8.4.2 Timer Status Register
The timer status register (TSR) is a read-only register shown in
Figure 8-6 contains flags for these events:
•
•
•
An active signal on the TCAP pin, transferring the contents of the
timer registers to the input capture registers
A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
A timer rollover from $FFFF to $0000
Address: $0013
Bit 7
6
5
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
ICF
OCF
TOF
U
U
U
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 8-6. Timer Status Register (TSR)
ICF — Input Capture Flag
The ICF bit is set automatically when an edge of the selected polarity
occurs on the TCAP pin. Clear the ICF bit by reading the timer status
register with ICF set and then reading the low byte ($0015) of the
input capture registers. Reset has no effect on ICF.
1 = Input capture
0 = No input capture
OCF — Output Compare Flag
The OCF bit is set automatically when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading the timer status register with OCF set and then reading
the low byte ($0017) of the output compare registers. Reset has no
effect on OCF.
1 = Output compare
0 = No output compare
Technical Data
96
MC68HC705C8A — Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer I/O Registers
TOF — Timer Overflow Flag
The TOF bit is automatically set when the 16-bit counter rolls over
from $FFFF to $0000. Clear the TOF bit by reading the timer status
register with TOF set and then reading the low byte ($0019) of the
timer registers. Reset has no effect on TOF.
1 = Timer overflow
0 = No timer overflow
Bits 4–0 — Not used; these bits always read 0
8.4.3 Timer Registers
The read-only timer registers (TRH and TRL) shown in Figure 8-7
contain the current high and low bytes of the 16-bit counter. Reading
TRH before reading TRL causes TRL to be latched until TRL is read.
Reading TRL after reading the timer status register clears the timer
overflow flag bit (TOF). Writing to the timer registers has no effect.
Bit 7
6
5
4
3
2
1
Bit 0
Register Name and Address: Timer Register High — $0018
Read: Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Reset initializes TRH to $FF
Register Name and Address: Timer Register Low — $0019
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset initializes TRL to $FC
= Unimplemented
Figure 8-7. Timer Registers (TRH and TRL)
MC68HC705C8A — Rev. 3
Technical Data
97
MOTOROLA
Capture/Compare Timer
Capture/Compare Timer
Reading TRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer, as shown in
Figure 8-8. The buffer value remains fixed even if the high byte is read
more than once. Reading TRL reads the transparent low byte buffer and
completes the read sequence of the timer registers.
INTERNAL DATA BUS
7
7
0
0
LATCH
8
LOW BYTE BUFFER
15
$0018
TIMER REGISTER HIGH
READ TRH
TIMER REGISTER LOW
$0019
Figure 8-8. Timer Register Reads
NOTE: To prevent interrupts from occurring between readings of TRH and TRL,
set the interrupt mask (I bit) in the condition code register before reading
TRH, and clear the mask after reading TRL.
8.4.4 Alternate Timer Registers
The alternate timer registers (ATRH and ATRL) shown in Figure 8-9
contain the current high and low bytes of the 16-bit counter. Reading
ATRH before reading ATRL causes ATRL to be latched until ATRL is
read. Reading does not affect the timer overflow flag (TOF). Writing to
the alternate timer registers has no effect.
Technical Data
98
MC68HC705C8A — Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer I/O Registers
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Register Name and Address: Alternate Timer Register High — $001A
Read: Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reset:
Reset initializes ATRH to $FF
Register Name and Address: Alternate Timer Register Low — $001B
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset initializes ATRL to $FC
= Unimplemented
Figure 8-9. Alternate Timer Registers (ATRH and ATRL)
Reading ATRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer, as shown in
Figure 8-10.
INTERNAL DATA BUS
7
7
0
0
LATCH
8
LOW BYTE BUFFER
15
$001A
ALTERNATE TIMER REGISTER HIGH
ALTERNATE TIMER REGISTER LOW
$001B
READ ATRH
Figure 8-10. Alternate Timer Register Reads
NOTE: To prevent interrupts from occurring between readings of ATRH and
ATRL, set the interrupt mask (I bit) in the condition code register before
reading ATRH, and clear the mask after reading ATRL.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
99
Capture/Compare Timer
Capture/Compare Timer
8.4.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the read-only input capture
registers (ICRH and ICRL) shown in Figure 8-11. Reading ICRH before
reading ICRL inhibits further captures until ICRL is read. Reading ICRL
after reading the timer status register clears the input capture flag (ICF).
Writing to the input capture registers has no effect.
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Register Name and Address: Input Capture Register High — $0014
Read: Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reset:
Unaffected by reset
Register Name and Address: Input Capture Register Low — $0015
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unaffected by reset
= Unimplemented
Figure 8-11. Input Capture Registers (ICRH and ICRL)
NOTE: To prevent interrupts from occurring between readings of ICRH and
ICRL, set the interrupt mask (I bit) in the condition code register before
reading ICRH and clear the mask after reading ICRL.
Technical Data
100
MC68HC705C8A — Rev. 3
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer I/O Registers
8.4.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the read/write
output compare registers (OCRH and OCRL) shown in Figure 8-12, the
planned TCMP pin action takes place. Writing to OCRH before writing to
OCRL inhibits timer compares until OCRL is written. Reading or writing
to OCRL after reading the timer status register clears the output
compare flag (OCF).
Bit 7
6
5
4
3
2
1
Bit 0
Register Name and Address: Output Compare Register High — $0016
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Unaffected by reset
Register Name and Address: Output Compare Register Low — $0017
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
Figure 8-12. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading the timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Capture/Compare Timer
101
Capture/Compare Timer
Technical Data
102
MC68HC705C8A — Rev. 3
Capture/Compare Timer
MOTOROLA
Technical Data — MC68HC705C8A
Section 9. EPROM/OTPROM (PROM)
9.1 Contents
9.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
9.3
9.3.1
9.3.2
EPROM/OTPROM (PROM) Programming. . . . . . . . . . . . . . .104
Program Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Preprogramming Steps . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.4
PROM Programming Routines . . . . . . . . . . . . . . . . . . . . . . . .111
Program and Verify PROM. . . . . . . . . . . . . . . . . . . . . . . . .111
Verify PROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Secure PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Secure PROM and Verify. . . . . . . . . . . . . . . . . . . . . . . . . .113
Secure PROM and Dump. . . . . . . . . . . . . . . . . . . . . . . . . .113
Load Program into RAM and Execute . . . . . . . . . . . . . . . .114
Execute Program in RAM. . . . . . . . . . . . . . . . . . . . . . . . . .115
Dump PROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.5
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Mask Option Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.5.1
9.5.2
9.5.3
9.6
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.2 Introduction
This section describes erasable, programmable read-only
memory/one-timeprogrammable read-onlymemory(EPROM/OTPROM
(PROM)) programming.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
EPROM/OTPROM (PROM)
103
EPROM/OTPROM (PROM)
9.3 EPROM/OTPROM (PROM) Programming
The internal PROM can be programmed efficiently using the Motorola
MC68HC05PGMR-2 programmer board, which can be purchased from
a Motorola-authorized distributor. The user can program the
microcontroller unit (MCU) using this printed circuit board (PCB) in
conjunction with an EPROM device already programmed with user code.
Only standalone programming is discussed in this section. For more
information concerning the MC68HC05PGMR and its usages, contact a
local Motorola representative for a copy of the MC68HC05PGMR
Programmer Board User’s Manual #2, Motorola document number
MC68HC05PGMR2/D1.
Refer to Figure 9-1 for an EPROM programming flowchart. Figure 9-2
provides a schematic of the MC68HC05PGMR PCB with the reference
designators defined in Table 9-1.
Table 9-1. MC68HC05PGMR PCB Reference Designators
Reference
Designators
Device
Type
V
Ground
+5 V
+12 V
–12 V
Notes
PP
U1
U2
2764
14, 20
20
1, 26, 27, 28
—
—
—
1
—
—
—
8
—
3
8 K x 8-bit EPROM
40-pin DIP socket
44-lead PLCC socket
Driver/receiver
MCU
40
44
16
1
U3
MCU
22
4
U4
MC145406
NMA0512S
9
—
—
VR1
2.5
6
4
DC-DC converter
Technical Data
104
MC68HC705C8A — Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM) Programming
START
APPLY V
PP
NTRYS = 0
START AT BEGINNING
OF MEMORY
LAT = 1
WRITE PROM DATA
PGM = 1
WAIT 1 ms
PGM = 0
LAT = 0
YES
WRITE
ADDITIONAL
BYTE
NO
NTRYS = NTRYS + 1
NO
NTRYS = 2
YES
VPP OFF
END
Figure 9-1. EPROM/OTPROM Programming Flowchart
MC68HC705C8A — Rev. 3
Technical Data
105
MOTOROLA
EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM)
VR1 NMA0512S
DC-DC CONVERTER
(OPTIONAL)
S1
OFF
ON
A
+5 V
1
5
R15
10 K
V
0 V
CC
+
C1
P1
100 µF
–V
GND
2
+V
6
+5 V
+12 V
–12 V
4
2
3
5
1
OFF
ON
4
40
VDD
+12 V
39
38
OSC1
OSC2
B
C
–12 V
3
V
V
PP
PP
D1
1N4001
V
PP
GND
1
2
RESET
IRQ
D
E
F
G
H
I
+5 V
16
9
37
36
35
34
33
32
31
P3
TCAP
PD7
30
3
2
14
15
PD1
RXD
TXD
3
2
PD1
PD0
TCMP
PD5
29
11
10
9
PD0
A0
10
9
(A0)
(A1)
(A2)
(A3)
(A4)
(A5)
(A6)
(A7)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
U1
U4
MC145406
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PD4
2764
J
A1
A2
A3
A4
A5
A6
8
1
+5 V
8
PD3
K
L
+12 V –12 V
1
8
7
PD2
V
PP
26
27
28
6
7
U2
NC
40-PIN DIP
SOCKET
5
6
PGM
5
4
23
22
CTS
V
CC
PC5
PC6
M
5
6
3
4
C5
0.1 µF
DSR
DCD
DTR
GND
GND
A7
N
(A8)
28
27
26
25
24
8
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
11 (D0)
12 (D1)
12
13
14
15
16
17
18
19
20
PC0
PC1
PC2
PC3
PC4
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
D0
D1
CE
20
1
(A9)
(A8)
(A9)
(A10)
25
24
21
(D2)
(D3)
13
15
(A10)
(A11)
(A12)
A8
D2
D3
7
A9
16 (D4)
A10
A11
A12
OE
D4
D5
(A11) 23
(D5)
(D6)
17
18
(A12)
2
D6
D7
21
19 (D7)
22
PC7
O
V
GND
SS
14
20
Notes:
1. The asterisk (*) denotes option T
command only.
2. Unless otherwise specified, resistors are in ohms,
±5% 1/4 W; capacitors are in µF; voltages are dc.
P
Q
(ENABLE)
3. Device type numbers shown in circuit are for
reference only. Device type number varies
with manufacturer.
R
S
Figure 9-2. PROM Programming Circuit
Technical Data
106
MC68HC705C8A — Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM) Programming
R2
J1
2
NC
R3 10 K
1
3
3
1
NC
NC
NC
NC
10 K
R1
+5 V
A
B
C
38
39
40
+12 V
NC
2.7 K
R5
C2
+5 V
S2
OUT
RESET
1.0 µF
10 M
Y1
R13
10 K
R4
10 K
C3
22 pF
C4
22 pF
P2
+5 V
2.0 MHz
IRQ
2
+5 V
S5
D
E
F
G
H
I
S3
S4
S6
PD5
PD4
PD3
PD2
PD7
34
33
32
31
36
J
K
L
+5 V
+5 V
1
2
R10*
470
R12
10 K
VERF
R7
R6
R9
R8
J2
10 K 10 K
10 K 10 K
TCAP
TCMP
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
DS2*
+5 V
37
35
12
13
14
15
16
17
18
19
11
10
9
(VERF)
M
(PROG)
C6
N
NC
NC
0.1 µF
PROG
DS1*
(A5)
(A4)
(A3)
(A2)
(A1)
(A0)
7
39
38
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
PB4
PD7
8
TCMP
PD5
PD4
PD3
PD2
PD1
PD0
PC0
PC1
PC2
9
37
36
35
PD5
PD4
PD3
R11*
470
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
10
11
12
13
14
15
16
17
U3
34 PD2
44-LEAD PLCC
SOCKET
+5 V
(D0)
(D1)
(D2)
(D3)
(D4)
33
32
31
30
PD1
8
PD0
(A8)
(A9)
7
6
5
(A10)
29
4
28
27
26
25
24
30
29
23
22
21
PC3
PC4
PD1
PD0
PC5
PC6
PC7
O
P
NC
NC
Q
R
S
V
SS
20
Figure 9-2. PROM Programming Circuit (Continued)
MC68HC705C8A — Rev. 3
Technical Data
107
MOTOROLA
EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM)
To program the PROM MCU, the MCU is installed in the PCB, along with
an EPROM device programmed with user code; the MCU is then
subjected to a series of routines. The routines necessary to program,
verify, and secure the PROM MCU are:
•
•
•
•
Program and verify PROM
Verify PROM contents only
Secure PROM and verify
Secure PROM and dump through the serial communications
interface (SCI)
Other board routines available to the user are:
•
•
•
Load program into random-access memory (RAM) and execute
Execute program in RAM
Dump PROM contents (binary upload)
The user first configures the MCU for the bootstrap mode of operations
by installing a fabricated jumper across pins 1 and 2 of the board’s mode
select header, J1. Next, the board’s mode switches (S3, S4, S5, and S6)
are set to determine the routine to be executed after the next reset, as
shown in Table 9-2.
Table 9-2. PROM Programming Routines
Routine
Program and verify PROM
S3
Off
Off
On
On
Off
Off
Off
S4
Off
Off
Off
On
On
Off
On
S5
Off
On
On
On
Off
Off
On
S6
Off
Off
Off
Off
Off
On
Off
Verify PROM contents only
Secure PROM contents and verify
Secure PROM contents and dump
Load program into RAM and execute
Execute program in RAM
Dump PROM contents
Technical Data
108
MC68HC705C8A — Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM) Programming
9.3.1 Program Register
The program register (PROG) shown in Figure 9-3 is used for PROM
programming.
Address: $001C
Bit 7
6
0
0
5
0
0
4
0
0
3
0
0
2
LAT
0
1
0
0
Bit 0
PGM
0
Read:
Write:
Reset:
0
0
Figure 9-3. Program Register (PROG)
LAT — Latch Enable Bit
This bit is both readable and writable.
1 = Enables PROM data and address bus latches for programming
on the next byte write cycle
0 = Latch disabled. PROM data and address buses are unlatched
for normal CPU operations.
PGM — Program Bit
If LAT is cleared, PGM cannot be set.
1 = Enables VPP power to the PROM for programming
0 = VPP is disabled.
Bits 1 and 3−7 — Not used; always read 0
MC68HC705C8A — Rev. 3
Technical Data
109
MOTOROLA
EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM)
9.3.2 Preprogramming Steps
Before programming the PROM using an MC68HC05PGMR PCB in
standalone mode, the user should ensure that:
•
•
•
A jumper is installed on pins 1 and 2 of mode select header J1.
An EPROM is programmed with the necessary user code.
The erasure window (if any) of the device to be programmed is
covered.
•
•
VDD of +5 Vdc is available on the board.
VPP is available on the board.
NOTE: If the VPP level at the MCU exceeds +16 Vdc, then the MC68HC705C8A
MCU device will suffer permanent damage.
Once those conditions are met, the user should take these steps before
beginning programming:
1. Remove the VPP power source.
2. Set switch 1 in the OFF position (removes VDD).
3. Place the programmed EPROM in socket U1.
4. Insert the erased PROM MCU device to be programmed in the
proper socket:
– MC68HC705C8S or MC68HC705C8P in socket U2 (40-pin
dual in-line package (DIP)) or
– MC68HC705C8FN in socket U3 (44-pin plastic leaded chip
carrier (PLCC)) with the device notch at the upper right corner
of the socket.
5. Set switch S2 in the RESET position.
NOTE: No PROM MCU should be inserted in or removed from its board socket
(U2 or U3) while VPP (P1, slot 5) or VDD (switch 1) is active on the board.
Technical Data
110
MC68HC705C8A — Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
PROM Programming Routines
9.4 PROM Programming Routines
This subsection describes the routines necessary to program, verify, and
secure the PROM device, and other routines available to the user.
9.4.1 Program and Verify PROM
The program and verify PROM routine copies the contents of the
external EPROM into the MCU PROM with direct correspondence
between the addresses. Memory addresses in the MCU that are not
implemented in PROM are skipped. Unprogrammed addresses in the
EPROM being copied should contain $00 bytes to speed up the
programming process.
To run the program and verify the PROM routine on the PROM MCU,
take these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Restore the VPP power source.
3. Set switches S3, S4, S5, and S6 in the OFF position (selects
proper routine).
4. Set switch 2 in the OUT position (routine is activated).
The red light-emitting diode (LED) is illuminated, showing that the
programming part of the routine is running. The LED goes out
when programming is finished. The verification part of the routine
now begins. When the green LED is illuminated, verification is
successfully completed and the routine is finished.
5. Set switch 2 in the RESET position.
At this point, if no other MCU is to be programmed or secured, remove
VPP power from the board. If another routine is to be performed on the
MCU being programmed, the user can then set switches S3, S4, S5, and
S6 to the positions necessary to select the next routine, and begin the
routine by setting switch 2 to the OUT position. If no other routine is to
be performed, remove VDD from the board and remove the MCU from
the programming socket.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
EPROM/OTPROM (PROM)
111
EPROM/OTPROM (PROM)
9.4.2 Verify PROM Contents
The verify PROM contents routine is normally run automatically after the
PROM is programmed. Direct entry to this routine causes the PROM
contents of the MCU to be compared to the contents of the external
memory locations of the EPROM at the same addresses.
To invoke the verify PROM contents routine of the MCU, take these
steps:
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD
.
3. Set switches S3, S4, and S6 in the OFF position.
4. Set S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
The red LED is not illuminated during this routine, since no
programming takes place. If verification fails, the routine halts with
the failing address in the external memory bus. When the green
LED is illuminated, verification is completed successfully and the
routine is finished.
6. Set switch 2 in the RESET position.
At this point, if another routine is to be performed on the MCU being
programmed, the user can set switches S3, S4, S5, and S6 to the
positions necessary to select the next routine and move switch S2 to the
OUT position to start the routine. If no other routine is to be performed,
remove VDD from the board and remove the MCU from the programming
socket.
9.4.3 Secure PROM
The secure PROM routines are used after the PROM is successfully
programmed and verified. Only the SEC bit of the option register
($1FDF) is programmed, but VPP is necessary. Once this bit is
programmed, PROM is secure and can be neither verified nor dumped.
Technical Data
112
MC68HC705C8A — Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
PROM Programming Routines
9.4.4 Secure PROM and Verify
This routine is used after the PROM is programmed successfully to
verify the contents of the MCU PROM against the contents of the
EPROM and then to secure the PROM. To accomplish this routine, take
these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Restore VPP power to the programming board.
3. Set switches S4 and S6 in the OFF position.
4. Set switches S3 and S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
Execution time for this routine is about one second.
6. Set switch 2 in the RESET position when the routine is completed.
No LED is illuminated during this routine. Further, the end of the routine
does not mean that the SEC bit was verified. To ensure that security is
properly enabled, attempt to perform another verify routine. If the green
LED does not light, the PROM has been secured properly.
9.4.5 Secure PROM and Dump
This routine is used after the PROM is successfully programmed to
dump the contents of the MCU PROM through the SCI (binary upload)
and then to secure the PROM. To accomplish this routine, take these
steps:
1. Set switch 1 in the ON position (restores VDD).
2. Restore VPP power to the programming board.
3. Set switch S6 in the OFF position.
4. Set switches S3, S4, and S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
Execution time for this routine is about one second.
6. Set switch 2 in the RESET position when the routine is completed.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
EPROM/OTPROM (PROM)
113
EPROM/OTPROM (PROM)
No LED is illuminated during this routine. Further, the end of the routine
does not mean that the SEC bit was verified. To ensure that security is
properly enabled, attempt to perform another verify routine. If the green
LED does not light, the PROM has been secured properly.
9.4.6 Load Program into RAM and Execute
In the load program in RAM and execute routine, user programs are
loaded via the SCI port and then executed. Data is loaded sequentially
starting at address $0050. After the last byte is loaded, control is
transferred to the RAM program starting at $0051. The first byte loaded
is the count of the total number of bytes in the program plus the count
byte. The program starts at location $0051 in RAM. During initialization,
the SCI is configured for eight data bits and one stop bit. The baud rate
is 4800 with a 2-MHz crystal or 9600 with a 4-MHz crystal.
To load a program into RAM and execute it, take these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD
.
3. Set switches S3, S5, and S6 in the OFF position.
4. Set switch S4 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
The downloaded program starts executing as soon as the last byte is
received by the SCI.
Execution of the routine can be held off by setting the byte count in the
count byte (the first byte loaded) to a value greater than the number of
bytes to be loaded. After loading the last byte, the firmware waits for
more data. Program execution does not begin. At this point, placing
switch 2 in the RESET position resets the MCU with the RAM data intact.
Any other routine can be entered, including the one to execute the
program in RAM, simply by setting switches S3–S6 as necessary to
select the desired routine, then setting switch 2 in the OUT position.
Technical Data
114
MC68HC705C8A — Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
PROM Programming Routines
9.4.7 Execute Program in RAM
This routine allows the MCU to transfer control to a program previously
loaded in RAM. This program is executed once bootstrap mode is
entered, if switch S6 is in the ON position and switch 2 is in the OUT
position, without any firmware initialization. The program must start at
location $0051 to be compatible with the load program in RAM routine.
To run the execute program in RAM routine, take these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD
.
3. Set switch S6 in the OFF position.
4. Switches S3, S4, and S5 can be in either position.
5. Set switch 2 in the OUT position (routine is activated).
NOTE: The non-programmable watchdog COP is disabled in bootloader mode,
even if the NCOPE bit is programmed.
9.4.8 Dump PROM Contents
In the dump PROM contents routine, the PROM contents are dumped
sequentially to the SCI output, provided the PROM has not been
secured. The first location sent is $0020 and the last location sent is
$1FFF. Unused locations are skipped so that no gaps exist in the data
stream. The external memory address lines indicate the current location
being sent. Data is sent with eight data bits and one stop bit at 4800 baud
with a 2-MHz crystal or 9600 baud with a 4-MHz crystal.
To run the dump PROM contents routine, take these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD
.
3. Set switches S3 and S6 in the OFF position.
4. Set switches S4 and S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
6. Once PROM dumping is complete, set switch 2 in the RESET
position.
MC68HC705C8A — Rev. 3
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EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM)
9.5 Control Registers
This subsection describes the three registers that control memory
configuration, PROM security, and IRQ edge or level sensitivity; port B
pullups; and non-programmable COP enable/disable.
9.5.1 Option Register
The option register shown in Figure 9-4 is used to select the IRQ
sensitivity, enable the PROM security, and select the memory
configuration.
Address: $1FDF
Bit 7
RAM0
0
6
RAM1
0
5
0
0
4
0
0
3
SEC*
*
2
1
IRQ
1
Bit 0
0
Read:
Write:
Reset:
U
0
*Implemented as an EPROM cell
= Unimplemented
U = Unaffected
Figure 9-4. Option Register (Option)
RAM0 — Random-Access Memory Control Bit 0
1 = Maps 32 bytes of RAM into page zero starting at address
$0030. Addresses from $0020 to $002F are reserved. This bit
can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 48 bytes of PROM at location $0020–$005F.
RAM1 — Random-Access Memory Control Bit 1
1 = Maps 96 bytes of RAM into page one starting at address $0100.
This bit can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 96 bytes of PROM at location $0100.
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MC68HC705C8A — Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
Control Registers
SEC — Security Bit
This bit is implemented as an EPROM cell and is not affected by
reset.
1 = Security enabled
0 = Security off; bootloader able to be enabled
IRQ — Interrupt Request Pin Sensitivity Bit
IRQ is set only by reset, but can be cleared by software. This bit can
only be written once.
1 = IRQ pin is both negative edge- and level-sensitive.
0 = IRQ pin is negative edge-sensitive only.
Bits 5, 4, and 0 — Not used; always read 0
Bit 2 — Unaffected by reset; reads either 1 or 0
9.5.2 Mask Option Register 1
Mask option register 1 (MOR1) shown in Figure 9-5 is an EPROM
register that enables the port B pullup devices. Data from MOR1 is
latched on the rising edge of the voltage on the RESET pin.
See 4.3.3 Port B Interrupts.
Address: $1FF0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
PBPU0/
COPC
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
Reset:
Erased:
Unaffected by reset
0
0
0
0
0
0
0
0
Figure 9-5. Mask Option Register 1 (MOR1)
PBPU7–PBPU0/COPC — Port B Pullup Enable Bits 7–0
These EPROM bits enable the port B pullup devices.
1 = Port B pullups enabled
0 = Port B pullups disabled
MC68HC705C8A — Rev. 3
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MOTOROLA
EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM)
NOTE: PBPU0/COPC programmed to a 1 enables the port B pullup bit. This bit
is also used to clear the non-programmable COP (MC68HC05C4A
type). Writing to this bit to clear the COP will not affect the state of the
port B pull-up (bit 0). See 5.3.3 Programmable and
Non-Programmable COP Watchdog Resets.
When using the MC68HC705C8A in an MC68HC705C8 or
MC68HSC705C8 application, program locations $1FF0 and $1FF1 to
$00.
9.5.3 Mask Option Register 2
Mask option register 2 (MOR2) shown in Figure 9-6 is an EPROM
register that enables the non-programmable COP watchdog. Data from
MOR2 is latched on the rising edge of the voltage on the RESET pin.
See 5.3.3 Programmable and Non-Programmable COP Watchdog
Resets.
Address: $1FF1
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
NCOPE
Reset:
Erased:
Unaffected by reset
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-6. Mask Option Register 2 (MOR2)
NCOPE — Non-Programmable COP Watchdog Enable Bit
This EPROM bit enables the non-programmable COP watchdog.
1 = Non-programmable COP watchdog enabled
0 = Non-programmable COP watchdog disabled
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EPROM/OTPROM (PROM)
MOTOROLA
EPROM/OTPROM (PROM)
EPROM Erasing
9.6 EPROM Erasing
The erased state of an EPROM or OTPROM byte is $00. EPROM
devices can be erased by exposure to a high intensity ultraviolet (UV)
light with a wave length of 2537 Å. The recommended erasure dosage
(UV intensity on a given surface area x exposure time) is 15 Ws/cm2. UV
lamps should be used without short-wave filters, and the EPROM device
should be positioned about one inch from the UV source.
OTPROM devices are shipped in an erased state. Once programmed,
they cannot be erased. Electrical erasing procedures cannot be
performed on either EPROM or OTPROM devices.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
EPROM/OTPROM (PROM)
119
EPROM/OTPROM (PROM)
Technical Data
120
MC68HC705C8A — Rev. 3
EPROM/OTPROM (PROM)
MOTOROLA
Technical Data — MC68HC705C8A
Section 10. Serial Communications Interface (SCI)
10.1 Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.4 SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.5 SCI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
10.6 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.6.1 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.6.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.6.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
10.6.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.6.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
10.2 Introduction
The serial communications interface (SCI) module allows high-speed
asynchronous communication with peripheral devices and other
microcontroller units (MCUs).
MC68HC705C8A — Rev. 3
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121
MOTOROLA
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
10.3 Features
Features of the SCI module include:
•
•
•
•
•
•
Standard mark/space non-return-to-zero format
Full-duplex operation
32 programmable baud rates
Programmable 8-bit or 9-bit character length
Separately enabled transmitter and receiver
Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
•
Interrupt-driven operation capability with five interrupt flags:
– Transmitter data register empty
– Transmission complete
– Receiver data register full
– Receiver overrun
– Idle receiver input
•
•
Receiver framing error detection
1/16 bit-time noise detection
10.4 SCI Data Format
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 10-1.
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Serial Communications Interface (SCI)
MOTOROLA
Serial Communications Interface (SCI)
SCI Operation
8-BIT DATA FORMAT
(BIT M IN SCCR1 CLEAR)
NEXT
START
BIT
START
STOP
BIT 0
BIT 0
BIT 1
BIT 1
BIT 2
BIT 2
BIT 3
BIT 3
BIT 4
BIT 5
BIT 6
BIT 6
BIT 7
BIT
BIT
9-BIT DATA FORMAT
(BIT M IN SCCR1 SET)
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 4
BIT 5
BIT 7
BIT 8
Figure 10-1. SCI Data Format
10.5 SCI Operation
The SCI allows full-duplex, asynchronous, RS232 or RS422 serial
communication between the MCU and remote devices, including other
MCUs. The transmitter and receiver of the SCI operate independently,
although they use the same baud-rate generator. This subsection
describes the operation of the SCI transmitter and receiver.
10.5.1 Transmitter
Figure 10-2 shows the structure of the SCI transmitter. Figure 10-3 is a
summary of the SCI transmitter input/output (I/O) registers.
•
Character Length — The transmitter can accommodate either
8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCCR1) determines character length. When transmitting 9-bit
data, bit T8 in SCCR1 is the ninth bit (bit 8).
•
Character Transmission — During transmission, the transmit shift
register shifts a character out to the PD1/TDO pin. The SCI data
register (SCDR) is the write-only buffer between the internal data
bus and the transmit shift register.
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Technical Data
MOTOROLA
Serial Communications Interface (SCI)
123
Serial Communications Interface (SCI)
SCDR ($0011)
1X
TRANSMIT SHIFT REGISTER
BAUD RATE
CLOCK
PIN BUFFER
AND CONTROL
PD1/
TDO
H 8
7
6
5
4
3
2
1
0
L
TRANSMITTER
CONTROL LOGIC
SCSR ($0010)
SCCR1 ($000E)
TDRE
TIE
TC
TCIE
SCI RECEIVE
REQUESTS
SCCR2 ($000F)
SCI INTERRUPT
REQUEST
Figure 10-2. SCI Transmitter
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Serial Communications Interface (SCI)
MOTOROLA
Serial Communications Interface (SCI)
SCI Operation
Addr.
Register Name
Bit 7
6
5
SCP1
0
4
SCP0
0
3
2
SCR2
U
1
SCR1
U
Bit 0
SCR0
U
Read:
Baud Rate Register
$000D
(Baud) Write:
See page 136.
Reset:
Read:
U
R8
U
U
T8
U
WAKE
U
SCI Control Register 1
M
$000E
$000F
$0010
$0011
(SCCR1) Write:
See page 130.
Reset:
Read:
U
U
SCI Control Register 2
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
(SCCR2) Write:
See page 131.
Reset:
0
0
0
0
0
0
0
Read: TDRE
TC
RDRF
IDLE
OR
NF
FE
SCI Status Register
(SCSR) Write:
See page 133.
Reset:
Read:
1
1
0
0
0
0
0
U
SCI Data Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(SCDR) Write:
See page 129.
Reset:
Unaffected by reset
U = Unaffected
= Unimplemented
Figure 10-3. SCI Transmitter I/O Register Summary
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and
then writing data to the SCDR begins the transmission. At the start
of a transmission, transmitter control logic automatically loads the
transmit shift register with a preamble of logic 1s. After the
preamble shifts out, the control logic transfers the SCDR data into
the shift register. A logic 0 start bit automatically goes into the least
significant bit (LSB) position of the shift register, and a logic 1 stop
bit goes into the most significant bit (MSB) position.
When the data in the SCDR transfers to the transmit shift register,
the transmit data register empty (TDRE) flag in the SCI status
register (SCSR) becomes set. The TDRE flag indicates that the
SCDR can accept new data from the internal data bus.
When the shift register is not transmitting a character, the
PD1/TDO pin goes to the idle condition, logic 1. If software clears
the TE bit during the idle condition, and while TDRE is set, the
transmitter relinquishes control of the PD1/TDO pin.
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Technical Data
MOTOROLA
Serial Communications Interface (SCI)
125
Serial Communications Interface (SCI)
•
Break Characters — Writing a logic 1 to the SBK bit in SCCR2
loads the shift register with a break character. A break character
contains all logic 0s and has no start and stop bits. Break
character length depends on the M bit in SCCR1. As long as SBK
is at logic 1, transmitter logic continuously loads break characters
into the shift register. After software clears the SBK bit, the shift
register finishes transmitting the last break character and then
transmits at least one logic 1. The automatic logic 1 at the end of
a break character is to guarantee the recognition of the start bit of
the next character.
•
Idle Characters — An idle character contains all logic 1s and has
no start or stop bits. Idle character length depends on the M bit in
SCCR1. The preamble is a synchronizing idle character that
begins every transmission.
Clearing the TE bit during a transmission relinquishes the
PD1/TDO pin after the last character to be transmitted is shifted
out. The last character may already be in the shift register, or
waiting in the SCDR, or it may be a break character generated by
writing to the SBK bit. Toggling TE from logic 0 to logic 1 while the
last character is in transmission generates an idle character (a
preamble) that allows the receiver to maintain control of the
PD1/TDO pin.
•
Transmitter Interrupts — These sources can generate SCI
transmitter interrupt requests:
– Transmit Data Register Empty (TDRE) — The TDRE bit in the
SCSR indicates that the SCDR has transferred a character to
the transmit shift register. TDRE is a source of SCI interrupt
requests. The transmission complete interrupt enable bit
(TCIE) in SCCR2 is the local mask for TDRE interrupts.
– Transmission Complete (TC) — The TC bit in the SCSR
indicates that both the transmit shift register and the SCDR are
empty and that no break or idle character has been generated.
TC is a source of SCI interrupt requests. The transmission
complete interrupt enable bit (TCIE) in SCCR2 is the local
mask for TC interrupts.
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Serial Communications Interface (SCI)
MOTOROLA
Serial Communications Interface (SCI)
SCI Operation
10.5.2 Receiver
Figure 10-4 shows the structure of the SCI receiver. Refer to
Figure 10-3 for a summary of the SCI receiver I/O registers.
16X
BAUD RATE
÷16
RECEIVE SHIFT REGISTER
CLOCK
PD0/
RDI
PIN BUFFER
AND CONTROL
DATA
RECOVERY
8
7 6 5 4 3 2 1 0
DISABLE
DRIVER
IDLE MSB RDRF OR
RE
M
WAKEUP
LOGIC
SCCR1 ($000E)
SCSR ($0010)
SCDR ($0011)
RDRF
RIE
IDLE
ILIE
SCI TRANSMIT
REQUESTS
OR
RIE
SCCR2 ($000F)
SCI INTERRUPT
REQUEST
Figure 10-4. SCI Receiver
MC68HC705C8A — Rev. 3
Technical Data
127
MOTOROLA
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
•
Character Length — The receiver can accommodate either 8-bit
or 9-bit data. The state of the M bit in SCI control register 1
(SCCR1) determines character length. When receiving 9-bit data,
bit R8 in SCCR1 is the ninth bit (bit 8).
•
Character Reception — During reception, the receive shift register
shifts characters in from the PD0/RDI pin. The SCI data register
(SCDR) is the read-only buffer between the internal data bus and
the receive shift register.
After a complete character shifts into the receive shift register, the
data portion of the character is transferred to the SCDR, setting
the receive data register full (RDRF) flag. The RDRF flag can be
used to generate an interrupt.
•
Receiver Wakeup — So that the MCU can ignore transmissions
intended only for other receivers in multiple-receiver systems, the
MCU can be put into a standby state. Setting the receiver wakeup
enable (RWU) bit in SCI control register 2 (SCCR2) puts the MCU
into a standby state during which receiver interrupts are disabled.
Either of two conditions on the PD0/RDI pin can bring the MCU out
of the standby state:
– Idle input line condition — If the PD0/RDI pin is at logic 1 long
enough for 10 or 11 logic 1s to shift into the receive shift
register, receiver interrupts are again enabled.
– Address mark — If a logic 1 occurs in the most significant bit
position of a received character, receiver interrupts are again
enabled.
The state of the WAKE bit in SCCR1 determines which of the two
conditions wakes up the MCU.
•
Receiver Noise Immunity — The data recovery logic samples
each bit 16 times to identify and verify the start bit and to detect
noise. Any conflict between noise detection samples sets the
noise flag (NF) in the SCSR. The NF bit is set at the same time
that the RDRF bit is set.
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MOTOROLA
Serial Communications Interface (SCI)
SCI I/O Registers
•
•
Framing Errors — If the data recovery logic does not detect a logic
1 where the stop bit should be in an incoming character, it sets the
framing error (FE) bit in the SCSR. The FE bit is set at the same
time that the RDRF bit is set.
Receiver Interrupts — These sources can generate SCI receiver
interrupt requests:
– Receive Data Register Full (RDRF) — The RDRF bit in the
SCSR indicates that the receive shift register has transferred a
character to the SCDR.
– Receiver Overrun (OR) — The OR bit in the SCSR indicates
that the receive shift register shifted in a new character before
the previous character was read from the SCDR.
– Idle Input (IDLE) — The IDLE bit in the SCSR indicates that 10
or 11 consecutive logic 1s shifted in from the PD0/RDI pin.
10.6 SCI I/O Registers
These I/O registers control and monitor SCI operation:
•
•
•
•
SCI data register (SCDR)
SCI control register 1 (SCCR1)
SCI control register 2 (SCCR2)
SCI status register (SCSR)
10.6.1 SCI Data Register
The SCI data register (SCDR) shown in Figure 10-5 is the buffer for
characters received and for characters transmitted.
Address: $0011
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Unaffected by reset
Figure 10-5. SCI Data Register (SCDR)
MC68HC705C8A — Rev. 3
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MOTOROLA
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
10.6.2 SCI Control Register 1
SCI control register 1 (SCCR1) shown in Figure 10-6 has these
functions:
•
Stores ninth SCI data bit received and ninth SCI data bit
transmitted
•
•
Controls SCI character length
Controls SCI wakeup method
Address: $000E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R8
T8
U
M
U
WAKE
Write:
Reset:
U
U
= Unimplemented
U = Unaffected
Figure 10-6. SCI Control Register 1 (SCCR1)
R8 — Bit 8 (Received)
When the SCI is receiving 9-bit characters, R8 is the ninth bit of the
received character. R8 receives the ninth bit at the same time that the
SCDR receives the other eight bits. Reset has no effect on the R8 bit.
T8 — Bit 8 (Transmitted)
When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the
transmitted character. T8 is loaded into the transmit shift register at
the same time that SCDR is loaded into the transmit shift register.
Reset has no effect on the T8 bit.
M — Character Length Bit
This read/write bit determines whether SCI characters are eight or
nine bits long. The ninth bit can be used as an extra stop bit, as a
receiver wakeup signal, or as a mark or space parity bit. Reset has no
effect on the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
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MOTOROLA
Serial Communications Interface (SCI)
SCI I/O Registers
WAKE — Wakeup Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition of the PD0/RDI pin. Reset has no effect
on the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
10.6.3 SCI Control Register 2
SCI control register 2 (SCCR2) shown in Figure 10-7 has these
functions:
•
•
•
•
•
•
Enables the SCI receiver and SCI receiver interrupts
Enables the SCI transmitter and SCI transmitter interrupts
Enables SCI receiver idle interrupts
Enables SCI transmission complete interrupts
Enables SCI wakeup
Transmits SCI break characters
Address: $000F
Bit 7
6
TCIE
0
5
RIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
Read:
TIE
Write:
Reset:
0
Figure 10-7. SCI Control Register 2 (SCCR2)
TIE — Transmit Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the TDRE bit
becomes set. Reset clears the TIE bit.
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
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MOTOROLA
Serial Communications Interface (SCI)
131
Serial Communications Interface (SCI)
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the TC bit
becomes set. Reset clears the TCIE bit.
1 = TC interrupt requests enabled
0 = TC interrupt requests disabled
RIE — Receive Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the RDRF bit
or the OR bit becomes set. Reset clears the RIE bit.
1 = RDRF interrupt requests enabled
0 = RDRF interrupt requests disabled
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the IDLE bit
becomes set. Reset clears the ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
TE — Transmit Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PD1/TDO pin. Reset clears the TE bit.
1 = Transmission enabled
0 = Transmission disabled
RE — Receive Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver and receiver interrupts but does not affect the
receiver interrupt flags. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable Bit
This read/write bit puts the receiver in a standby state. Typically, data
transmitted to the receiver clears the RWU bit and returns the receiver
to normal operation. The WAKE bit in SCCR1 determines whether an
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MOTOROLA
Serial Communications Interface (SCI)
SCI I/O Registers
idle input or an address mark brings the receiver out of the standby
state. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops
the break codes and transmits a logic 1 as a start bit. Reset clears the
SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
10.6.4 SCI Status Register
The SCI status register (SCSR) shown in Figure 10-8 contains flags to
signal these conditions:
•
•
•
•
•
•
•
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Address: $0010
Bit 7
6
5
4
3
2
1
Bit 0
U
Read: TDRE
Write:
TC
RDRF
IDLE
OR
NF
FE
Reset:
1
1
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 10-8. SCI Status Register (SCSR)
MC68HC705C8A — Rev. 3
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
TDRE — Transmit Data Register Empty Bit
This clearable, read-only bit is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set and then writing to the SCDR. Reset
sets the TDRE bit. Software must initialize the TDRE bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Bit
This clearable, read-only bit is set when the TDRE bit is set and no
data, preamble, or break character is being transmitted. TC generates
an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC
bit by reading the SCSR with TC set and then writing to the SCDR.
Reset sets the TC bit. Software must initialize the TC bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF
bit by reading the SCSR with RDRF set and then reading the SCDR.
Reset clears the RDRF bit.
1 = Received data available in SCDR
0 = Received data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an interrupt request if
the ILIE bit in SCCR2 is also set. Clear the IDLE bit by reading the
SCSR with IDLE set, and then reading the SCDR. Reset clears the
IDLE bit.
1 = Receiver input idle
0 = Receiver input not idle
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Serial Communications Interface (SCI)
MOTOROLA
Serial Communications Interface (SCI)
SCI I/O Registers
OR — Receiver Overrun Bit
This clearable, read-only bit is set if the SCDR is not read before the
receive shift register receives the next word. OR generates an
interrupt request if the RIE bit in SCCR2 is also set. The data in the
shift register is lost, but the data already in the SCDR is not affected.
Clear the OR bit by reading the SCSR with OR set and then reading
the SCDR. Reset clears the OR bit.
1 = Receiver shift register full and RDRF = 1
0 = No receiver overrun
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when noise is detected in data
received in the SCI data register. Clear the NF bit by reading the
SCSR and then reading the SCDR. Reset clears the NF bit.
1 = Noise detected in SCDR
0 = No noise detected in SCDR
FE — Receiver Framing Error Bit
This clearable, read-only flag is set when a logic 0 is located where a
stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR bit is set and the FE bit is not set. Clear the FE
bit by reading the SCSR and then reading the SCDR. Reset clears the
FE bit.
1 = Framing error
0 = No framing error
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Serial Communications Interface (SCI)
135
Serial Communications Interface (SCI)
10.6.5 Baud Rate Register
The baud rate register shown in Figure 10-9 selects the baud rate for
both the receiver and the transmitter.
Address: $000D
Bit 7
U
6
5
SCP1
0
4
SCP0
0
3
2
SCR2
U
1
SCR1
U
Bit 0
SCR0
U
Read:
Write:
Reset:
U
U
= Unimplemented
U = Unaffected
Figure 10-9. Baud Rate Register (Baud)
SCP1 and SCP0 — SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator
clock, as shown in Table 10-1. Resets clear both SCP1 and SCP0.
Table 10-1. Baud Rate Generator Clock Prescaling
SCP[1:0]
Baud Rate Generator Clock
Internal clock ÷ 1
00
01
10
11
Internal clock ÷ 3
Internal clock ÷ 4
Internal clock ÷ 13
Technical Data
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MC68HC705C8A — Rev. 3
Serial Communications Interface (SCI)
MOTOROLA
Serial Communications Interface (SCI)
SCI I/O Registers
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate, as shown in
Table 10-2. Reset has no effect on the SCR2–SCR0 bits.
Table 10-2. Baud Rate Selection
SCR[2:1:0]
000
SCI Baud Rate (Baud)
Prescaled clock ÷ 1
Prescaled clock ÷ 2
Prescaled clock ÷ 4
Prescaled clock ÷ 8
Prescaled clock ÷ 16
Prescaled clock ÷ 32
Prescaled clock ÷ 64
Prescaled clock ÷ 128
001
010
011
100
101
110
111
Table 10-3 shows all possible SCI baud rates derived from crystal
frequencies of 2 MHz, 4 MHz, and 4.194304 MHz.
MC68HC705C8A — Rev. 3
Technical Data
137
MOTOROLA
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
Table 10-3. Baud Rate Selection Examples
SCI Baud Rate
= 4 MHz f = 4.194304 MHz
OSC
SCP[1:0]
SCR[2:1:0]
f
= 2 MHz
f
OSC
OSC
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
62.50 Kbaud
31.25 Kbaud
15.63 Kbaud
7813 baud
3906 baud
1953 baud
976.6 baud
488.3 baud
20.83 Kbaud
10.42 Kbaud
5208 baud
2604 baud
1302 baud
651.0 baud
325.5 baud
162.8 baud
15.63 Kbaud
7813 baud
3906 baud
1953 baud
976.6 baud
488.3 baud
244.1 baud
122.1 baud
4808 baud
2404 baud
1202 baud
601.0 baud
300.5 baud
150.2 baud
75.12 baud
37.56 baud
125 Kbaud
131.1 Kbaud
65.54 Kbaud
32.77 Kbaud
16.38 Kbaud
8192 baud
4096 baud
2048 baud
1024 baud
43.69 Kbaud
21.85 Kbaud
10.92 Kbaud
5461 baud
2731 baud
1365 baud
682.7 baud
341.3 baud
32.77 Kbaud
16.38 Kbaud
8192 baud
4906 baud
2048 baud
1024 baud
512.0 baud
256.0 baud
10.08 Kbaud
5041 baud
2521 baud
1260 baud
630.2 baud
315.1 baud
157.5 baud
78.77 baud
62.50 Kbaud
31.25 Kbaud
15.63 Kbaud
7813 baud
3906 baud
1953 baud
976.6 baud
41.67 Kbaud
20.83 Kbaud
10.42 Kbaud
5208 baud
2604 baud
1302 baud
651.0 baud
325.5 baud
31.25 Kbaud
15.63 Kbaud
7813 baud
3906 baud
1953 baud
976.6 baud
488.3 baud
244.1 baud
9615 baud
4808 baud
2404 baud
1202 baud
601.0 baud
300.5 baud
150.2 baud
75.12 baud
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MC68HC705C8A — Rev. 3
Serial Communications Interface (SCI)
MOTOROLA
Technical Data — MC68HC705C8A
Section 11. Serial Peripheral Interface (SPI)
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
11.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
11.4.1 Pin Functions in Master Mode . . . . . . . . . . . . . . . . . . . . . .143
11.4.2 Pin Functions in Slave Mode . . . . . . . . . . . . . . . . . . . . . . .144
11.5 Multiple-SPI Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
11.6 Serial Clock Polarity and Phase . . . . . . . . . . . . . . . . . . . . . . .146
11.7 SPI Error Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.1 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.2 Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.3 Overrun Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.8 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.9 SPI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.9.1 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
11.9.2 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
11.9.3 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
11.2 Introduction
The serial peripheral interface (SPI) module allows full-duplex,
synchronous, serial communication with peripheral devices.
MC68HC705C8A — Rev. 3
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MOTOROLA
Serial Peripheral Interface (SPI)
139
Serial Peripheral Interface (SPI)
11.3 Features
Features of the SPI include:
•
•
•
Full-duplex operation
Master and slave modes
Four programmable master mode frequencies (1.05 MHz
maximum)
•
•
•
•
•
2.1-MHz maximum slave mode frequency
Serial clock with programmable polarity and phase
End of transmission interrupt flag
Write collision error flag
Bus contention error flag
Figure 11-1 shows the structure of the SPI module. Figure 11-2 is a
summary of the SPI input/output (I/O) registers.
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
Features
INTERNAL
CLOCK
(XTAL ÷2)
S
PD2/
MISO
M
M
S
SPI SHIFT REGISTER
7
6 5 4 3 2
1
0
PD3/
MOSI
DIVIDER
÷2
÷4
÷6 ÷32
SHIFT
CLOCK
PD4/
SCK
SPDR ($000C)
SPI CLOCK (MASTER)
SELECT
M
S
CLOCK
LOGIC
PD5/
SS
MSTR
SPE
SPIE
MSTR
SPE
SPI CONTROL
DWOM
SPCR ($000A)
SPSR ($000B)
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 11-1. SPI Block Diagram
MC68HC705C8A — Rev. 3
Technical Data
141
MOTOROLA
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
Addr.
Register Name
Bit 7
SPIE
0
6
5
4
3
CPOL
U
2
CPHA
U
1
SPR1
U
Bit 0
SPR0
U
Read:
SPI Control Register
SPE
MSTR
$000A
(SPCR) Write:
See page 149.
Reset:
0
0
Read: SPIF
WCOL
MODF
SPI Status Register
(SPSR) Write:
$000B
$000C
See page 151.
Reset:
Read:
0
0
0
SPI Data Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
BIt 2
Bit 1
Bit 0
(SPDR) Write:
See page 149.
Reset:
Unaffected by reset
= Unimplemented U = Unaffected
Figure 11-2. SPI I/O Register Summary
11.4 Operation
The master/slave SPI allows full-duplex, synchronous, serial
communication between the microcontroller unit (MCU) and peripheral
devices, including other MCUs. As the 8-bit shift register of a master SPI
transmits each byte to another device, a byte from the receiving device
enters the master SPI shift register. A clock signal from the master SPI
synchronizes data transmission.
Only a master SPI can initiate transmissions. Software begins the
transmission from a master SPI by writing to the SPI data register
(SPDR). The SPDR does not buffer data being transmitted from the SPI.
Data written to the SPDR goes directly into the shift register and begins
the transmission immediately under the control of the serial clock. The
transmission ends after eight cycles of the serial clock when the SPI flag
(SPIF) becomes set. At the same time that SPIF becomes set, the data
shifted into the master SPI from the receiving device transfers to the
SPDR. The SPDR buffers data being received by the SPI. Before the
master SPI sends the next byte, software must clear the SPIF bit by
reading the SPSR and then accessing the SPDR.
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
Operation
In a slave SPI, data enters the shift register under the control of the serial
clock from the master SPI. After a byte enters the shift register of a slave
SPI, it transfers to the SPDR. To prevent an overrun condition, slave
software must then read the byte in the SPDR before another byte enters
the shift register and is ready to transfer to the SPDR.
Figure 11-3 shows how a master SPI exchanges data with a slave SPI.
PD3/MOSI
SPI SHIFT REGISTER
SPI SHIFT REGISTER
PD2/MISO
PD5/SS
7
6
5
4
3
2
1
0
7 6 5 4 3 2 1 0
SPDR ($000C)
SPDR ($000C)
PD4/SCK
MASTER MCU
SLAVE MCU
Figure 11-3. Master/Slave Connections
11.4.1 Pin Functions in Master Mode
Setting the MSTR bit in the SPI control register (SPCR) configures the
SPI for operation in master mode. The master-mode functions of the SPI
pins are:
•
•
•
•
PD4/SCK (serial clock) — In master mode, the PD4/SCK pin is the
synchronizing clock output.
PD3/MOSI (master output, slave input) — In master mode, the
PD3/MOSI pin is the serial output.
PD2/MISO (master input, slave output) — In master mode, the
PD2/MISO pin is configured as the serial input.
PD5/SS (slave select) — In master mode, the PD5/SS pin protects
against driver contention caused by the simultaneous operation of
two SPIs in master mode. A logic 0 on the PD5/SS pin of a master
SPI disables the SPI, clears the MSTR bit, and sets the mode-fault
flag (MODF).
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Serial Peripheral Interface (SPI)
143
Serial Peripheral Interface (SPI)
11.4.2 Pin Functions in Slave Mode
Clearing the MSTR bit in the SPCR configures the SPI for operation in
slave mode. The slave-mode functions of the SPI pins are:
•
•
•
•
PD4/SCK (serial clock) — In slave mode, the PD4/SCK pin is the
input for the synchronizing clock signal from the master SPI.
PD3/MOSI (master output, slave input) — In slave mode, the
PD3/MOSI pin is the serial input.
PD2/MISO (master input, slave output) — In slave mode, the
PD2/MISO pin is the serial output.
PD5/SS (slave select) — In slave mode, the PD5/SS pin enables
the SPI for data and serial clock reception from a master SPI.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases with only one SPI slave MCU, the slave MCU SS
line can be tied to VSS as long as CPHA = 1 clock modes are used.
The WCOL flag bit can be improperly set when attempting the first
transmission after a reset if these conditions are present: MSTR = 0,
CPOL = 0, CPHA = 1, SS pin = 0, and SCK pin = 1. The reset states of
the CPOL and CPHA bits are 0 and 1, respectively. Under normal
operating conditions (CPOL = 0, CPHA = 1), the SCK input will be low.
The incorrect setting of the WCOL bit can be prevented in two ways:
1. Send a dummy transmission after reset, clear the WCOL flag, and
then proceed with the real transmission.
2. Use the MSTR bit in the SPCR (SPI control register). This is
accomplished by setting the MSTR bit at the same time the CPOL
and CPHA bits are programmed to the desired logic levels. Then,
the data register can be written to if desired. After this, the MSTR
bit should be set to a logic 0, the SPE (SPI enable bit) should be
set to a logic 1, and the CPOL, CPHA, SPR1, and SPR0 bits set
to the desired logic levels. If this procedure is followed after a reset
and before the first access to the SPDR, the WCOL flag will not be
set.
Technical Data
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
Multiple-SPI Systems
Example:
LDA #$1C ; MSTR = 1, CPOL = 1, CPHA = 1,
; SPR1 = SPR0 = 0
STA SPCR ; SPI control register
LDA #$4C ; MSTR = 0, SPE = 1, CPOL = 1, CPHA = 1,
; SPR1 = SPR0 = 0
STA SPCR ; SPI control register
11.5 Multiple-SPI Systems
In a multiple-SPI system, all PD4/SCK pins are connected together, all
PD3/MOSI pins are connected together, and all PD2/MISO pins are
connected together.
Before a transmission, one SPI is configured as master and the rest are
configured as slaves. Figure 11-4 is a block diagram showing a single
master SPI and three slave SPIs.
MASTER MCU
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
V
DD
2
I/O
PORT
1
0
SLAVE MCU 2
SLAVE MCU 1
SLAVE MCU 0
Figure 11-4. One Master and Three Slaves Block Diagram
Figure 11-5 is another block diagram with two master/slave SPIs and
three slave SPIs.
MC68HC705C8A — Rev. 3
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MOTOROLA
Serial Peripheral Interface (SPI)
145
Serial Peripheral Interface (SPI)
MASTER/SLAVE
MCU 1
MASTER/SLAVE
MCU 2
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
0
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
0
1
1
I/O
PORT
I/O
PORT
2
2
3
3
SLAVE MCU 2
SLAVE MCU 1
SLAVE MCU 0
Figure 11-5. Two Master/Slaves and Three Slaves Block Diagram
11.6 Serial Clock Polarity and Phase
To accommodate the different serial communication requirements of
peripheral devices, software can change the phase and polarity of the
SPI serial clock. The clock polarity bit (CPOL) and the clock phase bit
(CPHA), both in the SPCR, control the timing relationship between the
serial clock and the transmitted data. Figure 11-6 shows how the CPOL
and CPHA bits affect the clock/data timing.
SS
SCK (A)
SCK (B)
SCK (C)
SCK (D)
SDO/SDI
CPHA CPOL
0
1
0
1
0
0
1
1
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
CAPTURE STROBE
Figure 11-6. SPI Clock/Data Timing
Technical Data
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
SPI Error Conditions
11.7 SPI Error Conditions
These conditions produce SPI system errors:
•
•
•
Bus contention caused by multiple master SPIs (mode fault error)
Writing to the SPDR during a transmission (write-collision error)
Failing to read the SPDR before the next incoming byte sets the
SPIF bit (overrun error)
11.7.1 Mode Fault Error
A mode fault error results when a logic 0 occurs on the PD5/SS pin of a
master SPI. The MCU takes these actions when a mode fault error
occurs:
•
•
•
Puts the SPI in slave mode by clearing the MSTR bit
Disables the SPI by clearing the SPE bit
Sets the MODF bit
11.7.2 Write Collision Error
Writing to the SPDR during a transmission causes a write collision error
and sets the WCOL bit in the SPSR. Either a master SPI or a slave SPI
can generate a write collision error.
•
•
Master — A master SPI can cause a write collision error by writing
to the SPDR while the previously written byte is still being shifted
out to the PD3/MOSI pin. The error does not affect the
transmission of the previously written byte, but the byte that
caused the error is lost.
Slave — A slave SPI can cause a write collision error in either of
two ways, depending on the state of the CPHA bit:
– CPHA = 0 — A slave SPI can cause a write collision error by
writing to the SPDR while the PD5/SS pin is at logic 0. The
error does not affect the byte in the SPDR, but the byte that
caused the error is lost.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Serial Peripheral Interface (SPI)
147
Serial Peripheral Interface (SPI)
– CPHA = 1 — A slave SPI can cause a write collision error by
writing to the SPDR while receiving a transmission, that is,
between the first active SCK edge and the end of the eighth
SCK cycle. The error does not affect the transmission from the
master SPI, but the byte that caused the error is lost.
11.7.3 Overrun Error
Failing to read the byte in the SPDR before a subsequent byte enters the
shift register causes an overrun condition. In an overrun condition, all
incoming data is lost until software clears SPIF. The overrun condition
has no flag.
11.8 SPI Interrupts
The SPIF bit in the SPSR indicates a byte has shifted into or out of the
SPDR. The SPIF bit is a source of SPI interrupt requests. The SPI
interrupt enable bit (SPIE) in the SPCR is the local mask for SPIF
interrupts.
The MODF bit in the SPSR indicates a mode error and is a source of SPI
interrupt requests. The MODF bit is set when a logic 0 occurs on the
PD5/SS pin while the MSTR bit is set. The SPI interrupt enable bit (SPIE)
in the SPCR is the local mask for MODF interrupts.
11.9 SPI I/O Registers
These input/output (I/O) registers control and monitor SPI operation:
•
•
•
SPI data register (SPDR)
SPI control register (SPCR)
SPI status register (SPSR)
Technical Data
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
SPI I/O Registers
11.9.1 SPI Data Register
The SPDR shown in Figure 11-7 is the read buffer for characters
received by the SPI. Writing a byte to the SPDR places the byte directly
into the SPI shift register.
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Unaffected by reset
Figure 11-7. SPI Data Register (SPDR)
11.9.2 SPI Control Register
•
•
•
•
Enables SPI interrupt requests
Enables the SPI
Configures the SPI as master or slave
Selects serial clock polarity, phase, and frequency
Address: $000A
Bit 7
SPIE
0
6
SPE
0
5
4
MSTR
0
3
CPOL
U
2
CPHA
U
1
SPR1
U
Bit 0
SPR0
U
Read:
Write:
Reset:
= Unimplemented
U = Unaffected
Figure 11-8. SPI Control Register (SPCR)
SPIE — SPI Interrupt Enable Bit
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
1 = SPI interrupts enabled
0 = SPI interrupts disabled
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MOTOROLA
Serial Peripheral Interface (SPI)
149
Serial Peripheral Interface (SPI)
SPI — SPI Enable Bit
This read/write bit enables the SPI. Reset clears the SPE bit.
1 = SPI enabled
0 = SPI disabled
MSTR — Master Bit
This read/write bit selects master mode operation or slave mode
operation. Reset clears the MSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the PD4/SCK pin
between transmissions. To transmit data between SPIs, the SPIs
must have identical CPOL bits. Reset has no effect on the CPOL bit.
1 = PD4/SCK pin at logic 1 between transmissions
0 = PD4/SCK pin at logic 0 between transmissions
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. To transmit data between SPIs, the SPIs must
have identical CPHA bits. When CPHA = 0, the PD5/SS pin of the
slave SPI must be set to logic 1 between bytes. Reset has no effect
on the CPHA bit.
1 = Edge following first active edge on PD4/SCK latches data
0 = First active edge on PD4/SCK latches data
SPR1 and SPR0 — SPI Clock Rate Bits
These read/write bits select the master mode serial clock rate, as
shown in Table 11-1. The SPR1 and SPR0 bits of a slave SPI have
no effect on the serial clock. Reset has no effect on SPR1 and SPR0.
Table 11-1. SPI Clock Rate Selection
SPR[1:0]
SPI Clock Rate
Internal Clock ÷ 2
Internal Clock ÷ 4
Internal Clock ÷ 16
Internal Clock ÷ 32
00
01
10
11
Technical Data
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
SPI I/O Registers
11.9.3 SPI Status Register
The SPSR shown in Figure 11-9 contains flags to signal these
conditions:
•
•
•
SPI transmission complete
Write collision
Mode fault
Address: $000B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
SPIF
WCOL
MODF
0
0
0
= Unimplemented
Figure 11-9. SPI Status Register (SPSR)
SPIF — SPI Flag
This clearable, read-only bit is set each time a byte shifts out of or into
the shift register. SPIF generates an interrupt request if the SPIE bit
in the SPCR is also set. Clear SPIF by reading the SPSR with SPIF
set and then reading or writing the SPDR. Reset clears the SPIF bit.
1 = Transmission complete
0 = Transmission not complete
WCOL — Write Collision Bit
This clearable, read-only flag is set when software writes to the SPDR
while a transmission is in progress. Clear the WCOL bit by reading the
SPSR with WCOL set and then reading or writing the SPDR. Reset
clears WCOL.
1 = Invalid write to SPDR
0 = No invalid write to SPDR
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Serial Peripheral Interface (SPI)
151
Serial Peripheral Interface (SPI)
MODF — Mode Fault Bit
This clearable, read-only bit is set when a logic 0 occurs on the
PD5/SS pin while the MSTR bit is set. MODF generates an interrupt
request if the SPIE bit is also set. Clear the MODF bit by reading the
SPSR with MODF set and then writing to the SPCR. Reset clears
MODF.
1 = PD5/SS pulled low while MSTR bit set
0 = PD5/SS not pulled low while MSTR bit set
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Serial Peripheral Interface (SPI)
MOTOROLA
Technical Data — MC68HC705C8A
Section 12. Instruction Set
12.1 Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .158
12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .159
12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .160
12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .162
12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
12.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
12.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
MC68HC705C8A — Rev. 3
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Instruction Set
153
Instruction Set
12.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
12.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction.
The eight addressing modes are:
•
•
•
•
•
•
•
•
Inherent
Immediate
Direct
Extended
Indexed, no offset
Indexed, 8-bit offset
Indexed, 16-bit offset
Relative
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Instruction Set
MOTOROLA
Instruction Set
Addressing Modes
12.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
12.3.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
12.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
12.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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Instruction Set
155
Instruction Set
12.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
12.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
12.3.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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Instruction Set
MOTOROLA
Instruction Set
Instruction Types
12.3.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
12.4 Instruction Types
The MCU instructions fall into five categories:
•
•
•
•
•
Register/memory instructions
Read-modify-write instructions
Jump/branch instructions
Bit manipulation instructions
Control instructions
MC68HC705C8A — Rev. 3
Technical Data
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MOTOROLA
Instruction Set
Instruction Set
12.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 12-1. Register/Memory Instructions
Instruction
Add memory byte and carry bit to accumulator
Add memory byte to accumulator
AND memory byte with accumulator
Bit test accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare accumulator
CMP
CPX
Compare index register with memory byte
Exclusive OR accumulator with memory byte
Load accumulator with memory byte
Load Index register with memory byte
Multiply
EOR
LDA
LDX
MUL
ORA
OR accumulator with memory byte
Subtract memory byte and carry bit from
accumulator
SBC
Store accumulator in memory
STA
STX
SUB
Store index register in memory
Subtract memory byte from accumulator
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Instruction Set
MOTOROLA
Instruction Set
Instruction Types
12.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE: Do not use read-modify-write operations on write-only registers.
Table 12-2. Read-Modify-Write Instructions
Instruction
Arithmetic shift left (same as LSL)
Arithmetic shift right
Mnemonic
ASL
ASR
(1)
Bit clear
BCLR
(1)
Bit set
BSET
Clear register
CLR
COM
DEC
INC
Complement (one’s complement)
Decrement
Increment
Logical shift left (same as ASL)
Logical shift right
LSL
LSR
NEG
ROL
ROR
Negate (two’s complement)
Rotate left through carry bit
Rotate right through carry bit
Test for negative or zero
(2)
TST
1. Unlike other read-modify-write instructions, BCLR and BSET use
only direct addressing.
2. TST is an exception to the read-modify-write sequence because it
does not write a replacement value.
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MOTOROLA
Instruction Set
Instruction Set
12.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
Technical Data
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Instruction Set
MOTOROLA
Instruction Set
Instruction Types
Table 12-3. Jump and Branch Instructions
Instruction
Branch if carry bit clear
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if carry bit set
Branch if equal
Branch if half-carry bit clear
Branch if half-carry bit set
Branch if higher
Branch if higher or same
Branch if IRQ pin high
Branch if IRQ pin low
Branch if lower
BHS
BIH
BIL
BLO
BLS
Branch if lower or same
Branch if interrupt mask clear
Branch if minus
BMC
BMI
Branch if interrupt mask set
Branch if not equal
Branch if plus
BMS
BNE
BPL
Branch always
BRA
BRCLR
BRN
BRSET
BSR
JMP
Branch if bit clear
Branch never
Branch if bit set
Branch to subroutine
Unconditional jump
Jump to subroutine
JSR
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MOTOROLA
Instruction Set
Instruction Set
12.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 12-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Bit clear
Branch if bit clear
Branch if bit set
Bit set
BRCLR
BRSET
BSET
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Instruction Set
MOTOROLA
Instruction Set
Instruction Types
12.4.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 12-5. Control Instructions
Instruction
Mnemonic
CLC
CLI
Clear carry bit
Clear interrupt mask
No operation
NOP
RSP
RTI
Reset stack pointer
Return from interrupt
Return from subroutine
Set carry bit
RTS
SEC
SEI
Set interrupt mask
Stop oscillator and enable IRQ pin
Software interrupt
STOP
SWI
Transfer accumulator to index register
Transfer index register to accumulator
Stop CPU clock and enable interrupts
TAX
TXA
WAIT
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MOTOROLA
Instruction Set
Instruction Set
12.5 Instruction Set Summary
Table 12-6. Instruction Set Summary (Sheet 1 of 6)
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
ii
dd
hh ll
ee ff
ff
ADC #opr
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
2
3
4
5
4
3
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
Add without Carry
Logical AND
A ← (A) + (M) + (C)
—
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
2
3
4
5
4
3
A ← (A) + (M)
—
ii
dd
hh ll
ee ff
ff
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
2
3
4
5
4
3
A ← (A) (M)
— —
—
dd
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
INH
IX1
IX
38
48
58
68
78
5
3
3
6
5
C
0
Arithmetic Shift Left (Same as LSL)
— —
— —
b7
b7
b0
b0
ff
dd
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
INH
IX1
IX
37
47
57
67
77
5
3
3
6
5
C
Arithmetic Shift Right
ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? C = 0
— — — — — REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
BCS rel
BEQ rel
BHCC rel
BHCS rel
BHI rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
25 rr
27 rr
28 rr
29 rr
22 rr
24 rr
3
3
3
3
3
3
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? C Z = 0 — — — — — REL
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL
BHS rel
Branch if Higher or Same
Technical Data
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Instruction Set
MOTOROLA
Instruction Set
Instruction Set Summary
Table 12-6. Instruction Set Summary (Sheet 2 of 6)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL
2F rr
2E rr
3
3
BIL rel
Branch if IRQ Pin Low
ii
dd
hh ll
ee ff
ff
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
2
3
4
5
4
3
Bit Test Accumulator with Memory Byte
(A) (M)
— —
—
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? C = 1
— — — — — REL
25 rr
23 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? C Z = 1 — — — — — REL
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
PC ← (PC) + 2 + rel ? Mn = 0 — — — —
BRN rel
Branch Never
PC ← (PC) + 2 + rel ? 1 = 0
— — — — — REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
PC ← (PC) + 2 + rel ? Mn = 1 — — — —
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
Set Bit n
Mn ← 1
— — — — —
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
— — — — — REL
AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
— 0 — — —
INH
INH
98
9A
2
2
Clear Interrupt Mask
MC68HC705C8A — Rev. 3
Technical Data
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MOTOROLA
Instruction Set
Instruction Set
Table 12-6. Instruction Set Summary (Sheet 3 of 6)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
dd
ff
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
5
3
3
6
5
Clear Byte
— — 0 1 —
ii
dd
hh ll
ee ff
ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
2
3
4
5
4
3
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
Decrement Byte
(A) – (M)
— —
dd
ff
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
5
3
3
6
5
— —
— —
— —
— —
— —
1
ii
dd
hh ll
ee ff
ff
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
2
3
4
5
4
3
(X) – (M)
dd
ff
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
5
3
3
6
5
—
—
—
ii
dd
hh ll
ee ff
ff
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
2
3
4
5
4
3
EXCLUSIVE OR Accumulator with Memory
Byte
A ← (A) (M)
dd
ff
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
5
3
3
6
5
Increment Byte
dd
hh ll
ee ff
ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
2
3
4
3
2
Unconditional Jump
PC ← Jump Address
— — — — —
Technical Data
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Instruction Set
MOTOROLA
Instruction Set
Instruction Set Summary
Table 12-6. Instruction Set Summary (Sheet 4 of 6)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
dd
hh ll
ee ff
ff
JSR opr
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
— — — — —
ii
dd
hh ll
ee ff
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
2
3
4
5
4
3
Load Accumulator with Memory Byte
A ← (M)
X ← (M)
— —
—
—
ii
dd
hh ll
ee ff
ff
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
2
3
4
5
4
3
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
— —
dd
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
38
48
58
68
78
5
3
3
6
5
C
0
— —
b7
b0
ff
dd
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
INH
IX1
IX
34
44
54
64
74
5
3
3
6
5
0
C
Logical Shift Right
Unsigned Multiply
— — 0
b7
b0
ff
1
1
MUL
X : A ← (X) × (A)
0 — — — 0
INH
42
dd
ff
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
IX1
IX
30
40
50
60
70
5
3
3
6
5
Negate Byte (Two’s Complement)
— —
NOP
No Operation
— — — — —
INH
9D
2
ii
dd
hh ll
ee ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
2
3
4
5
4
3
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
A ← (A) (M)
— —
—
dd
ff
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
INH
IX1
IX
39
49
59
69
79
5
3
3
6
5
C
— —
b7
b0
MC68HC705C8A — Rev. 3
Technical Data
167
MOTOROLA
Instruction Set
Instruction Set
Table 12-6. Instruction Set Summary (Sheet 5 of 6)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
dd
ff
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
INH
IX1
IX
36
46
56
66
76
5
3
3
6
5
C
Rotate Byte Right through Carry Bit
— —
b7
b0
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $00FF
— — — — —
INH
9C
2
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
INH
80
9
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
— — — — —
INH
81
6
ii
dd
hh ll
ee ff
ff
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
2
3
4
5
4
3
Subtract Memory Byte and Carry Bit from
Accumulator
A ← (A) – (M) – (C)
— —
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
— 1 — — —
INH
INH
99
9B
2
2
Set Interrupt Mask
dd
hh ll
ee ff
ff
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
4
5
6
5
4
Store Accumulator in Memory
Stop Oscillator and Enable IRQ Pin
Store Index Register In Memory
M ← (A)
— —
—
STOP
— 0 — — —
INH
8E
2
dd
hh ll
ee ff
ff
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
4
5
6
5
4
M ← (X)
— —
— —
—
ii
dd
hh ll
ee ff
ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
2
3
4
5
4
3
Subtract Memory Byte from Accumulator
A ← (A) – (M)
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
1
0
SWI
TAX
Software Interrupt
— 1 — — —
INH
INH
83
97
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Transfer Accumulator to Index Register
X ← (A)
— — — — —
2
Technical Data
168
MC68HC705C8A — Rev. 3
Instruction Set
MOTOROLA
Instruction Set
Opcode Map
Table 12-6. Instruction Set Summary (Sheet 6 of 6)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
dd
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
4
3
3
5
4
Test Memory Byte for Negative or Zero
(M) – $00
A ← (X)
— —
—
ff
TXA
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
— — — — —
— — — —
INH
INH
9F
8F
2
2
WAIT
A
C
Accumulator
Carry/borrow flag
opr
PC
Operand (one or two bytes)
Program counter
CCR Condition code register
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
dd
Direct address of operand
dd rr
DIR
ee ff
EXT
ff
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
rel
rr
SP
X
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
H
Z
Zero flag
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
#
Immediate value
Logical AND
ii
Immediate operand byte
Logical OR
IMM
INH
IX
IX1
IX2
M
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
( )
–( )
←
?
If
:
Concatenated with
Set or cleared
N
Negative flag
n
Any bit
—
Not affected
12.6 Opcode Map
See Table 12-7.
MC68HC705C8A — Rev. 3
Technical Data
169
MOTOROLA
Instruction Set
Table 12-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
INH
IX1
IX
7
INH
INH
IMM
A
DIR
B
EXT
IX2
IX1
E
IX
F
MSB
LSB
MSB
LSB
0
1
2
4
5
6
8
9
C
D
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
SUB
SUB
SUB
SUB
SUB
SUB
CMP
SBC
CPX
AND
BIT
0
1
0
3
DIR 2
5
BRCLR0
DIR 2
5
BRSET1
DIR 2
5
BRCLR1
DIR 2
5
BRSET2
DIR 2
5
BRCLR2
DIR 2
5
BRSET3
DIR 2
5
BRCLR3
DIR 2
5
BRSET4
DIR 2
5
BRCLR4
DIR 2
5
BRSET5
DIR 2
5
BRCLR5
DIR 2
5
BRSET6
DIR 2
5
BRCLR6
DIR 2
5
BRSET7
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
6
RTS
INH
2
2
2
2
2
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
CMP
IX2 2
IX1 1
4
CMP
IX1 1
IX
3
BCLR0
BRN
CMP
CMP
CMP
1
2
3
DIR 2
5
REL
3
1
IMM 2
2
DIR 3
3
EXT 3
4
IX
3
11
5
4
BSET1
BHI
MUL
SBC
SBC
SBC
SBC
CPX
AND
BIT
SBC
CPX
AND
BIT
2
3
DIR 2
5
REL
3
1
5
INH
3
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
3
6
5
10
SWI
INH
BCLR1
BLS
COM
COMA
COMX
COM
COM
LSR
CPX
CPX
CPX
3
3
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX 1
5
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET2
BCC
LSR
LSRA
LSRX
LSR
AND
AND
AND
4
4
3
DIR 2
5
BCLR2 BCS/BLO
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BIT
BIT
BIT
5
5
3
DIR 2
5
REL
3
IMM 2
2
DIR 3
3
LDA
DIR 3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
5
3
3
6
5
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
ASR
LDA
LDA
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
EOR
ADC
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
6
6
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
IMM 2
EXT 3
5
IX2 2
6
IX1 1
5
IX
4
2
4
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
STA
7
7
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
1
1
1
1
1
1
1
INH
2
2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
CLC
EOR
EOR
EOR
8
8
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
DEC
SEC
ADC
ADC
ADC
9
9
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
ORA
IX1 1
IX
3
BSET5
BPL
DEC
DECA
DECX
DEC
CLI
ORA
ORA
ORA
A
B
C
D
E
F
A
B
C
D
E
F
3
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX
3
4
BCLR5
BMI
SEI
ADD
ADD
ADD
ADD
JMP
JSR
LDX
STX
3
DIR 2
5
REL
3
INH 2
2
IMM 2
DIR 3
2
EXT 3
3
IX2 2
4
IX1 1
3
IX
2
5
3
3
6
5
BSET6
BMC
INC
INCA
INCX
INC
TST
INC
TST
RSP
INH
JMP
JMP
3
DIR 2
5
REL 2
3
DIR 1
4
INH 1
3
INH 2
3
IX1 1
5
IX
4
2
6
DIR 3
5
EXT 3
6
IX2 2
7
IX1 1
6
IX
5
2
BCLR6
BMS
TST
TSTA
TSTX
NOP
BSR
JSR
JSR
3
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
REL 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
2
BSET7
BIL
STOP
LDX
LDX
LDX
3
DIR 2
5
DIR 2
5
BCLR7
DIR 2
REL
3
BIH
REL 2
1
INH
2
WAIT
INH 1
2
2
IMM 2
DIR 3
4
EXT 3
5
STX
EXT 3
IX2 2
6
IX1 1
5
IX
4
5
3
3
6
5
BRCLR7
CLR
DIR 1
CLRA
INH 1
CLRX
INH 2
CLR
CLR
TXA
INH
STX
3
DIR 2
IX1 1
IX 1
2
DIR 3
IX2 2
IX1 1
IX
MSB
INH = Inherent
IMM = Immediate
DIR = Direct
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
0
MSB of Opcode in Hexadecimal
Number of Cycles
LSB
5
BRSET0 Opcode Mnemonic
DIR Number of Bytes/Addressing Mode
LSB of Opcode in Hexadecimal
0
EXT = Extended
3
Technical Data — MC68HC705C8A
Section 13. Electrical Specifications
13.1 Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
13.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .173
13.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
13.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.7 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .175
13.8 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .176
13.9 5.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
13.10 3.3-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . .185
13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . .187
13.2 Introduction
This section contains electrical and timing specifications.
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Electrical Specifications
171
Ele c tric a l Sp e c ific a tions
13.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD
.
(1)
Symbol
Value
Unit
Rating
Supply voltage
V
–0.3 to +7.0
V
DD
V
–0.3
SS
Input voltage
V
V
In
to V +0.3
DD
V
–0.3 to
16.0
DD
Programming voltage
V
PP
V
– 0.3
SS
Bootstrap mode (IRQ pin only)
Current drain per pin excluding
V
In
V
to 2 x V + 0.3
DD
I
25
mA
V
and V
DD
SS
Storage temperature range
1. Voltages referenced to V
T
–65 to +150
°C
STG
SS
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 13.7 5.0-Volt DC Electrical Characteristics and
13.8 3.3-Volt DC Electrical Characteristics for guaranteed operating
conditions.
Technical Data
172
MC68HC705C8A — Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
Operating Temperature Range
13.4 Operating Temperature Range
(1)
Symbol
Value
Unit
Rating
(2)
Operating temperature range
MC68HC705C8ACB
MC68HC705C8ACFB
MC68HC705C8ACFS
MC68HC705C8ACP
T to T
L
H
T
°C
A
– 40 to + 85
MC68HC705C8ACFN
MC68HC705C8ACFS
1. Voltages referenced to V
SS
2. C = Extended temperature range (– 40°C to + 85°C)
P = Plastic dual in-line package (PDIP)
B = Plastic shrink dual in-line package (SDIP)
S = Ceramic dual in-line package (cerdip)
FN = Plastic-leaded chip carrier (PLCC)
FB = Quad flat pack (QFP)
FS = Ceramic-leaded chip carrier (CLCC)
13.5 Thermal Characteristics
Characteristic
Thermal resistance
Symbol
Value
Unit
Plastic dual in-line package (DIP)
Ceramic dual in-line package (cerdip)
Plastic leaded chip carrier (PLCC)
Quad flat pack (QFP)
60
50
70
95
60
θ
°C/W
JA
Plastic shrink DIP (SDIP)
V
= 4.5 V
DD
V
DD
Pins
R1
R2
C
PA7–PA0
PB7–PB0
PC7–PC0
PD4–PD1
R2
3.26 kΩ
2.38 kΩ
50 pF
(SEE TABLE)
TEST
POINT
C
R1
(SEE TABLE)
(SEE TABLE)
V
= 3.0 V
DD
Pins
R1
R2
C
PA7–PA0
PB7–PB0
PC7–PC0
PD4–PD1
10.91 kΩ
6.32 kΩ
50 pF
PD7, PD5, PD0
6 kΩ
6 kΩ
200 pF
Figure 13-1. Equivalent Test Load
MC68HC705C8A — Rev. 3
Technical Data
173
MOTOROLA
Electrical Specifications
Ele c tric a l Sp e c ific a tions
13.6 Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
TJ = TA + (PD x θJA) (1)
Where:
TA = ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD = PINT + PI/O
PINT = ICC × VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O < PINT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately:
K
PD =
(2)
(3)
TJ + 273°C
Solving equations (1) and (2) for K gives:
= PD x (TA + 273°C) + θJA x (PD)2
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
Technical Data
174
MC68HC705C8A — Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
5.0-Volt DC Electrical Characteristics
13.7 5.0-Volt DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
V
—
—
—
0.1
—
OL
Output voltage, I
≤ 10.0 µA
V
Load
V
V
– 0.1
V
DD
OH
Output high voltage
I
= –0.8 mA, PA7–PA0, PB7–PB0, PC6–PC0, TCMP
Load
(see Figure 13-2)
V
– 0.8
—
—
—
—
—
—
V
V
OH
DD
I
I
= –1.6 mA, PD4–PD1 (see Figure 13-3)
Load
= –5.0 mA, PC7
Load
Output low voltage (see Figure 13-4)
I
= 1.6 mA
Load
V
OL
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
= 20 mA, PC7
—
—
—
—
0.4
0.4
I
Load
Input high voltage
V
0.7 x V
V
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0, PD7,
TCAP, IRQ, RESET, OSC1
—
—
V
V
IH
DD
DD
Input low voltage
V
V
0.2 x V
DD
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0, PD7,
TCAP, IRQ, RESET, OSC1
IL
SS
V
EPROM programming voltage
EPROM/OTPROM programming current
User mode current
14.5
—
14.75
5
15.0
10
V
mA
mA
V
PP
I
PP
I
—
—
± 10
—
PP
V
Data-retention mode (0°C to 70°C)
2.0
—
RM
(3)
Supply current
(4)
Run
—
—
5.0
1.95
7.0
3.0
mA
mA
(5)
Wait
I
DD
(6)
Stop
—
—
5.0
5.0
50
50
µµA
µµA
25°C
–40°C to +85°C
I/O ports hi-z leakage current
I
—
—
—
—
± 10
± 1
µA
µA
IL
PA7–PA0, PB7–PB0, PC7–PC0, PD4–PD1, PD7, RESET
I
Input current, IRQ, TCAP, OSC1, PD0, PD5
In
Capacitance
C
—
—
—
—
12
8
Out
Ports (as input or output)
RESET, IRQ, TCAP, PD0–PD5, PD7
pF
C
In
1. V = 5 V ± 10%; V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. I measured with port B pullup devices disabled.
DD
4. Run (operating) I measured using external square wave clock source (f
= 4.2 MHz). All inputs 0.2 V from rail. No dc
DD
OSC
loads. Less than 50 pF on all outputs. C = 20 pF on OSC2. OSC2 capacitance linearly affects run I
.
DD
L
5. Wait I measured using external square wave clock source (f
= 4.2 MHz). All inputs 0.2 V from rail. No dc loads. Less
DD
OSC
than 50 pF on all outputs. C = 20 pF on OSC2. V = 0.2 V, V = V – 0.2 V. All ports configured as inputs. SPI and SCI
L
IL
IH
DD
disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait I
.
DD
6. Stop I measured with OSC1 = V . All ports configured as inputs. V = 0.2 V, V = V – 0.2 V.
DD
DD
IL
IH
DD
MC68HC705C8A — Rev. 3
Technical Data
175
MOTOROLA
Electrical Specifications
Ele c tric a l Sp e c ific a tions
13.8 3.3-Volt DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
V
V
—
—
—
0.1
—
OL
Output voltage, I
≤ 10.0 µA
V
Load
V
V
– 0.1
DD
OH
Output high voltage
I
= –0.2 mA
Load
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(see Figure 13-2)
—
—
—
—
—
—
V
– 0.3
V
OH
DD
I
I
= –0.4 mA
Load
PD4–PD1 (see Figure 13-3)
= –1.5 mA
Load
PC7
Output low voltage (see Figure 13-4)
I
I
= 0.4 mA
Load
V
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
= 6.0 mA
—
—
—
0.3
0.3
V
V
OL
Load
—
PC7
Input high voltage
V
0.7 x V
V
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0,
PD7, TCAP, IRQ, RESET, OSC1
—
IH
DD
DD
Input low voltage
V
V
0.2 x V
DD
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0,
PD7, TCAP, IRQ, RESET, OSCI
—
—
V
V
IL
SS
V
Data-retention mode (0°C to 70°C)
2.0
—
RM
(3)
Supply current
(4)
Run
—
—
—
1.53
0.711
2.0
3.0
1.0
20
mA
mA
µA
I
DD
(5)
Wait
(6)
Stop
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0, PC7–PC0, PD4–PD1,
PD7, RESET
I
I
—
—
—
—
± 10
± 1
µA
µA
IL
In
Input current
IRQ, TCAP, OSC1, PD5, PD0
1. V = 3.3 V ± 10%; V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
2. Typical values at midpoint of voltage range, 25°C only.
3. I measured with port B pullup devices disabled.
DD
4. Run (operating) I measured using external square wave clock source (f
= 2.0 MHz). All inputs 0.2 V from rail. No dc
DD
OSC
loads. Less than 50 pF on all outputs. C = 20 pF on OSC2. OSC2 capacitance linearly affects run I
L
DD.
5. Wait I measured using external square wave clock source (f
= 2.0 MHz). All inputs 0.2 V from rail. No dc loads. Less
DD
OSC
than 50 pF on all outputs. C = 20 pF on OSC2. V = 0.2 V, V = V – 0.2 V. All ports configured as inputs. SPI and SCI
L
IL
IH
DD
disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait I
.
DD
6. Stop I measured with OSC1 = V . All ports configured as inputs. V = 0.2 V; V = V – 0.2 V.
DD
DD
IL
IH
DD
Technical Data
176
MC68HC705C8A — Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt DC Electrical Characteristics
5.0
4.0
3.0
2.0
V
0
.
5
=
V
V
0
.
3
=
D
VD
SEE NOTE 1
1.0
0.8
SEE NOTE 2
0.2
0
0
0.2
0.4
0.6
0.8
VDD – VOH (VOLTS)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for (VDD – VOH
≤ 800 mV @ IOH = –0.8 mA.
)
)
2. At VDD = 3.3 V, devices are specified and tested for (VDD – VOH
≤ 300 mV @ IOH = –0.2 mA.
(a) V
versus I
for Ports A, B, PC6–PC0, and TCMP
OH
OH
8.0
6.0
4.0
SEE NOTE 1
V
0
.
2.0
1.6
3
=
V
SEE NOTE 2
0.4
0
0
0.2
0.4
0.6
VDD – VOH (VOLTS)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for
(VDD – VOH) ≤ 800 mV @ IOH = –1.6 mA.
2. At VDD = 3.3 V, devices are specified and tested for
(VDD – VOH) ≤ 300 mV @ IOH = –0.4 mA.
(b) V
versus I
for PD4–PD1
OH
OH
Figure 13-2. Typical Voltage Compared to Current
MC68HC705C8A — Rev. 3
Technical Data
177
MOTOROLA
Electrical Specifications
Ele c tric a l Sp e c ific a tions
6.0
5.0
4.0
3.0
V
0
.
5
=
V
V
0
.
3
=
D
D
SEE NOTE 1
V
2.0
1.6
1.0
SEE NOTE 2
0.4
0
0
0.1
0.2
OL (VOLTS)
0.3
0.4
V
Notes:
1. At VDD = 5.0 V, devices are specified and tested for
VOL ≤ 400 mV @ IOL = 1.6 mA.
2. At VDD = 3.3 V, devices are specified and tested for
VOL ≤ 300 mV @ IOL = 0.4 mA.
(c) V versus I for All Ports Except PC7
OL
OL
Figure 13-2. Typical Voltage Compared to Current (Continued)
Technical Data
178
MC68HC705C8A — Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt DC Electrical Characteristics
2.0
1.8
1.6
1.4
1.2
1.0
0.8
D
D
0.6
0.4
0.2
V
3
.
3
=
V DD
0.0
2.0
0.0
0.5
1.0
1.5
INTERNAL FREQUENCY 1 tCYC (MHz)
(a) Wait Mode
5.5
5.0
4.5
4.0
D
D
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.0
0.0
0.5
1.0
1.5
INTERNAL FREQUENCY 1 tCYC (MHz)
(b) Run Mode
Figure 13-3. Typical Current versus Internal
Frequency for Run and Wait Modes
MC68HC705C8A — Rev. 3
Technical Data
179
MOTOROLA
Electrical Specifications
Ele c tric a l Sp e c ific a tions
3.0 mA
2.5 mA
T = –40°C to 85°C
VDD = 3.3 V ± 10%
D
I D
)
G
2.0 mA
1.5 mA
N
I
T
A
R
E
P
O
(
N
U
R
1.0 mA
500 mA
0
I
T
I
A
W
(20 µA)
750 kHz
STOP IDD
500 kHz
0
1 MHz
250 kHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
(a) Maximum Current Drain versus Frequency @ 3.3 V ± 10 %
7.0 mA
T = –40°C to 85°C
VDD = 5.0 V ± 10%
6.0 mA
5.0 mA
4.0 mA
3.0 mA
2.0 mA
D
D
1.0 mA
0
STOP IDD
(50 µA)
0
2 MHz
500 kHz
1 MHz
1.5 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
(b) Maximum Current Drain versus Frequency @ 5 V ± 10%
Figure 13-4. Total Current Drain versus Frequency
Technical Data
180
MC68HC705C8A — Rev. 3
MOTOROLA
Electrical Specifications
Electrical Specifications
5.0-Volt Control Timing
13.9 5.0-Volt Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Frequency of operation
Crystal option
f
—
dc
4.2
4.2
MHz
OSC
External clock option
Internal operating frequency
Crystal (f
÷ 2)
f
—
dc
2.1
2.1
MHz
OSC
OP
External clock (f
÷ 2)
OSC
t
Cycle time (see Figure 13-7)
480
—
ns
CYC
t
Crystal oscillator startup time (see Figure 13-7)
—
100
ms
OXOV
Stop recovery startup time (crystal oscillator)
t
—
8
100
ms
ILCH
(see Figure 13-6)
t
t
RESET pulse width (see Figure 13-7)
—
RL
CYC
Timer
t
t
4.0
125
RESL
—
—
—
CYC
(2)
Resolution
t
, t
ns
TH TL
Input capture pulse width (see Figure 13-5)
Input capture pulse period (see Figure 13-5)
(3)
t
t
CYC
TLTL
Interrupt pulse width low (edge-triggered)
t
125
(4)
—
ns
ILIH
(see Figure 4-2. External Interrupt Timing)
Interrupt pulse period
t
t
—
—
ILIL
CYC
(see Figure 4-2. External Interrupt Timing)
t
, t
OSC1 pulse width
90
ns
OH OL
1. V = 5.0 Vdc ± 10%, V = 0 Vdc; T = T to T
H
DD
SS
A
L
2. Since a 2-bit prescaler in the timer must count four internal cycles (t
the timer resolution.
), this is the limiting minimum factor in determining
CYC
3. The minimum period, t
, should not be less than the number of cycle times it takes to execute the capture interrupt ser-
TLTL
vice routine plus 24 t
.
CYC
4. The minimum period, t , should not be less than the number of cycle times it takes to execute the interrupt service routine
ILIL
plus 19 t
.
CYC
MC68HC705C8A — Rev. 3
Technical Data
181
MOTOROLA
Electrical Specifications
Ele c tric a l Sp e c ific a tions
13.10 3.3-Volt Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Frequency of operation
Crystal option
—
dc
2.0
2.0
f
MHz
OSC
External clock option
Internal operating frequency
—
dc
1.0
1.0
Crystal (fOSC ÷ 2)
f
MHz
OP
External clock (fOSC ÷ 2)
t
Cycle time (see Figure 13-7)
1000
—
ns
CYC
t
Crystal oscillator startup time (see Figure 13-7)
—
100
ms
OXOV
Stop recovery startup time (crystal oscillator)
t
—
100
ms
ILCH
(see Figure 13-6)
RESET pulse width, excluding power-up
t
t
8
—
RL
CYC
(see Figure 13-7)
Timer
(2)
t
t
4.0
250
RESL
—
—
—
CYC
Resolution
t
, t
ns
Input capture pulse width (see Figure 13-5)
Input capture pulse period (see Figure 13-5)
TH TL
(3)
t
t
CYC
TLTL
Interrupt pulse width low (edge-triggered)
t
250
(4)
—
ns
ILIH
(see Figure 4-2. External Interrupt Timing)
Interrupt pulse period
t
t
—
—
ILIL
CYC
(see Figure 4-2. External Interrupt Timing)
t
, t
OSC1 pulse width
200
ns
OH OL
1. V = 3.3 Vdc ± 0.3 Vdc, V = 0 Vdc; T = T to T
H
DD
SS
A
L
2. Since a 2-bit prescaler in the timer must count four internal cycles (t
the timer resolution.
), this is the limiting minimum factor in determining
CYC
3. The minimum period, t
, should not be less than the number of cycle times it takes to execute the capture interrupt ser-
TLTL
vice routine plus 24 t
.
CYC
4. The minimum period, t , should not be less than the number of cycle times it takes to execute the interrupt service routine
ILIL
plus 19 t
.
CYC
tTLTL
tTH
tTL
*
*
*
EXTERNAL SIGNAL
(TCAP PIN 37)
*
Refer to timer resolution data in Figure 13-6 and Figure 13-7.
Figure 13-5. Timer Relationships
Technical Data
182
MC68HC705C8A — Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt Control Timing
(1)
OSC1
tRL
RESET
(2)
tILIH
IRQ
(3)
tILCH
4064 tCYC
IRQ
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
(4)
1FFE
1FFE
1FFE
1FFE
1FFF
RESET OR INTERRUPT
VECTOR FETCH
Notes:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive option
3. IRQ pin level and edge-sensitive option
4. RESET vector address shown for timing example
Figure 13-6. Stop Recovery Timing Diagram
MC68HC705C8A — Rev. 3
Technical Data
183
MOTOROLA
Electrical Specifications
tVDDR
VDD THRESHOLD (1-2 V TYPICAL)
V
DD
*
OSC1
tOXOV
tCYC
INTERNAL
PROCESSOR
CLOCK
INTERNAL
ADDRESS
1FFE
1FFF
NEW PC
1FFE
1FFE
1FFE
1FFE
PCH
1FFF
PCL
NEW PC
**
BUS
INTERNAL
DATA
OP
CODE
OP
CODE
NEW
PCH
NEW
PCL
***
BUS
tRL
RESET
* *
*
*
OSC1 line is not meant to represent frequency. It is only used to represent time.
** Internal timing signal and bus information are not available externally.
***The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
Figure 13-7. Power-On Reset and External Reset Timing Diagram
Electrical Specifications
5.0-Volt Serial Peripheral Interface (SPI) Timing
13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing
(1)
(2)
Symbol
Min
Max
Unit
Number
Characteristic
Operating frequency
f
f
Master
Slave
dc
dc
0.5
2.1
OP(M)
OP
f
MHz
OP(S)
Cycle time
Master
t
t
1
2
3
4
5
6
7
2.0
480
—
—
CYC(M)
CYC
Slave
t
ns
CYC(S)
Enable lead time
Master
(3)
t
—
—
ns
Lead(M)
Slave
t
240
Lead(S)
Enable lag time
Master
t
(2)
—
—
ns
ns
ns
ns
ns
Lag(M)
720
Slave
t
Lag(S)
Clock (SCK) high time
t
Master
Slave
340
190
—
—
W(SCKH)M
t
W(SCKH)S
Clock (SCK) low time
Master
t
340
190
—
—
W(SCKL)M
Slave
t
W(SCKL)S
Data setup time (inputs)
t
Master
Slave
100
100
—
—
SU(M)
t
SU(S)
Data hold time (inputs)
t
Master
Slave
100
100
—
—
H(M)
t
H(S)
(4)
Access time
t
8
9
0
120
240
ns
ns
A
Slave
(5)
Disable time
t
—
DIS
Slave
Data valid time
t
Master (before capture edge)
t
10
0.25
—
—
240
V(M)
CYC(M)
(6)
t
ns
Slave (after enable edge)
V(S)
Continued
MC68HC705C8A — Rev. 3
Technical Data
185
MOTOROLA
Electrical Specifications
Ele c tric a l Sp e c ific a tions
(1)
(2)
Symbol
Min
Max
Unit
Number
Characteristic
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
t
t
11
0.25
0
—
—
HO(M)
CYC(M)
t
ns
HO(S)
(7)
Rise time
t
12
13
—
—
100
2.0
ns
µs
R(M)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
t
R(S)
(8)
Fall time
t
—
—
100
2.0
ns
µs
F(M)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
t
F(S)
1. Numbers refer to dimensions in Figure 13-8 and Figure 13-9.
2. V = 5.0 Vdc ± 10%
DD
3. Signal production depends on software.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 200 pF on all SPI pins
7. 20% of V to 70% of V ; C = 200 pF
DD
DD
L
8. 70% of V to 20% of V ; C = 200 pF
DD
DD
L
Technical Data
186
MC68HC705C8A — Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt Serial Peripheral Interface (SPI) Timing
13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing
(1)
(2)
Symbol
Min
Max
Unit
Number
Characteristic
Operating frequency
f
f
Master
Slave
0.5
2.1
OP(M)
OP
dc
f
MHz
OP(S)
Cycle time
Master
t
t
1
2
3
4
5
6
7
2.0
1
—
—
CYC(M)
CYC
Slave
t
ns
CYC(S)
Enable lead time
Master
(3)
t
—
—
ns
Lead(M)
Slave
t
500
Lead(S)
Enable lag time
Master
t
(2)
—
—
ns
ns
ns
ns
ns
Lag(M)
1500
Slave
t
Lag(S)
Clock (SCK) high time
Master
t
720
400
—
—
W(SCKH)M
Slave
t
W(SCKH)S
Clock (SCK) low time
Master
t
720
400
—
—
W(SCKL)M
Slave
t
W(SCKL)S
Data setup time (inputs)
t
Master
Slave
200
200
—
—
SU(M)
t
SU(S)
Data hold time (inputs)
t
Master
Slave
200
200
—
—
H(M)
t
H(S)
(4)
Access time
t
8
9
0
250
500
ns
ns
A
Slave
(5)
Disable time
t
—
DIS
Slave
Data valid time
t
Master (before capture edge)
t
10
0.25
—
—
500
V(M)
CYC(M)
(6)
t
ns
Slave (after enable edge)
V(S)
Continued
MC68HC705C8A — Rev. 3
Technical Data
187
MOTOROLA
Electrical Specifications
Ele c tric a l Sp e c ific a tions
(1)
(2)
Symbol
Min
Max
Unit
Number
Characteristic
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
t
t
11
0.25
0
—
—
HO(M)
CYC(M)
t
ns
HO(S)
(7)
Rise time
t
12
13
—
—
200
2.0
ns
µs
R(M)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
t
R(S)
(8)
Fall time
t
—
—
200
2.0
ns
µs
F(M)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
t
F(S)
1. Numbers refer to dimensions in Figure 13-8 and Figure 13-9.
2. V = 3.3 Vdc ± 10%
3. SDigDnal production depends on software.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 200 pF on all SPI pins
7. 20% of V to 70% of V ; C = 200 pF
DD
DD
L
8. 70% of V to 20% of V ; C = 200 pF
DD
DD
L
Technical Data
188
MC68HC705C8A — Rev. 3
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt Serial Peripheral Interface (SPI) Timing
SS
INPUT
SS pin of master held high.
12
13
12
13
7
1
5
4
SCK (CPOL = 0)
OUTPUT
NOTE
4
5
12
SCK (CPOL = 1)
OUTPUT
NOTE
6
MISO
MSB IN
BITS 6–1
BITS 6–1
LSB IN
INPUT
10
11
MASTER MSB OUT
10
11
MASTER LSB OUT
12
MOSI
OUTPUT
13
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
INPUT
SS pin of master held high.
1
13
12
12
SCK (CPOL = 0)
OUTPUT
5
4
NOTE
NOTE
4
5
13
SCK (CPOL = 1)
OUTPUT
6
7
MISO
MSB IN
BITS 6–1
BITS 6–1
LSB IN
INPUT
10
11
MASTER MSB OUT
10
11
MASTER LSB OUT
12
MOSI
OUTPUT
13
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 13-8. SPI Master Timing
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
189
Electrical Specifications
Ele c tric a l Sp e c ific a tions
SS
INPUT
13
12
12
3
1
SCK (CPOL = 0)
(INPUT
11
4
4
5
2
SCK (CPOL = 1)
INPUT
13
SLAVE LSB OUT
11
9
8
MISO
INPUT
SLAVE MSB OUT
BITS 6–1
BITS 6–1
NOTE
6
7
10
MOSI
OUTPUT
MSB IN
LSB IN
Note: Not defined, but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
13
12
1
SCK (CPOL = 0)
INPUT
5
4
4
5
2
3
SCK (CPOL = 1)
INPUT
10
SLAVE MSB OUT
12
10
13
9
8
MISO
OUTPUT
NOTE
BITS 6–1
BITS 6–1
SLAVE LSB OUT
6
7
11
MOSI
INPUT
MSB IN
LSB IN
Note: Not defined, but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 13-9. SPI Slave Timing
Technical Data
190
MC68HC705C8A — Rev. 3
Electrical Specifications
MOTOROLA
Technical Data — MC68HC705C8A
Section 14. Mechanical Specifications
14.1 Contents
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
14.3 40-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . .192
14.4 40-Pin Ceramic Dual In-Line Package (Cerdip) . . . . . . . . . . .193
14.5 44-Lead Plastic-Leaded Chip Carrier (PLCC) . . . . . . . . . . . .194
14.6 44-Lead Ceramic-Leaded Chip Carrier (CLCC) . . . . . . . . . . .195
14.7 44-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . .196
14.8 42-Pin Shrink Dual In-Line Package (SDIP). . . . . . . . . . . . . .197
14.2 Introduction
Package dimensions available at the time of this publication for the
MC68HC705C8A are provided in this section. The packages are:
•
•
•
•
•
•
40-pin plastic dual in-line package (PDIP)
40-pin ceramic dual-in-line package (cerdip)
44-lead plastic-leaded chip carrier (PLCC)
44-lead ceramic-leaded chip carrier (CLCC)
44-pin quad flat pack (QFP)
42-pin shrink dual in-line package (SDIP)
MC68HC705C8A — Rev. 3
Technical Data
191
MOTOROLA
Mechanical Specifications
Mechanical Specifications
14.3 40-Pin Plastic Dual In-Line Package (PDIP)
40
21
20
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
B
C
D
F
51.69
13.72
3.94
52.45
14.22
5.08
2.035
0.540
0.155
0.014
0.040
2.065
0.560
0.200
0.022
0.060
B
1
0.36
0.56
1.02
1.52
2.54 BSC
0.100 BSC
G
H
J
K
L
L
A
1.65
0.20
2.92
2.16
0.38
3.43
0.065
0.008
0.115
0.085
0.015
0.135
C
N
15.24 BSC
0.600 BSC
0°
1°
0°
1°
M
N
0.51
1.02
0.020
0.040
J
K
SEATING
PLANE
M
H
G
F
D
NOTES:
1.POSITION TOLERANCE OF LEADS (D), SHALL
BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITIONS, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2.DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3.DIMENSION B DOES NOT INCLUDE MOLD FLASH.
Figure 14-1. MC68HC705C8AP Package Dimensions (Case #711)
Technical Data
192
MC68HC705C8A — Rev. 3
MOTOROLA
Mechanical Specifications
Mechanical Specifications
40-Pin Ceramic Dual In-Line Package (Cerdip)
14.4 40-Pin Ceramic Dual In-Line Package (Cerdip)
40
1
21
20
B
A
L
N
C
INCHES
DIM MIN MAX
MILLIMETERS
DATUM
PLANE
T
MIN MAX
K
A
B
C
D
F
2.020 2.096 51.31 53.23
0.500 0.610 12.70 15.94
0.160 0.240 4.06 6.09
0.015 0.022 0.38 0.55
0.050 0.065 1.27 1.65
SEATING
PLANE
J
G
M
F
D40 PL
φ 0.25(0.010)
G
J
0.100 BSC
0.008 0.012 0.20 0.30
2.54 BSC
T A
M
M
K
L
M
0.125 0.160 3.17 4.06
0.600 BSC
0° 15°
0.020 0.050 0.51 1.27
15.24 BSC
0° 15°
N
Figure 14-2. MC68HC705C8AS Package Dimensions (Case #734A)
MC68HC705C8A — Rev. 3
Technical Data
193
MOTOROLA
Mechanical Specifications
Mechanical Specifications
14.5 44-Lead Plastic-Leaded Chip Carrier (PLCC)
M
S
S
N
0.007(0.180)
T
L-M
B
D
-N-
YBRK
M
S
S
0.007(0.180)
T
L-M
N
U
Z
-M-
-L-
V
X
G1
W
D
44
1
S
S
S
N
0.010 (0.25)
T
L-M
VIEW D-D
M
M
S
S
S
S
A
R
0.007(0.180)
0.007(0.180)
T
T
L-M
L-M
N
N
M
S
S
N
0.007(0.180)
T
L-M
H
Z
J
K1
E
0.004 (0.10)
G
K
C
SEATING
PLANE
-T-
G1
F
VIEW S
S
S
S
M
S
S
0.010 (0.25)
T
L-M
N
0.007(0.180)
T
L-M
N
VIEW S
NOTES:
INCHES
MIN
MILLIMETERS
1.DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2.DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3.DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
DIM
MAX
0.695
0.695
0.180
0.110
0.019
MIN
17.40
17.40
4.20
MAX
17.65
17.65
4.57
A
B
0.685
0.685
0.165
0.090
0.013
C
E
2.29
2.79
F
0.33
0.48
4.DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5.CONTROLLING DIMENSION: INCH.
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.650
0.650
0.032
0.66
0.51
0.81
6.THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE DETERMINED
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7.DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940198). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
K
R
0.64
0.656
0.656
0.048
0.048
0.056
0.020
10°
16.51
16.51
1.07
16.66
16.66
1.21
1.21
1.42
0.50
10°
U
V
W
X
Y
Z
0.042
0.042
0.042
1.07
1.07
2°
2°
15.50
1.02
G1
K1
0.610
0.040
0.630
16.00
Figure 14-3. MC68HC705C8AFN Package Dimensions (Case #777)
Technical Data
194
MC68HC705C8A — Rev. 3
Mechanical Specifications
MOTOROLA
Mechanical Specifications
44-Lead Ceramic-Leaded Chip Carrier (CLCC)
14.6 44-Lead Ceramic-Leaded Chip Carrier (CLCC)
M
S
S
S
L
0.18 (0.007)
T N -P
B
-N-
Y BRK
M
S
S
S
L
0.18 (0.007)
T N -P
U
D
-L-
W
S
D
G1
DETAIL D-D
44
1
M
S
S
S
L
0.25 (0.010)
T N -P
-P-
M
M
M
-P
M
0.20 (0.008)
T L
N
V
NOTES:
1. DATUMS -L-, -N-, AND -P- DETERMINED
WHERE TOP OF LEAD SHOULDER EXIT
BODY.
2. DIMINSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING
PLANE.
3. DIMINSIONS R AND U DO NOT INCLUDE
GLASS MENISCUS. ALLOWABLE GLASS
RUNOUT IS 0.25 (0.010) PER SIDE.
M
S
S
S
S
0.18 (0.007)
0.18 (0.007)
T L
N
-P
-P
A
R
M
S
S
T L
N
4. DIMINSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
C
E
MILLIMETERS
INCHES
MIN
0.685
0.685
0.165
0.090
0.013
DIM MIN
MAX
17.40 17.65
17.40 17.65
MAX
0.695
0.695
0.180
0.110
0.019
0.10 (0.004)
A
B
C
E
J
G
SEATING
PLANE
-T-
4.20
2.29
0.33
4.57
2.79
0.48
DETAIL S
G1
F
S
S
S
S
0.25 (0.010)
T L
N
-P
G
H
J
K
R
S
U
V
W
Y
1.27 BSC
0.050 BSC
0.66
0.51
0.64
0.81
0.026
0.020
0.025
0.650
0.273
0.650
0.042
0.042
---
0.032
---
---
---
---
16.51 16.66
6.94 7.26
16.51 16.66
0.656
0.286
0.656
0.048
0.048
0.020
0.630
---
M
M
S
S
S
0.18 (0.007)
0.18 (0.007)
T L
N
-P
L
H
S
S
S
T N -P
1.07
1.07
---
1.21
1.21
0.50
G1 14.99 16.00
K1 1.02 ---
0.590
0.040
K1
K
M
M
S
S
S
-P
0.18 (0.007)
0.18 (0.007)
T L
N
F
S
S
S
L
T N -P
DETAIL S
Figure 14-4. MC68HC705C8AFS Package Dimensions (Case #777B)
MC68HC705C8A — Rev. 3
Technical Data
195
MOTOROLA
Mechanical Specifications
Mechanical Specifications
14.7 44-Pin Quad Flat Pack (QFP)
B
B
L
33
23
22
34
-A-, -B-, -D-
DETAIL A
F
-A-
-B-
BASE METAL
J
N
DETAIL A
D
S
S
0.20 (0.008)M C A-B
D
44
12
1
11
SECTION B-B
NOTES:
1. 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-D-
2. 2. CONTROLLING DIMENSION: MILLIMETER.
3. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT
DATUM PLANE -H-.
5. 5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -C-.
A
M
S
S
S
0.20 (0.008) C A-B
0.05 (0.002) A-B
S
D
D
M
S
0.20 (0.008) H A-B
6. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDEMOLDMISMATCHANDAREDETERMINED
AT DATUM PLANE -H-.
M
DETAIL C
E
DATUM
PLANE
C
-C-
7. 7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
-H-
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT.
0.01 (0.004)
SEATING
PLANE
H
G
M
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
E
F
9.90 10.10 0.390 0.398
9.90 10.10 0.390 0.398
M
2.10
0.30
2.00
0.30
2.45 0.083 0.096
0.45 0.012 0.018
2.10 0.079 0.083
0.40 0.012 0.016
T
G
H
J
K
L
M
N
Q
R
S
T
U
V
W
X
0.80 BSC
0.031 BSC
--- 0.010
DATUM
PLANE
-H-
---
0.013
0.65
0.25
R
0.23 0.005 0.009
0.95 0.026 0.037
8.00 REF
0.315 REF
10
5
0.13
10
5
°
°
°
°
K
Q
0.17 0.005 0.007
W
0
0.13
7
0
7
°
°
°
°
X
0.30 0.005 0.012
12.95 13.45 0.510 0.530
0.13
--- 0.005
---
---
---
0
0
°
°
DETAIL C
12.95 13.45 0.510 0.530
0.40
--- 0.016
---
1.6 REF
0.063 REF
Figure 14-5. MC68HC705C8AFB Package Dimensions (Case #824A)
Technical Data
196
MC68HC705C8A — Rev. 3
Mechanical Specifications
MOTOROLA
Mechanical Specifications
42-Pin Shrink Dual In-Line Package (SDIP)
14.8 42-Pin Shrink Dual In-Line Package (SDIP)
-A-
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
42
1
22
21
-B-
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
INCHES
MIN MAX
MILLIMETERS
MIN MAX
L
DIM
A
B
C
D
F
1.435 1.465 36.45 37.21
0.540 0.560 13.72 14.22
H
C
0.155 0.200
0.014 0.022
0.032 0.046
0.070 BSC
3.94
0.36
0.81
5.08
0.56
1.17
G
H
J
1.778 BSC
7.62 BSC
0.300 BSC
-T-
SEATING
PLANE
0.008 0.015
0.115 0.135
0.600 BSC
0.20
2.92
0.38
3.43
K
L
N
G
15.24 BSC
M
F
M
N
0° 15°
0.020 0.040
0°
0.51
15°
1.02
K
J 42 PL
0.25 (0.010)
D 42 PL
M
S
B
M
S
A
T
0.25 (0.010)
T
Figure 14-6. MC68HC705C8AB Package Dimensions (Case #858)
MC68HC705C8A — Rev. 3
Technical Data
197
MOTOROLA
Mechanical Specifications
Mechanical Specifications
Technical Data
198
MC68HC705C8A — Rev. 3
Mechanical Specifications
MOTOROLA
Technical Data — MC68HC705C8A
Section 15. Ordering Information
15.1 Contents
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.2 Introduction
This section contains ordering information for the available package
types.
15.3 MCU Order Numbers
Table 15-1 lists the MC order numbers.
Table 15-1. MC68HC705C8A Order Numbers
Package Type
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Order Number
(1) (2)
40-pin plastic dual in-line package (PDIP)
44-lead plastic-leaded chip carrier (PLCC)
44-lead ceramic-leaded chip carrier (CLCC)
40-pin windowed ceramic DIP (Cerdip)
44-pin quad flat pack (QFP)
MC68HC705C8AC
P
(3)
MC68HC705C8ACFN
MC68HC705C8ACFS
(4)
(5)
MC68HC705C8ACS
MC68HC705C8ACFB
(6)
(7)
42-pin shrink dual in-line package (SDIP)
MC68HC705C8ACB
1. C = Extended temperature range (–40°C to +85°C)
2. P = Plastic dual in-line package (PDIP)
3. FN = Plastic-leaded chip carrier (PLCC)
4. FS = Ceramic-leaded chip carrier (CLCC)
5. S = Windowed ceramic dual in-line package (Cerdip)
6. FB = Quad flat pack (QFP)
7. B = Shrink dual in-line package (SDIP)
MC68HC705C8A — Rev. 3
Technical Data
199
MOTOROLA
Ordering Information
Ordering Information
Technical Data
200
MC68HC705C8A — Rev. 3
Ordering Information
MOTOROLA
Technical Data — MC68HC705C8A
Appendix A. MC68HSC705C8A
A.1 Contents
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
5.0-Volt High-Speed DC Electrical Characteristics. . . . . . . . .202
3.3-Volt High-Speed DC Electrical Characteristics . . . . . . . .203
5.0-Volt High-Speed Control Timing. . . . . . . . . . . . . . . . . . . .204
3.3-Volt High-Speed Control Timing. . . . . . . . . . . . . . . . . . . .204
5.0-Volt High-Speed SPI Timing . . . . . . . . . . . . . . . . . . . . . .205
3.3-Volt High-Speed SPI Timing. . . . . . . . . . . . . . . . . . . . . . .207
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
A.2 Introduction
The MC68HSC705C8A is an enhanced, high-speed version of the
MC68HC705C8A, featuring a 4-MHz bus speed.
The data in this document, MC68HC705C8A Technical Data Rev. 3,
applies to the MC68HSC705C8A with the exceptions given in this
appendix.
The computer operating properly (COP) mode bits (CM1 and CM0 in the
COP control register) select the timeout period of the programmable
COP watchdog, as shown in Table A-1. See Figure 5-3.
Programmable COP Control Register (COPCR).
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
MC68HSC705C8A
201
MC68HSC705C8A
Table A-1. Programmable COP Timeout Period Selection
Programmable COP Timeout Period
COP
Timeout
Rate
CM1:CM0
f
= 8.0 MHz
= 4.0 MHz
f
= 4.0 MHz
= 2.0 MHz
f
= 3.5795 MHz
= 1.7897 MHz
f
OSC
= 2.0 MHz
= 1.0 MHz
OSC
OSC
OSC
f
f
f
f
OP
OP
OP
OP
15
00
01
10
11
8.192 ms
32.77 ms
131.07 ms
524.29 ms
16.38 ms
65.54 ms
262.14 ms
1.048 s
18.31 ms
73.24 ms
292.95 ms
1.172 s
32.77 ms
131.07 ms
524.29 ms
2.097 s
f
÷ 2
÷ 2
÷ 2
OP
OP
OP
17
19
f
f
21
f
÷ ÷2
OP
A.3 5.0-Volt High-Speed DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
Output high voltage
I
I
I
= –0.8 mA
Load
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
= –1.6 mA
—
—
—
—
—
—
V
V
– 0.8
DD
V
Load
OH
PD4–PD1
= –5.0 mA
Load
PC7
Output low voltage
I
I
= 1.6 mA
Load
V
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
= 20 mA
—
—
—
—
0.4
0.4
V
OL
Load
PC7
(3)
Supply current
(4)
Run
—
—
5.92
2.27
14
7.0
mA
mA
(5)
Wait
I
DD
(6)
Stop
—
—
5
2.0
50
50
µA
µA
25°C
–40°C to +85°C
1. V = 5 V ± 10%; V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. I measured with port B pullup devices disabled.
DD
4. Run (operating) I measured using external square wave clock source (f
= 8.0 MHz). All inputs 0.2 V from rail. No dc
DD
OSC
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly affects run I
.
DD
5. Wait I measured using external square wave clock source (f
= 8.0 MHz). All inputs 0.2 V from rail. No dc loads. Less
DD
OSC
than 50 pF on all outputs. C = 20 pF on OSC2. V = 0.2 V, V = V – 0.2 V. All ports configured as inputs. SPI and SCI
L
IL
IH
DD
disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait I
.
DD
6. Stop I measured with OSC1 = V . All ports configured as inputs. V = 0.2 V, V = V – 0.2 V.
DD
DD
IL
IH
DD
Technical Data
202
MC68HC705C8A — Rev. 3
MC68HSC705C8A
MOTOROLA
MC68HSC705C8A
A.4 3.3-Volt High-Speed DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Output high voltage
Typ
I
I
I
= –0.2 mA
Load
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
= –0.4 mA
—
—
—
—
—
—
V
V
– 0.3
DD
V
Load
OH
PD4–PD1
= –1.5 mA
Load
PC7
Output low voltage
I
I
= 0.4 mA
Load
V
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
= 6.0 mA
—
—
—
—
0.3
0.3
V
OL
Load
PC7
(3)
Supply current
(4)
Run
—
—
—
1.91
0.915
2.0
6.0
2.0
20
mA
mA
µA
I
DD
(5)
Wait
(6)
Stop
1. V = 3.3 V ± 10%; V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. I measured with port B pullup devices disabled.
DD
4. Run (operating) I measured using external square wave clock source (f
= 4.2 MHz). All inputs 0.2 V from rail. No dc
DD
OSC
loads. Less than 50 pF on all outputs. C = 20 pF on OSC2. OSC2 capacitance linearly affects run I
.
DD
L
5. Wait I measured using external square wave clock source (f
= 4.2 MHz). All inputs 0.2 V from rail. No dc loads. Less
DD
OSC
than 50 pF on all outputs. C = 20 pF on OSC2. V = 0.2 V, V = V – 0.2 V. All ports configured as inputs. SPI and SCI
L
IL
IH
DD
disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait IDD
.
6. Stop I measured with OSC1 = V . All ports configured as inputs. V = 0.2 V; V = V – 0.2 V.
DD
DD
IL
IH
DD
MC68HC705C8A — Rev. 3
Technical Data
203
MOTOROLA
MC68HSC705C8A
MC68HSC705C8A
A.5 5.0-Volt High-Speed Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Oscillator frequency
Crystal oscillator
External clock
f
—
dc
8.0
8.0
MHz
OSC
Internal operating frequency (f
÷ 2)
OSC
f
—
dc
4.0
4.0
MHz
Crystal oscillator
External clock
OP
t
Cycle time
250
65
—
—
—
—
ns
ns
ns
ns
CYC
t
, t
Input capture pulse width
TH TL
t
Interrupt pulse width low (edge-triggered)
OSC1 pulse width
65
ILIH
t
, t
45
OH OL
1. V = 5 V ± 10%; V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
A.6 3.3-Volt High-Speed Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Oscillator frequency
Crystal oscillator
External clock
f
—
dc
4.0
4.0
MHz
OSC
Internal operating frequency (f
÷ 2)
OSC
f
—
dc
2.0
2.0
MHz
Crystal oscillator
External clock
OP
t
Cycle time
476
125
125
90
—
—
—
—
ns
ns
ns
ns
CYC
t
, t
Input capture pulse width
TH TL
t
Interrupt pulse width low (edge-triggered)
OSC1 pulse width
ILIH
t
, t
OH OL
1. V = 3.3 V ± 10%; V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
Technical Data
204
MC68HC705C8A — Rev. 3
MC68HSC705C8A
MOTOROLA
MC68HSC705C8A
A.7 5.0-Volt High-Speed SPI Timing
Diagram
(2)
Symbol
Min
Max
Unit
Characteristic
Operating frequency
(1)
Number
f
f
Master
Slave
dc
dc
0.5
4.0
OP(S)
OP
f
MHz
OP(S)
Cycle time
Master
t
t
1
2
3
4
5
6
7
2.0
250
—
—
CYC(M)
CYC
Slave
t
ns
CYC(S)
Enable lead time
Master
(3)
t
—
—
ns
Lead(M)
Note
125
Slave
t
Lead(S)
Enable lag time
Master
(2)
t
—
—
ns
ns
ns
ns
ns
Lag(M)
Note
375
Slave
t
Lag(S)
Clock (SCK) high time
t
Master
Slave
170
95
—
—
W(SCKH)M
t
W(SCKH)S
Clock (SCK) low time
Master
t
170
95
—
—
W(SCKL)M
Slave
t
W(SCKL)S
Data setup time (inputs)
t
Master
Slave
50
50
—
—
SU(M)
t
SU(S)
Data hold time (inputs)
t
Master
Slave
50
50
—
—
H(M)
t
H(S)
(4)
Access time
t
8
9
0
60
ns
ns
A
Slave
(5)
Disable time
t
—
120
DIS
Slave
Data valid time
t
Master (before capture edge)
t
10
0.25
—
—
120
V(M)
CYC(M)
(6)
t
ns
Slave (after enable edge)
V(S)
Continued
MC68HC705C8A — Rev. 3
Technical Data
205
MOTOROLA
MC68HSC705C8A
MC68HSC705C8A
Diagram
(2)
Symbol
Min
Max
Unit
Characteristic
(1)
Number
Data hold time (outputs)
t
t
11
12
13
Master (after capture edge)
Slave (after enable edge)
0.25
0
—
—
HO(M)
CYC(M)
t
ns
HO(S)
(7)
Rise time
t
—
—
50
2.0
ns
µs
RM
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
t
RS
(8)
Fall time
t
—
—
50
2.0
ns
µs
FM
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
t
FS
1. Diagram numbers refer to dimensions in Figure 13-8. SPI Master Timing and Figure 13-9. SPI Slave Timing.
2. V = 5 V ± 10%; V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
3. Signal production depends on software.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 200 pF on all SPI pins.
7. 20% of V to 70% of V ; C = 200 pF
DD
DD
L
8. 70% of V to 20% of V ; C = 200 pF
DD
DD
L
Technical Data
206
MC68HC705C8A — Rev. 3
MC68HSC705C8A
MOTOROLA
MC68HSC705C8A
A.8 3.3-Volt High-Speed SPI Timing
Diagram
(2)
Symbol
Min
Max
Unit
Characteristic
Operating frequency
(1)
Number
f
f
Master
Slave
dc
dc
0.5
2.1
OP(S)
OP
f
MHz
OP(S)
Cycle time
Master
t
t
1
2
3
4
5
6
7
2.0
480
—
—
CYC(M)
CYC
Slave
t
ns
CYC(S)
Enable lead time
Master
(3)
t
—
—
ns
Lead(M)
Note
240
Slave
t
Lead(S)
Enable lag time
Master
(2)
t
—
—
ns
ns
ns
ns
ns
Lag(M)
Note
720
Slave
t
Lag(S)
Clock (SCK) high time
Master
t
340
190
—
—
W(SCKH)M
Slave
t
W(SCKH)S
Clock (SCK) low time
Master
t
340
190
—
—
W(SCKL)M
Slave
t
W(SCKL)S
Data setup time (inputs)
t
Master
Slave
100
100
—
—
SU(M)
t
SU(S)
Data hold time (inputs)
t
Master
Slave
100
100
—
—
H(M)
t
H(S)
(4)
Access time
t
8
9
ns
ns
A
0
120
240
Slave
(5)
Disable time
t
DIS
—
Slave
Data valid time
t
Master (before capture edge)
t
10
0.25
—
—
240
V(M)
CYC(M)
(6)
t
ns
Slave (after enable edge)
V(S)
Continued
MC68HC705C8A — Rev. 3
Technical Data
207
MOTOROLA
MC68HSC705C8A
MC68HSC705C8A
Diagram
(2)
Symbol
Min
Max
Unit
Characteristic
(1)
Number
Data hold time (outputs)
t
t
11
12
13
Master (after capture edge)
Slave (after enable edge)
0.25
0
—
—
HO(M)
CYC(M)
t
ns
HO(S)
(7)
Rise time
t
—
—
100
2.0
ns
µs
RM
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
t
RS
(8)
Fall time
t
—
—
100
2.0
ns
µs
FM
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
t
FS
1. Diagram numbers refer to dimensions in Figure 13-8. SPI Master Timing and Figure 13-9. SPI Slave Timing.
2. V = 3.3 V ± 10%; V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
3. Signal production depends on software.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 200 pF on all SPI pins
7. 20% of V to 70% of V ; C = 200 pF
DD
DD
L
8. 70% of V to 20% of V ; C = 200 pF
DD
DD
L
Technical Data
208
MC68HC705C8A — Rev. 3
MC68HSC705C8A
MOTOROLA
MC68HSC705C8A
A.9 Ordering Information
Table A-2 provides ordering information for the MC68HSC705C8A.
Table A-2. MC68HSC705C8A Order Numbers
Package Type
40-pin plastic dual in-line package (PDIP)
44-lead plastic-leaded chip carrier (PLCC)
Temperature Range
–40°C to +85°C
Order Number
(1) (2)
MC68HSC705C8AC
P
(3)
(4)
–40°C to +85°C
MC68HSC705C8ACFN
MC68HSC705C8ACFS
44-lead ceramic-leaded chip carrier (CLCC)
40-pin ceramic DIP (cerdip)
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
(5)
MC68HSC705C8ACS
(6)
44-pin quad flat pack (QFP)
MC68HSC705C8ACFB
(7)
42-pin shrink dual in-line package (SDIP)
MC68HSC705C8ACB
1. C = Extended temperature range (–40°C to +85°C)
2. P = Plastic dual in-line package (PDIP)
3. FN = Plastic-leaded chip carrier (PLCC)
4. FS = Ceramic-leaded chip carrier (CLCC)
5. S = Windowed ceramic dual in-line package (cerdip)
6. FB = Quad flat pack (QFP)
7. B = Shrink dual in-line package (SDIP)
MC68HC705C8A — Rev. 3
Technical Data
209
MOTOROLA
MC68HSC705C8A
MC68HSC705C8A
Technical Data
210
MC68HC705C8A — Rev. 3
MC68HSC705C8A
MOTOROLA
Technical Data — MC68HC705C8A
Index
A
accumulator (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45, 154, 155, 158
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
B
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
C
C bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 47, 160
COP watchdog (non-programmable)
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
timeout period formula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
when clock monitor enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
COP watchdog (programmable)
COP control register (COPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 64
COP reset register (COPRST). . . . . . . . . . . . . . . . . . . . . . . . . . . 64
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
timeout period selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Index
211
Index
CPU
instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155, 158, 163
accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154, 155, 158
condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 160
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . 154, 155, 156, 158
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157, 160
D
data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
E
electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
electrical specifications (high-speed part)
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
SPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 103
control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
EPROM erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
mask option register 1 (MOR1) . . . . . . . . . . . . . . . . . . . . . . . . . 117
mask option register 2 (MOR2) . . . . . . . . . . . . . . . . . . . . . . . . . 118
option register (option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
preprogramming steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
program register (PROG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MC68HC05PGMR programmer board . . . . . . . . . . . . . . . . . 104
programming circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Technical Data
212
MC68HC705C8A — Rev. 3
Index
MOTOROLA
Index
programming flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
programming routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 111
F
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
H
high-speed part (MC68HSC705C8A) . . . . . . . . . . . . . . . . . . . . . . . 201
I
I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36, 77
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 79
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 82
data direction register C (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . . 86
port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
port A data register (PORTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
port A I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port A pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
port B data register (PORTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
port B I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
port B pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
port C data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
port C I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port C pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
I/O bits
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
I/O register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
index register (X). . . . . . . . . . . . . . . . . . . . . . . . 45, 154, 155, 156, 158
instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Index
213
Index
interrupt processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . 57
stacking order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
interrupts
external interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
internal function diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
port B interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
port B I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SCI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
J
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
L
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
data-retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
stop mode
non-programmable COP in stop mode flowchart . . . . . . . . . . 74
non-programmable COP watchdog in stop mode. . . . . . . . . . 73
programmable COP in stop mode flowchart. . . . . . . . . . . . . . 72
programmable COP watchdog in stop mode . . . . . . . . . . . . . 71
SCI during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SPI during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
stop/wait mode function flowchart. . . . . . . . . . . . . . . . . . . . . . 70
wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
non-programmable COP watchdog in wait mode. . . . . . . . . . 75
programmable COP watchdog in wait mode . . . . . . . . . . . . . 75
Technical Data
214
MC68HC705C8A — Rev. 3
Index
MOTOROLA
Index
M
mask option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 117, 118
MC68HSC705C8A (high-speed part) . . . . . . . . . . . . . . . . . . . . . . . 201
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
programmable COP timeout period selection . . . . . . . . . . . . . . 202
SPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
memory
bootloader ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35, 38
PROM (EPROM/OTPROM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35, 38
O
on-chip memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
opcode map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
OSC1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
OSC2 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
oscillator
ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
external clock signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Index
215
Index
P
pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 78
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 79
port A data register (PORT A) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
port A I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port A pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 81
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 82
port B data register (PORTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
port B I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
port B pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 85
data direction register C (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . . 86
port C data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
port C I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port C pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 88
power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 157, 160
programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
programming model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PROM (EPROM/OTPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
R
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
registers
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
reset and interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . 59
RESET pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
clock monitor reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65, 67
with STOP instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Technical Data
216
MC68HC705C8A — Rev. 3
Index
MOTOROLA
Index
COP watchdog resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
non-programmable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
non-programmable COP watchdog diagram . . . . . . . . . . . . . 67
programmable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
programmable COP watchdog diagram . . . . . . . . . . . . . . . . . 63
enabling both programmable and non-programmable COPs . . . 65
external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ROM (bootloader) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
S
serial communications interface (SCI). . . . . . . . . . . . . . . . . . . . . . . 121
baud rate generator clock prescaling. . . . . . . . . . . . . . . . . . . . . 136
baud rate register (baud) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
baud rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
baud rate selection examples . . . . . . . . . . . . . . . . . . . . . . . . . . 138
during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SCI control register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . . . . . . 130
SCI control register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . . . . . . 131
SCI data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SCI data register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SCI I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SCI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SCI operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SCI receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SCI status register (SCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SCI transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
serial peripheral interface (SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
master/slave connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
multiple-SPI systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
pin functions in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
pin functions in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
serial clock polarity and phase. . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Index
217
Index
SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SPI clock/data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SPI control register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SPI data register (SPDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SPI error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SPI I/O register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SPI I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SPI status register (SPSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
stop mode
non-programmable COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
non-programmable COP flowchart. . . . . . . . . . . . . . . . . . . . . . . . 74
programmable COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
programmable COP flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SCI during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SPI during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
stop/wait mode function flowchart . . . . . . . . . . . . . . . . . . . . . . . . 70
T
TCAP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TCMP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
alternate timer registers (ATRH and ATRL). . . . . . . . . . . . . . . . . 99
I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
input capture registers (ICRH and ICRL) . . . . . . . . . . . . . . . . . . 100
output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
timer control register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
timer I/O register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
timer registers (TRH and TRL). . . . . . . . . . . . . . . . . . . . . . . . . . . 97
timer status register (TSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Technical Data
218
MC68HC705C8A — Rev. 3
Index
MOTOROLA
Index
V
VDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VSS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
W
wait mode
non-programmable COP watchdog in wait mode . . . . . . . . . . . . 75
programmable COP watchdog in wait mode . . . . . . . . . . . . . . . . 75
stop/wait mode function flowchart . . . . . . . . . . . . . . . . . . . . . . . . 70
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Index
219
Index
Technical Data
220
MC68HC705C8A — Rev. 3
Index
MOTOROLA
HOW TO REACH US:
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81-3-3440-3569
ASIA/PACIFIC:
Information in this document is provided solely to enable system and software
implementers to use Motorola products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits or
integrated circuits based on the information in this document.
Motorola Semiconductors H.K. Ltd.;
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Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
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suitability of its products for any particular purpose, nor does Motorola assume any
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and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts.
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the failure of the Motorola product could create a situation where personal injury or
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MC68HC705C8A/D
相关型号：
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