MC68HRC705SJ7CP [MOTOROLA]
8-BIT, OTPROM, 2.1MHz, MICROCONTROLLER, PDIP28, PLASTIC, DIP-28;
| 型号： | MC68HRC705SJ7CP |
| 厂家： | 
MOTOROLA |
| 描述： | 8-BIT, OTPROM, 2.1MHz, MICROCONTROLLER, PDIP28, PLASTIC, DIP-28 可编程只读存储器 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总230页 (文件大小：1111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HC705JJ7GRS/D
Rev. 3.0
68HC705JJ7
68HC705JP7
68HC705SJ7
68HC705SP7
68HRC705JJ7
68HRC705JP7
68HRC705SJ7
68HRC705SP7
Ge ne ra l Re le a se Sp e c ific a tion
Aug ust 12, 1997
We ste rn MCU De sig n Ce nte r
Te m p e , Arizo na
Ge ne ra l Re le a se Sp e c ific a tion
Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
2
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
List of Se c tions
Se c tion 1. Ge ne ra l De sc rip tion . . . . . . . . . . . . . 19
Se c tion 2. Me m ory . . . . . . . . . . . . . . . . . . . . . . . 31
Se c tion 3. Ce ntra l Proc e ssor Unit (CPU) . . . . . . 39
Se c tion 4. Inte rrup ts. . . . . . . . . . . . . . . . . . . . . . . 45
Se c tion 5. Re se ts . . . . . . . . . . . . . . . . . . . . . . . . . 59
Se c tion 6. Op e ra ting Mod e s . . . . . . . . . . . . . . . 69
Se c tion 7. Pa ra lle l Inp ut/ Outp ut. . . . . . . . . . . . . 77
Se c tion 8. Ana log Sub syste m . . . . . . . . . . . . . . 103
Se c tion 9. Sim p le Se ria l Inte rfa c e . . . . . . . . . . 137
Se c tion 10. Core Tim e r . . . . . . . . . . . . . . . . . . . 147
Se c tion 11. Prog ra m m a b le Tim e r. . . . . . . . . . . 155
Se c tion 12. Pe rsona lity EPROM. . . . . . . . . . . . . 171
Se c tion 13. EPROM/ OTPROM . . . . . . . . . . . . . . 179
Se c tion 14. Instruc tion Se t. . . . . . . . . . . . . . . . . 187
Se c tion 15. Ele c tric a l Sp e c ific a tions . . . . . . . . 205
Se c tion 16. Me c ha nic a l Sp e c ific a tions. . . . . . 221
Se c tion 17. Ord e ring Inform a tion. . . . . . . . . . . 225
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
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List of Sections
List of Se c tions
General Release Specification
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MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
List of Sections
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Ta b le of Conte nts
Section 1. General Description
1.1
1.2
1.3
1.4
1.5
1.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
V
and V Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
SS
DD
1.7
OSC1 and OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . . .26
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . .27
1.7.1
1.7.2
1.7.3
1.7.4
1.7.5
1.8
1.9
RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IRQ/V Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PP
1.10 PA0–PA5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.11 PB0–PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.12 PC0–PC7 (MC68HC705JP7) . . . . . . . . . . . . . . . . . . . . . . . . . .29
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Interrupt Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
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Section 3. Central Processor Unit (CPU)
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Index Register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .42
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Section 4. Interrupts
4.1
4.2
4.3
4.4
4.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.6
4.6.1
4.6.2
4.6.3
IRQ/V Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
PA0–PA3 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
IRQ Status and Control Register (ISCR). . . . . . . . . . . . . . .53
PP
4.7
4.7.1
4.7.2
Core Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Core Timer Overflow Interrupt. . . . . . . . . . . . . . . . . . . . . . .55
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.8
Programmable Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . .56
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .56
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.8.1
4.8.2
4.8.3
4.9
Serial Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.10 Analog Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.10.1
4.10.2
Comparator Input Match Interrupt . . . . . . . . . . . . . . . . . . . .58
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
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MOTOROLA
Table of Contents
Section 5. Resets
5.1
5.2
5.3
5.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.5
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Computer Operating Properly (COP) Reset . . . . . . . . . . . .62
Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . .64
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.5.1
5.5.2
5.5.3
5.5.4
5.6
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . .66
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
External Oscillator and Internal Low-Power Oscillator . . . .67
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
Section 6. Operating Modes
6.1
6.2
6.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Oscillator Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.4
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.4.1
6.4.2
6.4.3
6.4.4
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Ta b le of Conte nts
Section 7. Parallel Input/Output
7.1
7.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . .79
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .80
Pulldown Register A (PDRA). . . . . . . . . . . . . . . . . . . . . . . .81
Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .82
Port A Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . .84
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .85
Pulldown Register B (PDRB). . . . . . . . . . . . . . . . . . . . . . . .86
Port B Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
PB0, PBI, PB2 and PB3 Logic. . . . . . . . . . . . . . . . . . . . . . .87
PB4/AN4/TCMP/CMP1 Logic . . . . . . . . . . . . . . . . . . . . . . .89
PB5/SDO Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
PB6/SDI Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
PB7/SCK Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.5
Port C (28-Pin Versions Only) . . . . . . . . . . . . . . . . . . . . . . . . .99
Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . .99
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . .100
Port C Pulldown Devices. . . . . . . . . . . . . . . . . . . . . . . . . .100
Port C Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
7.5.1
7.5.2
7.5.3
7.5.4
7.6
Port Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Section 8. Analog Subsystem
8.1
8.2
8.3
8.4
8.5
8.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Analog Multiplex Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Analog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Analog Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
A/D Conversion Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.7
8.7.1
8.7.1.1
Voltage Measurement Methods . . . . . . . . . . . . . . . . . . . . . . .128
Absolute Voltage Readings. . . . . . . . . . . . . . . . . . . . . . . .129
Internal Absolute Reference. . . . . . . . . . . . . . . . . . . . . .129
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Table of Contents
8.7.1.2
8.7.2
8.7.2.1
8.7.2.2
External Absolute Reference . . . . . . . . . . . . . . . . . . . . .130
Ratiometric Voltage Readings. . . . . . . . . . . . . . . . . . . . . .131
Internal Ratiometric Reference . . . . . . . . . . . . . . . . . . .131
External Ratiometric Reference . . . . . . . . . . . . . . . . . . .131
8.8
8.8.1
8.8.2
Voltage Comparator Features . . . . . . . . . . . . . . . . . . . . . . . .133
Voltage Comparator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Voltage Comparator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
8.9
Current Source Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
8.10 Internal Temperature Sensing Diode Features. . . . . . . . . . . .134
8.11 Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
8.12 Port B Interaction with Analog Inputs . . . . . . . . . . . . . . . . . . .135
8.13 Port B Pins As Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
8.14 Port B Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
8.15 Noise Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Section 9. Simple Serial Interface
9.1
9.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.3
SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . .140
9.3.1
9.3.2
9.3.3
9.4
SIOP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . .141
SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . .144
SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . .145
9.4.1
9.4.2
9.4.3
Section 10. Core Timer
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.3 Core Timer Status and Control Register (CTSCR). . . . . . . . .149
10.4 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . . .151
10.5 COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
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Section 11. Programmable Timer
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.3 Timer Registers (TMRH and TMRL). . . . . . . . . . . . . . . . . . . .158
11.4 Alternate Counter Registers (ACRH and ACRL) . . . . . . . . . .160
11.5 Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . . .162
11.6 Output Compare Registers (OCRH and OCRL). . . . . . . . . . .164
11.7 Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . .166
11.8 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . .168
11.9 Timer Operation During Wait Mode . . . . . . . . . . . . . . . . . . . .169
11.10 Timer Operation During Stop Mode . . . . . . . . . . . . . . . . . . . .169
11.11 Timer Operation During Halt Mode. . . . . . . . . . . . . . . . . . . . .169
Section 12. Personality EPROM
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
12.3 PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
12.3.1
12.3.2
PEPROM Bit Select Register (PEBSR). . . . . . . . . . . . . . .173
PEPROM Status and Control Register (PESCR) . . . . . . .174
12.4 PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
12.5 PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
12.6 PEPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Section 13. EPROM/OTPROM
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.3 EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.3.1
13.3.2
13.3.3
EPROM Programming Register (EPROG) . . . . . . . . . . . .180
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . .181
EPROM Security Bit (EPMSEC) . . . . . . . . . . . . . . . . . . . .184
13.4 EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
13.4.1
13.4.2
MOR Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
EPMSEC Programming. . . . . . . . . . . . . . . . . . . . . . . . . . .186
13.5 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
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Section 14. Instruction Set
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
14.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
14.3.1
14.3.2
14.3.3
14.3.4
14.3.5
14.3.6
14.3.7
14.3.8
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
14.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .192
Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . .193
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .194
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .196
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
14.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
14.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Section 15. Electrical Specifications
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
15.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .207
15.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
15.6 Supply Current Characteristics (V = 4.5 to 5.5 Vdc). . . . . .208
DD
15.7 Supply Current Characteristics (V = 2.7 to 3.3 Vdc). . . . . .209
DD
15.8 DC Electrical Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . .210
15.9 DC Electrical Characteristics (3.0 Vdc). . . . . . . . . . . . . . . . . .211
15.10 Analog Subsystem Characteristics (5.0 Vdc) . . . . . . . . . . . . .212
15.11 Analog Subsystem Characteristics (3.0 Vdc) . . . . . . . . . . . . .213
15.12 Control Timing (5.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
15.13 Control Timing (3.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
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15.14 PEPROM and EPROM Programming Characteristics . . . . . .216
15.15 SIOP Timing (V = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . .216
DD
15.16 SIOP Timing (V = 3.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . .217
DD
15.17 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Section 16. Mechanical Specifications
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
16.3 20-Pin Plastic Dual In-Line Package (Case 738) . . . . . . . . . .222
16.4 20-Pin Small Outline Integrated Circuit (Case 751D) . . . . . . .222
16.5 28-Pin Plastic Dual In-Line Package (Case 710) . . . . . . . . . .223
16.6 28-Pin Small Outline Integrated Circuit (Case 751F) . . . . . . .223
16.7 20-Pin Windowed Ceramic Integrated Circuit (Case 732) . . .224
16.8 28-Pin Windowed Ceramic Integrated Circuit (Case 733A) . .224
Section 17. Ordering Information
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
17.3 MC68HC705JJ7 Order Numbers . . . . . . . . . . . . . . . . . . . . . .226
17.4 MC68HC705JP7 Order Numbers. . . . . . . . . . . . . . . . . . . . . .227
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
List of Fig ure s
Figure
Title
Page
1-1
1-2
1-3
User Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .23
User Mode Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
EPO Oscillator Connections. . . . . . . . . . . . . . . . . . . . . . . . .26
2-1
2-2
2-3
2-4
2-5
2-6
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
I/O Registers $0000–$000F . . . . . . . . . . . . . . . . . . . . . . . . .34
I/O Registers $0010–$001F . . . . . . . . . . . . . . . . . . . . . . . . .35
Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
COP and Security Register (COPR) . . . . . . . . . . . . . . . . . .37
3-1
3-2
3-3
3-4
3-5
3-6
68HC05 Programming Model. . . . . . . . . . . . . . . . . . . . . . . .40
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . . .42
4-1
4-2
4-3
4-4
Interrupt Stacking Order. . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
External Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . .53
5-1
5-2
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
COP and Security Register (COPR) . . . . . . . . . . . . . . . . . .63
6-1
6-2
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . .70
Stop/Wait/Halt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .72
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List of Fig ure s
Figure
Title
Page
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . .79
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .80
Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . .81
Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . .84
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .85
Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . .86
PB0:3 Pin I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
PB4/AN4/TCMP/CMP1 Pin I/O Circuit . . . . . . . . . . . . . . . . .89
PB5/SDO Pin I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . .92
PB6/SDI Pin I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
PB7/SCK Pin I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . .99
Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . .100
Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
7-9
7-10
7-11
7-12
7-13
7-14
7-15
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
Analog Subsystem Block Diagram. . . . . . . . . . . . . . . . . . .105
Analog Multiplex Register (AMUX). . . . . . . . . . . . . . . . . . .106
Comparator 2 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . .107
INV Bit Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Analog Control Register (ACR) . . . . . . . . . . . . . . . . . . . . .111
Analog Status Register (ASR) . . . . . . . . . . . . . . . . . . . . . .115
Single-Slope A/D Conversion Method . . . . . . . . . . . . . . . .118
A/D Conversion — Full Manual Control (Mode 0) . . . . . . .124
A/D Conversion — Manual/Auto
Discharge Control (Mode 1) . . . . . . . . . . . . . . . . . . . . .125
A/D Conversion — TOF/ICF Control (Mode 2). . . . . . . . . .126
A/D Conversion — OCF/ICF Control (Mode 3) . . . . . . . . .127
8-10
8-11
9-1
9-2
9-3
9-4
9-5
9-6
SIOP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
SIOP Timing Diagram (CPHA = 0). . . . . . . . . . . . . . . . . . .139
SIOP Timing Diagram (CPHA = 1). . . . . . . . . . . . . . . . . . .140
SIOP Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . .141
SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . .144
SIOP Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . .145
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Figure
Title
Page
10-1
10-2
10-3
10-4
Core Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .148
Core Timer Status and Control Register (CTSCR) . . . . . .149
Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . .151
COP and Security Register (COPR) . . . . . . . . . . . . . . . . .152
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
Programmable Timer Overall Block Diagram. . . . . . . . . . .157
Programmable Timer Block Diagram . . . . . . . . . . . . . . . . .158
Programmable Timer Registers (TMRH and TMRL) . . . . .159
Alternate Counter Block Diagram. . . . . . . . . . . . . . . . . . . .160
Alternate Counter Registers (ACRH and ACRL) . . . . . . . .161
Timer Input Capture Block Diagram. . . . . . . . . . . . . . . . . .162
Input Capture Registers (ICRH and ICRL). . . . . . . . . . . . .163
Timer Output Compare Block Diagram . . . . . . . . . . . . . . .164
Output Compare Registers (OCRH and OCRL). . . . . . . . .165
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . .166
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . .168
12-1
12-2
12-3
Personality EPROM Block Diagram. . . . . . . . . . . . . . . . . .172
PEPROM Bit Select Register (PEBSR) . . . . . . . . . . . . . . .173
PEPROM Status and Control Register (PESCR). . . . . . . .174
13-1
13-2
13-3
EPROM Programming Register (EPROG). . . . . . . . . . . . .180
Mask Option Register (MOR). . . . . . . . . . . . . . . . . . . . . . .182
EPROM Security in COP Register (COP) . . . . . . . . . . . . .184
15-1
15-2
15-3
15-4
SIOP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . .218
Internal Reset Timing Diagram. . . . . . . . . . . . . . . . . . . . . .219
Low-Voltage Reset Timing Diagram. . . . . . . . . . . . . . . . . .219
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List of Ta b le s
Table
Title
Page
1-1
Device Options by Part Number . . . . . . . . . . . . . . . . . . . . . . . .22
4-1
4-2
Reset/Interrupt Vector Addresses. . . . . . . . . . . . . . . . . . . . . . .47
Oscillator Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6-1
Oscillator Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7-1
7-2
7-3
7-4
Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Port B Pin Functions — PB0:4 . . . . . . . . . . . . . . . . . . . . . . . . .91
Port B Pin Functions — PB5:7 . . . . . . . . . . . . . . . . . . . . . . . . .98
Port C Pin Functions (28-Pin Versions Only) . . . . . . . . . . . . .102
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
Comparator 2 Input Sources . . . . . . . . . . . . . . . . . . . . . . . . .107
Channel Select Bus Combinations . . . . . . . . . . . . . . . . . . . . .110
A/D Conversion Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
A/D Conversion Parameters. . . . . . . . . . . . . . . . . . . . . . . . . .121
Sample Conversion Timing (V = 5.0 Vdc) . . . . . . . . . . . . .122
DD
Absolute Voltage Reading Errors . . . . . . . . . . . . . . . . . . . . . .130
Ratiometric Voltage Reading Errors . . . . . . . . . . . . . . . . . . . .132
Voltage Comparator Setup Conditions . . . . . . . . . . . . . . . . . .133
9-1
SIOP Clock Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . .143
10-1 Core Timer Interrupt Rates and COP Timeout Selection . . . .151
10-2 COP Watchdog Recommendations . . . . . . . . . . . . . . . . . . . .153
11-1 Output Compare Initialization Example . . . . . . . . . . . . . . . . .166
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Table
Title
Page
12-1 PEPROM Bit Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
14-1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . .192
14-2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .193
14-3 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .195
14-4 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .196
14-5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
14-6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
14-7 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
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Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 1. Ge ne ra l De sc rip tion
1.1 Conte nts
1.2
1.3
1.4
1.5
1.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
V
and V Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
SS
DD
1.7
OSC1 and OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . . .26
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . .27
1.7.1
1.7.2
1.7.3
1.7.4
1.7.5
1.8
1.9
RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IRQ/V Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PP
1.10 PA0–PA5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.11 PB0–PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.12 PC0–PC7 (MC68HC705JP7) . . . . . . . . . . . . . . . . . . . . . . . . . .29
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
19
General Description
Ge ne ra l De sc rip tion
1.2 Introd uc tion
The Motorola MC68HC705JJ7 and MC68HC705JP7 are EPROM
versions of the MC68HC05JJ/JP Family of microcontrollers.
1.3 Fe a ture s
• Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7)
or 28-Pin Package (MC68HC705JP7)
• 6160 Bytes of User EPROM (Including 16 Bytes of User Vectors)
• 224 Bytes of Low-Power User RAM (4 Transistors)
• 64 Bits of Personality EPROM (Serial Access)
• 16-Bit Programmable Timer with Input Capture and Output
Compare
• 15-Stage Core Timer Including 8-Bit Free-Running Counter
and 4-Stage Selectable Real-Time Interrupt Generator
• Simple Serial Input/Output Port (SIOP) with Interrupt Capability
• Two Voltage Comparators, One of Which Can be Combined with
the 16-Bit Programmable Timer to Create a 4-Channel, Single-
Slope A/D Converter
• Output of Voltage Comparator Can Drive Port Pin PB4 Directly
Under Software Control
• 14 I/O Lines (MC68HC705JJ7) or 22 I/O Lines (MC68HC705JP7)
Including High-Source/Sink Current Capability on 6 I/O Pins
(MC68HC705JJ7) or 14 I/O Pins (MC68HC705JP7)
• Programmable 8-Bit Mask Option Register (MOR) to Select Mask
Options Found in ROM-Based Versions
• MOR Selectable Software Programmable Pulldowns on All I/O
Pins and Keyboard Scan Interrupt on Four I/O Pins
• Software Mask and Request Bit for IRQ Interrupt with MOR
Selectable Sensitivity on IRQ Interrupt (Edge- and Level-Sensitive
or Edge-Only)
General Release Specification
20
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Description
General Description
Features
• On-Chip Oscillator with Device Option of Crystal/Ceramic
Resonator or RC Operation and MOR Selectable Shunt Resistor,
Approximately 2 MΩ
• Internal Oscillator for Lower-Power Operation, Approximately
100 kHz (500 kHz Selected as Device Option)
1
• EPROM Security Bit to Aid in Locking Out Access to
Programmable EPROM array
• MOR Selectable (COP) Watchdog System
• Power-Saving Stop and Wait Mode Instructions (MOR Selectable
STOP Conversion to Halt and Option for Fast 16-Cycle Restart,
and Power-On Reset)
• On-Chip Temperature Measurement Diode
• MOR Selectable Low-Voltage Inhibit to Reset CPU in Low-Voltage
Conditions
• Illegal Address Reset
• Internal Steering Diode and Pullup Device on RESET Pin to V
DD
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
21
General Description
Ge ne ra l De sc rip tion
1.4 De vic e Op tions
The following MC68HC705JJ7/MC68HC705JP7 device options are
available:
• On-Chip Oscillator Type: Crystal/Ceramic Resonator Connections
or Resistor-Capacitor (RC) Connections
• Nominal Frequency of Internal Low Power Oscillator: 100 or
500 kHz
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
Any reference to voltage, current, or frequency specified in the following
sections will refer to the nominal values. The exact values and their
tolerance or limits are specified in Section 15. Electrical
Specifications.
Combinations of the various device options are specified by part
number. Refer to Table 1-1 and to Section 17. Ordering Information
for specific ordering information.
Table 1-1. Device Options by Part Number
Part
Number
Pin
Count
Oscillator
Type
Internal LPO Nominal
Frequency (kHz)
MC68HC705JJ7
MC68HC705JP7
20
28
Crystal/Resonator
Crystal/Resonator
100
100
MC68HC705SJ7
MC68HC705SP7
20
28
Crystal/Resonator
Crystal/Resonator
500
500
MC68HRC705JJ7
MC68HRC705JP7
20
28
Resistor-Capacitor
Resistor-Capacitor
100
100
MC68HRC705SJ7
MC68HRC705SP7
20
28
Resistor-Capacitor
Resistor-Capacitor
500
500
General Release Specification
22
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Description
General Description
Device Options
OSC1
OSC2
EXTERNAL
OSCILLATOR
+
COMP1
V
DD
-
INTERNAL
OSCILLATOR
+
CURRENT
SOURCE
COMP2
-
÷2
16-BIT TIMER
(1) INPUT CAPTURE
(1) OUTPUT COMPARE
TCAP
TCMP
INT
V
COMPARATOR
CONTROL &
MULTIPLEXER
LVR
DD
TEMPERATURE
DIODE
ICF
OCF
TOF
15-STAGE
CORE TIMER
SYSTEM
V
SS
WATCHDOG &
ILLEGAL ADDR
DETECT
V
SS
PB0/AN0
PB1/AN1
PB2/AN2
V
SS
CPU CONTROL
CPU REGISTERS
ALU
INT
PB3/AN3/TCAP
PB4/AN4/TCMP/CMP1*
PB5/SDO
RESET
IRQ/V
68HC05 CPU
PP
ACCUM
PB6/SDI
INDEX REG
PB7/SCK
STK PTR
0 0 0 0 0 0 0 0 1 1
INT
SIMPLE SERIAL
INTERFACE
(SIOP)
PROGRAM COUNTER
COND CODE REG 1 1 1 H I N Z C
PA5*
PA4*
PA3*†
PA2*†
PA1*†
PA0*†
BOOT ROM — 240 BYTES
STATIC RAM (4T) — 224 BYTES
PC7*
PC6*
USER EPROM — 6160 BYTES
PC5*
PERSONALITY EPROM — 64 BITS
PORT C
PC4*
PC3*
PC2*
PC1*
PC0*
ONLY ON
28-PIN
VERSIONS
* High sink current capability
* High source current capability
† IRQ interrupt capability
Figure 1-1. User Mode Block Diagram
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
23
General Description
Ge ne ra l De sc rip tion
1.5 Func tiona l Pin De sc rip tion
Refer to Figure 1-2 for the pinouts of the MC68HC705JJ7 and
MC68HC705JP7 in the user mode.
The following paragraphs give a description of the general function of
each pin.
MC68HC705JJ7
PB1/AN1
PB2/AN2
PB0/AN0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
PB3/AN3/TCAP
*PB4/AN4/TCMP/CMP1
PB5/SDO
V
SS
OSC1
OSC2
RESET
PB6/SDI
PB7/SCK
IRQ/V
PP
*PA5
PA0*†
PA1*†
PA2*†
* PA4
†* PA3
MC68HC705JP7
PB1/AN1
PB2/AN2
PB3/AN3/TCAP
*PB4/AN4/TCMP/CMP1
PB5/SDO
* PC4
PB0/AN0
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
2
DD
V
3
SS
OSC1
OSC2
PC3*
4
5
6
*PC5
PC2*
7
* PC6
PC1*
8
*PC7
PC0*
9
PB6/SDI
RESET
10
11
12
13
14
PB7/SCK
*PA5
IRQ/V
PP
PA0*†
PA1*†
PA2*†
* PA4
†* PA3
* Denotes 10 mA sink /5 mA source capability
† Denotes IRQ interrupt capability
Figure 1-2. User Mode Pinouts
General Release Specification
24
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Description
General Description
VDD and VSS Pins
1.6 VDD a nd VSS Pins
Power is supplied to the MCU through V and V . V is the positive
DD
SS DD
supply, and V is ground. The MCU operates from a single power
SS
supply.
Very fast signal transitions occur on the MCU pins. The short rise and
fall times place very high short-duration current demands on the power
supply. To prevent noise problems, special care should be taken to
provide good power supply bypassing at the MCU by using bypass
capacitors with good high-frequency characteristics that are positioned
as close to the MCU as possible. Bypassing requirements vary,
depending on how heavily the MCU pins are loaded.
1.7 OSC1 a nd OSC2 Pins
The OSC1 and OSC2 pins are the connections for the external pin
oscillator (EPO). The OSC1 and OSC2 pins can accept the following
sets of components:
1. A crystal as shown in Figure 1-3 (a)
2. A ceramic resonator as shown in Figure 1-3 (a)
3. An external resistor as shown in Figure 1-3 (b)
4. An external clock signal as shown in Figure 1-3 (c)
The selection of the crystal/ceramic resonator or RC oscillator
configuration is done by product part number selection as described in
Section 17. Ordering Information.
The frequency, f , of the EPO or external clock source is divided by two
osc
to produce the internal operating frequency, f . An internal 2 MΩ
OP
resistor may be selected between OSC1 and OSC2 by the OSCRES bit
in the mask option register (MOR).
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
25
General Description
Ge ne ra l De sc rip tion
MCU
MCU
R
MCU
2 MΩ
OSC1
OSC2
OSC1
OSC2
OSC1
OSC2
UNCONNECTED
EXTERNAL CLOCK
(a) Crystal or
(b) RC Oscillator
Connections
(c) External
Clock Source
Connection
Ceramic Resonator
Connections
Figure 1-3. EPO Oscillator Connections
1.7.1 Crysta l Osc illa tor
The circuit in Figure 1-3 (a) shows a typical oscillator circuit for an AT-
cut, parallel resonant crystal. The crystal manufacturer’s
recommendations should be followed, as the crystal parameters
determine the external component values required to provide maximum
stability and reliable startup. The load capacitance values used in the
oscillator circuit design should include all stray capacitances. The crystal
and components should be mounted as close as possible to the pins for
startup stabilization and to minimize output distortion. An internal startup
resistor of approximately 2 MΩ can be provided between OSC1 and
OSC2 for the crystal type oscillator by use of the OSCRES bit in the
MOR.
NOTE: In general, a 32-kHz crystal is not recommended for use with the
MC68HC705JJ7/MC68HC705JP7 unless specifically indicated by the
crystal manufacturer.
1.7.2 Ce ra m ic Re sona tor Osc illa tor
In cost-sensitive applications, a ceramic resonator can be used in place
of the crystal. The circuit in Figure 1-3 (a) can be used for a ceramic
resonator. The resonator manufacturer’s recommendations should be
followed, as the resonator parameters determine the external
component values required for maximum stability and reliable starting.
General Release Specification
26
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Description
General Description
OSC1 and OSC2 Pins
The load capacitance values used in the oscillator circuit design should
include all stray capacitances. The ceramic resonator and components
should be mounted as close as possible to the pins for startup
stabilization and to minimize output distortion. An internal startup resistor
of approximately 2 MΩ can be provided between OSC1 and OSC2 for
the ceramic resonator type oscillator by use of the OSCRES bit in the
MOR.
1.7.3 RC Osc illa tor
The lowest cost oscillator is the RC oscillator configuration where a
resistor is connected between the two oscillator pins as shown in Figure
1-3 (b). The internal startup resistor of approximately 2 MΩ is not
recommended between OSC1 and OSC2 for the RC-type oscillator.
The selection of the RC oscillator configuration is done by product part
number selection as described in Section 17. Ordering Information.
1.7.4 Exte rna l Cloc k
An external clock from another CMOS-compatible device can be
connected to the OSC1 input, with the OSC2 input not connected, as
shown in Figure 1-3 (c). This oscillator can be selected via software.
This configuration is possible regardless of whether the crystal/ceramic
resonator or RC oscillator configuration is used.
1.7.5 Inte rna l Low-Powe r Osc illa tor
An internal low-power oscillator (LPO) is provided which is the default
oscillator out of reset. When operating from this internal LPO, the other
oscillator can be powered down by software to further conserve power.
The selection of the LPO configuration is done by product part number
selection as described in Section 17. Ordering Information.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
27
General Description
Ge ne ra l De sc rip tion
1.8 RESET Pin
The RESET pin can be used as an input to reset the MCU to a known
startup state by pulling it to the low state. It also functions as an output
to indicate that an internal COP watchdog, illegal address, or low-voltage
reset has occurred. The RESET pin contains a pullup device to allow the
pin to be left disconnected without an external pullup resistor. The
RESET pin also contains a steering diode that, when the power is
removed, will discharge to V any charge left on an external capacitor
DD
connected between the RESET pin and V . The RESET pin also
SS
contains an internal Schmitt trigger to improve its noise immunity as an
input.
1.9 IRQ/ VPP Pin
The IRQ/V input pin drives the asynchronous IRQ interrupt function of
PP
the CPU. The IRQ interrupt function uses the LEVEL bit in the MOR to
provide either negative edge-sensitive triggering or both negative edge-
sensitive and low level-sensitive triggering. If the LEVEL bit is set to
enable level-sensitive triggering, the IRQ/V pin requires an external
PP
resistor to V for “wired-OR” operation. If the IRQ/V pin is not used,
DD
PP
it must be tied to the V supply. The IRQ/V pin contains an internal
DD
PP
Schmitt trigger as part of its input to improve noise immunity. The voltage
on this pin may affect the mode of operation if the voltage on the
IRQ/V pin is above V when the device is released from a reset
PP
DD
condition.
The IRQ/V pin may be taken above V in order to program an
PP
DD
EPROM memory location or personality EPROM bit. For more
information, refer to 15.14 PEPROM and EPROM Programming
Characteristics.
NOTE: Each of the PA0 through PA3 I/O pins may be connected as an OR
function with the IRQ interrupt function by the PIRQ bit in the MOR. This
capability allows keyboard scan applications where the transitions or
levels on the I/O pins will behave the same as the IRQ/V pin, except
PP
that active transitions and levels are inverted. The edge or level
sensitivity selected by the LEVEL bit in the MOR for the IRQ/V pin also
PP
General Release Specification
28
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Description
General Description
PA0–PA5
applies to the I/O pins that are ORed to create the IRQ signal. For more
information, refer to 4.6 External Interrupts.
1.10 PA0–PA5
These six I/O lines comprise port A, a general-purpose bidirectional I/O
port. This port also has four pins which have keyboard interrupt
capability. All six of these pins have high current source and sink
capability.
All of these pins have software programmable pulldowns which can be
disabled by the SWPDI bit in the MOR.
1.11 PB0–PB7
These eight I/O lines comprise port B, a general-purpose bidirectional
I/O port. This port is also shared with the 16-bit programmable timer
input capture and output compare functions, with the two voltage
comparators in the analog subsystem, and with the simple serial
interface (SIOP).
The outputs of voltage comparator 1 can directly drive the PB4 pin; and
the PB4 pin has high current source and sink capability.
All of these pins have software programmable pulldowns which can be
disabled by the SWPDI bit in the MOR.
1.12 PC0–PC7 (MC68HC705JP7)
These eight I/O lines comprise port C, a general-purpose bidirectional
I/O port. This port is only available on the 28-pin MC68HC705JP7. All
eight of these pins have high current source and sink capability.
All of these pins have software programmable pulldowns which can be
disabled by the SWPDI bit in the MOR.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
29
General Description
Ge ne ra l De sc rip tion
General Release Specification
30
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Description
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 2. Me m ory
2.1 Conte nts
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Interrupt Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.2 Introd uc tion
2.3 Me m ory Ma p
This section describes the organization of the memory on the
MC68HC705JJ7/MC68HC705JP7.
The CPU can address 8 kilobytes of memory space as shown in
Figure 2-1. The EPROM portion of memory holds the program
instructions, fixed data, user defined vectors, and interrupt service
routines. The RAM portion of memory holds variable data. I/O registers
are memory mapped so that the CPU can access their locations in the
same way that it accesses all other memory locations.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
31
Memory
Me m ory
$0000
$001F
$0020
I/O REGISTERS
32 BYTES
USER RAM
224 BYTES
$00C0
$00FF
STACK RAM
64 BYTES
$00FF
$0100
$06FF
$0700
UNIMPLEMENTED
1536 BYTES
USER EPROM
6144 BYTES
$1EFF
$1F00
$1FEF
$1FF0
$1FFF
INTERNAL TEST ROM
240 BYTES
USER VECTORS
(EPROM) 16 BYTES
Figure 2-1. Memory Map
2.4 Inp ut/ Outp ut Re g iste rs
The first 32 addresses of the memory space, $0000–$001F, contain the
I/O registers section as summarized in Figure 2-2.
One I/O register is located outside the 32-byte I/O section, which is the
computer operating properly (COP) register mapped at $1FF0.
The assignment of each control, status, and data bit in the I/O register
space from $0000–$001F is given in Figure 2-3 and Figure 2-4.
General Release Specification
32
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Memory
Memory
Input/Output Registers
Address
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Register Name
Port A Data Register
Port B Data Register
Port C Data Register *
Analog MUX Register
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register *
Unused
Core Timer Status & Control Register
Core Timer Counter
Serial Control Register
Serial Status Register
Serial Data Register
IRQ Status & Control Register
Personality EPROM Bit Select Register
Personality EPROM Status & Control Register
Port A and Port C Pulldown Register *
Port B Pulldown Register
Timer Control Register
Timer Status Register
Input Capture Register (MSB)
Input Capture Register (LSB)
Output Compare Register (MSB)
Output Compare Register (LSB)
Timer Counter Register (MSB)
Timer Counter Register (LSB)
Alternate Counter Register (MSB)
Alternate Counter Register (LSB)
EPROM Programming Register
Analog Control Register
Analog Status Register
Reserved
Figure 2-2. I/O Registers
* Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
33
Memory
Me m ory
Addr.
Register
R/W Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
0
$0000
Port A Data, PORTA
PA5
PA4
PA3
PA2
PA1
PA0
$0001
$0002
Port B Data, PORTB
* Port C Data, PORTC
PB7
PC7
PB6
PC6
PB5
PC5
INV
PB4
PC4
PB3
PC3
PB2
PC2
PB1
PC1
PB0
PC0
$0003
$0004
$0005
$0006
$0007
Analog MUX Register, AMUX
Port A Data Direction, DDRA
Port B Data Direction, DDRB
* Port C Data Direction, DDRC
Unimplemented
HOLD DHOLD
VREF
MUX4
MUX3
MUX2
MUX1
0
0
DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Read: CTOF
Write:
RTIF
6
0
0
$0008 CTimer Status/Control, CTSCR
CTOFE
5
RTIE
4
RT1
1
RT0
CTOFR RTIFR
Read: BIT7
Write:
3
2
BIT0
$0009
$000A
$000B
$000C
$000D
$000E
$000F
CTimer Counter, CTCR
Serial Control, SCR
Read:
SPIE
Write:
0
SPIR
0
SPE
LSBF
0
MSTR
0
CPHA
0
SPR1
0
SPR0
0
Read: SPIF
Write:
DCOL
Serial Status, SSR
Read:
BIT7
Serial Data, SDR
6
5
4
3
2
0
1
BIT0
0
Write:
Read:
IRQE
Write:
0
IRQF
0
IRQ Status & Control, ISCR
PEPROM Bit Select, PEBSR
OM2
OM1
R
IRQR
Read:
PEB7
Write:
PEB6
0
PEB5
PEPGM
PEB4
0
PEB3
PEB2
PEB1
PEB0
Read: PEDATA
Write:
0
0
0
PEPZRF
PEPROM Status/Control,
PESCR
R
R
R
= Unimplemented
R
= Reserved
Figure 2-3. I/O Registers $0000–$000F
* Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
General Release Specification
34
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Memory
Memory
Input/Output Registers
Addr.
Register
R/W Bit 7
6
5
4
3
2
1
Bit 0
Read:
* Port A & Port C Pulldown,
PDRA
$0010
Write: PDICH PDICL PDIA5
Read:
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
Port B Pulldown, PDRB
Timer Control, TCR
Write: PDIB7
PDIB6
PDIB5
PDIB4
0
PDIB3
0
PDIB2
0
PDIB1
IEDG
0
PDIB0
OLVL
0
Read:
ICIE
OCIE
TOIE
Write:
Read:
ICF
0
12
4
0
11
3
0
10
2
Timer Status, TSR
OCF
14
TOF
13
Write:
Read: BIT15
Write:
9
1
BIT8
BIT0
Input Capture MSB, ICRH
Input Capture LSB, ICRL
Output Compare MSB, OCRH
Output Compare LSB, OCRL
Timer Counter MSB, TMRH
Timer Counter LSB, TMRL
Read: BIT7
Write:
6
5
Read:
BIT15
Write:
14
13
12
11
10
9
BIT8
Read:
BIT7
6
5
4
3
2
1
9
BIT0
BIT8
Write:
Read: BIT15
Write:
14
13
12
11
10
Read: BIT7
Write:
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
BIT0
BIT8
BIT0
Read: BIT15
Write:
$001A Alternate. Counter MSB, ACRH
Read: BIT7
Write:
$001B
Alternate. Counter LSB, ACRL
Read:
Write:
Read:
Write:
0
0
0
0
0
$001C EPROM Programming, EPROG
ELAT
MPGM EPGM
R
R
R
R
$001D
$001E
$001F
Analog Control, ACR
Analog Status, ASR
Reserved
CHG
ATD2
CPF1
ATD1
0
ICEN
0
CPIE
CP2EN CP1EN
ISEN
Read: CPF2
Write:
CMP2
VOFF
CMP1
COE1
CPFR2 CPFR1
R
R
R
Read:
Write:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
= Unimplemented
R
= Reserved
Figure 2-4. I/O Registers $0010–$001F
* Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
35
Memory
Me m ory
2.5 Inte rrup t Ve c tor Ma p p ing
The interrupt vectors are contained in the upper memory addresses
above $1FF0 as shown in Figure 2-5.
Address
$1FF0
$1FF1
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
Register Name
COP Register & EPROM Security
Mask Option Register
Analog Interrupt Vector (MSB)
Analog Interrupt Vector (LSB)
Serial Interrupt Vector (MSB)
Serial Interrupt Vector ((LSB)
Timer Interrupt Vector (MSB)
Timer Interrupt Vector (LSB)
CTimer Interrupt Vector (MSB)
CTimer Interrupt Vector (LSB)
External IRQ Vector (MSB)
External IRQ Vector (LSB)
SWI Vector (MSB)
SWI Vector (LSB)
Reset Vector (MSB)
Reset Vector (LSB)
Figure 2-5. Vector Mapping
2.6 RAM
The 224 addresses from $0020 to $00FF serve as both the user RAM
and the stack RAM. The CPU uses five RAM bytes to save all CPU
register contents before processing an interrupt. During a subroutine
call, the CPU uses two bytes to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE: Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
General Release Specification
36
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Memory
Memory
EPROM
2.7 EPROM
The EPROM is located in two areas of the memory map:
• Addresses $0700–$1EFF contain 6144 bytes of user EPROM.
• Addresses $1FF0–$1FFF contain 16 bytes of EPROM reserved
for user vectors and COP and security register, and the mask
option register.
2.8 COP Re g iste r
As shown in Figure 2-6, a register location is provided at $1FF0 to set
1
the EPROM security , select the optional features, and reset the COP
watchdog timer. The OPT bit controls the function of the PB4 port pin
and the availability to add an offset to any measured analog voltages.
See 8.5 Analog Status Register for more information
$1FF0
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
EPMSEC
OPT
COPC
= Unimplemented
Figure 2-6. COP and Security Register (COPR)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
37
Memory
Me m ory
General Release Specification
38
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Memory
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 3. Ce ntra l Proc e ssor Unit (CPU)
3.1 Conte nts
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Index Register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .42
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .44
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA Central Processor Unit (CPU)
General Release Specification
39
Ce ntra l Proc e ssor Unit (CPU)
3.2 Introd uc tion
This section describes the CPU registers. Figure 3-1 shows the five
CPU registers. CPU registers are not part of the memory map.
7
0
0
0
0
A
X
ACCUMULATOR (A)
7
INDEX REGISTER (X)
15
0
6
1
5
0
1
0
1
0
0
0
0
0
8
1
7
SP
STACK POINTER (SP)
15
1
10
PCH
PCL
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
7
1
5
1
4
0
1
H
I
N
Z
C
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 3-1. 68HC05 Programming Model
3.3 Ac c um ula tor (A)
The accumulator is a general-purpose 8-bit register as shown in Figure
3-2. The CPU uses the accumulator to hold operands and results of
arithmetic and non-arithmetic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by Reset
Figure 3-2. Accumulator (A)
General Release Specification
40
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU)
Index Register (X)
3.4 Ind e x Re g iste r (X)
The index register is a general-purpose 8-bit register as shown in Figure
3-3. In the indexed addressing modes, the CPU uses the byte in the
index register to determine the conditional address of the operand.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by Reset
Figure 3-3. Index Register (X)
The 8-bit index register can also serve as a temporary data storage
location.
3.5 Sta c k Pointe r (SP)
The stack pointer is a 16-bit register that contains the address of the next
location on the stack as shown in Figure 3-4. During a reset or after the
reset stack pointer (RSP) instruction, the stack pointer initializes to
$00FF. The address in the stack pointer decrements as data is pushed
onto the stack and increments as data is pulled from the stack.
Bit
Bit
0
15 14 13 12 11 10
9
0
0
8
0
0
7
1
1
6
1
1
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Figure 3-4. Stack Pointer (SP)
The 10 most significant bits of the stack pointer are permanently fixed at
0000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations;
an interrupt uses five locations.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA Central Processor Unit (CPU)
General Release Specification
41
Ce ntra l Proc e ssor Unit (CPU)
3.6 Prog ra m Counte r (PC)
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched as shown in Figure 3-5. The
three most significant bits of the program counter are ignored internally
and appear as 111 during stacking and subroutine calls.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Bit
Bit
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
1
0
1
0
1
0
Loaded with Vector from $1FFE and $1FFF
Figure 3-5. Program Counter (PC)
3.7 Cond ition Cod e Re g iste r (CCR)
The condition code register is an 8-bit register whose three most
significant bits are permanently fixed at 111 as shown in Figure 3-6. The
condition code register contains the interrupt mask and four flags that
indicate the results of the instruction just executed. The following
paragraphs describe the functions of the condition code register.
Bit 7
1
6
1
1
5
1
1
4
3
I
2
1
Bit 0
Z
Read:
Write:
Reset:
H
U
N
U
C
U
1
1
U
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
General Release Specification
42
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU)
Condition Code Register (CCR)
Half-Carry Flag (H)
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD or ADC operation. The
half-carry flag is required for binary coded decimal (BCD) arithmetic
operations. Reset has no affect on the half-carry flag.
Interrupt Mask (I)
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is a logic zero, the CPU saves the
CPU registers on the stack, sets the interrupt mask, and then fetches
the interrupt vector. If an interrupt request occurs while the interrupt
mask is set, the interrupt request is latched. The CPU processes the
latched interrupt as soon as the interrupt mask is cleared again.
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a CLI
instruction.
Negative Flag (N)
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result. Reset has
no affect on the negative flag.
Zero Flag (Z)
The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00. Reset has
no affect on the zero flag.
Carry/Borrow Flag (C)
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag. Reset
has no affect on the carry/borrow flag.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA Central Processor Unit (CPU)
General Release Specification
43
Ce ntra l Proc e ssor Unit (CPU)
3.8 Arithm e tic / Log ic Unit (ALU)
The ALU performs the arithmetic and logical operations defined by the
instruction set. The binary arithmetic circuits decode instructions and set
up the ALU for the selected operation. Most binary arithmetic is based
on the addition algorithm, carrying out subtraction as negative addition.
Multiplication is not performed as a discrete operation but as a chain of
addition and shift operations within the ALU. The multiply instruction
(MUL) requires 11 internal clock cycles to complete this chain of
operations.
General Release Specification
44
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Central Processor Unit (CPU) MOTOROLA
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 4. Inte rrup ts
4.1 Conte nts
4.2
4.3
4.4
4.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.6
4.6.1
4.6.2
4.6.3
IRQ/V Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
PA0–PA3 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
IRQ Status and Control Register (ISCR). . . . . . . . . . . . . . .53
PP
4.7
4.7.1
4.7.2
Core Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Core Timer Overflow Interrupt. . . . . . . . . . . . . . . . . . . . . . .55
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.8
Programmable Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . .56
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .56
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.8.1
4.8.2
4.8.3
4.9
Serial Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.10 Analog Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.10.1
4.10.2
Comparator Input Match Interrupt . . . . . . . . . . . . . . . . . . . .58
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
45
Interrupts
Inte rrup ts
4.2 Introd uc tion
An interrupt temporarily stops normal program execution to process a
particular event. An interrupt does not stop the execution of the
instruction in progress, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
CPU registers on the stack and loads the program counter with a
user-defined vector address.
4.3 Inte rrup t Ve c tors
Table 4-1 summarizes the reset and interrupt sources and vector
assignments.
General Release Specification
46
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Interrupts
Interrupts
Interrupt Vectors
Table 4-1. Reset/Interrupt Vector Addresses
MOR
Control
Bit
Global
Hardware
Mask
Local
Software
Mask
Priority
(1 = Highest)
Vector
Address
Function
Source
Power-On Logic
RESET Pin
Low-Voltage Reset
Illegal Address Reset
—
Reset
—
—
—
—
1
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
1
COP Watchdog
COPEN
Software
Interrupt
(SWI)
Same Priority
As Instruction
User Code
—
—
IRQ/V Pin
PP
PA3 Pin
PA2 Pin
PA1 Pin
PA0 Pin
External
Interrupt (IRQ)
I Bit
IRQE Bit
2
2
PIRQ
Core Timer
Interrupts
TOF Bit
RTIF Bit
TOFE Bit
RTIE Bit
—
—
I Bit
I Bit
3
4
$1FF8–$1FF9
$1FF6–$1FF7
Programmable
Timer
ICF Bit
OCF Bit
TOF Bit
ICIE Bit
OCIE Bit
TOIE Bit
Interrupts
Serial
Interrupt
SPIF Bit
—
—
I Bit
I Bit
SPIE Bit
CPIE Bit
5
6
$1FF4–$1FF5
$1FF2–$1FF3
Analog
Interrupt
CPF1 Bit
CPF2 Bit
NOTES:
1. COPEN enables the COP watchdog timer.
2. PIRQ enables port A external interrupts on PA0–PA3.
NOTE: If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
actually interrupt a lower priority interrupt service routine unless the
lower priority interrupt service routine clears the I bit.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
47
Interrupts
Inte rrup ts
4.4 Inte rrup t Proc e ssing
The CPU does the following actions to begin servicing an interrupt:
• Stores the CPU registers on the stack in the order shown in
Figure 4-1
• Sets the I bit in the condition code register to prevent further
interrupts
• Loads the program counter with the contents of the appropriate
interrupt vector locations as shown in Table 4-1
The return from interrupt (RTI) instruction causes the CPU to recover its
register contents from the stack as shown in Figure 4-1. The sequence
of events caused by an interrupt is shown in the flow chart in Figure 4-2.
$0020
$0021
(Bottom of RAM)
(Bottom of Stack)
$00BE
$00BF
$00C0
$00C1
$00C2
Unstacking
Order
n
n+1
n+2
n+3
n+4
Condition Code Register
Accumulator
5
4
3
2
1
1
2
3
4
5
Index Register
Program Counter (High Byte)
Program Counter (Low Byte)
Stacking
Order
$00FD
$00FE
$00FF
Top of Stack (RAM)
Figure 4-1. Interrupt Stacking Order
General Release Specification
48
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Interrupts
Interrupts
Interrupt Processing
FROM
RESET
YES
I BIT SET?
NO
YES
YES
YES
YES
YES
EXTERNAL
CLEAR IRQ LATCH.
INTERRUPT?
NO
CORE TIMER
INTERRUPT?
NO
TIMER
INTERRUPT?
NO
SERIAL
INTERRUPT?
NO
ANALOG
INTERRUPT?
STACK PCL, PCH, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
NO
FETCH NEXT
INSTRUCTION.
SWI
YES
YES
INSTRUCTION?
NO
RTI
UNSTACK CCR, A, X, PCH, PCL.
EXECUTE INSTRUCTION.
INSTRUCTION?
NO
Figure 4-2. Interrupt Flowchart
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
49
Interrupts
Inte rrup ts
4.5 Softwa re Inte rrup t
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.6 Exte rna l Inte rrup ts
These sources can generate external interrupts:
• IRQ/V pin
PP
• PA3–PA0 pins
Setting the I bit in the condition code register or clearing the IRQE bit in
the interrupt status and control register disables these external
interrupts.
4.6.1 IRQ/ V Pin
PP
An interrupt signal on the IRQ/V pin latches an external interrupt
PP
request. To help clean up slow edges, the input from the IRQ/V pin is
PP
processed by a Schmitt trigger gate. When the CPU completes its
current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU
then tests the I bit in the condition code register and the IRQE bit in the
IRQ status and control register (ISCR). If the I bit is clear and the IRQE
bit is set, then the CPU begins the interrupt sequence. The CPU clears
the IRQ latch while it fetches the interrupt vector, so that another
external interrupt request can be latched during the interrupt service
routine. As soon as the I bit is cleared during the return from interrupt,
the CPU can recognize the new interrupt request. Figure 4-3 shows the
logic for external interrupts.
NOTE: If the IRQ/V pin is not in use, it should be connected to the V pin.
PP
DD
The IRQ/V pin can be negative edge-triggered only or negative edge-
PP
and low level-triggered. External interrupt sensitivity is programmed with
the LEVEL bit in the mask option register (MOR).
General Release Specification
50
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Interrupts
Interrupts
External Interrupts
With the edge- and level-sensitive trigger MOR option, a falling edge or
a low level on the IRQ/V pin latches an external interrupt request. The
PP
edge- and level-sensitive trigger MOR option allows connection to the
IRQ/V pin of multiple wired-OR interrupt sources. As long as any
PP
source is holding the IRQ low, an external interrupt request is present,
and the CPU continues to execute the interrupt service routine.
With the edge-sensitive-only trigger option, a falling edge on the
IRQ/V pin latches an external interrupt request. A subsequent
PP
interrupt request can be latched only after the voltage level on the
IRQ/V pin returns to a logic one and then falls again to logic zero.
PP
V
TO
PP
USER EPROM
AND PEPROM
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ/V
PP
PA3
PA2
PA1
PA0
V
DD
IRQ
LATCH
EXTERNAL
INTERRUPT
REQUEST
R
RST
IRQ VECTOR FETCH
IRQ STATUS/CONTROL REGISTER ($000D)
MASK OPTION REGISTER ($1FF1)
INTERNAL DATA BUS
Figure 4-3. External Interrupt Logic
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
51
Interrupts
Inte rrup ts
NOTE: The response of the IRQ/V pin can be affected if the external interrupt
PP
capability of the PA0 through PA3 pins is enabled. If the port A pins are
enabled as external interrupts, then any high level on a PA0–PA3 pin will
cause the IRQ changes and state to be ignored until all of the PA0–PA3
pins have returned to a low level.
4.6.2 PA0–PA3 Pins
Programming the PIRQ bit in the MOR to a logic one enables the
PA0–PA3 pins (PA0:3) to serve as additional external interrupt sources.
A rising edge on a PA0:3 pin latches an external interrupt request. After
completing the current instruction, the CPU tests the IRQ latch. If the
IRQ latch is set, the CPU then tests the I bit in the condition code register
and the IRQE bit in the ISCR. If the I bit is clear and the IRQE bit is set,
the CPU then begins the interrupt sequence. The CPU clears the IRQ
latch while it fetches the interrupt vector, so that another external
interrupt request can be latched during the interrupt service routine. As
soon as the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request.
The PA0:3 pins can be edge-triggered or edge- and level-triggered.
External interrupt triggering sensitivity is selected by the LEVEL bit in the
MOR.
With the edge- and level-sensitive trigger MOR option, a rising edge or
a high level on a PA0:3 pin latches an external interrupt request. The
edge- and level-sensitive trigger MOR option allows connection to a
PA0:3 pin of multiple wired-OR interrupt sources. As long as any source
is holding the pin high, an external interrupt request is present, and the
CPU continues to execute the interrupt service routine.
With the edge-sensitive only trigger MOR option, a rising edge on a
PA0:3 pin latches an external interrupt request. A subsequent external
interrupt request can be latched only after the voltage level of the
previous interrupt signal returns to a logic zero and then rises again to a
logic one.
General Release Specification
52
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Interrupts
Interrupts
External Interrupts
NOTE: If the port A pins are enabled as external interrupts, then a high level on
any PA0:3 pin will drive the state of the IRQ function such that the
IRQ/V pin and other PA0:3 pins to be ignored until ALL of the PA0:3
PP
pins have returned to a low level. Similarly, if the IRQ/V pin is at a low
PP
level, the PA0:3 pins will be ignored until the IRQ/V pin returns to a
PP
high state.
4.6.3 IRQ Sta tus a nd Control Re g iste r (ISCR)
The IRQ status and control register (ISCR), shown in Figure 4-4,
contains an external interrupt mask (IRQE), an external interrupt flag
(IRQF), and a flag reset bit (IRQR). Unused bits will read as logic zeros.
The ISCR also contains two control bits for the oscillators, external pin
oscillator, and internal low-power oscillator. Reset sets the IRQE and
OM2 bits; and clears all the other bits.
$000D
Read:
Write:
Reset:
Bit 7
IRQE
1
6
OM2
1
5
OM1
0
4
0
3
2
0
1
0
Bit 0
0
IRQF
R
0
IRQR
U
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 4-4. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
OM1 and OM2 — Oscillator Selects
These bits control the selection and enabling of the oscillator source
for the MCU. One choice is the internal low-power oscillator (LPO).
The other choice is the external pin oscillator (EPO) which is common
to most MC68HC05 MCU devices. The EPO uses external
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Interrupts
Inte rrup ts
components like filter capacitors and a crystal or ceramic resonator
and consumes more power. The selection and enable conditions for
these two oscillators are shown in Table 4-2.
Table 4-2. Oscillator Selection
Internal
Low-Power
Oscillator
(LPO)
External
Pin
Oscillator
(EPO)
Oscillator
Selected
by CPU
Power
Consumption
OM2 OM1
0
0
1
1
0
1
0
1
Internal
External
Internal
Internal
Enabled
Disabled
Enabled
Enabled
Disabled
Enabled
Disabled
Enabled
Lowest
Normal
Lowest
Normal
Therefore, the lowest power is consumed when OM1 is cleared. The
state with both OM1 and OM2 set is provided so that the EPO can be
started and allowed to stabilize while the LPO still clocks the MCU.
The reset state is for OM1 to be cleared and OM2 to be set, which
selects the LPO and disables the EPO.
IRQF — External Interrupt Request Flag
The IRQ flag is a clearable, read-only bit that is set when an external
interrupt request is pending. Writing to the IRQF bit has no effect.
Reset clears the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
The following conditions set the IRQ flag:
• An external interrupt signal on the IRQ/V pin
PP
• An external interrupt signal on pin PA0, PA1, PA2, or PA3
when the PA0–PA3 pins are enabled by the PIRQ bit in the
MOR to serve as external interrupt sources.
The following conditions clear the IRQ flag:
• When the CPU fetches the interrupt vector
• When a logic one is written to the IRQR bit
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MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Interrupts
MOTOROLA
Interrupts
Core Timer Interrupts
IRQR — Interrupt Request Reset
This write-only bit clears the IRQF flag bit and prevents redundant
execution of interrupt routines. Writing a logic one to IRQR clears the
IRQF. Writing a logic zero to IRQR has no effect. IRQR always reads
as a logic zero. Reset has no affect on IRQR.
1 = Clear IRQF flag bit
0 = No effect
4.7 Core Tim e r Inte rrup ts
The core timer can generate the following interrupts:
• Timer overflow interrupt
• Real-time interrupt
Setting the I bit in the condition code register disables core timer
interrupts. The controls and flags for these interrupts are in the core
timer status and control register (CTSCR) located at $0008.
4.7.1 Core Tim e r Ove rflow Inte rrup t
An overflow interrupt request occurs if the core timer overflow flag (TOF)
becomes set while the core timer overflow interrupt enable bit (TOFE) is
also set. The TOF flag bit can be reset by writing a logical one to the
CTOFR bit in the CTSCR or by a reset of the device.
4.7.2 Re a l-Tim e Inte rrup t
A real-time interrupt request occurs if the real-time interrupt flag (RTIF)
in the CTSCR becomes set while the real-time interrupt enable bit
(RTIE) is also set. The RTIF flag bit can be reset by writing a logical one
to the RTIFR bit in the CTSCR or by a reset of the device.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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Interrupts
Inte rrup ts
4.8 Prog ra m m a b le Tim e r Inte rrup ts
The 16-bit programmable timer can generate an interrupt whenever the
following events occur:
• Input capture
• Output compare
• Timer counter overflow
Setting the I bit in the condition code register disables timer interrupts.
The controls for these interrupts are in the timer control register (TCR)
located at $0012 and in the status bits in the timer status register (TSR)
located at $0013.
4.8.1 Inp ut Ca p ture Inte rrup t
An input capture interrupt occurs if the input capture flag (ICF) becomes
set while the input capture interrupt enable bit (ICIE) is also set. The ICF
flag bit is in the TSR, and the ICIE enable bit is located in the TCR. The
ICF flag bit is cleared by a read of the TSR with the ICF flag bit set, and
then followed by a read of the LSB of the input capture register (ICRL)
or by reset. The ICIE enable bit is unaffected by reset.
4.8.2 Outp ut Com p a re Inte rrup t
An output compare interrupt occurs if the output compare flag (OCF)
becomes set while the output compare interrupt enable bit (OCIE) is also
set. The OCF flag bit is in the TSR and the OCIE enable bit is in the TCR.
The OCF flag bit is cleared by a read of the TSR with the OCF flag bit
set, and then followed by an access to the LSB of the output compare
register (OCRL) or by reset. The OCIE enable bit is unaffected by reset.
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Interrupts
Interrupts
Serial Interrupts
4.8.3 Tim e r Ove rflow Inte rrup t
A timer overflow interrupt occurs if the timer overflow flag (TOF)
becomes set while the timer overflow interrupt enable bit (TOIE) is also
set. The TOF flag bit is in the TSR and the TOIE enable bit is in the TCR.
The TOF flag bit is cleared by a read of the TSR with the TOF flag bit set,
and then followed by an access to the LSB of the timer registers (TMRL)
or by reset. The TOIE enable bit is unaffected by reset.
4.9 Se ria l Inte rrup ts
The simple serial interface can generate the following interrupts:
• Receive sequence complete
• Transmit sequence complete
Setting the I bit in the condition code register disables serial interrupts.
The controls for these interrupts are in the serial control register (SCR)
located at $000A and in the status bits in the serial status register (SSR)
located at $000B.
A transfer complete interrupt occurs if the serial interrupt flag (SPIF)
becomes set while the serial interrupt enable bit (SPIE) is also set. The
SPIF flag bit is in the serial status register (SSR) located at $000B, and
the SPIE enable bit is located in the serial control register (SCR) located
at $000A. The SPIF flag bit is cleared by a read of the SSR with the SPIF
flag bit set, and then followed by a read or write to the serial data register
(SDR) located at $000C. The SPIF flag bit can also be reset by writing a
one to the SPIR bit in the SCR.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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Interrupts
Inte rrup ts
4.10 Ana log Inte rrup ts
The analog subsystem can generate the following interrupts:
• Voltage on positive input of comparator 1 is greater than the
voltage on the negative input of comparator 1
• Voltage on positive input of comparator 2 is greater than the
voltage on the negative input of comparator 2
• Trigger of the input capture interrupt from the programmable timer
as described in 4.8.1 Input Capture Interrupt.
Setting the I bit in the condition code register disables analog subsystem
interrupts. The controls for these interrupts are in the analog subsystem
control register (ACR) located at $001D, and the status bits are in the
analog subsystem status register (ASR) located at $001E.
4.10.1 Com p a ra tor Inp ut Ma tc h Inte rrup t
A comparator input match interrupt occurs if either compare flag bit
(CPF1 or CPF2) in the ASR becomes set while the comparator interrupt
enable bit (CPIE) in the ACR is also set. The CPF1 and CPF2 flag bits
can be reset by writing a one to the corresponding CPFR1 or CPFR2 bits
in the ASR. Reset clears these bits.
4.10.2 Inp ut Ca p ture Inte rrup t
The analog subsystem can also generate an input capture interrupt
through the 16-bit programmable timer. The input capture can be
triggered when there is a match in the input conditions for the voltage
comparator 2. If comparator 2 sets the CP2F flag bit in the ASR and the
input capture enable (ICEN) in the ACR is set, then an input capture will
be performed by the programmable timer. If the ICIE enable bit in the
TCR is also set, then an input compare interrupt will occur. Reset clears
these bits.
NOTE: For the analog subsystem to generate an interrupt using the input
capture function of the programmable timer, the ICEN enable bit in the
ACR, and the ICIE and IEDG bits in the TCR must all be set.
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Interrupts
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 5. Re se ts
5.1 Conte nts
5.2
5.3
5.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.5
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Computer Operating Properly (COP) Reset . . . . . . . . . . . .62
Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . .64
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.5.1
5.5.2
5.5.3
5.5.4
5.6
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . .66
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
External Oscillator and Internal
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . .67
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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General Release Specification
59
Resets
Re se ts
5.2 Introd uc tion
This section describes the five reset sources and how they initialize the
MCU. A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user defined reset vector address. The following conditions
produce a reset:
• Initial power-up of device (power-on reset)
• A logic zero applied to the RESET pin (external reset)
• Timeout of the COP watchdog (COP reset)
• Low voltage applied to the device (LVR reset)
• Fetch of an opcode from an address not in the memory map
(illegal address reset)
Figure 5-1 shows a block diagram of the reset sources and their
interaction.
MASK OPTION REGISTER ($1FF1)
INTERNAL DATA BUS
COP WATCHDOG
LOW-VOLTAGE RESET
POWER-ON RESET
V
DD
ILLEGAL ADDRESS RESET
INTERNAL
ADDRESS BUS
S
TO CPU
RST
RESET
D
AND
RESET
LATCH
SUBSYSTEMS
R
3-CYCLE
CLOCKED
1-SHOT
INTERNAL
CLOCK
Figure 5-1. Reset Sources
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Resets
Resets
Power-On Reset
5.3 Powe r-On Re se t
A positive transition on the V pin generates a power-on reset. The
DD
power-on reset is strictly for conditions during powering up and cannot
be used to detect drops in power supply voltage.
A delay of 16 or 4064 internal bus cycles (t
) after the oscillator
CYC
becomes active allows the clock generator to stabilize. If the RESET pin
is at logic zero at the end of this multiple t time, the MCU remains in
CYC
the reset condition until the signal on the RESET pin goes to a logic one.
5.4 Exte rna l Re se t
A logic zero applied to the RESET pin for a minimum of one and one half
t
generates an external reset. This pin is connected to a Schmitt
cyc
trigger input gate to provide an upper and lower threshold voltage
separated by a minimum amount of hysteresis. The external reset
occurs whenever the RESET pin is pulled below the lower threshold and
remains in reset until the RESET pin rises above the upper threshold.
This active low input will generate the internal RST signal that resets the
CPU and peripherals.
The RESET pin can also be pulled to a low state by an internal pulldown
device that is activated by three internal reset sources. This RESET
pulldown device will only be asserted for three to four cycles of the
internal bus or as long as the internal reset source is asserted.
NOTE: Do not connect the RESET pin directly to V , as this may overload
DD
some power supply designs if the internal pulldown on the RESET pin
should activate. If an external reset function is not required, the RESET
pin should be left unconnected.
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Resets
Re se ts
5.5 Inte rna l Re se ts
The four internally generated resets are the initial power-on reset
function, the COP watchdog timer reset, the low-voltage reset, and the
illegal address detector. Only the COP watchdog timer reset, low-
voltage reset, and illegal address detector will also assert the pulldown
device on the RESET pin for the duration of the reset function or for three
to four internal bus cycles, whichever is longer.
5.5.1 Powe r-On Re se t (POR)
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out); that
function can be performed by the LVR. Depending on the DELAY bit in
the mask option register (MOR), there is an oscillator stabilization delay
of 16 or 4064 internal bus cycles after the LPO becomes active.
The POR will generate the RST signal which will reset the CPU. If any
other reset function is active at the end of the 16 or 4064 cycle delay, the
RST signal will remain in the reset condition until the other reset
condition(s) end.
POR will not activate the pulldown device on the RESET pin. V must
DD
drop below V
for the internal POR circuit to detect the next rise of
POR
V .
DD
5.5.2 Com p ute r Op e ra ting Prop e rly (COP) Re se t
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic zero to the COPC bit
of the COP register at location $1FF0. The COP register, shown in
Figure 5-2, is a write-only register that returns the contents of EPROM
location $1FF0 when read.
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MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Resets
Resets
Internal Resets
$1FF0
Read:
Write:
Reset:
Bit 7
EPMSEC
U
6
OPT
U
5
4
3
2
1
Bit 0
COPC
U
U
U
U
U
U
= Unimplemented
U = Unaffected
Figure 5-2. COP and Security Register (COPR)
1
EPMSEC — EPROM Security
The EPMSEC bit is a write-only security bit to protect the contents of
the user EPROM code stored in locations $0700–$1FFF.
OPT — Optional Features
The OPT bit enables two additional features: direct drive by
comparator 1 output to PB4; and voltage offset capability to sample
capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic zero to COPC
prevents the COP watchdog from resetting the MCU. Reset clears the
COPC bit.
1 = No effect on COP watchdog timer
0 = Reset COP watchdog timer
The COP watchdog reset will assert the pulldown device to pull the
RESET pin low for three to four cycles of the internal bus.
The COP watchdog reset function can be enabled or disabled by
programming the COPEN bit in the MOR.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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General Release Specification
63
Resets
Re se ts
5.5.3 Low-Volta g e Re se t (LVR)
The LVR activates the RST reset signal to reset the device when the
voltage on the V pin falls below the LVR trip voltage. The LVR will
DD
assert the pulldown device to pull the RESET pin low for three to four
cycles of the internal bus.
The LVR reset function can be enabled or disabled by programming the
LVREN bit in the MOR.
NOTE: The LVR is intended for applications where the V supply voltage
DD
normally operates above 4.5 volts.
5.5.4 Ille g a l Ad d re ss Re se t
An opcode fetch (execution of an instruction) at an address that is not in
the EPROM (locations $0700–$1FFF) or the RAM (locations
$0020–$00FF) generates an illegal address reset. The illegal address
reset will assert the pulldown device to pull the RESET pin low for three
to four cycles of the internal bus.
5.6 Re se t Sta te s
The following paragraphs describe how the various resets initialize the
MCU.
5.6.1 CPU
A reset has the following effects on the CPU:
• Loads the stack pointer with $FF
• Sets the I bit in the condition code register, inhibiting interrupts
• Loads the program counter with the user defined reset vector from
locations $1FFE and $1FFF
• Clears the stop latch, enabling the CPU clock
• Clears the wait latch, bringing the CPU out of the wait mode
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MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Resets
Resets
Reset States
5.6.2 I/ O Re g iste rs
A reset has the following effects on I/O registers:
• Clears bits in data direction registers configuring pins as inputs:
– DDRA5–DDRA0 in DDRA for port A
– DDRB7–DDRB0 in DDRA for port B
– DDRC7–DDRC0 in DDRC for port C*
• Clears bits in pulldown inhibit registers to enable pulldown
devices:
– PDIA5–PDIA0 in PDRA for port A
– PDIB7–PDIB0 in PDRB for port B
– PDICH and PDICL in PDRA for port C*
• Has no effect on port A, B, or C* data registers
• Sets the IRQE bit in the interrupt status and control register (ISCR)
5.6.3 Core Tim e r
A reset has the following effects on the core timer:
• Clears the core timer counter register (CTCR)
• Clears the core timer interrupt flag and enable bits in the core timer
status and control register (CTSCR)
• Sets the real-time interrupt rate selection bits (RT0 and RT1) such
that the device will start with the longest real-time interrupt and
longest COP timeout delays
5.6.4 COP Wa tc hd og
A reset clears the COP watchdog timeout counter.
*Features related to Port C are only available on the 28-pin MC68HC705JP7 devices
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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General Release Specification
65
Resets
Re se ts
5.6.5 16-Bit Prog ra m m a b le Tim e r
A reset has the following effects on the 16-bit programmable timer:
• Initializes the timer counter registers (TMRH and TMRL) to a value
of $FFFC
• Initializes the alternate timer counter registers (ACRH and ACRL)
to a value of $FFFC
• Clears all the interrupt enables and the output level bit (OLVL) in
the timer control register (TCR)
• Does not affect the input capture edge bit (IEDG) in the TCR
• Does not affect the interrupt flags in the timer status register (TSR)
• Does not affect the input capture registers (ICRH and ICRL)
• Does not affect the output compare registers (OCRH and OCRL)
5.6.6 Se ria l Inte rfa c e
A reset has the following effects on the serial interface:
• Clears all bits in the SIOP control register (SCR)
• Clears all bits in the SIOP status register (SSR)
• Does not affect the contents of the SIOP data register (SDR)
A reset, therefore, disables the SIOP and leaves the shared port B pins
as general I/O. Any pending interrupt flag is cleared and the SIOP
interrupt is disabled. Also the baud rate defaults to the slowest rate.
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MOTOROLA
Resets
Resets
Reset States
5.6.7 Ana log Sub syste m
A reset has the following effects on the analog subsystem:
• Clears all the bits in the multiplex register (AMUX) bits except the
hold switch bit (HOLD) which is set
• Clears all the bits in the analog control register (ACR)
• Clears all the bits in the analog status register (ASR)
A reset, therefore, connects the negative input of comparator 2 to the
channel selection bus, which is switched to V . Both comparators are
SS
set up as non-inverting (a higher positive voltage on the positive input
results in a positive output) and both are powered down. The current
source and discharge device on the PB0/AN0 pin is disabled and
powered down. Any analog subsystem interrupt flags are cleared and
the analog interrupt is disabled. Direct drive by comparator 1 to the PB4
pin and the voltage offset to the sample capacitor are disabled (if both
are enabled by the OPT bit being set in the MOR).
5.6.8 Exte rna l Osc illa tor a nd Inte rna l Low-Powe r Osc illa tor
A reset presets the oscillator select bits (OM1 and OM2) in the interrupt
status and control register (ISCR) such that the device runs from the
internal oscillator (OM1 = 0, OM2 = 1) which has the following effects on
the oscillators:
• The internal low-power oscillator is enabled and selected
• The external oscillator is disabled
• The CPU bus clock is driven from the internal low-power oscillator
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
67
Resets
Re se ts
General Release Specification
68
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Resets
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 6. Op e ra ting Mod e s
6.1 Conte nts
6.2
6.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Oscillator Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.4
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.4.1
6.4.2
6.4.3
6.4.4
6.2 Introd uc tion
This section describes the operation of the device with respect to the
oscillator source and the low-power modes:
• Stop mode
• Wait mode
• Halt mode
• Data-retention mode
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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General Release Specification
69
Operating Modes
Op e ra ting Mod e s
6.3 Osc illa tor Sourc e
The MCU can be clocked by either an internal low-power oscillator
(LPO) without external components or by an external pin oscillator
(EPO) which uses external components. The enable and selection of the
clock source is determined by the state of the oscillator select bits (OM1
and OM2) in the interrupt status and control register (ISCR) as shown in
Figure 6-1.
$000D
Read:
Write:
Reset:
Bit 7
IRQE
1
6
OM2
1
5
OM1
0
4
0
3
2
0
1
0
Bit 0
0
IRQF
R
0
IRQR
0
0
0
0
= Unimplemented
= Reserved
R
Figure 6-1. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable
This read/write bit enables external interrupts. Refer to Section 4.
Interrupts for more details.
OM1 and OM2 — Oscillator Selects
These bits control the selection and enabling of the oscillator source
for the MCU. One choice is the internal LPO and the other oscillator
is the EPO which is common to most MC68HC05 MCU devices. The
EPO uses external components like filter capacitors and a crystal or
ceramic resonator and consumes more power than the LPO. The
selection and enable conditions for these two oscillators are shown in
Table 6-1. Reset clears OM1 and sets OM2, which selects the LPO
and disables the EPO.
.
Table 6-1. Oscillator Selection
External
Internal
Oscillator
Selected
Pin
Power
OM2 OM1
Low-Power
Oscillator Consumption
(EPO)
Oscillator (LPO)
0
0
1
1
0
1
0
1
Internal
External
Internal
Internal
Enabled
Disabled
Enabled
Enabled
Disabled
Enabled
Disabled
Enabled
Lowest
Normal
Lowest
Normal
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Operating Modes
Operating Modes
Low-Power Modes
Therefore, the lowest power is consumed when OM1 is cleared. The
state with both OM1 and OM2 set is provided so that the EPO can be
started up and allowed to stabilize while the LPO still clocks the MCU.
NOTE: When switching from LPO to EPO, the user must be careful to ensure
that the EPO has been enabled and powered up long enough to stabilize
before shifting clock sources.
IRQF — External Interrupt Request Flag
The IRQF flag is a clearable, read-only bit that is set when an external
interrupt request is pending. Refer to Section 4. Interrupts for more
details.
IRQR — Interrupt Request Reset
This write-only bit clears the IRQF flag bit and prevents redundant
execution of interrupt routines. Refer to Section 4. Interrupts for
more details.
6.4 Low-Powe r Mod e s
Four modes of operation reduce power consumption:
• Stop mode
• Wait mode
• Halt mode
• Data-retention mode
Figure 6-2 shows the sequence of events in stop, wait, and halt modes.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
71
Operating Modes
Op e ra ting Mod e s
STOP
HALT
WAIT
YES
SWAIT BIT
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
TURN OFF CPU CLOCK.
KEEP OTHER MODULE
CLOCKS ACTIVE.
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
TURN OFF CPU CLOCK.
KEEP OTHER MODULE
CLOCKS ACTIVE.
IN MOR SET?
NO
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
CLEAR CTOF, RTIF, CTOFE, AND RTIE BITS IN TSCR.
CLEAR ICF, OCF, AND TOF BITS IN TSR.
CLEAR ICIE, OCIE, AND TOIE BITS IN TCR.
DISABLE EXTERNAL PIN OSCILLATOR.
YES
YES
EXTERNAL
RESET?
EXTERNAL
RESET?
TURN OFF INTERNAL LOW-POWER OSCILLATOR.
NO
NO
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
EXTERNAL
EXTERNAL
EXTERNAL
INTERRUPT?
INTERRUPT?
RESET?
NO
NO
NO
CORE
TIMER
INTERRUPT?
CORE
TIMER
INTERRUPT?
YES
EXTERNAL
INTERRUPT?
NO
NO
NO
PROG.
TIMER
INTERRUPT?
PROG.
TIMER
INTERRUPT?
TURN ON SELECTED OSCILLATOR.
RESET STABILIZATION DELAY TIMER.
NO
NO
SIOP
INTERRUPT?
SIOP
INTERRUPT?
NO
NO
YES
END OF
STABILIZATION
DELAY?
ANALOG
INTERRUPT?
ANALOG
INTERRUPT?
NO
NO
NO
COP
RESET?
COP
RESET?
TURN ON CPU CLOCK.
NO
NO
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT.
a. SAVE CPU REGISTERS ON STACK.
b. SET I BIT IN CCR.
c. LOAD PC WITH INTERRUPT VECTOR.
Figure 6-2. Stop/Wait/Halt Flowchart
General Release Specification
72
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Operating Modes
Operating Modes
Low-Power Modes
6.4.1 Stop Mod e
The STOP instruction puts the MCU in a mode with the lowest power
consumption and affects the MCU as follows:
• Turns off the CPU clock and all internal clocks by stopping both
the external pin oscillator and the internal low-power oscillator.
The selection of the oscillator by the OM1 and OM2 bits in the
ISCR is not affected. The stopped clocks turn off the COP
watchdog, the core timer, the programmable timer, the analog
subsystem, and the SIOP.
• Removes any pending core timer interrupts by clearing the core
timer interrupt flags (CTOF and RTIF) in the core timer status and
control register (CTSCR)
• Disables any further core timer interrupts by clearing the core
timer interrupt enable bits (CTOFE and RTIE) in the CTSCR
• Removes any pending programmable timer interrupts by clearing
the timer interrupt flags (ICF, OCF, and TOF) in the timer status
register (TSR).
• Disables any further programmable timer interrupts by clearing the
timer interrupt enable bits (ICIE, OCIE, and TOIE) in the timer
control register (TCR).
• Enables external interrupts via the IRQ/V pin by setting the
PP
IRQE bit in the IRQ status and control register (ISCR). External
interrupts are also enabled via the PA0 through PA3 pins, if the
port A interrupts are enabled by the PIRQ bit in the mask option
register (MOR).
• Enables interrupts in general by clearing the I bit in the condition
code register
The STOP instruction does not affect any other bits, registers, or I/O
lines.
The following conditions bring the MCU out of stop mode:
• An external interrupt signal on the IRQ/V pin — A high-to-low
PP
transition on the IRQ/V pin loads the program counter with the
PP
contents of locations $1FFA and $1FFB.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
73
Operating Modes
Op e ra ting Mod e s
• An external interrupt signal on a port A external interrupt pin — If
selected by the PIRQ bit in the MOR, a low-to-high transition on a
PA3–PA0 pin loads the program counter with the contents of
locations $1FFA and $1FFB.
• External reset — A logic zero on the RESET pin resets the MCU
and loads the program counter with the contents of locations
$1FFE and $1FFF.
When the MCU exits stop mode, processing resumes after a
stabilization delay of 16 or 4064 internal bus cycles, depending on the
state of the DELAY bit in the MOR.
NOTE: Execution of the STOP instruction without setting the SWAIT bit in the
MOR will cause the oscillators to stop, and, therefore, disable the COP
watchdog timer. If the COP watchdog timer is to be used, stop mode
should be changed to halt mode as described in 6.4.3 Halt Mode.
6.4.2 Wa it Mod e
The WAIT instruction puts the MCU in a low-power wait mode which
consumes more power than the stop mode and affects the MCU as
follows:
• Enables interrupts by clearing the I bit in the condition code
register
• Enables external interrupts by setting the IRQE bit in the IRQ
status and control register
• Stops the CPU clock which drives the address and data buses, but
allows the selected oscillator to continue to clock the core timer,
programmable timer, analog subsystem, and SIOP
The WAIT instruction does not affect any other bits, registers, or I/O
lines.
General Release Specification
74
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Operating Modes
Operating Modes
Low-Power Modes
The following conditions restart the CPU bus clock and bring the MCU
out of wait mode:
• An external interrupt signal on the IRQ/V pin — A high-to-low
PP
transition on the IRQ/V pin loads the program counter with the
PP
contents of locations $1FFA and $1FFB.
• An external interrupt signal on a port A external interrupt pin — If
selected by PIRQ bit in the MOR, a low-to-high transition on a
PA3–PA0 pin loads the program counter with the contents of
locations $1FFA and $1FFB.
• A core timer interrupt — A core timer overflow or a real-time
interrupt loads the program counter with the contents of locations
$1FF8 and $1FF9.
• A programmable timer interrupt — A programmable timer interrupt
driven by an input capture, output compare, or timer overflow
loads the program counter with the contents of locations $1FF6
and $1FF7.
• An SIOP interrupt — An SIOP interrupt driven by the completion
of transmitted or received 8-bit data loads the program counter
with the contents of locations $1FF4 and $1FF5.
• An analog subsystem interrupt — An analog subsystem interrupt
driven by a voltage comparison loads the program counter with
the contents of locations $1FF2 and $1FF3.
• A COP watchdog reset — A timeout of the COP watchdog resets
the MCU and loads the program counter with the contents of
locations $1FFE and $1FFF. Software can enable real time
interrupts so that the MCU can periodically exit the wait mode to
reset the COP watchdog.
• An external reset — A logic zero on the RESET pin resets the
MCU and loads the program counter with the contents of locations
$1FFE and $1FFF.
When the MCU exits the wait mode there is no delay before code
executes like occurs when exiting the stop or halt modes.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
75
Operating Modes
Op e ra ting Mod e s
6.4.3 Ha lt Mod e
The STOP instruction puts the MCU in halt mode if selected by the
SWAIT bit in the MOR. Halt mode is identical to wait mode, except that
a variable recovery delay occurs when the MCU exits halt mode. A
recovery time of from 1 to 16 or from 1 to 4064 internal bus cycles can
be selected by the DELAY bit in the MOR.
If the SWAIT bit is set in the MOR to put the MCU in halt mode, the COP
watchdog cannot be turned off inadvertently by a STOP instruction.
6.4.4 Da ta -Re te ntion Mod e
In the data-retention mode, the MCU retains RAM contents and CPU
register contents at V voltages as low as 2.0 Vdc. The data retention
DD
feature allows the MCU to remain in a low-power consumption state
during which it retains data, but the CPU cannot execute instructions.
To put the MCU in the data retention mode:
1. Drive the RESET pin to a logic zero.
2. Lower the V voltage. The RESET pin must remain low
DD
continuously during data retention mode.
To take the MCU out of the data retention mode:
1. Return V to normal operating voltage.
DD
2. Return the RESET pin to a logic one.
General Release Specification
76
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Operating Modes
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 7. Pa ra lle l Inp ut/ Outp ut
7.1 Conte nts
7.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . .79
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .80
Pulldown Register A (PDRA). . . . . . . . . . . . . . . . . . . . . . . .81
Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .82
Port A Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . .84
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .85
Pulldown Register B (PDRB). . . . . . . . . . . . . . . . . . . . . . . .86
Port B Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
PB0, PBI, PB2 and PB3 Logic. . . . . . . . . . . . . . . . . . . . . . .87
PB4/AN4/TCMP/CMP1 Logic . . . . . . . . . . . . . . . . . . . . . . .89
PB5/SDO Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
PB6/SDI Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
PB7/SCK Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.5
Port C (28-Pin Versions Only) . . . . . . . . . . . . . . . . . . . . . . . . .99
Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . .99
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . .100
Port C Pulldown Devices. . . . . . . . . . . . . . . . . . . . . . . . . .100
Port C Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
7.5.1
7.5.2
7.5.3
7.5.4
7.6
Port Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
77
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
7.2 Introd uc tion
The MC68HC705JJ7 has 14 bidirectional I/O pins which form two
parallel I/O ports, A and B. The MC68HC705JP7 has 22 bidirectional I/O
pins which form three parallel I/O ports, A, B and C. Each I/O pin is
programmable as an input or an output. The contents of the data
direction registers determine the data direction of each of the I/O pins.
All I/O pins have software programmable pulldown devices which can be
enabled or disabled globally by the SWPDI bit in the mask option register
(MOR).
7.3 Port A
Port A is a 6-bit, general-purpose bidirectional I/O port with these
features:
• Individual programmable pulldown devices
• High current sinking capability on all port A pins, with a maximum
total for port A
• High current sourcing capability on all port A pins, with a maximum
total for port A
• External interrupt capability (pins PA3–PA0)
General Release Specification
78
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Parallel Input/Output
Parallel Input/Output
Port A
7.3.1 Port A Da ta Re g iste r (PORTA)
The port A data register contains a bit for each of the port A pins. When
a port A pin is programmed to be an output, the state of its data register
bit determines the state of the output pin. When a port A pin is
programmed to be an input, reading the port A data register returns the
logic state of the pin. The upper two bits of the port A data register will
always read as logical zeros.
$0000
Read:
Bit 7
0
6
0
5
4
3
2
1
Bit 0
PA0
PA5
PA4
PA3
PA2
PA1
Write:
Reset:
Unaffected by Reset
KYBD3 KYBD2 KYBD1 KYBD0
Alternate:
= Unimplemented
Figure 7-1. Port A Data Register (PORTA)
PA5–PA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in the port A data
direction register (DDRA). Reset has no effect on port A data.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
79
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
7.3.2 Da ta Dire c tion Re g iste r A (DDRA)
The contents of the port A data direction register (DDRA) determine
whether each port A pin is an input or an output. Writing a logic one to a
DDRA bit enables the output buffer for the associated port A pin. A
DDRA bit set to a logic one also disables the pulldown device for that pin.
Writing a logic zero to a DDRA bit disables the output buffer for the
associated port A pin. The upper two bits always read as logical zeros.
A reset initializes all DDRA bits to logic zeros, configuring all port A pins
as inputs and disabling the voltage comparators from driving PA4 or
PA5.
$0004
Read:
Write:
Reset:
Bit 7
0
6
0
5
4
3
2
1
Bit 0
DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-2. Data Direction Register A (DDRA)
DDRA5–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears the
DDRA5–DDRA0 bits.
1 = Corresponding port A pin configured as output and pulldown
device disabled
0 = Corresponding port A pin configured as input
General Release Specification
80
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Parallel Input/Output
MOTOROLA
Parallel Input/Output
Port A
7.3.3 Pulld own Re g iste r A (PDRA)
All port A pins can have software programmable pulldown devices
enabled or disabled globally by SWPDI bit in the MOR. These pulldown
devices are controlled by the write-only pulldown register A (PDRA)
shown in Figure 7-3. Clearing the PDIA5–PDIA0 bits in the PDRA turns
on the pulldown devices if the port A pin is an input. Reading the PDRA
returns undefined results since it is a write-only register, therefore do not
change the value in PDRA with read/modify/write instructions. On the
MC68HC705JP7 the PDRA contains two pulldown control bits (PDICH
and PDICL) for port C. Reset clears the PDIA5–PDIA0, PDICH and
PDICL bits, which turns on all the port A and port C pulldown devices.
$0010
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write: PDICH
Reset:
PDICL
0
PDIA5
0
PDIA4
0
PDIA3
0
PDIA2
0
PDIA1
0
PDIA0
0
0
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA)
PDICH — Upper Port C Pulldown Inhibit Bits (MC68HC705JP7)
Writing to this write-only bit controls the port C pulldown devices on
the upper four bits (PC4:7). Reading these pulldown register A bits
returns undefined data. Reset clears bit PDICH.
1 = Upper four port C pins pulldown devices turned off
0 = Upper four port C pins pulldown devices turned on if pin has
been programmed by the DDRC to be an input
PDICL — Lower Port C Pulldown Inhibit Bits (MC68HC705JP7)
Writing to this write-only bit controls the port C pulldown devices on
the lower four bits (PC0:3). Reading these pulldown register A bits
returns undefined data. Reset clears bit PDICL.
1 = Lower four port C pins pulldown devices turned off
0 = Lower four port C pins pulldown devices turned on if pin has
been programmed by the DDRC to be an input
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
81
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
PDIA5–PDIA0 — Port A Pulldown Inhibit Bits
Writing to these write-only bits controls the port A pulldown devices.
Reading these pulldown register A bits returns undefined data. Reset
clears bits PDIA5–PDIA0.
1 = Corresponding port A pin pulldown device turned off
0 = Corresponding port A pin pulldown device turned on if pin has
been programmed by the DDRA to be an input
7.3.4 Port A Exte rna l Inte rrup ts
The PIRQ bit in the MOR enables the PA3–PA0 pins to serve as external
interrupt pins in addition to the IRQ/V pin. The active interrupt state for
PP
the PA3–PA0 pins is a logic one or a rising edge. A state of the PIRQ bit
in the MOR determines whether external interrupt inputs are edge-
sensitive only or both edge- and level-sensitive. Port A interrupts are
also interactive with each other and the IRQ/VPP pin as described in
4.6 External Interrupts.
NOTE: When testing for external interrupts, the BIH and BIL instructions test the
voltage on the IRQ/V pin, not the state of the internal IRQ signal.
PP
Therefore, BIH and BIL cannot test the port A external interrupt pins.
7.3.5 Port A Log ic
When a PA0:PA5 pin is programmed as an output, reading the port bit
actually reads the value of the data latch and not the voltage on the pin
itself. When a PA0:PA5 pin is programmed as an input, reading the port
bit reads the voltage level on the pin. The data latch can always be
written, regardless of the state of its DDR bit. Figure 7-4 shows the I/O
logic of PA0:PA5 pins of port A.
The data latch can always be written, regardless of the state of its DDR
bits. Table 7-1 summarizes the operations of the port A pins.
General Release Specification
82
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Parallel Input/Output
Parallel Input/Output
Port A
EXTERNAL
INTERRUPT
REQUEST
(PA0:3)
READ $0004
WRITE $0004
DATA DIRECTION
REGISTER A
BIT DDRAx
R
PORT A DATA
REGISTER
BIT PAx
WRITE $0000
PAx
HIGH SINK/SOURCE
CURRENT
CAPABILITY
READ $0000
WRITE $0010
PULLDOWN
REGISTER A
BIT PDIAx
PULLDOWN
DEVICE
R
RESET
MASK OPTION REGISTER ($1FF1)
Figure 7-4. Port A I/O Circuit
Table 7-1. Port A Pin Functions
PORTA Access
Port A
Result on
Port A
Pin(s)
SWPDI
(in MOR)
(Pin or Data Register)
Port A Pins
PDIAx
DDRAx*
Read
Write
Pulldown
Pin
PA0
PA1
PA2
PA3
PA4
PA5
0
0
1
X
0
0
Pin
Data
On
Off
Off
Off
PAx In
1
X
X
0
0
1
Pin
Pin
Data
Data
Data
PAx In
PAx In
Data
PAx Out
* DDRA can always be read or written.
X = Don’t care
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
83
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
7.4 Port B
Port B is an 8-bit, general-purpose bidirectional I/O port with the
following features:
• Programmable pulldown devices
• PB0–PB4 are shared with the analog subsystem
• PB3 and PB4 are shared with the 16-bit programmable timer
• PB4 can be driven directly by the output of comparator 1
• PB5–PB7 are shared with the simple serial interface (SIOP)
• High current sinking capability on the PB4 pin
• High current sourcing capability on the PB4 pin
7.4.1 Port B Da ta Re g iste r (PORTB)
The port B data register contains a bit for each of the port B pins. When
a port B pin is programmed to be an output, the state of its data register
bit determines the state of the output pin. When a port B pin is
programmed to be an input, reading the port B data register returns the
logic state of the pin. Reset has no effect on port B data.
$0001
Read:
Bit 7
PB7
6
5
4
3
2
1
Bit 0
PB0
PB6
PB5
PB4
PB3
PB2
PB1
Write:
Reset:
Unaffected by Reset
Alternate:
Alternate:
Alternate:
SCK
SCK
SCK
SDI
SDI
SDI
SDO
SDO
SDO
AN4
AN3
TCAP
TCAP
AN2
AN2
AN2
AN1
AN1
AN1
AN0
AN0
AN0
TCMP
CMP1
Figure 7-5. Port B Data Register (PORTB)
PB0-PB7 — Port B Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register B. Reset has no effect on port B data.
General Release Specification
84
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Parallel Input/Output
MOTOROLA
Parallel Input/Output
Port B
7.4.2 Da ta Dire c tion Re g iste r B (DDRB)
The contents of the port B data direction register (DDRB) determine
whether each port B pin is an input or an output. Writing a logic one to a
DDRB bit enables the output buffer for the associated port B pin. A
DDRB bit set to a logic one also disables the pulldown device for that pin.
Writing a logic zero to a DDRB bit disables the output buffer for the
associated port B pin. A reset initializes all DDRB bits to logic zeros,
configuring all port B pins as inputs.
$0005
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
0
0
0
0
0
0
0
0
Figure 7-6. Data Direction Register B (DDRB)
DDRB7–DDRB0 — Port B Data Direction Bits
These read/write bits control port B data direction. Reset clears the
bits DDRB7–DDRB0.
1 = Corresponding port B pin configured as output and pulldown
device disabled
0 = Corresponding port B pin configured as input
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
85
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
7.4.3 Pulld own Re g iste r B (PDRB)
All port B pins can have software programmable pulldown devices
enabled or disabled globally by the SWPDI bit in the MOR. These
pulldown devices are individually controlled by the write-only pulldown
register B (PDRB) shown in Figure 7-7. Clearing the PDIB7–PDIB0 bits
in the PDRB turns on the pulldown devices if the port B pin is an input.
Reading the PDRB returns undefined results since it is a write-only
register. Reset clears the PDIB7–PDIB0 bits, which turns on all the port
B pulldown devices.
$0011
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PDIB7
0
PDIB6
0
PDIB5
0
PDIB4
0
PDIB3
0
PDIB2
0
PDIB1
0
DIB0
0
= Unimplemented
Figure 7-7. Pulldown Register B (PDRB)
PDIB7–PDIB0 — Port B Pulldown Inhibit Bits
Writing to these write-only bits controls the port B pulldown devices.
Reading these pulldown register B bits returns undefined data. Reset
clears bits PDIB7–PDIB0.
1 = Corresponding port B pin pulldown device turned off
0 = Corresponding port B pin pulldown device turned on if pin has
been programmed by the DDRB to be an input
7.4.4 Port B Log ic
All port B pins have the general I/O port logic similar to port A; but they
also share this function with inputs or outputs from other modules, which
are also attached to the pin itself or override the general I/O function.
PB0, PB1, PB2, and PB3 simply share their inputs with another module.
PB4, PB5, PB6, and PB7 will have their operation altered by outputs or
controls from other modules.
General Release Specification
86
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Parallel Input/Output
Parallel Input/Output
Port B
7.4.5 PB0, PBI, PB2 a nd PB3 Log ic
The typical I/O logic shown in Figure 7-8 is used for PB0, PB1, PB2, and
PB3 pins of port B. When these port B pins are programmed as an
output, reading the port bit actually reads the value of the data latch and
not the voltage on the pin itself. When these port B pins are programmed
as an input, reading the port bit reads the voltage level on the pin. The
data latch can always be written, regardless of the state of its DDRB bit.
The operations of the PB0:3 pins are summarized in Table 7-2.
READ $0005
WRITE $0005
ANALOG SUBSYSTEM,
AND PROGRAMMABLE
TIMER INPUT CAPTURE
(PINS PB0, PB1, PB2, PB3)
DATA DIRECTION
REGISTER B
BIT DDRBx
R
PORT BDATA
REGISTER
BIT PBx
WRITE $0001
PBx
READ $0001
WRITE $0011
PULLDOWN
REGISTER B
BIT PDIBx
PULLDOWN
DEVICE
R
RESET
MASK OPTION REGISTER ($1FF1)
Figure 7-8. PB0:3 Pin I/O Circuit
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
87
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
The PB0:3 pins share their inputs with another module. When using the
other attached module, the following conditions must be observed:
1. If the DDRB configures the pin as an output, then the port data
register can provide an output which may conflict with any external
input source to the other module. The pulldown device will be
disabled in this case.
2. If the DDRB configures the pin as an input, then reading the port
data register will return the state of the input in terms of the digital
threshold for that pin (analog inputs will default to logic states).
3. If DDRB configures the pin as an input and the pulldown device is
activated for a pin, it will also load the input to the other module.
4. If interaction between the port logic and the other module is not
desired, the pin should be configured as an input by clearing the
appropriate DDRB bit. The input pulldown device is disabled by
clearing the appropriate PDRB bit (or by disabling programmable
pulldowns with the SWPDI bit in the MOR).
General Release Specification
88
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Parallel Input/Output
Parallel Input/Output
Port B
7.4.6 PB4/ AN4/ TCMP/ CMP1 Log ic
The PB4/AN4/TCMP/CMP1 pin can be used as a simple I/O port pin, be
controlled by the OLVL bit from the output compare function of the 16-bit
programmable timer, or be controlled directly by the output of
comparator 1 as shown in Figure 7-9. The PB4 data, the programmable
timer OLVL bit, and the output of comparator 1 are all logically ORed
together to drive the pin. Also, the analog subsystem input channel 4
multiplexer is connected directly to this pin. The operations of PB4 pin
are summarized in Table 7-2.
ANALOG SUBSYSTEM
INPUT AN4 AND
TIMER OUTPUT COMPARE
READ $0005
WRITE $0005
DATA DIRECTION
REGISTER B
BIT DDRB4
R
PORT BDATA
REGISTER
BIT PB4
WRITE $0001
PB4
AN4
TCMP
HIGH SINK/
SOURCE CURRENT
CAPABILITY
OLVL
(TIMER OUTPUT COMPARE)
CMP1
(COMPARATOR 1 OUT)
READ $0001
WRITE $0011
PULLDOWN
REGISTER B
BIT PDIB4
PULLDOWN
DEVICE
R
RESET
MASK OPTION REGISTER ($1FF1)
MASK OPTION REGISTER ($1FF0)
Figure 7-9. PB4/AN4/TCMP/CMP1 Pin I/O Circuit
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
89
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
When using the PB4/AN4/TCMP/CMP1 pin, the following interactions
must be noted:
1. If the OLVL timer output compare function is the required output
function, then the DDRB4 bit must be set, the PB4 data bit must
be cleared and the OPT bit in the MOR must be cleared. The
PB4/AN4/TCMP/CMP1 pin becomes an output which follows the
state of the OLVL bit. The pulldown device will be disabled in this
case. The analog subsystem would not normally use this pin as an
analog input in this case.
2. If the PB4 data bit is the required output function, then the DDRB4
bit must be set, the OLVL bit in the TCR must be cleared and the
OPT bit in the MOR must be cleared. The pulldown device will be
disabled in this case. The analog subsystem would not normally
use this pin as an analog input in this case.
3. If the comparator 1 output is the desired output function then the
PB4 data bit must be cleared, the DDRB4 bit must be set, the
OLVL bit in the TCR must be cleared and the OPT bit in the MOR
must be set. The PB4/AN4/TCMP/CMP1 pin becomes an output
which follows the state of the OLVL bit. The pulldown device will
be disabled in this case. The analog subsystem would not
normally use this pin as an analog input in this case.
4. If the PB4 pin is to be an input to the analog subsystem or a digital
input, then the DDRB4 bit must be cleared. In this case, the PB4
pin can still be read; but the voltage present will be returned as a
binary value. Depending on the external application, the PB4
pulldown may also be disabled by setting the PDIB4 pulldown
inhibit bit. In this case both the digital and analog functions
connected to this pin can be utilized.
.
General Release Specification
90
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Parallel Input/Output
Parallel Input/Output
Port B
Table 7-2. Port B Pin Functions — PB0:4
Control Bits
Timer
PORTB Access
Result on
(Pin or Data
Register)
Port B Pins
Port B
Pin
Comparator 1
Port B
SWPDI
in
OPT in
CMP1 COE1
OLVL MOR
PDIBx DDRBx* Read
Write Pulldown
Pin
MOR
0
0
1
0
0
0
1
0
0
0
1
1
1
1
1
Pin
Pin
Pin
Data
Pin
Pin
Pin
Data
Data
Data
1
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
On
Off
Off
Off
On
Off
Off
Off
Off
Off
Off
Off
PBx In
PBx In
PBx In
PBx Out
PB4 In
PB4 In
PB4 In
PB4 Out
PB4 Out
PB4 Out
1
PB0
PB1
PB2
PB3
0
X
X
X
X
1
X
X
0
X
0
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
0
X
0
1
X
1
0
1
1
X
1
0
0
0
1
X
X
X
X
X
X
PB4
X
1
1
1
* DDRB can always be read or written.
X = Don’t Care
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
91
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
7.4.7 PB5/ SDO Log ic
The PB5/SDO pin can be used as a simple I/O port pin or be controlled
by the SIOP serial interface as shown in Figure 7-10. The operations of
the PB5 pin are summarized in Table 7-3.
SERIAL DATA OUT (SDO)
V
DD
SERIAL ENABLE (SPE)
READ $0005
WRITE $0005
DATA DIRECTION
REGISTER B
BIT DDRB5
R
PORT B DATA
REGISTER
BIT PB5
PB5
SDO
WRITE $0001
READ $0001
WRITE $0011
PULLDOWN
REGISTER B
BIT PDIB5
PULLDOWN
DEVICE
R
RESET
MASK OPTION REGISTER ($1FF1)
Figure 7-10. PB5/SDO Pin I/O Circuit
General Release Specification
92
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Parallel Input/Output
Parallel Input/Output
Port B
When using the PB5/SDO pin, the following interactions must be noted:
1. If the SIOP function is required, then the SPE bit in the SCR must
be set. This causes the PB5/SDO pin buffer to be enabled and to
be driven by the serial data output (SDO) from the SIOP. The
pulldown device will be disabled in this case.
2. If the SIOP function is in control of the PB5/SDO pin, the DDRB5
and PB5 data register bits are still accessible to the CPU and can
be altered or read without affecting the SIOP functionality.
However, if the DDRB5 bit is cleared, reading the PB5 data
register will return the current state of the PB5/SDO pin.
3. If the SIOP function is terminated by clearing the SPE bit in the
SCR, then the last conditions stored in the DDRB5, PDIB5, and
PB5 register bits will then control the PB5/SDO pin.
4. If the PB5/SDO pin is to be a digital input, then both the SPE bit in
the SCR and the DDRB5 bit must be cleared. Depending on the
external application, the pulldown device may also be disabled by
setting the PDIB5 pulldown inhibit bit.
5. If the PB5/SDO pin is to be a digital output, then the SPE bit in the
SCR must be cleared and the PDIB5 bit must be set. The pulldown
device will be disabled in this case.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
93
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
7.4.8 PB6/ SDI Log ic
The PB6/SDI pin can be used as a simple I/O port pin or be controlled
by the SIOP serial interface as shown in Figure 7-11. The operations of
PB6/SDI pin are summarized in Table 7-3.
SERIAL DATA IN (SDI)
SERIAL ENABLE (SPE)
READ $0005
WRITE $0005
DATA DIRECTION
REGISTER B
BIT DDRB6
R
PORT B DATA
PB6
SDI
WRITE $0001
REGISTER
BIT PB6
READ $0001
WRITE $0011
PULLDOWN
PULLDOWN
REGISTER B
DEVICE
BIT PDIB6
R
RESET
MASK OPTION REGISTER ($1FF1)
Figure 7-11. PB6/SDI Pin I/O Circuit
General Release Specification
94
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Parallel Input/Output
Parallel Input/Output
Port B
When using the PB6/SDI pin, the following interactions must be noted:
1. If the SIOP function is required, then the SPE bit in the SCR must
be set. This causes the PB6/SDI pin buffer to be disabled to allow
the PB6/SDI pin to act as an input that feeds the serial data input
(SDI) of the SIOP. The pulldown device is disabled in this case.
2. If the SIOP function is in control of the PB6/SDI pin, the DDRB6
and PB6 data register bits are still accessible to the CPU and can
be altered or read without affecting the SIOP functionality.
However, if the DDRB6 bit is cleared, reading the PB6 data
register will return the current state of the PB6/SDI pin.
3. If the SIOP function is terminated by clearing the SPE bit in the
SCR, then the last conditions stored in the DDRB6, PDIB6, and
PB6 register bits will then control the PB6/SDI pin.
4. If the PB6/SDI pin is to be a digital input, then both the SPE bit in
the SCR and the DDRB6 bit must be cleared. Depending on the
external application, the pulldown device may also be disabled by
setting the PDIB6 pulldown inhibit bit.
5. If the PB6/SDI pin is to be a digital output, then the SPE bit in the
SCR must be cleared and the DDRB6 bit must be set. The
pulldown device will be disabled in this case.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
95
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
7.4.9 PB7/ SCK Log ic
The PB7/SCK pin can be used as a simple I/O port pin or be controlled
by the SIOP serial interface as shown in Figure 7-12. The operations of
the PB7/SCK pin are summarized in Table 7-3.
SERIAL DATA CLOCK (SCK)
CLOCK SOURCE (MSTR)
SERIAL ENABLE (SPE)
READ $0005
WRITE $0005
DATA DIRECTION
REGISTER B
BIT DDRB7
R
PORT B DATA
PB7
SCK
WRITE $0001
REGISTER
BIT PB7
READ $0001
WRITE $0011
PULLDOWN
PULLDOWN
REGISTER B
DEVICE
BIT PDIB7
R
RESET
MASK OPTION REGISTER ($1FF1)
Figure 7-12. PB7/SCK Pin I/O Circuit
General Release Specification
96
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Parallel Input/Output
Parallel Input/Output
Port B
When using the PB7/SCK pin, the following interactions must be noted:
1. If the SIOP function is required, then the SPE bit in the SCR must
be set. This causes the PB7/SCK pin buffer to be controlled by the
MSTR control bit in the SCR. The pulldown device is disabled in
these cases.
a. If the MSTR bit is set, then the PB7/SCK pin buffer will be
enabled and driven by the serial data clock (SCK) from the
SIOP.
b. If the MSTR bit is clear, then the PB7/SCK pin buffer will be
disabled, allowing the PB7/SCK pin to drive the serial data
clock (SCK) into the SIOP.
2. If the SIOP function is in control of the PB7/SCK pin, the DDRB7
and PB7 data register bits are still accessible to the CPU and can
be altered or read without affecting the SIOP functionality.
However, if the DDRB7 bit is cleared, reading the PB7 data
register will return the current state of the PB7/SCK pin.
3. If the SIOP function is terminated by clearing the SPE bit in the
SCR, then the last conditions stored in the DDRB7, PDIB7, and
PB7 register bits will then control the PB7/SCK pin.
4. If the PB7/SCK pin is to be a digital input, then both the SPE bit in
the SCR and the DDRB7 bit must be cleared. Depending on the
external application, the pulldown device may also be disabled by
setting the PDIB7 pulldown inhibit bit.
5. If the PB7/SCK pin is to be a digital output, then the SPE bit in the
SCR must be cleared and the DDRB7 bit must be set. The
pulldown device will be disabled when the pin is set as an output.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
97
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
Table 7-3. Port B Pin Functions — PB5:7
Control Bits
PORTB Access
(Pin or Data
Register)
Result on
Port B
SIOP
Pin
Port B Pins
SWPDI
in
MOR
Port B
SPE
MSTR
PDIBx DDRBx*
Read
Pin
Write
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Pulldown
Pin
0
0
1
X
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
1
On
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
Off
Off
PB5 In
PB5 In
PB5 In
PB5 Out
SDO Out
SDO Out
PB6 In
PB6 In
PB6 In
PB6 Out
SDI In
Pin
0
X
X
X
Pin
PB5
Data
SDO
Data
Pin
1
0
1
0
X
X
X
X
X
X
0
0
1
X
0
1
Pin
X
X
Pin
PB6
Data
SDI
Data
Pin
X
X
SDI In
0
0
1
X
0
1
PB7 In
PB7 In
PB7 In
PB7 Out
SCK In
SCK In
SCK Out
SCK Out
Pin
X
X
Pin
Data
SCK
Data
SCK
Data
PB7
0
1
X
X
X
X
1
* DDRB can always be read or written.
X = Don’t Care
General Release Specification
98
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Parallel Input/Output
Parallel Input/Output
Port C (28-Pin Versions Only)
7.5 Port C (28-Pin Ve rsions Only)
Port C is a 8-bit, general-purpose bidirectional I/O port with these
features:
• Individual programmable pulldown devices
• High current sinking capability on all port C pins, with a maximum
total for port C
• High current sourcing capability on all port C pins, with a maximum
total for port C
7.5.1 Port C Da ta Re g iste r (PORTC)
The port C data register contains a bit for each of the port C pins. When
a port C pin is programmed to be an output, the state of its data register
bit determines the state of the output pin. When a port C pin is
programmed to be an input, reading the port C data register returns the
logic state of the pin.
$0002
Read:
Write:
Reset:
Bit 7
PC7
6
5
4
3
2
1
Bit 0
PC0
PC6
PC5
PC4
PC3
PC2
PC1
Unaffected by Reset
Figure 7-13. Port C Data Register (PORTC)
PC7–PC0 — Port C Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in the port C data
direction register (DDRC). Reset has no effect on port C data.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
99
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
7.5.2 Da ta Dire c tion Re g iste r C (DDRC)
The contents of the port C data direction register (DDRC) determine
whether each port C pin is an input or an output. Writing a logic one to a
DDRC bit enables the output buffer for the associated port C pin. A
DDRC bit set to a logic one also disables the pulldown device for that pin.
Writing a logic zero to a DDRC bit disables the output buffer for the
associated port C pin. A reset initializes all DDRC bits to logic zeros,
configuring all port C pins as inputs.
$0006
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-14. Data Direction Register C (DDRC)
DDRC7–DDRC0 — Port C Data Direction Bits
These read/write bits control port C data direction. Reset clears the
DDRC7–DDRC0 bits.
1 = Corresponding port C pin configured as output and pulldown
device disabled
0 = Corresponding port C pin configured as input
7.5.3 Port C Pulld own De vic e s
All port C pins can have software programmable pulldown devices
enabled or disabled globally by the SWPDI bit in the MOR. These
pulldown devices are individually controlled by the write-only pulldown
register A (PDRA) shown in Figure 7-3. PDICH controls the upper four
pins (PC7:4) and PDICL controls the lower four pins (PC3:0). Clearing
the PDICH or PDICL bits in the PDRA turns on the pulldown devices if
the port C pin is an input. Reading the PDRA returns undefined results
since it is a write-only register. Reset clears the PDICH and PDICL bits,
which turns on all the port C pulldown devices.
General Release Specification
100
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Parallel Input/Output
Parallel Input/Output
Port C (28-Pin Versions Only)
7.5.4 Port C Log ic
Figure 7-15 shows the I/O logic of port C.
When a port C pin is programmed as an output, reading the port bit
actually reads the value of the data latch and not the voltage on the pin
itself. When a port C pin is programmed as an input, reading the port bit
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its DDR bit. Table 7-4 summarizes the
operations of the port C pins.
READ $0006
WRITE $0006
DATA DIRECTION
REGISTER C
BIT DDRCx
R
PORT C DATA
REGISTER
BIT PCx
WRITE $0002
PCx
HIGH SINK/SOURCE
CURRENT CAPABILITY
READ $0002
WRITE $0010
PULLDOWN
REGISTER A
BIT PDICx
PULLDOWN
DEVICE
R
RESET
MASK OPTION REGISTER ($1FF1)
Figure 7-15. Port C I/O Circuit
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
101
Parallel Input/Output
Pa ra lle l Inp ut/ Outp ut
Table 7-4. Port C Pin Functions (28-Pin Versions Only)
Control Bits
Port C
PORTC Access
Result on
Port C
Pin(s)
(Pin or Data Register)
Port C Pins
SWPDI
(in MOR)
PDICH
PDICL
DDRCx*
Read
Pin
Write
Data
Data
Data
Data
Data
Data
Data
Data
Pulldown
Pin
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
0
0
1
X
0
0
1
X
X
X
X
X
0
0
1
0
0
0
1
0
0
0
1
On
Off
Off
Off
On
Off
Off
Off
PCx In
PCx In
PCx In
PCx Out
PCx In
PCx In
PCx In
PCx Out
Pin
X
X
X
X
X
X
Pin
Data
Pin
1
Pin
X
X
Pin
Data
* DDRC can always be read or written.
X = Don’t care
7.6 Port Tra nsitions
Glitches and temporary floating inputs can occur if the control bits
regarding each port I/O pin are not performed in the correct sequence.
• Do not use read-modify-write instructions on pulldown register A
or B.
• Avoid glitches on port pins by writing to the port data register
before changing data direction register bits from a logic zero to a
logic one.
• Avoid a floating port input by clearing its pulldown register bit
before changing its data direction register bit from a logic one to a
logic zero.
• The SWPDI bit in the MOR turns off all port pulldown devices and
disables software control of the pulldown devices. Reset has no
effect on the pulldown devices when the SWPDI bit is set.
• Two or more output pins of the same port can be connected
electrically so as to provide output currents up to the sum of the
maximum specified drive currents as defined in 15.8 DC
Electrical Characteristics (5.0 Vdc) and 15.9 DC Electrical
Characteristics (3.0 Vdc). Care must be taken to assure that all
ganged pins always maintain the same output logic value.
General Release Specification
102
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Parallel Input/Output
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 8. Ana log Sub syste m
8.1 Conte nts
8.2
8.3
8.4
8.5
8.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Analog Multiplex Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Analog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Analog Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
A/D Conversion Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.7
8.7.1
Voltage Measurement Methods . . . . . . . . . . . . . . . . . . . . . . .128
Absolute Voltage Readings. . . . . . . . . . . . . . . . . . . . . . . .129
Internal Absolute Reference. . . . . . . . . . . . . . . . . . . . . .129
External Absolute Reference . . . . . . . . . . . . . . . . . . . . .130
Ratiometric Voltage Readings. . . . . . . . . . . . . . . . . . . . . .131
Internal Ratiometric Reference . . . . . . . . . . . . . . . . . . .131
External Ratiometric Reference . . . . . . . . . . . . . . . . . . .131
8.7.1.1
8.7.1.2
8.7.2
8.7.2.1
8.7.2.2
8.8
8.8.1
8.8.2
Voltage Comparator Features . . . . . . . . . . . . . . . . . . . . . . . .133
Voltage Comparator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Voltage Comparator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
8.9
Current Source Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
8.10 Internal Temperature Sensing Diode Features. . . . . . . . . . . .134
8.11 Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
8.12 Port B Interaction with Analog Inputs . . . . . . . . . . . . . . . . . . .135
8.13 Port B Pins As Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
8.14 Port B Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
8.15 Noise Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
103
Analog Subsystem
Ana log Sub syste m
8.2 Introd uc tion
The analog subsystem of the MC68HC705JJ7/MC68HC705JP7 is
based on two on-chip voltage comparators and a selectable current
charge/discharge function as shown in Figure 8-1.
This configuration provides several features:
• Two (2) independent voltage comparators with external access to
both inverting and non-inverting inputs
• One voltage comparator can be connected as a single-slope A/D
and the other connected as a single-voltage comparator. The
possible single-slope A/D connection provides the following
features:
– A/D conversions can use V or an external voltage as a
DD
reference with software used to calculate ratiometric or
absolute results
– Channel access of up to four inputs via multiplexer control with
independent multiplexer control allowing mixed input
connections
– Access to V and V for calibration
DD
SS
– Divide by 2 to extend input voltage range
– Each comparator can be inverted to calculate input offsets
– Internal sample and hold capacitor
– direct digital output of comparator 1 to the PB4 pin
Voltages are resolved by measuring the time it takes an external
capacitor to charge up to the level of the unknown input voltage being
measured. The beginning of the A/D conversion time can be started by
several means:
• Output compare from the 16-bit programmable timer
• Timer overflow from the 16-bit programmable timer
• Direct software control via a register bit
The end of the A/D conversion time can be captured by these means:
• Input capture in the 16-bit programmable timer
• Interrupt generated by the comparator output
• Software polling of the comparator output using software loop time
General Release Specification
104
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
Introduction
PB3/AN3/TCAP
2 TO 1
MUX
V
TCAP
DD
I
PORTB
LOGIC
CHG
CHG
ATD1
ATD2
ISEN
CHARGE
CURRENT
CONTROL
LOGIC
PB0
AN0
I
DISCHG
V
DD
CP2EN
ICEN
CP2EN
COMP2
+
-
INTERNAL
TEMPERATURE
DIODE
CP1EN
CPIE
INV
$001D
ANALOG
INTERRUPT
V
DD
CPF2
CPF1
CMP2
VREF
MUX1
SAMPLE
CAP
PORTB
LOGIC
CMP1
VOFF
PB1
AN1
100 MV
OFFSET
PORTB
LOGIC
$001E
PB2
AN2
CP1EN
OPT (MOR)
MUX2
MUX3
PORTB
LOGIC
+
-
HOLD
DHOLD
INV
COMP1
INV
PB3
AN3
TCAP
VREF
VREF
MUX4
MUX3
MUX2
MUX1
PORTB
LOGIC
PB4
AN4
TCMP
MUX4
PORT B
CONTROL
LOGIC
OLVL
V
COE1
OPT
AOFF
$0003
V
+
-
SS
MUX4
MUX3
MUX2
MUX1
DENOTES
INTERNAL
V
SS
ANALOG V
SS
Figure 8-1. Analog Subsystem Block Diagram
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
105
Analog Subsystem
Ana log Sub syste m
8.3 Ana log Multip le x Re g iste r
The analog multiplex register (AMUX) controls the general
interconnection and operation. The control bits in the AMUX are shown
in Figure 8-2.
$0003
Read:
Write:
Reset:
Bit 7
HOLD
1
6
DHOLD
0
5
INV
0
4
VREF
0
3
MUX4
0
2
MUX3
0
1
MUX2
0
Bit 0
MUX1
0
Figure 8-2. Analog Multiplex Register (AMUX)
HOLD, DHOLD
These read/write bits control the source connection to the negative
input of voltage comparator 2 shown in Figure 8-3. This allows the
voltage on the internal temperature sensing diode, the channel
selection bus, or the divide-by-two channel selection bus to charge
the internal sample capacitor and to also be presented to comparator
2. The decoding of these sources is given in Table 8-1.
During the hold case when both the HOLD and DHOLD bits are clear
the VOFF bit in the Analog Status Register (ASR) can offset the V
SS
reference on the sample capacitor by approximately 100 mV. This
offset source is bypassed whenever the sample capacitor is being
charged with either the HOLD or DHOLD bit set. The VOFF bit must
be enabled by the OPT bit in the COPR at location $1FF0.
During a reset the HOLD bit is set and the DHOLD bit is cleared,
which connects the internal sample capacitor to the channel selection
bus. And since a reset also clears the MUX1:4 bits then the channel
selection bus will be connected to V and the internal sample
SS
capacitor will be discharged to V following the reset.
SS
NOTE: When sampling a voltage for later conversion the HOLD and DHOLD bit
should be cleared before making any changes in the MUX channel
selection. If the MUX channel and the HOLD/DHOLD are changed on
the same write cycle to the AMUX register, the sampled voltage may be
altered during the channel switching.
General Release Specification
106
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
Analog Multiplex Register
V
DD
PB0
+
-
COMP2
INTERNAL
TEMPERATURE
DIODE
CHANNEL
SELECTION
BUS
SAMPLE
CAP
VOFF
OPT (MOR)
HOLD
V
SS
OFFSET
DHOLD
Figure 8-3. Comparator 2 Input Circuit
Table 8-1 Comparator 2 Input Sources
HOLD DHOLD
(AMUX) (AMUX) (MOR)
OPT
VOFF
(ASR)
Voltage
Offset
Source To Negative Input
Case
of Comparator 2
0
1
X
0
Sample capacitor connected to comparator
2 negative input; very low leakage current.
No
Hold
Sample
Voltage
0
0
Sample capacitor connected to comparator
2 negative input; bottom of capacitor
1
1
Yes
offset from V by approximately 100 mV,
SS
very low leakage current.
Signal on channel selection bus is divided
by 2 and connected to sample capacitor
and comparator 2 negative input
Divided
Input
0
1
1
1
0
1
X
X
X
X
X
X
No
No
No
Signal on channel selection bus is
connected directly to sample capacitor
and comparator 2 negative input.
Direct
Input
Internal
Temperature
Diode
Internal temperature sensing diode
connected directly to sample capacitor
and comparator 2 negative input.
X = Don’t Care
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
107
Analog Subsystem
Ana log Sub syste m
INV
This is a read/write bit that controls the relative polarity of the inherent
input offset voltage of the voltage comparators. This bit allows voltage
comparisons to be made with both polarities and then averaged
together by taking the sum of the two readings and then dividing by 2
(logical shift right).
The polarity of the input offset is reversed by interchanging the
internal voltage comparator inputs while also inverting the comparator
output. This interchange does not alter the action of the voltage
comparator output with respect to its port pins. That is, the output will
only go high if the voltage on the positive input (PB2 pin for
comparator 1 and PB0 pin for comparator 2) is above the voltage on
the respective negative input (PB3 pin for comparator 1 and PB1 pin
for comparator 2). This is shown schematically in Figure 8-4. This bit
is cleared by a reset of the device.
1 = The voltage comparators are internally inverted.
0 = The voltage comparators are not internally inverted.
RISE
WHEN
V+ > V-
RISE
WHEN
V+ > V-
V+
V+
V-
V
V
IO
+
+
COMP
-
IO
COMP
-
V-
INV = 0
INV = 1
Figure 8-4. INV Bit Action
NOTE: The effect of changing the state of the INV bit is to only change the
polarity of the input offset voltage. It does not change the output phase
of the CPF1 or CPF2 flags with respect to the external port pins.
General Release Specification
108
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
Analog Multiplex Register
NOTE: Either comparator may generate an output flag when the inputs are
exchanged due to a change in the state of the INV bit. It is therefore
recommended that the INV bit not be changed while waiting for a
comparator flag. Further, any changes to the state of the INV bit should
be followed by writing a logical one to both the CPFR1 and CPFR2 bits
to clear any extraneous CPF1 or CPF2 flags that may have occurred.
VREF
This read/write bit connects the channel select bus to V for making
DD
a reference voltage measurement. It cannot be selected if any of the
other input sources to the channel select bus are selected as shown
in Table 8-2. This bit is cleared by a reset of the device.
1 = Channel select bus connected to V if all MUX1:4 are cleared.
DD
0 = Channel select bus cannot be connected to V .
DD
MUX1:4
These are read/write bits that connect the analog subsystem pins to
the channel select bus and voltage comparator 2 for purposes of
making a voltage measurement. They can be selected individually or
combined with any of the other input sources to the channel select
bus as shown in Table 8-2.
NOTE: The V
voltage source shown in Figure 8-1 depicts a small offset
AOFF
voltage generated by the total chip current passing through the package
bond wires and lead frame that are attached to the single V pin. This
SS
offset raises the internal V reference (AV ) in the analog subsystem
SS
SS
with respect to the external V pin. Turning on the V MUX to the
SS
SS
channel select bus connects it to this internal AV reference line.
SS
When making A/D conversions this AV offset gets placed on the
SS
external ramping capacitor since the discharge device on the PB0/AN0
pin discharges the external capacitor to the internal AV line. Under
SS
these circumstances the positive input (+) to comparator 2 will always be
higher than the negative input (–) until the negative input reaches the
AV offset voltage plus any offset in comparator 2.
SS
Therefore, input voltages cannot be resolved if they are less than the
sum of the AV offset and the comparator offset, because they will
SS
always yield a low output from the comparator.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
109
Analog Subsystem
Ana log Sub syste m
Table 8-2. Channel Select Bus Combinations
Analog Multiplex Register
VREF MUX4 MUX3 MUX2 MUX1
Channel Select Bus Connected to:
PB4/AN4/
PB3/AN3/
V
V
SS
PB2/AN2
PB1/AN1
DD
TCMP
TCAP
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
—
—
—
—
—
—
On
—
On
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
On
—
—
—
—
On
On
—
—
—
On
—
—
On
On
On
On
—
—
—
On
—
—
On
On
—
—
On
—
On
On
On
On
On
On
On
On
—
—
—
On
—
—
On
On
—
—
On
—
On
On
On
On
—
—
On
—
On
On
—
On
—
X = Don’t care
— = High impedance
General Release Specification
110
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
Analog Control Register
8.4 Ana log Control Re g iste r
The analog control register (ACR) controls the power-up, interrupt, and
flag operation. The analog subsystem draws about 500 µA of current
while it is operating. The resulting power consumption can be reduced
by powering down the analog subsystem when not in use. This can be
done by clearing three enable bits (ISEN, CP1EN, and CP2EN) in the
ACR at $001D. Since these bits are cleared following a reset, the voltage
comparators and the charge current source will be powered down
following a reset of the device.
The control bits in the ACR are shown in Figure 8-5. All the bits in this
register are cleared by a reset of the device.
$001D
Read:
Write:
Reset:
Bit 7
CHG
0
6
ATD2
0
5
ATD1
0
4
ICEN
0
3
CPIE
0
2
1
Bit 0
ISEN
0
CP2EN CP1EN
0
0
Figure 8-5. Analog Control Register (ACR)
CHG
The CHG enable bit allows direct control of the charge current source
and the discharge device; and also reflects the state of the discharge
device. This bit is cleared by a reset of the device.
1 = If the ISEN bit is also set the charge current source is sourcing
current out of the PB0/AN0 pin. Writing a logical one enables
the charging current out of the PB0/AN0 pin.
0 = The discharge device is sinking current into the PB0/AN0 pin.
Writing a logical zero disables the charging current and
enables the discharging current into the PB0/AN0 pin, if the
ISEN bit is also set.
ATD1:2
The ATD1:2 enable bits select one of the four operating modes used
for making A/D conversions via the single-slope method.These four
modes are given in Table 8-3. These bits have no effect if the ISEN
enable bit is cleared. These bits are cleared by a reset of the device
and thereby return the analog subsystem to the manual A/D
conversion method.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
111
Analog Subsystem
Ana log Sub syste m
Table 8-3. A/D Conversion Options
A/D
A/D Options
Charge
Option
Control
Mode
Current Flow To/From PB0/AN0
ISEN ATD2 ATD1 CHG
Current
Source and
Discharge
Disabled
0
X
X
X
Current control disabled, no source or sink current
Disabled
Begin sinking current when the CHG bit is cleared
and continue to sink current until the CHG bit is set.
1
1
0
0
0
0
0
1
Manual
Charge and
Discharge
0
1
Begin sourcing current when the CHG bit is set and
continue to source current until the CHG bit is
cleared.
Begin sinking current when the CHG bit is cleared
and continue to sink current until the CHG bit is set.
(The CHG bit is cleared by writing a logical zero to
it or when the CPF2 flag bit is set.)
1
1
0
0
1
1
0
1
Manual
Charge and
Automatic
Discharge
Begin sourcing current when the CHG bit is set; and
continue to source current until the CHG bit is
cleared. (The CHG bit is set by writing a logical one
to it or cleared when the CPF2 flag bit is set.)
Automatic
Charge and
Discharge
(TOF–ICF)
Synchronized
to Timer
The CHG bit remains cleared until the next timer
TOF occurs.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
2
3
The CHG bit remains set until the next timer ICF
occurs.
Automatic
Charge and
Discharge
(OCF–ICF)
Synchronized
to Timer
The CHG bit remains cleared until the next timer
OCF occurs.
The CHG bit remains set until the next timer ICF
occurs.
General Release Specification
112
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Analog Subsystem
MOTOROLA
Analog Subsystem
Analog Control Register
ICEN
This is a read/write bit that enables a voltage comparison to trigger the
input capture register of the programmable timer when the CPF2 flag
bit is set. Therefore, an A/D conversion could be started by receiving
an OCF or TOF from the programmable timer and then terminated
when the voltage on the external ramping capacitor reaches the level
of the unknown voltage. The time of termination will be stored in the
16-bit buffer located at $0014 and $0015. This bit is automatically set
whenever mode 2 or 3 is selected by setting the ATD2 control bit. This
bit is cleared by a reset of the device.
1 = Connects the CPF2 flag bit to the timer input capture register
0 = Connects the PB3/AN3 pin to the timer input capture register
NOTE: In order for the input capture to occur when the output of comparator 2
goes high the IEDG bit in the TCR must also be set.
NOTE: When the ICEN bit is set, the input capture function of the programmable
timer is not connected to the PB3/AN3/TCAP pin but is driven by the
CPF2 output flag from comparator 2. To return to capturing times from
external events, the ICEN bit must first be cleared before the timed event
occurs.
CPIE
This is a read/write bit that enables an analog interrupt when either of
the CPF1 or CPF2 flag bits is set to a logical one. This bit is cleared
by a reset of the device.
1 = Enables analog interrupts when comparator flag bits are set
0 = Disables analog interrupts when comparator flag bits are set
NOTE: If both the ICEN and CPIE bits are set they will both generate an interrupt
by different paths. One will be the programmable timer interrupt due to
the input capture; and the other will be the analog interrupt due to the
output of comparator 2 going high. In this case the input capture interrupt
will be entered first due to its higher priority. The analog interrupt will then
need to be serviced even if the comparator 2 output has been reset or
the input capture flag (ICF) has been cleared.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
113
Analog Subsystem
Ana log Sub syste m
CP2EN
The CP2EN enable bit controls power to voltage comparator 2 in the
analog subsystem. Powering down a comparator will drop the supply
current by about 100 µA. This bit is cleared by a reset of the device.
1 = Writing a logical one powers up voltage comparator 2
0 = Writing a logical zero powers down voltage comparator 2
NOTE: Voltage comparators power up slower than digital logic; and their
outputs may go through indeterminate states which might set their
respective flags (CPF1, CPF2). It is therefore recommended to power up
the charge current source first (ISEN); then to power up any
comparators, and finally clear the flag bits by writing a logic one to the
respective CPFR1 or CPFR2 bits in the ACR.
CP1EN
The CP1EN enable bit will power down the voltage comparator 1 in
the analog subsystem. Powering down a comparator will drop the
supply current by about 100 µA. This bit is cleared by a reset of the
device.
1 = Writing a logical one powers up voltage comparator 1
0 = Writing a logical zero powers down voltage comparator 1
ISEN
The ISEN enable bit will power down the charge current source and
disable the discharge device in the analog subsystem. Powering
down the current source will drop the supply current by about 200 µA.
This bit is cleared by a reset of the device.
1 = Writing a logical one powers up the ramping current source and
enables the discharge device on the PB0/AN0 pin.
0 = Writing a logical zero powers down the ramping current source
and disables the discharge device on the PB0/AN0 pin.
NOTE: The analog subsystem has support circuitry which draws about 80 µA of
current. This current will be powered down if both comparators and the
charge current source are powered down (ISEN, CP1EN, and CP2EN
all cleared). Powering up either comparator or the charge current source
will activate the support circuitry.
General Release Specification
114
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
Analog Status Register
8.5 Ana log Sta tus Re g iste r
The analog status register (ASR) contains status and control of the
comparator flag bits. These bits in the ASR are shown in Figure 8-6. All
the bits in this register are cleared by a reset of the device.
$001E
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
CMP1
R
CPF2
CPF1
0
CPFR2
0
0
CPFR1
0
CMP2
COE1
VOFF
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 8-6. Analog Status Register (ASR)
CPF2
This read-only flag bit is edge sensitive to the rising output of
comparator 2. It is set when the voltage on the PB0/AN0 pin rises
above the voltage on sample capacitor which creates a positive edge
on the output of comparator 2, regardless of the state of the INV bit in
the AMUX register. This bit is reset by writing a logical one to the
CPFR2 reset bit in the ASR. This bit is cleared by a reset of the
device.
1 = A positive transition on the output of comparator 2 has occurred
since the last time the CPF2 flag has been cleared.
0 = A positive transition on the output of comparator 2 has not
occurred since the last time the CPF2 flag has been cleared.
CPF1
This read-only flag bit is edge sensitive to the rising output of
comparator 1. It is set when the voltage on the PB2/AN2 pin rises
above the voltage on the PN3/AN3/TCAP pin which creates a positive
edge on the output of comparator 1, regardless of the state of the INV
bit in the AMUX register. This bit is reset by writing a logical one to the
CPFR1 reset bit in the ASR. This bit is cleared by a reset of the
device.
1 = A positive transition on the output of comparator 1 has occurred
since the last time the CPF1 flag has been cleared.
0 = A positive transition on the output of comparator 1 has not
occurred since the last time the CPF1 flag has been cleared.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
115
Analog Subsystem
Ana log Sub syste m
CPFR2
Writing a logical one to this write-only flag clears the CPF2 flag in the
ASR. Writing a logical zero to this bit has no effect. Reading the
CPFR2 bit will return a logical zero. By default, this bit looks cleared
following a reset of the device.
1 = Clears the CPF2 flag bit
0 = No effect
CPFR1
Writing a logical one to this write-only flag clears the CPF1 flag in the
ASR. Writing a logical zero to this bit has no effect. Reading the
CPFR1 bit will return a logical zero. By default, this bit looks cleared
after a reset of the device.
1 = Clears the CPF1 flag bit
0 = No effect
NOTE: The CPFR1 and CPFR2 bits should be written with logical ones following
a power up of either comparator. This will clear out any latched CPF1 or
CPF2 flag bits which might have been set during the slower power up
sequence of the analog circuitry.
If both inputs to a comparator are above the maximum common-mode
input voltage (V –1.5V) the output of the comparator is indeterminate
DD
and may set the comparator flag. Applying a reset to the device may only
temporarily clear this flag as long as both inputs of a comparator remain
above the maximum common-mode input voltages.
VOFF
This read-write bit controls the addition of an offset voltage to the
bottom of the sample capacitor. It is not active unless the OPT bit in
the COPR at location $1FF0 is set. Any reads of the VOFF bit location
return a logical zero if the OPT bit is clear. During the time that the
sample capacitor is connected to an input (either HOLD or DHOLD
set) the bottom of the sample capacitor is connected to V . The
SS
VOFF bit is cleared by a reset of the device. For more information see
8.11 Sample and Hold.
1 = Enables approximately 100 mV offset to be added to the
sample voltage when both the HOLD and DHOLD control bits
are cleared
0 = Connects the bottom of the sample capacitor to V
SS
General Release Specification
116
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
Analog Status Register
COE1
This read-write bit controls the output of comparator 1 to the PB4 pin.
It is not active unless the OPT bit in the COPR at location $1FF0 is
set. Any reads of the COE1 bit location return a logical zero if the OPT
bit is clear. The COE1 bit is cleared by a reset of the device.
1 = Enables the output of comparator 1 to be ORed with the PB4
data bit and OLVL bit, if the DDRB4 bit is also set.
0 = Disables the output of comparator 1 from affecting the PB4 pin.
CMP2
This read-only bit shows the state of comparator 2 during the time that
the bit is read. This bit is therefore the current state of the comparator
without any latched history. The CMP2 bit will be high if the voltage
on the PB0/AN0 pin is greater than the voltage on the PB1/AN1 pin,
regardless of the state of the INV bit in the AMUX register. Since a
reset disables comparator 2, this bit returns a logical zero following a
reset of the device.
1 = The voltage on the positive input on comparator 2 is higher than
the voltage on the negative input of comparator 2
0 = The voltage on the positive input on comparator 2 is lower than
the voltage on the negative input of comparator 2
CMP1
This read-only bit shows the state of comparator 1 during the time that
the bit is read. This bit is therefore the current state of the comparator
without any latched history. The CMP1 bit will be high if the voltage
on the PB2/AN2 pin is greater than the voltage on the PB3/AN3/TCAP
pin, regardless of the state of the INV bit in the AMUX register. Since
a reset disables comparator 1, this bit returns a logical zero following
a reset of the device.
1 = The voltage on the positive input on comparator 1 is higher than
the voltage on the negative input of comparator 1
0 = The voltage on the positive input on comparator 1 is lower than
the voltage on the negative input of comparator 1
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
117
Analog Subsystem
Ana log Sub syste m
8.6 A/ D Conve rsion Me thod s
The control bits in the ACR provide various options to charge or
discharge current through the PB0/AN0 pin in order to perform single-
slope A/D conversions using an external capacitor from the PB0/AN0 pin
to V as shown in Figure 8-7. The various A/D conversion triggering
SS
options are given in Table 8-3.
C x V
I
X
Charge Time =
V
–1.5 Vdc
DD
UNKNOWN VOLTAGE ON (–) INPUT
VOLTAGE ON
CAPACITOR
CONNECTED
TO (+) INPUT
CHARGE TIME
TO MATCH UNKNOWN
DISCHARGE TIME
TO RESET CAPACITOR
MAXIMUM CHARGE TIME
TO V –1.5 Vdc
DD
+ 5 V
V
DD
PB4/AN4
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
UNKNOWN
OR REFERENCE
SIGNALS
MC68HC705JJ7
MC68HC705JP7
V
SS
RAMP
CAP
Figure 8-7. Single-Slope A/D Conversion Method
The top three bits of the ACR control the charging and discharging
current into or out of the PB0/AN0 pin. These three bits will have no
effect on the PB0/AN0 pin if the ISEN enable bit is cleared. Any clearing
of the ISEN bit will immediately disable both the charge current source
and the discharge device. Since all these bits and the ISEN bit are
General Release Specification
118
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
A/D Conversion Methods
cleared when the device is reset, the MC68HC705JJ7/MC68HC705JP7
starts with the charge and discharge function disabled.
The length of time required to reach the maximum voltage to be
measured and the speed of the time counting mechanism will determine
the resolution of the reading. The time to ramp the external capacitor
voltage to match the maximum voltage is dependent on:
• Charging current to external capacitor
• Value of the external capacitor
• Clock rate for timing function
• Any prescaling of the clock to the timing function
• Desired resolution
The charging behavior is described by the general equation:
t
= C
x V / I
EXT X CHG
CHG
Where:
t
= Charge time (seconds)
CHG
C
V
= Capacitance (µF)
= Unknown voltage (volts)
EXT
X
I
= Charge current (µA)
CHG
Since the MCU can measure time in a variety of ways, the resolution of
the conversion will depend on the length of the time keeping function and
its prescaling to the oscillator frequency (f
time also equals:
). Therefore the charge
OSC
t
= P x N / f
OSC
CHG
Where:
P
N
= Prescaler value (÷ 2, ÷ 4, ÷ 8, etc.)
= Number of counts during charge time
= Oscillator clock frequency (Hz)
f
OSC
NOTE: Noise on the system ground or the external ramping capacitor can cause
the comparator to trip prematurely. Therefore in any given application it
is best to use the fastest possible ramp rate (shortest charge time).
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
119
Analog Subsystem
Ana log Sub syste m
The above two equations for the charge time, t
, can be combined to
CHG
form the following expression for the full scale count (N ) of the
FS
measured time versus the full scale unknown voltage (V ):
FS
N
= C
x V x f
/ (P x I
)
FS
EXT
FS
OSC
CHG
Since a given timing method has a fixed charge current and prescaler,
then the variation in the resultant count for a given unknown voltage is
mainly dependent on the operating frequency and the capacitance value
used. The desired external capacitance for a given voltage range, f
conversion method, and resolution is defined as:
,
OSC
C
= N x P x I
/ (V x f
)
EXT
FS
CHG
FS
OSC
NOTE: The value of any capacitor connected directly to the PB0/AN0 pin should
be limited to less than 2 microfarads. Larger capacitances will create
high discharge currents which may damage the device or create signal
noise.
The full scale voltage range for a given capacitance, f
method, and resolution is defined as:
, conversion
OSC
V
= N x P x I
/ (C
x f
)
FS
FS
CHG
EXT
OSC
Once charged to a given voltage a finite amount of time will be required
to discharge the capacitor back to its start voltage at V . This discharge
SS
time will be solely based on the value of capacitance used and the
sinking current of the internal discharge device. To allow a reasonable
time for the capacitor to return to V levels, the discharge time should
SS
last about 10 milliseconds per microfarad of capacitance attached to the
PB0 pin. If the total charge/discharge cycle time is critical, then the
discharge time should be at least 1/10 of the most recent charge time.
Shorter discharge times may be used if lesser accuracy in the voltage
measurement is acceptable.
NOTE: Sufficient time should be allowed to discharge the external capacitor or
subsequent charge times will be shortened with resultant errors in timing
conversion.
General Release Specification
120
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
A/D Conversion Methods
Table 8-4 gives the range of values of each parameter in the A/D timing
conversion; and Table 8-5 gives some A/D conversion examples for
several bit resolutions.
Table 8-4. A/D Conversion Parameters
Name
Function
Min
Typ
—
Max
Units
V
Unknown voltage on channel selection bus
Charging voltage on external capacitor
Maximum charging voltage on external capacitor
Charging current on external ramping capacitor
V
V
V
V
V
–1.5
V
V
V
X
SS
SS
DD
DD
DD
V
—
–1.5
–1.5
CAP
MAX
V
—
—
Refer to 15.10 Analog Subsystem
I
V
V
= 3 VDC
= 5 VDC
Characteristics (5.0 Vdc) and 15.11 Analog
CHG
DD
DD
Subsystem Characteristics (3.0 Vdc)
Refer to 15.10 Analog Subsystem
Characteristics (5.0 Vdc) and 15.11 Analog
Subsystem Characteristics (3.0 Vdc)
I
Discharge current on external ramping capacitor
DIS
Time to charge external capacitor
(100 kHz < f
4-bit result
6-bit result
8-bit result
10-bit result
12-bit result
< 4.0 MHz)
OSC
0.032
0.128
0.512
2.048
8.192
0.128
0.512
2.048
8.196
32.768
2.56
10.24
40.96
t
ms
CHG
(1)
120
(1)
120
t
Time to discharge external capacitor, C
—
0.0001
1
5
10
2.0
ms/µF
µF
DIS
EXT
C
Capacitance of external ramping capacitor
Number of counts for I to charge C
0.1
EXT
N
to V
X
1024
65536
counts
CHG
EXT
Prescaler into timing function (÷ P)
Using core timer
Using 16-bit programmable timer
Using software loops
8
8
24
8
8
8
8
P
÷ P
user defined user defined
Clock source frequency
(excluding any prescaling)
Refer to 15.12 Control Timing (5.0 Vdc)
and 15.13 Control Timing (3.0 Vdc)
f
OSC
1. Limited by requirement for CEXT to be less than 2.0 µF.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
121
MOTOROLA
Analog Subsystem
Ana log Sub syste m
Table 8-5. Sample Conversion Timing (V = 5.0 Vdc)
DD
V
f
t
C
EXT
X
OSC
CHG
Bits Counts
A/D Method
Clock Source
(Vdc)
(MHz)
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
(ms)
3.840
0.384
0.192
0.096
1.280
0.128
0.064
0.032
15.36
1.536
0.768
0.384
5.120
0.512
0.256
0.128
61.44
6.144
3.072
1.536
20.48
2.048
1.024
0.512
(µF)
Low Power Oscillator
External Pin Oscillator
Low Power Oscillator
External Pin Oscillator
Low Power Oscillator
External Pin Oscillator
Low Power Oscillator
External Pin Oscillator
Low Power Oscillator
External Pin Oscillator
Low Power Oscillator
External Pin Oscillator
Low Power Oscillator
External Pin Oscillator
Low Power Oscillator
External Pin Oscillator
0.110
0.011
0.006
0.003
0.037
0.004
0.002
0.001
0.439
0.044
0.022
0.011
0.585
0.059
0.029
0.015
1.755
0.176
0.088
0.044
0.585
0.059
0.029
0.015
Software Loop
(12 bus cycles)
4
4
16
16
3.5
(24 f
cycles)
OSC
Mode 0 or 1 (manual)
Programmable Timer
(prescaler = 8)
Mode 2 or 3
(TOF->ICF or OCF->ICF)
3.5
3.5
3.5
3.5
3.5
3.5
3.5
Software Loop
(12 bus cycles)
6
64
(24 f
cycles)
OSC
Mode 0 or 1 (manual)
Programmable Timer
(prescaler = 8)
Mode 2 or 3
(TOF->ICF or OCF->ICF)
6
64
Software Loop
(12 bus cycles)
8
256
256
1024
4096
(24 f
cycles)
OSC
Mode 0 or 1 (manual)
Programmable Timer
(prescaler = 8)
Mode 2 or 3
(TOF->ICF or OCF->ICF)
8
(note 1) (note 1)
Programmable Timer
(prescaler = 8)
Mode 2 or 3
(TOF->ICF or OCF->ICF)
8.192
4.096
2.048
0.234
0.117
0.059
10
12
(note 1) (note 1)
Programmable Timer
(prescaler = 8)
Mode 2 or 3
(TOF->ICF or OCF->ICF)
32.768
16.384
8.192
0.936
0.468
0.234
1. Not usable as the value of CEXT would be greater than 2.0 µF
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Analog Subsystem MOTOROLA
122
Analog Subsystem
A/D Conversion Methods
The mode selection bits in the ACR allow four methods of single-slope
A/D conversion. Each of these methods is shown in the following figures
using the signal names and parameters given in Table 8-4.
• Manual start and stop (mode 0) Figure 8-8
• Manual start and automatic discharge (mode 1) Figure 8-9
• Automatic start and stop from TOF to ICF (mode 2) Figure 8-10
• Automatic start and stop from OCF to ICF (mode 3) Figure 8-11
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
123
Analog Subsystem
Ana log Sub syste m
t
DIS
t
t
DIS
t
DIS
MAX
(MIN)
(MIN)
V
CAP
V
MAX
t
CHG
t
x I
CHG CHG
V
V =
X
X
C
EXT
CHG
COMP2
TOF
OCF
ICF
0
2
3
4
5
1
Point
Action
Software/Hardware Action
Dependent Variable(s)
Begin initial discharge and select mode 0
by clearing the CHG, ATD2, and ATD1
control bits in the ACR.
0
Software write
Software
1
2
V
falls to V
.
Wait out minimum t
Software write
time
V
, I , C
MAX DIS EXT
CAP
SS
DIS
Stop discharge and begin charge by setting
CHG control bit in ACR.
Software
V
rises to V and comparator 2 output
X
trips, setting CPF2 and CMP2.
CAP
3
4
Wait out t
None
time
V , I
, C
CHG EXT
CHG
X
V
reaches V
.
V
, I
, C
CAP
MAX
MAX CHG EXT
Begin next discharge by clearing the CHG
control bit in the ACR. Reset CPF2 by
writing a “1” to CPFR2.
5
Software write
Software
Figure 8-8. A/D Conversion — Full Manual Control (Mode 0)
General Release Specification
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MOTOROLA
Analog Subsystem
Analog Subsystem
A/D Conversion Methods
t
DIS
t
t
DIS
DIS
(MIN)
(MIN)
V
CAP
V
MAX
t
CHG
t
x I
CHG CHG
V
V =
X
X
C
EXT
CHG
COMP2
TOF
OCF
ICF
0
1
2
3
1
2
Point
Action
Software/Hardware Action
Dependent Variable(s)
Begin initial discharge and select
mode 1 by clearing CHG and
ATD2 and setting ATD1 in the
ACR.
0
Software write
Software
1
2
V
falls to V
.
Wait out minimum t
Software write
time
V
, I , C
MAX DIS EXT
CAP
SS
DIS
Stop discharge and begin charge by
setting CHG control bit in ACR.
Software
V
rises to V and comparator 2
X
CAP
output trips, setting CPF2 and
CMP2, which clears CHG control
bit in the ACR. Reset CPF2 by
writing a “1” to CPFR2.
Wait out t
CPF2 clears CHG control bit
time.
CHG
3
V , I
, C
CHG EXT
X
Figure 8-9. A/D Conversion — Manual/Auto Discharge Control (Mode 1)
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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General Release Specification
125
Analog Subsystem
Ana log Sub syste m
t
DIS
t
t
DIS
DIS
(MIN)
(MIN)
V
CAP
V
MAX
t
CHG
t
x I
CHG CHG
V
V =
X
X
C
EXT
CHG
COMP2
(TCAP)
TOF
OCF
ICF
0
1
2
3
1
2
Point
Action
Software/Hardware Action
Dependent Variable(s)
Begin initial discharge and select mode
2 by clearing CHG and ATD1 and
setting ATD2 in the ACR. Also set
ICEN bit in ACR and IEDG bit in TCR.
0
Software write
Software
1
2
V
falls to V
.
Wait out minimum t
time
V
, I , C
MAX DIS EXT
CAP
SS
DIS
Stop discharge and begin charge when
the next TOF sets the CHG control bit
in ACR.
Timer TOF sets the CHG control Free-running timer
bit in the ACR. counter overflow, f
OSC
V
rises to V and comparator 2
X
CAP
output trips, setting CPF2 and CMP2,
which causes an ICF from the timer
and clears the CHG control bit in ACR.
Must clear CPF2 in order to trap next
CPF2 flag.
Wait out t
Timer ICF clears the CHG
control bit in the ACR.
time
CHG
3
V , I
, C
CHG EXT
X
Figure 8-10. A/D Conversion — TOF/ICF Control (Mode 2)
General Release Specification
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MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
A/D Conversion Methods
t
DIS
t
t
DIS
DIS
(MIN)
(MIN)
V
CAP
V
MAX
t
CHG
t
x I
CHG CHG
V
V =
X
X
C
EXT
CHG
COMP2
(TCAP)
TOF
OCF
ICF
0
1
2
3
1
2
Point
Action
Software/Hardware Action
Dependent Variable(s)
Begin initial discharge and select mode
3 by clearing CHG and setting ATD2
and ATD1 in the ACR. Also set ICEN
bit in ACR and IEDG bit in TCR.
0
Software write
Software
V
falls to V . Set timer output
SS
compare registers (OCRH and OCRL)
to desired charge start time.
CAP
Wait out minimum t
Software write to OCRH, OCRL.
time.
V
, I , C
software
,
DIS
MAX DIS
EXT
1
2
Stop discharge and begin charge when
the next OCF sets the CHG control bit
in ACR.
Timer OCF sets the CHG control Free-running timer
bit in the ACR. output compare, f
OSC
V
rises to V and comparator 2
X
CAP
output trips, setting CPF2 and CMP2,
which causes an ICF from the timer
and clears the CHG control bit in ACR.
Must clear CPF2 in order to trap next
CPF2 flag. Load next OCF.
Wait out t
Timer ICF clears the CHG
control bit in the ACR.
time.
CHG
3
V , I
, C
CHG EXT
X
Figure 8-11. A/D Conversion — OCF/ICF Control (Mode 3)
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
127
Analog Subsystem
Ana log Sub syste m
8.7 Volta g e Me a sure m e nt Me thod s
The methods for obtaining a voltage measurement can use software
techniques to express these voltages as absolute or ratiometric
readings.
In most applications the external capacitor, the clock source, the
reference voltage and the charging current may vary between devices
and with changes in supply voltage or ambient temperature. All of these
variations must be considered when determining the desired resolution
of the measurement. The maximum and minimum extremes for the full
scale count will be:
N
= C
x V
x f
/ (P x I
)
CHGMAX
FSMIN
EXTMIN
FSMIN
OSCMIN
N
= C
x V
x f
/ (P x I
)
CHGMIN
FSMAX
EXTMAX
FSMAX
OSCMAX
The minimum count should be the desired resolution; and the counting
mechanism must be capable of counting to the maximum. The final
scaling of the count will be by a math routine which calculates:
V = V
x (N - N
) / (N
- N
)
X
REF
X
OFF
REF
OFF
Where:
V
V
= Known reference voltage
= Unknown voltage between V and V
REF
X
SS
REF
N
N
N
= Conversion count for unknown voltage
= Conversion count for known reference voltage (V
= Conversion count for minimum reference voltage (V )
X
)
REF
REF
OFF
SS
When V
is a stable voltage source such as a zener or other reference
REF
source, then the unknown voltage will be determined as an absolute
reading. If V is the supply source to the device (V ), then the
REF
DD
unknown voltage will be determined as a ratio of V , or a ratiometric
DD
reading.
If the unknown voltage applied to the comparator is greater than its
common-mode range (V –1.5 volts), then the external capacitor will
DD
try to charge to the same level. This will cause both comparator inputs
to be above the common-mode range and the output of the comparator
will be indeterminate. In this case the comparator output flags may also
be set even if the actual voltage on the positive input (+) is less than the
General Release Specification
128
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
Voltage Measurement Methods
voltage on the negative input (–). All A/D conversion methods should
have a maximum time check to determine if this case is occurring.
Once the maximum timeout detection has been made, the state of the
comparator outputs can be tested in order to determine the situation.
However, such tests should be carefully designed when using modes 1,
2, or 3 as these modes cause the immediate automatic discharge of the
external ramping capacitor before any software check can be made of
the output state of comparator 2.
NOTE: All A/D conversion methods should include a test for a maximum
elapsed time in order to detect error cases where the inputs may be
outside of the design specification.
8.7.1 Ab solute Volta g e Re a d ing s
The absolute value of a voltage measurement can be calculated in
software by first taking a reference reading from a fixed source and then
comparing subsequent unknown voltages to that reading as a
percentage of the reference voltage multiplied times the known
reference value.
The accuracy of absolute readings will depend on the error sources
taken into account using the features of the analog subsystem and
appropriate software as described in Table 8-6. As can be seen from this
table, most of the errors can be reduced by frequent comparisons to a
known voltage, use of the inverted comparator inputs, and averaging of
multiple samples.
8.7.1.1 Inte rna l Ab so lute Re fe re nc e
If a stable source of V is provided, the reference measurement point
DD
can be internally selected. In this case the reference reading can be
taken by setting the V
bit and clearing the MUX1:4 bits in the AMUX
REF
register. This connects the channel selection bus to the V pin. In order
DD
to stay within the V
range the DHOLD bit should be used to select
MAX
the 1/2 divided input.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
Analog Subsystem
129
Ana log Sub syste m
8.7.1.2 Exte rna l Ab so lute Re fe re nc e
If a stable external source is provided, the reference measurement point
can be any one of the channel selected pins from PB1–PB4. In this case
the reference reading can be taken by setting the MUX bit in the AMUX
which connects channel selection bus to the pin connected to the
external reference source. If the external reference is greater than
V
–1.5 volts, then the DHOLD bit should be used to select the 1/2
DD
divided input.
Table 8-6. Absolute Voltage Reading Errors
Accuracy Improvements Possible
Error Source
In Hardware
In Software
Change in reference
voltage
Calibration and storage of reference source
over temperature and supply voltage
Provide closer tolerance reference
Change in magnitude of
ramp current source
Compare unknown with recent
measurement from reference
Not adjustable
Non-linearity of ramp
current source vs.
voltage
Calibration and storage of voltages at 1/4,
1/2, 3/4, and FS
Not adjustable
Change in magnitude of
ramp capacitor
Compare unknown with recent
measurement from reference
Provide closer tolerance ramp capacitor
Use external oscillator with crystal
Frequency shift in
internal low-power
oscillator
Compare unknown with recent
measurement from reference
Frequency shift in
external oscillator
Compare unknown with recent
measurement from reference
Provide closer tolerance crystal
Use faster conversion times
Sampling capacitor
leakage
Compare unknown with recent
measurement from reference
Compare unknown with recent
measurement from reference OR avoid
use of divided input
Internal voltage divider
ratio
Not adjustable
Not adjustable
Sum two readings on reference or
unknown using INV and INV control bit
and divide by 2 (average of both)
Input offset voltage of
comparator 2
Close decoupling at V and V pins
and reduce supply source impedance
Average multiple readings on both the
reference and the unknown voltage
DD
SS
Noise internal to MCU
Noise external to MCU
Close decoupling of power supply, low
source impedances, good board
layout, use of multi-layer board
Average multiple readings on both the
reference and the unknown voltage
General Release Specification
130
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
Voltage Measurement Methods
8.7.2 Ra tiom e tric Volta g e Re a d ing s
The ratiometric value of a voltage measurement can be calculated in
software by first taking a reference reading from a reference source and
then comparing subsequent unknown voltages to that reading as a
percentage of the reference value. The accuracy of ratiometric readings
will depend on the variety of sources, but will generally be better than for
absolute readings. Many of these error sources can be taken into
account using the features of the analog subsystem and appropriate
software as described in Table 8-7. As with absolute measurements,
most of the errors can be reduced by frequent comparisons to the
reference voltage, use of the inverted comparator inputs, and averaging
of multiple samples.
8.7.2.1 Inte rna l Ra tio m e tric Re fe re nc e
If readings are to be ratiometric to V , the reference measurement
DD
point can be internally selected. In this case the reference reading can
be taken by setting the V
bit and clearing the MUX1:4 bits in the
REF
AMUX register which connects the channel selection bus to the V pin.
DD
In order to stay within the V
range the DHOLD bit should be used to
MAX
select the 1/2 divided input.
8.7.2.2 Exte rna l Ra tio m e tric Re fe re nc e
If readings are to be ratiometric to some external source, the reference
measurement point can be connected to any one of the channel selected
pins from PB1–PB4. In this case, the reference reading can be taken by
setting the MUX bit in the AMUX which connects channel selection bus
to the pin connected to the external reference source. If the external
reference is greater than V –1.5 volts, then the DHOLD bit should be
DD
used to select the 1/2 divided input.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
131
Analog Subsystem
Ana log Sub syste m
Table 8-7. Ratiometric Voltage Reading Errors
Accuracy Improvements Possible
Error Source
In Hardware
In Software
Change in reference
voltage
Compare unknown with recent
measurement from reference
Not required for ratiometric
Change in magnitude of
ramp current source
Compare unknown with recent
measurement from reference
Not adjustable
Non-linearity of ramp
current source vs. voltage
Calibration and storage of voltages at
1/4, 1/2, 3/4, and FS
Not adjustable
Change in magnitude of
ramp capacitor
Compare unknown with recent
measurement from reference
Not required for ratiometric
Not required for ratiometric
Not required for ratiometric
Frequency shift in internal
low-power oscillator
Compare unknown with recent
measurement from reference
Frequency shift in external
oscillator
Compare unknown with recent
measurement from reference
Compare unknown with recent
measurement from reference
Sampling capacitor leakage Use faster conversion times
Internal voltage divider ratio Not adjustable
Compare unknown with recent
measurement from reference
Sum two readings on reference or
unknown using INV and INV control bit
and divide by 2 (average of both)
Input offset voltage of
Not adjustable
comparator 2
Close decoupling at V and V pins
and reduce supply source impedance
Average multiple readings on both the
reference and the unknown voltage
DD
SS
Noise internal to MCU
Noise external to MCU
Close decoupling of power supply, low
source impedances, good board
layout, use of multi-layer board
Average multiple readings on both the
reference and the unknown voltage
General Release Specification
132
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Analog Subsystem
Analog Subsystem
Voltage Comparator Features
8.8 Volta g e Com p a ra tor Fe a ture s
The two internal comparators can be used as simple voltage
comparators if set up as described in Table 8-8. Both comparators can
be active in the Wait mode; and can directly restart the part by means of
the analog interrupt. Both comparators can also be active in the stop
mode, but cannot directly restart the part. However, the comparators can
directly drive PB4 which can then be connected externally to activate
either a port interrupt on the PA0:3 pins or the IRQ/V pin.
PP
Table 8-8. Voltage Comparator Setup Conditions
Prog. Timer
Input
Capture
Source
Current Discharge
Port B Pin
Pulldowns
Disabled
Port B Pin
as Inputs
Comparator Source
Device
Enable
Disable
Not
Affected
Not
Affected
DDRB2 = 0 PDIB2 = 1
DDRB3 = 0 PDIB3 = 1
Not
Affected
1
2
DDRB0 = 0 PDIB0 = 1
DDRB1 = 0 PDIB1 = 1
ICEN = 0
IEDG = 1
ISEN = 0 ISEN = 0
8.8.1 Volta g e Com p a ra tor 1
Voltage comparator 1 is always connected to two of the port B I/O pins.
These pins should be configured as inputs and have their software
programmable pulldowns disabled. Also, the negative input of voltage
comparator 1 is connected to the PB3/AN3/TCAP and shared with the
input capture function of the 16-bit programmable timer. Therefore, the
timer input capture interrupt should be disabled so that changes in the
voltage on the PB3/AN3/TCAP pin do not cause unwanted input capture
interrupts.
The output of comparator 1 can be connected to the port logic driving the
PB4/AN4/TCMP/CMP1 pin such that the output of the comparator is
ORed with the PB4 data bit and the OLVL bit from the 16-bit timer. This
capability requires that the OPT bit is set in the COPR at location $1FF0
and the COE1 bit is set in the ASR at location $001E.
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Analog Subsystem
Ana log Sub syste m
8.8.2 Volta g e Com p a ra tor 2
Voltage comparator 2 can be used as a simple comparator if its charge
current source and discharge device are disabled by clearing the ISEN
bit in the ACR. If the ISEN bit is set, the internal ramp discharge device
connected to PB0/AN0 may become active and try to pull down any
voltage source that may be connected to that pin. Also, since voltage
comparator 2 is always connected to two of the port B I/O pins, these
pins should be configured as inputs and have their software
programmable pulldowns disabled.
8.9 Curre nt Sourc e Fe a ture s
The internal current source connected to the PB0/AN0 pin supplies
about 100 µA of current when the discharge device is disabled and the
current source is active. Therefore, this current source can be used in an
application if the ISEN enable bit is set to power up the current source
and by setting the A/D conversion method to manual mode 0 (ATD1 and
ATD2 cleared) and the charge current enabled (CHG set).
8.10 Inte rna l Te m p e ra ture Se nsing Diod e Fe a ture s
An internal diode is forward biased to V and will have its voltage
SS
change approximately 2 mV for each degree centigrade rise in the
temperature of the device. This temperature sensing diode is powered
up from a current source only during the time that the diode is selected.
When on, this current source adds about 30 µA to the I current.
DD
The temperature sensing diode can be selected by setting both the
HOLD and DHOLD bits in the AMUX register (see 8.3 Analog Multiplex
Register).
8.11 Sa m p le a nd Hold
When using the internal sample capacitor to capture a voltage for later
conversion, the HOLD or DHOLD bit must be cleared first before
changing any channel selection. If both the HOLD (or DHOLD) bit and
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Analog Subsystem
Analog Subsystem
Port B Interaction with Analog Inputs
the channel selection are changed on the same write cycle, the sample
may be corrupted during the switching transitions.
NOTE: The sample capacitor can be affected by excessive noise created with
respect to the device’s V pin such that it may appear to leak down or
SS
charge up depending on the voltage level stored on the sample
capacitor. It is recommended to avoid switching large currents through
the port pins while a voltage is to remain stored on the sample capacitor.
The additional option of adding an offset voltage to the bottom of the
sample capacitor allows unknown voltages near V to be sampled and
SS
then shifted up past the comparator offset and the device offset caused
by a single V return pin. This offset also provides a means to measure
SS
the internal V level regardless of the comparator offset in order to
SS
determine N
as described in 8.7 Voltage Measurement Methods.
OFF
In either case the OPT bit must be set in the COPR located at $1FF0 and
the VOFF bit must be set in the ASR. It is not necessary to switch the
VOFF bit during conversions, since the offset is controlled by the HOLD
and DHOLD bits when the VOFF is active. Refer to 8.3 Analog
Multiplex Register for more details on the design and decoding of the
sample and hold circuit.
8.12 Port B Inte ra c tion with Ana log Inp uts
The analog subsystem is connected directly to the port B I/O pins without
any intervening gates. It is, therefore, possible to measure the voltages
on port B pins set as inputs or to have the analog voltage measurements
corrupted by port B pins set as outputs.
8.13 Port B Pins As Inp uts
All the port B pins will power up as inputs or return to inputs after a reset
of the device since the bits in the port B data direction register will be
reset.
If any port B pins are to be used for analog voltage measurements, they
should be left as inputs. In this case, not only can the voltage on the pin
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Analog Subsystem
Ana log Sub syste m
be measured, but the logic state of the port B pins can be read from
location $0002.
8.14 Port B Pulld owns
All the port B pins have internal software programmable pulldown
devices available dependent on the state of the SWPDI bit in the mask
option register (MOR).
If the pulldowns are enabled, they will create an approximate 100 µA
load to any analog source connected to the pin. In some cases, the
analog source may be able to supply this current without causing any
error due to the analog source output impedance. Since this may not
always be true, it is therefore best to disable port B pulldowns on those
pins used for analog input sources.
8.15 Noise Se nsitivity
In addition to the normal effects of electrical noise on the analog input
signal there can also be other noise related effects caused by the digital-
to-analog interface. Since there is only one V return for both the digital
SS
and the analog subsystems on the device, currents in the digital section
may affect the analog ground reference within the device. This can add
voltage offsets to measured inputs or cause channel-to-channel
crosstalk.
In order to reduce the impact of these effects, there should be no
switching of heavy I/O currents to or from the device while there is a
critical analog conversion or voltage comparison in process. Limiting
switched I/O currents to 2–4 mA during these times is recommended.
A noise reduction benefit can be gained with 0.1 µF bypass capacitors
from each analog input (PB4:1) to the V pin. Also, try to keep all the
SS
digital power supply or load currents from passing through any
conductors which are the return paths for an analog signal.
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Analog Subsystem
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 9. Sim p le Se ria l Inte rfa c e
9.1 Conte nts
9.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.3
SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . .140
9.3.1
9.3.2
9.3.3
9.4
SIOP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . .141
SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . .144
SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . .145
9.4.1
9.4.2
9.4.3
9.2 Introd uc tion
The simple synchronous serial I/O port (SIOP) subsystem is designed to
provide efficient serial communications with peripheral devices or other
MCUs. SIOP is implemented as a 3-wire master/slave system with serial
clock (SCK), serial data input (SDI), and serial data output (SDO). A
block diagram of the SIOP is shown in Figure 9-1.
The SIOP subsystem shares its input/output pins with port B. When the
SIOP is enabled (SPE bit set in the SCR), the port B data direction and
data registers are bypassed by the SIOP. The port B data direction and
data registers will remain accessible and can be altered by the
application software, but these actions will not affect the SIOP
transmitted or received data.
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Simple Serial Interface
Sim p le Se ria l Inte rfa c e
PORTB LOGIC
PORTB LOGIC
OSCILL
CLOCK
÷2
CLOCK
DIVIDER
AND
CLOCK
CONTROL
SPR0
SPR1
CPHA
MSTR
SPE
PB7
SCK
SELECT
LSBF
SPIR
SPIE
PB6
SDI
PORTB LOGIC
$000A
DIN
DOUT
CLK
LATCH
SIOP
INTERRUPT
8-BIT SHIFT
REGISTER
COMP
Q
S
ERROR
PB5
SDO
SPIF
R
DCOL
FORMAT CONTROL
(LSB OR MSB FIRST)
$000B
SIOP
DATA REGISTER
(SDR)
$000C
INTERNAL HC05 BUS
Figure 9-1. SIOP Block Diagram
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Simple Serial Interface
Simple Serial Interface
SIOP Signal Format
9.3 SIOP Sig na l Form a t
The SIOP subsystem can be software configured for master or slave
operation. No external mode selection inputs are available (for instance,
no slave select pin).
9.3.1 Se ria l Cloc k (SCK)
The state of the SCK output remains a fixed logic level during idle
periods between data transfers. The edges of SCK indicate the
beginning of each output data transfer and latch any incoming data
received. The first bit of transmitted data is output from the SDO pin on
the first falling edge of SCK. The first bit of received data is accepted at
the SDI pin on the first rising edge of SCK after the first falling edge. The
transfer is terminated upon the eighth rising edge of SCK.
The idle state of the SCK is determined by the state of the CPHA bit in
the SCR. When the CPHA is clear, SCK will remain idle at a logical one
as shown in Figure 9-2. When the CPHA is set, SCK will remain idle at
a logical zero as shown in Figure 9-3. In both cases, the SDO changes
data on the falling edge of the SCK, and the SDI latches data in on the
rising edge of SCK.
The master and slave modes of operation differ only in the means of
sourcing the SCK. In master mode, SCK is driven from an internal
source within the MCU. In slave mode, SCK is driven from a source
external to the MCU. The SCK frequency is based on one of four
divisions of the oscillator clock that is selected by the SPR0 and SPR1
bits in the SCR.
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
SDO
SCK
(IDLE = 1)
(CPHA = 0)
100 ns
100 ns
SDI
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
Figure 9-2. SIOP Timing Diagram (CPHA = 0)
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Simple Serial Interface
Sim p le Se ria l Inte rfa c e
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
SDO
(IDLE = 0)
SCK
(CPHA = 1)
100 ns
100 ns
SDI
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
Figure 9-3. SIOP Timing Diagram (CPHA = 1)
9.3.2 Se ria l Da ta Inp ut (SDI)
The SDI pin becomes an input as soon as the SIOP subsystem is
enabled. New data is presented to the SDI pin on the falling edge of
SCK. Valid data must be present at least 100 nanoseconds before the
rising edge of SCK and remain valid for 100 nanoseconds after the rising
edge of SCK. See Figure 9-3.
9.3.3 Se ria l Da ta Outp ut (SDO)
The SDO pin becomes an output as soon as the SIOP subsystem is
enabled. The state of the PB5/SDO pin reflects the value of the first bit
received on the previous transmission. Prior to enabling the SIOP, the
PB5/SDO can be initialized to determine the beginning state. While
SIOP is enabled, the port B logic cannot be used as a standard output
since that pin is connected to the last stage of the SIOP serial shift
register. A control bit (LSBF) is included in the SCR to allow the data to
be transmitted in either the MSB first format or the LSB first format.
The first data bit will be shifted out to the SDO pin on the first falling edge
of the SCK. The remaining data bits will be shifted out to the SDI pin on
subsequent falling edges of SCK. The SDO pin will present valid data at
least 100 nanoseconds before the rising edge of the SCK and remain
valid for 100 nanoseconds after the rising edge of SCK. See Figure 9-3.
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Simple Serial Interface
Simple Serial Interface
SIOP Registers
9.4 SIOP Re g iste rs
The SIOP is programmed and controlled by the SIOP control register
(SCR) located at address $000A, the SIOP status register (SSR) located
at address $000B, and the SIOP data register (SDR) located at address
$000C.
9.4.1 SIOP Control Re g iste r (SCR)
The SIOP control register (SCR) is located at address $000A and
contains seven control bits and a write-only reset of the interrupt flag.
Figure 9-4 shows the position of each bit in the register and indicates
the value of each bit after reset.
$000A
Read:
Write:
Reset:
Bit 7
SPIE
0
6
SPE
0
5
LSBF
0
4
MSTR
0
3
0
2
CPHA
0
1
SPR1
0
Bit 0
SPR0
0
SPIR
0
Figure 9-4. SIOP Control Register (SCR)
SPIE — Serial Peripheral Interrupt Enable
The SPIE bit enables the SIOP to generate an interrupt whenever the
SPIF flag bit in the SSR is set. Clearing the SPIE bit will not affect the
state of the SPIF flag bit and will not terminate a serial interrupt once
the interrupt sequence has started. Reset clears the SPIE bit.
1 = Serial interrupt enabled
0 = Serial interrupt disabled
NOTE: If the SPIE bit is cleared just after the serial interrupt sequence has
started (for instance, the CPU status is being stacked), then the CPU will
be unable to determine the source of the interrupt and will vector to the
reset vector as a default.
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Simple Serial Interface
Sim p le Se ria l Inte rfa c e
SPE — Serial Peripheral Enable
The SPE bit switches the port B interface such that SDO/PB5 is the
serial data output, SDI/PB6 is the serial data input, and SCK/PB7 is a
serial clock input in the slave mode or a serial clock output in the
master mode. The port B DDR and data registers can be manipulated
as usual, but these actions will not affect the transmitted or received
data. The SPE bit is readable and writable at any time, but clearing
the SPE bit while a transmission is in progress will 1) abort the
transmission, 2) reset the serial bit counter, and 3) convert port B to a
general-purpose I/O port. Reset clears the SPE bit.
1 = Serial peripheral enabled (port B I/O disabled)
0 = Serial peripheral disabled (port B I/O enabled)
LSBF — Least Significant Bit First
The LSBF bit controls the format of the transmitted and received data
to be transferred LSB or MSB first. Reset clears this bit.
1 = LSB transferred first
0 = MSB transferred first
MSTR — Master Mode Select
The MSTR bit configures the serial I/O port for master mode. A
transfer is initiated by writing to the SDR. Also, the SCK pin becomes
an output providing a synchronous data clock dependent upon the
divider of the oscillator frequency selected by the SPR0:1 bits. When
the device is in master mode, the SDO and SDI pins do not change
function. These pins behave exactly the same in both the master and
slave modes. The MSTR bit is readable and writable at any time
regardless of the state of the SPE bit. Clearing the MSTR bit will abort
any transfers that may have been in progress. Reset clears the MSTR
bit, placing the SIOP subsystem in slave mode.
1 = SIOP set up as master, SCK is an output
0 = SIOP set up as slave, SCK is an input
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Simple Serial Interface
Simple Serial Interface
SIOP Registers
SPIR — Serial Peripheral Interrupt Reset
The SPIR bit is a write-only control to reset the SPIF flag bit in the
SSR. Reading the SPIR bit will return a logical zero.
1 = Reset the SPIF flag bit
0 = No effect
CPHA — Clock Phase
The CPHA bit controls the clock timing and phase in the SIOP. Data
is changed on the falling edge of SCK and data is captured (read) on
the rising edge of SCK. This bit is cleared by reset.
1 = SCK is idle low
0 = SCK is idle high
SPR0:1 — Serial Peripheral Clock Rate Selects
The SPR0 and SPR1 bits select one of four clock rates given in Table
9-1 to be supplied on the PB7/SCK pin when the device is configured
with the SIOP as a master (MSTR = 1). The fastest rate is when both
SPR0 and SPR1 are set. Both the SPR0 and SPR1 bits are cleared
by reset, which places the SIOP clock selection at the slowest rate.
Table 9-1. SIOP Clock Rate Selection
SIOP Clock Rate
(Oscillator Frequency
Divided by:)
SPR1
SPR0
0
0
1
1
0
1
0
1
64
32
16
8
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Simple Serial Interface
Sim p le Se ria l Inte rfa c e
9.4.2 SIOP Sta tus Re g iste r (SSR)
The SIOP status register (SSR) is located at address $000B and
contains two read-only bits. Figure 9-5 shows the position of each bit in
the register and indicates the value of each bit after reset.
$000B
Read:
Write:
Reset:
Bit 7
6
5
0
4
0
3
0
2
0
1
0
Bit 0
0
SPIF
DCOL
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-5. SIOP Status Register (SSR)
SPIF — Serial Port Interrupt Flag
The SPIF is a read-only status bit that is set on the last rising edge of
SCK and indicates that a data transfer has been completed. It has no
effect on any future data transfers and can be ignored. The SPIF bit
can be cleared by reading the SSR followed by a read or write of the
SDR or by writing a logical one to the SPIR bit in the SCR. If the SPIF
is cleared before the last rising edge of SCK it will be set again on the
last rising edge of SCK. Reset clears the SPIF bit.
1 = Serial transfer complete, serial interrupt if the SPIE bit in SCR
is set
0 = Serial transfer in progress or serial interface idle
DCOL — Data Collision
The DCOL is a read-only status bit which indicates that an illegal
access of the SDR has occurred. The DCOL bit will be set when
reading or writing the SDR after the first falling edge of SCK and
before SPIF is set. Reading or writing the SDR during this time will
result in invalid data being transmitted or received. The DCOL bit is
cleared by reading the SSR (when the SPIF bit is set) followed by a
read or write of the SDR. If the last part of the clearing sequence is
done after another transfer has started, the DCOL bit will be set again.
Reset clears the DCOL bit.
1 = Illegal access of the SDR occurred
0 = No illegal access of the SDR detected
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Simple Serial Interface
Simple Serial Interface
SIOP Registers
9.4.3 SIOP Da ta Re g iste r (SDR)
The SIOP data register (SDR) is located at address $000C and serves
as both the transmit and receive data register. Writing to this register will
initiate a message transmission if the node is in master mode. The SIOP
subsystem is not double buffered and any write to this register will
destroy the previous contents. The SDR can be read at any time.
However, if a transfer is in progress the results may be ambiguous.
Writing to the SDR while a transfer is in progress can cause invalid data
to be transmitted and/or received. Figure 9-6 shows the position of each
bit in the register. This register is not affected by reset.
$000C
Read:
Write:
Reset:
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Unaffected by Reset
Figure 9-6. SIOP Data Register (SDR)
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Simple Serial Interface
Sim p le Se ria l Inte rfa c e
General Release Specification
146
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Simple Serial Interface
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 10. Core Tim e r
10.1 Conte nts
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
10.3 Core Timer Status and Control Register (CTSCR). . . . . . . . .149
10.4 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . . .151
10.5 COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.2 Introd uc tion
This section describes the operation of the core timer and the COP
watchdog as shown by the block diagram in Figure 10-1.
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Core Timer
Core Tim e r
RESET
INTERNAL
CLOCK
$0009
OVERFLOW
CORE TIMER COUNTER REGISTER
÷ 4
÷ 2
OSC1
BITS 0–7 OF 15-STAGE
RIPPLE COUNTER
INTERNAL CLOCK ÷ 1024
CORE TIMER
INTERRUPT
REQUEST
$0008
CORE TIMER STATUS/CONTROL REGISTER
RESET
RTI RATE SELECT
$1FF0
COP REGISTER
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
POWER-ON
RESET
COP
WATCHDOG
RESET
RESET
Figure 10-1. Core Timer Block Diagram
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Core Timer
Core Timer
Core Timer Status and Control Register (CTSCR)
10.3 Core Tim e r Sta tus a nd Control Re g iste r (CTSCR)
The read/write core timer status and control register (CTSCR) contains
the interrupt flag bits, interrupt enable bits, interrupt flag bit resets, and
the rate selects for the real time interrupt as shown in Figure 10-2.
$0008
Read:
Write:
Reset:
Bit 7
6
5
CTOFE
0
4
RTIE
0
3
2
1
RT1
1
Bit 0
RT0
1
CTOF
RTIF
0
CTOFR
0
0
RTIFR
0
0
0
= Unimplemented
Figure 10-2. Core Timer Status and Control Register (CTSCR)
CTOF — Core Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the core
timer counter roll over from $FF to $00. The CTOF flag bit generates
a timer overflow interrupt request if CTOFE is also set. The CTOF flag
bit is cleared by writing a logic one to the CTOFR bit. Writing to CTOF
has no effect. Reset clears CTOF.
1 = Overflow in core timer has occurred
0 = No overflow of core timer since CTOF last cleared
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected real time interrupt
(RTI) output becomes active. RTIF generates a real-time interrupt
request if RTIE is also set. The RTIF enable bit is cleared by writing a
logic one to the RTIFR bit. Writing to RTIF has no effect. Reset clears
RTIF.
1 = Overflow in real-time counter has occurred
0 = No overflow of real-time counter since RTIF last cleared
CTOFE — Core Timer Overflow Interrupt Enable
This read/write bit enables core timer overflow interrupts. Reset
clears CTOFE.
1 = Core timer overflow interrupts enabled
0 = Core timer overflow interrupts disabled
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Core Timer
Core Tim e r
RTIE — Real-Time Interrupt Enable
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
CTOFR — Core Timer Overflow Flag Reset
Writing a logic one to this write-only bit clears the CTOF bit. CTOFR
always reads as a logic zero. Reset does not affect CTOFR.
1 = Clear CTOF flag bit
0 = No effect on CTOF flag bit
RTIFR — Real-Time Interrupt Flag Reset
Writing a logic one to this write-only bit clears the RTIF bit. RTIFR
always reads as a logic zero. Reset does not affect RTIFR.
1 = Clear RTIF flag bit
0 = No effect on RTIF flag bit
RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0
These read/write bits select one of four real-time interrupt rates, as
shown in Table 10-1. Because the selected RTI output drives the
COP watchdog, changing the real -time interrupt rate also changes
the counting rate of the COP watchdog. Reset sets RT1 and RT0,
selecting the longest COP timeout period and longest real-time
interrupt period.
NOTE: Changing RT1 and RT0 when a COP timeout is imminent or uncertain
may cause a real-time interrupt request to be missed or an additional
real-time interrupt request to be generated. Clear the COP timer just
before changing RT1 and RT0.
General Release Specification
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Core Timer
Core Timer
Core Timer Counter Register (CTCR)
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
Timer Overflow
Interrupt Period
Real-Time
Interrupt Period
(RTI)
COP Timeout Period
COP = 7 to 8 RTI Periods
(milliseconds)
11
TOF = 1/(f
÷ 2 )
OSC
RTI
(milliseconds)
(microseconds)
Rate
= f
RT1 RT0
OSC
divided
by:
@ f (MHz)
@ f
(MHz)
@ f
(MHz)
OSC
OSC
OSC
4.2 MHz
Min Max
7.80 16.4 32.8 54.6 62.4
2.0 MHz
1.0 MHz
4.2
2.0
1.0
4.2
2.0
1.0
MHz MHz MHz
MHz MHz MHz
Min
Max
131
262
524
Min
Max
262
524
15
0
0
1
1
0
1
0
1
2
115
229
459
229
459
16
2
15.6 32.8 65.5
109
218
437
125
250
499
488 1024 2048
17
2
31.2 65.5
62.4 131
131
262
918 1049
18
2
918 1049 1835 2097
10.4 Core Tim e r Counte r Re g iste r (CTCR)
A 15-stage ripple counter driven by a divide-by-eight prescaler is the
basis of the core timer. The value of the first eight stages is readable at
any time from the read-only timer counter register as shown in
Figure 10-3.
$0009
Read:
Write:
Reset:
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-3. Core Timer Counter Register (CTCR)
Power-on clears the entire counter chain and begins clocking the
counter. After the startup delay (16 or 4064 internal bus cycles
depending on the DELAY bit in the mask option register (MOR)), the
power-on reset circuit is released, clearing the counter again and
allowing the MCU to come out of reset.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
151
Core Timer
Core Tim e r
Each count of the timer counter register takes eight oscillator cycles or
four cycles of the internal bus. A timer overflow function at the eighth
counter stage allows a timer interrupt every 2048 oscillator clock cycles
or every 1024 internal bus cycles.
10.5 COP Wa tc hd og
Four counter stages at the end of the core timer make up the computer
operating properly (COP) watchdog which can be enabled by the
COPEN bit in the MOR. The COP watchdog is a software error detection
system that automatically times out and resets the MCU if the COP
watchdog is not cleared periodically by a program sequence. Writing a
logic zero to COPC bit in the COP register clears the COP watchdog and
prevents a COP reset.
$1FF0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
OPT
Write: EPMSEC
Reset:
COPC
Unaffected by Reset
= Unimplemented
Figure 10-4. COP and Security Register (COPR)
1
EPMSEC — EPROM Security
The EPMSEC bit is a write-only security bit to protect the contents of
the user EPROM code stored in locations $0700–$1FFF.
OPT — Optional Features
The OPT bit enables two additional features: direct drive by
comparator outputs to port A; and voltage offset capability to sample
capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
General Release Specification
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MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Core Timer
Core Timer
COP Watchdog
COPC — COP Clear
This write-only bit resets the COP watchdog. The COP watchdog is
active in the run, wait, and halt modes of operation if the COP is
enabled by setting the COPEN bit in the MOR. The STOP instruction
disables the COP watchdog by clearing the counter and turning off its
clock source.
In applications that depend on the COP watchdog, the STOP
instruction can be disabled by setting the SWAIT bit in the MOR. In
applications that have wait cycles longer than the COP timeout
period, the COP watchdog can be disabled by clearing the COPEN
bit. Table 10-2 summarizes recommended conditions for enabling
and disabling the COP watchdog.
NOTE: If the voltage on the IRQ/V pin exceeds 1.5 × V , the COP watchdog
PP
DD
turns off and remains off until the IRQ/V pin voltage falls below
PP
1.5 × V .
DD
Table 10-2. COP Watchdog Recommendations
SWAIT
Voltage on
Recommended COP
Watchdog Condition
Wait/Halt Time
1
IRQ/V Pin
(in MOR)
PP
2
Less than 1.5 × V
Less than 1.5 × V
Less than 1.5 × V
1
1
0
X
Less than COP Timeout Period
Greater than COP Timeout Period
Enabled
DD
DD
DD
Disabled
Disabled
Disabled
3
X
More than 1.5 × V
X
DD
NOTES:
1. The SWAIT bit in the MOR converts STOP instructions to HALT instructions.
2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction.
3. X = don’t care.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
153
MOTOROLA
Core Timer
Core Tim e r
General Release Specification
154
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Core Timer
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 11. Prog ra m m a b le Tim e r
11.1 Conte nts
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.3 Timer Registers (TMRH and TMRL). . . . . . . . . . . . . . . . . . . .158
11.4 Alternate Counter Registers (ACRH and ACRL) . . . . . . . . . .160
11.5 Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . . .162
11.6 Output Compare Registers (OCRH and OCRL). . . . . . . . . . .164
11.7 Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . .166
11.8 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . .168
11.9 Timer Operation During Wait Mode . . . . . . . . . . . . . . . . . . . .169
11.10 Timer Operation During Stop Mode . . . . . . . . . . . . . . . . . . . .169
11.11 Timer Operation During Halt Mode. . . . . . . . . . . . . . . . . . . . .169
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
155
Programmable Timer
Prog ra m m a b le Tim e r
11.2 Introd uc tion
The MC68HC705JJ7/MC68HC705JP7 MCU contains a 16-bit
programmable timer with an input capture function and an output
compare function as shown by the block diagram in Figure 11-1.
The basis of the capture/compare timer is a 16-bit free-running counter
which increases in count with every four internal bus clock cycles. The
counter is the timing reference for the input capture and output compare
functions. The input capture and output compare functions provide a
means to latch the times at which external events occur, to measure
input waveforms, and to generate output waveforms and timing delays.
Software can read the value in the 16-bit free-running counter at any
time without affecting the counter sequence.
The I/O registers for the input capture and output compare functions are
pairs of 8-bit registers, because of the 16-bit timer architecture used.
Each register pair contains the high and low bytes of that function.
Generally, accessing the low byte of a specific timer function allows full
control of that function; however, an access of the high byte inhibits that
specific timer function until the low byte is also accessed.
Because the counter is 16 bits long and preceded by a fixed divide-by-
four prescaler, the counter rolls over every 262,144 internal clock cycles
(every 524,288 oscillator clock cycles). Timer resolution with a 4-MHz
crystal oscillator is 2 microsecond/count.
The interrupt capability, the input capture edge, and the output compare
state are controlled by the timer control register (TCR) located at $0012,
and the status of the interrupt flags can be read from the timer status
register (TSR) located at $0013.
General Release Specification
156
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Programmable Timer
Programmable Timer
Introduction
PB3
AN3
TCAP
EDGE
SELECT
& DETECT
LOGIC
INPUT
SELECT
MUX
ICRH ($0014)
TMRH ($0018)
ICRL ($0015)
TMRL ($0019)
ACRH ($001A)
ACRL ($001B)
CPF2
FLAG
BIT
FROM
ANALOG
SUBSYSTEM
INTERNAL
CLOCK
(OSC ÷ 2)
16-BIT COUNTER
÷ 4
ICEN
CONTROL
BIT
16-BIT COMPARATOR
PB4
D Q
C
PIN I/O
LOGIC
AN4
TCMP
OCRH ($0016)
OCRL ($0017)
ANALOG
COMP 1
TIMER
INTERRUPT
REQUEST
RESET
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
$0013
$0012
INTERNAL DATA BUS
Figure 11-1. Programmable Timer Overall Block Diagram
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
157
Programmable Timer
Prog ra m m a b le Tim e r
11.3 Tim e r Re g iste rs (TMRH a nd TMRL)
The functional block diagram of the 16-bit free-running timer counter and
timer registers is shown in Figure 11-2. The timer registers include a
transparent buffer latch on the LSB of the 16-bit timer counter.
READ
TMRL
LATCH
TMRL ($0019)
TMR LSB
READ
TMRH
READ
TMRH ($0018)
($FFFC)
INTERNAL
CLOCK
(OSC ÷ 2)
RESET
÷ 4
16-BIT COUNTER
OVERFLOW (TOF)
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REG.
TIMER STATUS REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 11-2. Programmable Timer Block Diagram
The timer registers (TMRH and TMRL) shown in Figure 11-3 are read-
only locations which contain the current high and low bytes of the 16-bit
free-running counter. Writing to the timer registers has no effect. Reset
of the device presets the timer counter to $FFFC.
General Release Specification
158
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Programmable Timer
Programmable Timer
Timer Registers (TMRH and TMRL)
$0018
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Bit 15
14
13
12
11
10
1
1
1
1
1
1
1
1
$0019
Read:
Write:
Reset:
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
1
1
1
1
1
1
0
0
= Unimplemented
Figure 11-3. Programmable Timer Registers (TMRH and TMRL)
The TMRL latch is a transparent read of the LSB until a read of the
TMRH takes place. A read of the TMRH latches the LSB into the TMRL
location until the TMRL is again read. The latched value remains fixed
even if multiple reads of the TMRH take place before the next read of the
TMRL. Therefore, when reading the MSB of the timer at TMRH, the LSB
of the timer at TMRL must also be read to complete the read sequence.
During power-on reset (POR), the counter is initialized to $FFFC and
begins counting after the oscillator startup delay. Because the counter is
16 bits and preceded by a fixed prescaler, the value in the counter
repeats every 262,144 internal bus clock cycles (524,288 oscillator
cycles).
When the free-running counter rolls over from $FFFF to $0000, the timer
overflow flag bit (TOF) is set in the TSR. When the TOF is set, it can
generate an interrupt if the timer overflow interrupt enable bit (TOIE) is
also set in the TCR. The TOF flag bit can only be reset by reading the
TMRL after reading the TSR.
Other than clearing any possible TOF flags, reading the TMRH and
TMRL in any order or any number of times does not have any effect on
the 16-bit free-running counter.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
159
Programmable Timer
Prog ra m m a b le Tim e r
NOTE: To prevent interrupts from occurring between readings of the TMRH and
TMRL, set the I bit in the condition code register (CCR) before reading
TMRH and clear the I bit after reading TMRL.
11.4 Alte rna te Counte r Re g iste rs (ACRH a nd ACRL)
The functional block diagram of the 16-bit free-running timer counter and
alternate counter registers is shown in Figure 11-4. The alternate
counter registers behave the same as the timer registers, except that
any reads of the alternate counter will not have any effect on the TOF
flag bit and timer interrupts. The alternate counter registers include a
transparent buffer latch on the LSB of the 16-bit timer counter.
INTERNAL
DATA
BUS
READ
ACRL
LATCH
ACRL ($001B)
TMR LSB
READ
ACRH
READ
ACRH ($001A)
($FFFC)
INTERNAL
CLOCK
(OSC ÷ 2)
RESET
÷ 4
16-BIT COUNTER
Figure 11-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH and ACRL) shown in
Figure 11-5 are read-only locations which contain the current high and
low bytes of the 16-bit free-running counter. Writing to the alternate
counter registers has no effect. Reset of the device presets the timer
counter to $FFFC.
General Release Specification
160
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Programmable Timer
Programmable Timer
Alternate Counter Registers (ACRH and ACRL)
$001A
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Bit 15
14
13
12
11
10
1
1
1
1
1
1
1
1
$001B
Read:
Write:
Reset:
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
1
1
1
1
1
1
0
0
= Unimplemented
Figure 11-5. Alternate Counter Registers (ACRH and ACRL)
The ACRL latch is a transparent read of the LSB until a read of the
ACRH takes place. A read of the ACRH latches the LSB into the ACRL
location until the ACRL is again read. The latched value remains fixed
even if multiple reads of the ACRH take place before the next read of the
ACRL. Therefore, when reading the MSB of the timer at ACRH, the LSB
of the timer at ACRL must also be read to complete the read sequence.
During power-on reset (POR), the counter is initialized to $FFFC and
begins counting after the oscillator startup delay. Because the counter is
16 bits and preceded by a fixed prescaler, the value in the counter
repeats every 262,144 internal bus clock cycles (524,288 oscillator
cycles).
Reading the ACRH and ACRL in any order or any number of times does
not have any effect on the 16-bit free-running counter or the TOF flag bit.
NOTE: To prevent interrupts from occurring between readings of the ACRH and
ACRL, set the I bit in the condition code register (CCR) before reading
ACRH and clear the I bit after reading ACRL.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
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Programmable Timer
Prog ra m m a b le Tim e r
11.5 Inp ut Ca p ture Re g iste rs (ICRH a nd ICRL)
The input capture function is a means to record the time at which an
event occurs. The source of the event can be the change on an external
pin (PB3/AN3/TCAP) or the CPF2 flag bit of voltage comparator 2 in the
analog subsystem. The ICEN bit in the analog subsystem control
register (ACR) at $001D selects which source is the input signal. When
the input capture circuitry detects an active edge on the selected source,
it latches the contents of the free-running timer counter registers into the
input capture registers as shown in Figure 11-6.
NOTE: Both the ICEN bit in the ACR and the IEDG bit in the TCR must be set
when using voltage comparator 2 to trigger the input capture function
Latching values into the input capture registers at successive edges of
the same polarity measures the period of the selected input signal.
Latching the counter values at successive edges of opposite polarity
measures the pulse width of the signal.
INTERNAL
DATA
BUS
READ
ICRH
PB3
AN3
TCAP
EDGE
SELECT
& DETECT
LOGIC
ICRH ($0014)
INPUT
SELECT
MUX
ICRL ($0015)
READ
ICRL
LATCH
INTERNAL
CLOCK
÷ 4
16-BIT COUNTER
INPUT CAPTURE (ICF)
CPF2
FLAG
BIT
(OSC ÷ 2)
TIMER
INTERRUPT
REQUEST
FROM
ANALOG
SUBSYSTEM
ICEN
CONTROL
BIT
RESET
TIMER CONTROL REG.
TIMER STATUS REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 11-6. Timer Input Capture Block Diagram
General Release Specification
162
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Programmable Timer
Programmable Timer
Input Capture Registers (ICRH and ICRL)
The input capture registers are made up of two 8-bit read-only registers
(ICRH and ICRL) as shown in Figure 11-7. The input capture edge
detector contains a Schmitt trigger to improve noise immunity. The edge
that triggers the counter transfer is defined by the input edge bit (IEDG)
in the TCR. Reset does not affect the contents of the input capture
registers.
The result obtained by an input capture will be one count higher than the
value of the free-running timer counter preceding the external transition.
This delay is required for internal synchronization. Resolution is affected
by the prescaler, allowing the free-running timer counter to increment
once every four internal clock cycles (eight oscillator clock cycles).
$0014
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Bit 15
14
13
12
11
10
Unaffected by Reset
$0015
Read:
Write:
Reset:
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Unaffected by Reset
= Unimplemented
Figure 11-7. Input Capture Registers (ICRH and ICRL)
Reading the ICRH inhibits future captures until the ICRL is also read.
Reading the ICRL after reading the timer status register (TSR) clears the
ICF flag bit. There is no conflict between reading the ICRL and transfers
from the free-running timer counters. The input capture registers always
contain the free-running timer counter value which corresponds to the
most recent input capture.
NOTE: To prevent interrupts from occurring between readings of the ICRH and
ICRL, set the I bit in the condition code register (CCR) before reading
ICRH and clear the I bit after reading ICRL.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
163
Programmable Timer
Prog ra m m a b le Tim e r
11.6 Outp ut Com p a re Re g iste rs (OCRH a nd OCRL)
The output compare function is a means of generating an output signal
when the 16-bit timer counter reaches a selected value as shown in
Figure 11-8. Software writes the selected value into the output compare
registers. On every fourth internal clock cycle (every eight oscillator
clock cycles) the output compare circuitry compares the value of the
free-running timer counter to the value written in the output compare
registers. When a match occurs, the timer transfers the output level
(OLVL) from the timer control register (TCR) to the PB4/AN4/TCMP pin.
Software can use the output compare register to measure time periods,
to generate timing delays, or to generate a pulse of specific duration or
a pulse train of specific frequency and duty cycle on the PB4/AN4/TCMP
pin.
R/W
OCRH
R/W
OCRL
OCRH ($0016)
OCRL ($0017)
EDGE
SELECT
DETECT
LOGIC
PB4
16-BIT COMPARATOR
AN4
TCMP
($FFFC)
INTERNAL
CLOCK
(OSC ÷ 2)
÷ 4
16-BIT COUNTER
OUTPUT COMPARE
(OCF)
TIMER
INTERRUPT
REQUEST
RESET
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 11-8. Timer Output Compare Block Diagram
General Release Specification
164
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Programmable Timer
Programmable Timer
Output Compare Registers (OCRH and OCRL)
The planned action on the PB4/AN4/TCMP pin depends on the value
stored in the OLVL bit in the TCR, and it occurs when the value of the
16-bit free-running timer counter matches the value in the output
compare registers shown in Figure 11-9. These registers are read/write
bits and are unaffected by reset.
Writing to the OCRH before writing to the OCRL inhibits timer compares
until the OCRL is written. Reading or writing to the OCRL after reading
the TCR will clear the output compare flag bit (OCF). The output
compare OLVL state will be clocked to its output latch regardless of the
state of the OCF.
$0016
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Bit 15
14
13
12
11
10
Unaffected by Reset
$0017
Read:
Write:
Reset:
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Unaffected by Reset
Figure 11-9. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use the following procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is
written.
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This
also clears the OCF flag bit in the TSR.
5. Enable interrupts by clearing the I bit in the condition code
register.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
165
Programmable Timer
Prog ra m m a b le Tim e r
A software example of this procedure is shown in Table 11-1.
Table 11-1. Output Compare Initialization Example
9B
...
SEI
...
DISABLE INTERRUPTS
.....
...
...
.....
B7
B6
BF
...
16
13
17
STA
LDA
STX
...
OCRH INHIBIT OUTPUT COMPARE
TSR
ARM OCF FLAG FOR CLEARING
OCRL READY FOR NEXT COMPARE, OCF CLEARED
.....
...
...
.....
9A
CLI
ENABLE INTERRUPTS
11.7 Tim e r Control Re g iste r (TCR)
The timer control register shown in Figure 11-10, performs the following
functions:
• Enables input capture interrupts
• Enables output compare interrupts
• Enables timer overflow interrupts
• Controls the active edge polarity of the TCAP signal
• Controls the active level of the TCMP output
Reset clears all the bits in the TCR with the exception of the IEDG bit
which is unaffected.
$0012
Read:
Write:
Reset:
Bit 7
ICIE
0
6
OCIE
0
5
TOIE
0
4
0
3
0
2
0
1
IEDG
U
Bit 0
OLVL
0
0
0
0
= Unimplemented
U = Unaffected
Figure 11-10. Timer Control Register (TCR)
General Release Specification
166
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Programmable Timer
Programmable Timer
Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable
This read/write bit enables interrupts caused by an active signal on
the TCAP pin or from CPF2 flag bit of the analog subsystem voltage
comparator 2. Reset clears the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable
This read/write bit enables interrupts caused by an active match of the
output compare function. Reset clears the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow.
Reset clears the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Capture Edge Select
The state of this read/write bit determines whether a positive or
negative transition triggers a transfer of the contents of the timer
register to the input capture register. This transfer can occur due to
transitions on the TCAP pin or the CPF2 flag bit of voltage comparator
2. Resets have no effect on the IEDG bit.
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
NOTE: The IEDG bit must be set when either Mode 2 or 3 of the analog
subsystem is being used for A/D conversions. Otherwise the input
capture will not occur on the rising edge of the comparator 2 flag.
OLVL — Output Compare Output Level Select
The state of this read/write bit determines whether a logic one or a
logic zero is transferred to the TCMP pin when a successful output
compare occurs. Resets clear the OLVL bit.
1 = Signal to TCMP pin goes high on output compare
0 = Signal to TCMP pin goes low on output compare
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
167
Programmable Timer
Prog ra m m a b le Tim e r
11.8 Tim e r Sta tus Re g iste r (TSR)
The timer status register (TSR) shown in Figure 11-11 contains flags for
the following events:
• An active signal on the TCAP pin or the CPF2 flag bit of voltage
comparator 2 in the analog subsystem, transferring the contents
of the timer registers to the input capture registers
• A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the PB4/AN4/TCMP pin if
that pin is set as an output
• An overflow of the timer registers from $FFFF to $0000
Writing to any of the bits in the TSR has no effect. Reset does not
change the state of any of the flag bits in the TSR.
$0013
Read:
Write:
Reset:
Bit 7
ICF
6
5
4
0
3
0
2
0
1
0
Bit 0
0
OCF
TOF
U
U
U
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 11-11. Timer Status Register (TSR)
ICF — Input Capture Flag
The ICF bit is automatically set when an edge of the selected polarity
occurs on the TCAP pin. Clear the ICF bit by reading the timer status
register with the ICF set, and then reading the low byte (ICRL, $0015)
of the input capture registers. Resets have no effect on ICF.
OCF — Output Compare Flag
The OCF bit is automatically set when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading the timer status register with the OCF set and then
accessing the low byte (OCRL, $0017) of the output compare
registers. Resets have no effect on OCF.
General Release Specification
168
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Programmable Timer
Programmable Timer
Timer Operation During Wait Mode
TOF — Timer Overflow Flag
The TOF bit is automatically set when the 16-bit timer counter rolls
over from $FFFF to $0000. Clear the TOF bit by reading the timer
status register with the TOF set and then accessing the low byte
(TMRL, $0019) of the timer registers. Resets have no effect on TOF.
11.9 Tim e r Op e ra tion During Wa it Mod e
During wait mode, the 16-bit timer continues to operate normally and
may generate an interrupt to trigger the MCU out of wait mode.
11.10 Tim e r Op e ra tion During Stop Mod e
When the MCU enters stop mode, the free-running counter stops
counting (the internal processor clock is stopped). It remains at that
particular count value until stop mode is exited by applying a low signal
to the IRQ/V pin, at which time the counter resumes from its stopped
PP
value as if nothing had happened. If stop mode is exited via an external
reset (logic low applied to the RESET pin), the counter is forced to
$FFFC.
If a valid input capture edge occurs during stop mode, the input capture
detect circuitry will be armed. This action does not set any flags or wake
up the MCU, but when the MCU does wake up there will be an active
input capture flag (and data) from the first valid edge. If the stop mode is
exited by an external reset, no input capture flag or data will be present
even if a valid input capture edge was detected during stop mode.
11.11 Tim e r Op e ra tion During Ha lt Mod e
When the MCU enters halt mode, the functions and states of the 16-bit
programmable timer are the same as for wait mode described in 11.9
Timer Operation During Wait Mode.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
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Programmable Timer
Prog ra m m a b le Tim e r
General Release Specification
170
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Programmable Timer
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 12. Pe rsona lity EPROM
12.1 Conte nts
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
12.3 PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
12.3.1
12.3.2
PEPROM Bit Select Register (PEBSR). . . . . . . . . . . . . . .173
PEPROM Status and Control Register (PESCR) . . . . . . .174
12.4 PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
12.5 PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
12.6 PEPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
12.2 Introd uc tion
This section describes how to program the 64-bit personality EPROM
(PEPROM). Figure 12-1 shows the structure of the PEPROM
subsystem.
NOTE: In packages with no quartz window, the PEPROM functions as one-time
programmable ROM (OTPROM).
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
171
Personality EPROM
Pe rsona lity EPROM
INTERNAL DATA BUS
PEPROM STATUS/CONTROL REGISTER
$000F
RESET
SINGLE
SENSE
AMPLIFIER
V
PP
ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
8-TO-1 COLUMN DECODER
AND MULTIPLEXER
8-TO-1 ROW DECODER
AND MULTIPLEXER
V
SWITCH
V SWITCH
PP
PP
ROW ZERO
DECODER
PEPROM BIT SELECT REGISTER
RESET
$000E
INTERNAL DATA BUS
Figure 12-1. Personality EPROM Block Diagram
General Release Specification
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MOTOROLA
Personality EPROM
Personality EPROM
PEPROM Registers
12.3 PEPROM Re g iste rs
Two I/O registers control programming and reading of the PEPROM:
• The PEPROM bit select register (PEBSR)
• The PEPROM status and control register (PESCR)
12.3.1 PEPROM Bit Se le c t Re g iste r (PEBSR)
The PEPROM bit select register (PEBSR) selects one of 64 bits in the
PEPROM array. Reset clears all the bits in the PEPROM bit select
register.
$000E
Read:
Write:
Reset:
Bit 7
PEB7
0
6
PEB6
0
5
PEB5
0
4
PEB4
0
3
PEB3
0
2
PEB2
0
1
PEB1
0
Bit 0
PEB0
0
Figure 12-2. PEPROM Bit Select Register (PEBSR)
PEB7 and PEB6 — Not connected to the PEPROM array
These read/write bits are available as storage locations. Reset clears
PEB7 and PEB6.
PEB5–PEB0 — PEPROM Bit Select Bits
These read/write bits select one of 64 bits in the PEPROM as shown
in Table 12-1. Bits PEB2–0 select the PEPROM row, and bits
PEB5–PEB3 select the PEPROM column. Reset clears PEB5–PEB0,
selecting the PEPROM bit in row zero, column zero.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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General Release Specification
173
Personality EPROM
Pe rsona lity EPROM
12.3.2 PEPROM Sta tus a nd Control Re g iste r (PESCR)
The PEPROM status and control register (PESCR) controls the
PEPROM programming voltage. This register also transfers the
PEPROM bits to the internal data bus and contains a flag bit when row
zero is selected.
$000F
Bit 7
6
0
5
PEPGM
0
4
0
3
2
0
1
0
Bit 0
Read: PEDATA
Write:
0
PEPRZF
R
R
0
R
0
Reset:
U
0
0
0
1
= Unimplemented
R
= Reserved
U = Unaffected
Figure 12-3. PEPROM Status and Control Register (PESCR)
PEDATA — PEPROM Data
This read-only bit is the output state of the PEPROM sense amplifier
and shows the state of the currently selected bit. The state of the
PEDATA bit does not affect the programming of the bit selected by the
PEBSR. Reset does not affect the PEDATA bit.
1 = PEPROM data is a logic one
0 = PEPROM data is a logic zero
PEPGM — PEPROM Program Control
This read/write bit controls the switches that apply the programming
voltage from the IRQ/V pin to the selected PEPROM bit cell. When
PP
the PEPGM bit is set the selected bit cell will be programmed to a
logical one, regardless of the state of the PEDATA bit. Reset clears
the PEPGM bit.
1 = Programming voltage applied to array bit
0 = Programming voltage not applied to array bit
General Release Specification
174
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Personality EPROM
MOTOROLA
Personality EPROM
PEPROM Registers
PEPRZF — PEPROM Row Zero Flag
This read-only bit is set when the PEPROM bit select register selects
the first row (row zero) of the PEPROM array. Selecting any other row
clears PEPRZF. Monitoring PEPRZF can reduce the code needed to
access one byte of eight PEPROM locations. Reset clears the
PEPROM bit select register, thereby setting the PEPRZF bit by
default.
1 = Row zero selected
0 = Row zero not selected
Table 12-1. PEPROM Bit Selection
PEBSR
PEPROM Bit Selected
$00
$01
|
Row 0
Column 0
Row 1
|
Column 0
|
V
V
V
$07
$08
$09
|
Row 7
Row 0
Row 1
|
Column 0
Column 1
Column 1
|
V
V
V
$37
$38
$39
|
Row 7
Row 0
Row 1
|
Column 6
Column 7
Column 7
|
V
V
V
$3E
$3F
Row 6
Row 7
Column 7
Column 7
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General Release Specification
175
Personality EPROM
Pe rsona lity EPROM
12.4 PEPROM Prog ra m m ing
Factory-provided software for programming the PEPROM is available
through the Motorola Freeware Bulletin Board Service (BBS). The
number is (512) 891-FREE. After making the connection, type bbs in
lowercase letters. Then press the return key to start the BBS software.
NOTE: While the PEPGM bit is set and the V voltage level is applied to the
PP
IRQ/V pin, do not access bits that are to be left unprogrammed
PP
(erased).
To program the PEPROM bits properly, the V voltage must be greater
DD
than 4.5 Vdc.
The PEPROM can also be programmed by user software with the V
PP
voltage level applied to the IRQ/V pin. The following sequence shows
PP
how to program each PEPROM bit:
1. Select a PEPROM bit by writing to the PEBSR.
2. Set the PEPGM bit in the PESCR.
3. Wait for the programming time, t
4. Clear the PEPGM bit.
.
EPGM
5. Move to next PEPROM bit to be programmed in step 1.
12.5 PEPROM Re a d ing
The following sequence shows how to read the PEPROM:
1. Select a bit by writing to the PEBSR.
2. Read the PEDATA bit in the PESCR.
3. Store the PEDATA bit in RAM or in a register.
4. Select another bit by changing the PEBSR.
5. Continue reading and storing the PEDATA bits until the required
personality EPROM data is retrieved and stored.
General Release Specification
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Personality EPROM
Personality EPROM
PEPROM Erasing
Reading the PEPROM is easiest when each PEPROM column contains
one byte. Selecting a row 0 bit selects the first bit, and incrementing the
PEPROM bit select register (PEBSR) selects the next bit in row 1 from
the same column. Incrementing PEBSR seven more times selects the
remaining bits of the column and ends up selecting the bit in row 0 of the
next column, thereby setting the row 0 flag, PEPRZF.
NOTE: A PEPROM byte that has been read can be transferred to the
personality EPROM bit select register (PEBSR) as a temporary storage
location such that subsequent reads of the PEBSR quickly yield that
PEPROM byte.
12.6 PEPROM Era sing
MCUs with windowed packages permit PEPROM erasure with
2
ultraviolet light. Erase the PEPROM by exposing it to 15 Ws/cm of
ultraviolet light with a wavelength of 2537 angstroms. Position the
ultraviolet light source 1 inch from the window. Do not use a shortwave
filter. The erased state of a PEPROM bit is a logic zero.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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General Release Specification
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Personality EPROM
Pe rsona lity EPROM
General Release Specification
178
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Personality EPROM
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 13. EPROM/ OTPROM
13.1 Conte nts
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.3 EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.3.1
13.3.2
13.3.3
EPROM Programming Register (EPROG) . . . . . . . . . . . .180
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . .181
EPROM Security Bit (EPMSEC) . . . . . . . . . . . . . . . . . . . .184
13.4 EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
13.4.1
13.4.2
MOR Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
EPMSEC Programming. . . . . . . . . . . . . . . . . . . . . . . . . . .186
13.5 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
13.2 Introd uc tion
This section describes how to program the 6160-byte
EPROM/OTPROM, the mask option register (MOR), and the EPROM
security bit (EPMSEC).
NOTE: In packages with no quartz window, the EPROM functions as one-time
programmable ROM (OTPROM).
13.3 EPROM Re g iste rs
The EPROM programming register (EPROG) controls the actual
programming of the EPROM bytes and the MOR. The mask option
register (MOR) controls eight mask options found on the ROM version
of this MCU. There is an additional EPROM bit (EPMSEC) located at the
COP address to provide EPROM array security.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
179
EPROM/OTPROM
EPROM/ OTPROM
13.3.1 EPROM Prog ra m m ing Re g iste r (EPROG)
The EPROM programming register shown in Figure 13-1 contains the
control bits for programming the EPROM. In normal operation, the
EPROM programming register contains all logic zeros.
$001C
Read:
Write:
Reset:
Bit 7
0
6
0
5
0
4
0
3
0
2
ELAT
0
1
MPGM
0
Bit 0
EPGM
0
R
0
R
0
R
0
R
0
0
= Unimplemented
R
= Reserved for test
Figure 13-1. EPROM Programming Register (EPROG)
EPGM — EPROM Programming
This read/write bit applies the voltage from the IRQ/V pin to the
PP
EPROM. To write the EPGM bit, the ELAT bit must already be set.
Clearing the ELAT bit also clears the EPGM bit. Reset clears EPGM.
1 = EPROM programming power switched on
0 = EPROM programming power switched off
MPGM — Mask Option Register (MOR) Programming
This read/write bit applies programming power from the IRQ/V pin
PP
to the MOR. Reset clears MPGM.
1 = MOR programming power switched on
0 = MOR programming power switched off
ELAT — EPROM Bus Latch
This read/write bit configures address and data buses for
programming the EPROM array. EPROM data cannot be read when
ELAT is set. Clearing the ELAT bit also clears the EPGM bit. Reset
clears ELAT.
1 = Address and data buses configured for EPROM programming
of the array. The address and data buses are latched in the
EPROM array when a subsequent write to the array is made.
Data in the EPROM array cannot be read.
0 = Address and data buses configured for normal operation
General Release Specification
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MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
EPROM/OTPROM
EPROM/OTPROM
EPROM Registers
Whenever the ELAT bit is cleared, the EPGM bit is also cleared. Both
the EPGM and the ELAT bit cannot be set using the same write
instruction. Any attempt to set both the ELAT and EPGM bit on the same
write instruction cycle will result in the ELAT bit being set and the EPGM
bit being cleared. To program a byte of EPROM, manipulate the EPROG
register as follows:
1. Set the ELAT bit in the EPROG register.
2. Write the desired data to the desired EPROM address.
3. Set the EPGM bit in the EPROG register for the specified
programming time, t
.
EPGM
4. Clear the ELAT and EPGM bits in the EPROG register.
13.3.2 Ma sk Op tion Re g iste r (MOR)
The mask option register (MOR) shown in Figure 13-2 is an EPROM
byte that controls eight mask options. The MOR is unaffected by reset.
The erased state of the MOR is $00. The options that can be
programmed by the MOR are:
1. Port software programmable pulldown devices (enable or disable)
2. Startup delay after stop (16 or 4064 cycles)
3. Oscillator shunt resistor (2 M or open)
4. STOP instruction (enable or disable)
5. Low-voltage reset (enable or disable)
6. Port A external interrupt function (enable or disable)
7. IRQ trigger sensitivity (edge-triggered only or both edge- and
level-triggered)
8. COP watchdog (enable or disable)
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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General Release Specification
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EPROM/OTPROM
EPROM/ OTPROM
$1FF1
Read:
Bit 7
6
5
4
3
2
1
Bit 0
SWPDI
DELAY OSCRES SWAIT
LVREN
PIRQ
LEVEL COPEN
Write:
Reset:
Erased:
Unaffected by Reset
0
0
0
0
0
0
0
0
Figure 13-2. Mask Option Register (MOR)
SWPDI — Software Pulldown Inhibit
This EPROM bit inhibits software control of the port A and port B
pulldown devices.
1 = Software pulldown inhibited
0 = Software pulldown enabled
DELAY — Stop Startup Delay
This EPROM bit selects the number of bus cycles that must elapse
before bus activity begins following a restart from the stop mode.
1 = Startup delay is 4064 bus cycles
0 = Startup delay is 16 bus cycles
CAUTION: The 16-cycle delay option will work properly in devices with the internal
low power oscillator or with a steady external clock source. Check
crystal/ceramic resonator specifications carefully before using the 16-
cycle delay option with a crystal or ceramic resonator.
OSCRES — Oscillator Resistor
This EPROM bit configures the on-chip oscillator an internal shunt
resistor.
1 = Oscillator configured with 2 M shunt resistor
0 = Oscillator configured without a shunt resistor
NOTE: The optional oscillator resistor is NOT recommended for devices that
use an external RC oscillator. For such devices, this bit should be left
erased as a zero.
General Release Specification
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EPROM/OTPROM
EPROM/OTPROM
EPROM Registers
SWAIT — STOP Conversion to WAIT
This EPROM bit disables the STOP instruction and prevents
inadvertently turning off the COP watchdog with a STOP instruction.
When the SWAIT bit is set, a STOP instruction puts the MCU in halt
mode. Halt mode is a wait-like low-power state. The internal oscillator
and timer clock continue to run, but the CPU clock stops. When the
SWAIT bit is clear, a STOP instruction stops the internal oscillator, the
internal clock, the CPU clock, the timer clock, and the COP watchdog
timer.
1 = STOP instruction converted to WAIT instruction
0 = STOP instruction not converted to WAIT instruction
LVREN — Low-Voltage Reset Enable
This EPROM bit enables the low-voltage reset (LVR) function.
1 = LVR function enabled
0 = LVR function disabled
PIRQ — Port A IRQ Enable
This EPROM bit enables the PA3–PA0 pins to function as external
interrupt sources.
1 = PA3–PA0 enabled as external interrupt sources
0 = PA3–PA0 not enabled as external interrupt sources
LEVEL — External Interrupt Sensitivity
This EPROM bit makes the external interrupt inputs level-triggered as
well as edge-triggered
1 = IRQ/V pin negative-edge triggered and low-level triggered;
PP
PA3–PA0 pins positive-edge triggered and high-level triggered
0 = IRQ/V pin negative-edge triggered only; PA3–PA0 pins
PP
positive-edge triggered only
COPEN — COP Watchdog Enable
This EPROM bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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General Release Specification
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EPROM/OTPROM
EPROM/ OTPROM
13.3.3 EPROM Se c urity Bit (EPMSEC)
An EPROM programmable bit is provided at the location of the COP
watchdog register at $1FF0 as shown in Figure 13-3. This bit allows
control of access to the EPROM array. Any accesses of the EPROM
locations will return undefined results when the EPMSEC bit is set. Refer
to 13.4.2 EPMSEC Programming for programming instructions.
$1FF0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
COPC
—
EPMSEC
OPT
Write:
Reset:
Erased:
Unaffected by Reset
0
—
—
—
—
—
—
= Unimplemented
Figure 13-3. EPROM Security in COP Register (COP)
1
EPMSEC — EPROM Security
This EPROM write-only bit enables the access to the EPROM array.
1 = Access to the EPROM array in non-user modes is denied
0 = Access to the EPROM array in non-user modes is enabled
13.4 EPROM Prog ra m m ing
A programming board is available from Motorola to download to the on-
chip EPROM/OTPROM using the factory-provided programming
software. Factory-provided software for programming the EPROM is
available through the Motorola Freeware Bulletin Board Service (BBS).
The number is (512) 891-FREE. After making the connection, type bbs
in lowercase letters and press the return key to start the BBS software.
The programming software copies to the 6144-byte space located at
EPROM addresses $0700–$1EFF and to the 16-byte space at
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
General Release Specification
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MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
EPROM/OTPROM
EPROM/OTPROM
EPROM Programming
addresses $1FF0–$1FFF which includes the mask option register at
address $1FF1, and the security bit at address $1FF0.
NOTE: To program the EPROM/OTPROM, MOR or EPMSEC bits properly, the
V
voltage must be greater than 4.5 volts.
DD
13.4.1 MOR Prog ra m m ing
The contents of the MOR should be programmed using the programmer
board. To program any bits in the MOR, the desired bit states must be
written to the MOR address and then the MPGM bit in the EPROG
register must be used. The following sequence will program the MOR:
1. Write the desired data to the MOR location ($1FF1).
2. Apply the programming voltage to the IRQ/V pin.
PP
3. Set the MPGM bit in the EPROG.
4. Wait for the programming time, t
.
MPGM
5. Clear the MPGM bit in the EPROG.
6. Remove the programming voltage from the IRQ/V pin.
PP
Once the MOR bits have been programmed, some of the options may
experience glitches in operation after removal of the programming
voltage. It is recommended that the part be reset before trying to verify
the contents of the user EPROM or the MOR itself.
NOTE: The contents of the EPROM or the MOR cannot be accessed if the
EPMSEC bit in the COP register has been set.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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EPROM/OTPROM
EPROM/ OTPROM
13.4.2 EPMSEC Prog ra m m ing
The state of the EPMSEC security bit should be programmed using the
programmer board. To program the EPMSEC bit, the desired state must
be written to the COP address and then the MPGM bit in the EPROG
register must be used. The following sequence will program the
EPMSEC bit:
1. Write the desired data to bit 7 of the COP location ($1FF0).
2. Apply the programming voltage to the IRQ/V pin.
PP
3. Set the MPGM bit in the EPROG.
4. Wait for the programming time, t
.
MPGM
5. Clear the MPGM bit in the EPROG.
6. Remove the programming voltage from the IRQ/V pin.
PP
Once the EPMSEC bit has been programmed to a logical one, access to
the contents of the EPROM and MOR in the expanded non-user modes
will be denied. It is therefore recommended that the user EPROM and
MOR in the part first be programmed and fully verified before setting the
EPMSEC bit.
13.5 EPROM Era sing
MCUs with windowed packages permit EPROM erasure with ultraviolet
2
light. Erase the EPROM by exposing it to 15 Ws/cm of ultraviolet light
with a wavelength of 2537 angstroms. Position the ultraviolet light
source 1 inch from the window. Do not use a shortwave filter. The erased
state of an EPROM bit is a logic zero.
NOTE: Unlike many commercial EPROMs, an erased EPROM byte will read as
$00. All unused locations should be programmed as zeros.
General Release Specification
186
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
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EPROM/OTPROM
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 14. Instruc tion Se t
14.1 Conte nts
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
14.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
14.3.1
14.3.2
14.3.3
14.3.4
14.3.5
14.3.6
14.3.7
14.3.8
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
14.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .192
Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . .193
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .194
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .196
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
14.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
14.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
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Instruc tion Se t
14.2 Introd uc tion
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
14.3 Ad d re ssing Mod e s
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
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Instruction Set
Addressing Modes
14.3.1 Inhe re nt
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
14.3.2 Im m e d ia te
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
14.3.3 Dire c t
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
14.3.4 Exte nd e d
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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Instruc tion Se t
14.3.5 Ind e xe d , No Offse t
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
14.3.6 Ind e xe d , 8-Bit Offse t
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
14.3.7 Ind e xe d ,16-Bit Offse t
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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Instruction Set
Instruction Types
14.3.8 Re la tive
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
14.4 Instruc tion Typ e s
The MCU instructions fall into the following five categories:
• Register/Memory Instructions
• Read-Modify-Write Instructions
• Jump/Branch Instructions
• Bit Manipulation Instructions
• Control Instructions
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Instruc tion Se t
14.4.1 Re g iste r/ Me m ory Instruc tions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 14-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Add Memory Byte to Accumulator
AND Memory Byte with Accumulator
Bit Test Accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare Accumulator
CMP
CPX
EOR
LDA
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Multiply
LDX
MUL
ORA
SBC
STA
OR Accumulator with Memory Byte
Subtract Memory Byte and Carry Bit from Accumulator
Store Accumulator in Memory
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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Instruction Set
Instruction Set
Instruction Types
14.4.2 Re a d -Mod ify-Write Instruc tions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE: Do not use read-modify-write operations on write-only registers.
Table 14-2. Read-Modify-Write Instructions
Instruction
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right
Bit Clear
Mnemonic
ASL
ASR
(1)
BCLR
(1)
Bit Set
BSET
Clear Register
CLR
COM
DEC
INC
Complement (One’s Complement)
Decrement
Increment
Logical Shift Left (Same as ASL)
Logical Shift Right
LSL
LSR
NEG
ROL
ROR
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
(2)
TST
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence be-
cause it does not write a replacement value.
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Instruc tion Se t
14.4.3 Jum p / Bra nc h Instruc tions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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Instruction Set
Instruction Set
Instruction Types
Table 14-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
Branch if Carry Bit Set
Branch if Equal
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
BHS
Branch if IRQ/V Pin High
BIH
PP
Branch if IRQ/V Pin Low
BIL
PP
Branch if Lower
BLO
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
BLS
BMC
BMI
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
BMS
BNE
BPL
Branch Always
BRA
Branch if Bit Clear
Branch Never
BRCLR
BRN
BRSET
BSR
Branch if Bit Set
Branch to Subroutine
Unconditional Jump
Jump to Subroutine
JMP
JSR
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Instruc tion Se t
14.4.4 Bit Ma nip ula tion Instruc tions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 14-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Bit Clear
Branch if Bit Clear
Branch if Bit Set
Bit Set
BRCLR
BRSET
BSET
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Instruction Set
Instruction Set
Instruction Types
14.4.5 Control Instruc tions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 14-5. Control Instructions
Instruction
Clear Carry Bit
Mnemonic
CLC
CLI
Clear Interrupt Mask
No Operation
NOP
RSP
RTI
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Set Carry Bit
RTS
SEC
SEI
Set Interrupt Mask
Stop Oscillator and Enable IRQ/V Pin
STOP
SWI
PP
Software Interrupt
Transfer Accumulator to Index Register
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
TAX
TXA
WAIT
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Instruction Set
Instruc tion Se t
14.5 Instruc tion Se t Sum m a ry
Table 14-6. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
ii
dd
hh ll
ee ff
ff
ADC #opr
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
2
3
4
5
4
3
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
Add without Carry
Logical AND
A ← (A) + (M) + (C)
↕ — ↕ ↕ ↕
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
2
3
4
5
4
3
A ← (A) + (M)
↕ — ↕ ↕ ↕
ii
dd
hh ll
ee ff
ff
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
2
3
4
5
4
3
A ← (A) (M)
— — ↕ ↕ —
dd
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
38
48
58
68
78
5
3
3
6
5
Arithmetic Shift Left (Same as LSL)
— — ↕ ↕ ↕ INH
C
0
IX1
IX
ff
b7
b7
b0
b0
dd
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
37
47
57
67
77
5
3
3
6
5
C
Arithmetic Shift Right
— — ↕ ↕ ↕ INH
IX1
IX
ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? C = 0
— — — — — REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
BCS rel
BEQ rel
BHCC rel
BHCS rel
BHI rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
25 rr
27 rr
28 rr
29 rr
22 rr
24 rr
3
3
3
3
3
3
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? C Z = 0 — — — — — REL
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL
BHS rel
Branch if Higher or Same
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Instruction Set
Instruction Set
Instruction Set Summary
Table 14-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
BIH rel
Branch if IRQ/V Pin High
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL
2F rr
2E rr
3
3
PP
BIL rel
Branch if IRQ/V Pin Low
PP
ii
dd
hh ll
ee ff
ff
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
2
3
4
5
4
3
Bit Test Accumulator with Memory Byte
(A) (M)
— — ↕ ↕ —
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? C = 1
— — — — — REL
25 rr
23 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? C Z = 1 — — — — — REL
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
PC ← (PC) + 2 + rel ? Mn = 1
— — — — ↕
BRN rel
Branch Never
— — — — — REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
— — — — ↕
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
Set Bit n
Mn ← 1
— — — — —
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
— — — — — REL
AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
— 0 — — —
INH
INH
98
9A
2
2
Clear Interrupt Mask
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Instruction Set
Instruc tion Se t
Table 14-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
dd
ff
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
5
3
3
6
5
Clear Byte
— — 0 1 —
ii
dd
hh ll
ee ff
ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
2
3
4
5
4
3
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
Decrement Byte
(A) – (M)
— — ↕ ↕ ↕
dd
ff
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
5
3
3
6
5
— — ↕ ↕
1
ii
dd
hh ll
ee ff
ff
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
2
3
4
5
4
3
(X) – (M)
— — ↕ ↕ ↕
— — ↕ ↕ —
— — ↕ ↕ —
dd
ff
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
5
3
3
6
5
ii
dd
hh ll
ee ff
ff
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
2
3
4
5
4
3
EXCLUSIVE OR Accumulator with Memory Byte
A ← (A) (M)
dd
ff
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
5
3
3
6
5
Increment Byte
— — ↕ ↕ —
dd
hh ll
ee ff
ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT CC
IX2
IX1
IX
BC
2
3
4
3
2
Unconditional Jump
PC ← Jump Address
— — — — —
DC
EC
FC
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Instruction Set
Instruction Set
Instruction Set Summary
Table 14-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
dd
hh ll
ee ff
ff
JSR opr
DIR
EXT CD
IX2
IX1
IX
BD
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
— — — — —
DD
ED
FD
ii
dd
hh ll
ee ff
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
2
3
4
5
4
3
Load Accumulator with Memory Byte
A ← (M)
X ← (M)
— — ↕ ↕ —
ii
dd
hh ll
ee ff
ff
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
2
3
4
5
4
3
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
— — ↕ ↕ —
dd
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
38
48
58
68
78
5
3
3
6
5
C
0
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
ff
dd
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
34
44
54
64
74
5
3
3
6
5
0
C
Logical Shift Right
— — 0 ↕ ↕ INH
b7
b0
IX1
IX
ff
MUL
Unsigned Multiply
X : A ← (X) × (A)
0 — — — 0
INH
42
11
dd
ff
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
30
40
50
60
70
5
3
3
6
5
Negate Byte (Two’s Complement)
No Operation
— — ↕ ↕ ↕ INH
IX1
IX
NOP
— — — — —
INH
9D
2
ii
dd
hh ll
ee ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
2
3
4
5
4
3
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
A ← (A) (M)
— — ↕ ↕ —
dd
ff
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
39
49
59
69
79
5
3
3
6
5
C
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
201
Instruction Set
Instruc tion Se t
Table 14-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
dd
ff
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
36
46
56
66
76
5
3
3
6
5
C
Rotate Byte Right through Carry Bit
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $00FF
— — — — —
INH
9C
2
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
↕ ↕ ↕ ↕ ↕ INH
80
9
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
— — — — —
INH
81
6
ii
dd
hh ll
ee ff
ff
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
2
3
4
5
4
3
Subtract Memory Byte and Carry Bit from
Accumulator
A ← (A) – (M) – (C)
— — ↕ ↕ ↕
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
— 1 — — —
INH
INH
99
9B
2
2
Set Interrupt Mask
dd
hh ll
ee ff
ff
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
4
5
6
5
4
Store Accumulator in Memory
M ← (A)
— — ↕ ↕ —
— 0 — — —
— — ↕ ↕ —
STOP
Stop Oscillator and Enable IRQ/V Pin
INH
8E
2
PP
dd
hh ll
ee ff
ff
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
4
5
6
5
4
Store Index Register In Memory
M ← (X)
ii
dd
hh ll
ee ff
ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
2
3
4
5
4
3
Subtract Memory Byte from Accumulator
A ← (A) – (M)
— — ↕ ↕ ↕
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
TAX
Software Interrupt
— 1 — — —
— — — — —
INH
INH
83
97
10
2
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Transfer Accumulator to Index Register
X ← (A)
General Release Specification
202
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Instruction Set
Instruction Set
Opcode Map
Table 14-6. Instruction Set Summary (Continued)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
dd
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
4
3
3
5
4
Test Memory Byte for Negative or Zero
(M) – $00
— — ↕ ↕ —
ff
TXA
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
A ← (X)
— — — — —
— 0 — — —
INH
INH
9F
8F
2
2
WAIT
A
C
Accumulator
Carry/borrow flag
opr Operand (one or two bytes)
PC Program counter
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DIR Direct addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
Relative program counter offset byte
Relative program counter offset byte
SP Stack pointer
ff
H
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
X
Z
#
Index register
Zero flag
Immediate value
Logical AND
hh ll High and low bytes of operand address in extended addressing
I
Interrupt mask
ii
Immediate operand byte
Logical OR
IMM Immediate addressing mode
INH Inherent addressing mode
Logical EXCLUSIVE OR
Contents of
( )
IX
IX1
IX2
M
N
n
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
–( ) Negation (two’s complement)
←
?
Loaded with
If
:
↕
—
Concatenated with
Set or cleared
Not affected
14.6 Op c od e Ma p
See Table 14-7.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
203
Instruction Set
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Table 14-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
INH
IX1
IX
7
INH
INH
IMM
A
DIR
B
EXT
IX2
IX1
E
IX
F
MSB
LSB
MSB
LSB
0
1
2
4
5
6
8
9
C
D
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
SUB
SUB
SUB
SUB
SUB
SUB
CMP
SBC
CPX
AND
BIT
0
1
0
3
DIR 2
5
BRCLR0
DIR 2
5
BRSET1
DIR 2
5
BRCLR1
DIR 2
5
BRSET2
DIR 2
5
BRCLR2
DIR 2
5
BRSET3
DIR 2
5
BRCLR3
DIR 2
5
BRSET4
DIR 2
5
BRCLR4
DIR 2
5
BRSET5
DIR 2
5
BRCLR5
DIR 2
5
BRSET6
DIR 2
5
BRCLR6
DIR 2
5
BRSET7
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
6
RTS
INH
2
2
2
2
2
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
CMP
IX2 2
IX1 1
4
CMP
IX1 1
IX
3
BCLR0
BRN
CMP
CMP
CMP
1
2
3
3
DIR 2
5
REL
3
1
IMM 2
2
DIR 3
3
EXT 3
4
IX
3
11
5
4
BSET1
BHI
MUL
SBC
SBC
SBC
SBC
CPX
AND
BIT
SBC
CPX
AND
BIT
2
DIR 2
5
REL
3
1
5
INH
3
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
3
6
5
10
SWI
INH
BCLR1
BLS
COM
COMA
COMX
COM
COM
LSR
CPX
CPX
CPX
3
3
3
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX 1
5
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET2
BCC
LSR
LSRA
LSRX
LSR
AND
AND
AND
4
4
DIR 2
5
BCLR2 BCS/BLO
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BIT
BIT
BIT
5
5
3
3
DIR 2
5
REL
3
IMM 2
2
DIR 3
3
LDA
DIR 3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
5
3
3
6
5
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
ASR
LDA
LDA
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDA
STA
6
6
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
IMM 2
EXT 3
5
IX2 2
6
IX1 1
5
IX
4
2
4
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
STA
7
7
3
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
1
1
1
1
1
1
1
INH
2
2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
CLC
EOR
EOR
EOR
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
8
8
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
DEC
SEC
ADC
ADC
ADC
9
9
3
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET5
BPL
DEC
DECA
DECX
DEC
CLI
SEI
ORA
ORA
ORA
A
B
C
D
E
F
A
B
C
D
E
F
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BCLR5
BMI
ADD
ADD
ADD
3
3
DIR 2
5
REL
3
INH 2
2
IMM 2
DIR 3
2
EXT 3
3
IX2 2
4
IX1 1
3
IX
2
5
3
3
6
5
BSET6
BMC
INC
INCA
INCX
INC
TST
INC
TST
RSP
INH
JMP
JMP
DIR 2
5
REL 2
3
DIR 1
4
INH 1
3
INH 2
3
IX1 1
5
IX
4
2
6
DIR 3
5
EXT 3
6
IX2 2
7
IX1 1
6
IX
5
2
BCLR6
BMS
TST
TSTA
TSTX
NOP
BSR
JSR
JSR
3
3
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
REL 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
2
BSET7
BIL
STOP
LDX
LDX
LDX
LDX
STX
DIR 2
5
DIR 2
5
BCLR7
DIR 2
REL
3
BIH
REL 2
1
INH
2
WAIT
INH 1
2
2
IMM 2
DIR 3
4
EXT 3
5
STX
EXT 3
IX2 2
6
IX1 1
5
IX
4
5
3
3
6
5
BRCLR7
CLR
DIR 1
CLRA
INH 1
CLRX
INH 2
CLR
CLR
TXA
INH
STX
3
DIR 2
IX1 1
IX 1
2
DIR 3
IX2 2
IX1 1
IX
MSB
INH = Inherent
IMM = Immediate
DIR = Direct
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
MSB of Opcode in Hexadecimal
Number of Cycles
0
LSB
5
BRSET0 Opcode Mnemonic
DIR Number of Bytes/Addressing Mode
LSB of Opcode in Hexadecimal
0
EXT = Extended
3
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 15. Ele c tric a l Sp e c ific a tions
15.1 Conte nts
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
15.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .207
15.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
15.6 Supply Current Characteristics (V = 4.5 to 5.5 Vdc). . . . . .208
DD
15.7 Supply Current Characteristics (V = 2.7 to 3.3 Vdc). . . . . .209
DD
15.8 DC Electrical Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . .210
15.9 DC Electrical Characteristics (3.0 Vdc). . . . . . . . . . . . . . . . . .211
15.10 Analog Subsystem Characteristics (5.0 Vdc) . . . . . . . . . . . . .212
15.11 Analog Subsystem Characteristics (3.0 Vdc) . . . . . . . . . . . . .213
15.12 Control Timing (5.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
15.13 Control Timing (3.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
15.14 PEPROM and EPROM Programming Characteristics . . . . . .216
15.15 SIOP Timing (V = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . .216
DD
15.16 SIOP Timing (V = 3.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . .217
DD
15.17 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
15.2 Introd uc tion
This section contains the electrical and timing specifications.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
205
Electrical Specifications
Ele c tric a l Sp e c ific a tions
15.3 Ma xim um Ra ting s
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating
Supply Voltage
Symbol
Value
Unit
V
–0.3 to +7.0
V
DD
Bootloader/Self-Check Mode
V
V
–0.3 to 17
SS
V
IN
(IRQ/V Pin Only)
PP
Current Drain Per Pin Excluding V and V
I
25
mA
°C
DD
SS
Operating Junction Temperature
Storage Temperature Range
T
+150
J
T
–65 to +150
°C
stg
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 15.8 DC Electrical Characteristics (5.0 Vdc) and 15.9
DC Electrical Characteristics (3.0 Vdc) for guaranteed operating
conditions.
General Release Specification
206
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Electrical Specifications
Electrical Specifications
Operating Temperature Range
15.4 Op e ra ting Te m p e ra ture Ra ng e
Characteristic
Symbol
Value
T to T
Unit
Operating Temperature Range
Extended
L
H
T
°C
A
–40 to +85
15.5 The rm a l Cha ra c te ristic s
Characteristic
Thermal Resistance
Symbol
Value
Unit
Plastic
SOIC
θ
60
°C/W
JA
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
207
Electrical Specifications
Ele c tric a l Sp e c ific a tions
15.6 Sup p ly Curre nt Cha ra c te ristic s (VDD = 4.5 to 5.5 Vd c )
Characteristic
RUN (Analog and LVR Disabled)
Symbol
Min
Typ
Max
Unit
Internal Low-Power Oscillator at 100 kHz
Internal Low-Power Oscillator at 500 kHz
External Oscillator Running at 4.2 MHz
—
—
—
150
375
3.00
568
1100
5.20
µA
µA
mA
I
I
DD
DD
WAIT (Analog and LVR Disabled)
Internal Low-Power Oscillator at 100 kHz
Internal Low-Power Oscillator at 500 kHz
External Oscillator Running at 4.2 MHz
—
—
—
45
75
1.00
85
375
2.20
µA
µA
mA
STOP (Analog and LVR Disabled)
25 °C
–40 °C to 85 °C
I
I
—
—
2
4
10
20
µA
µA
DD
DD
Incremental I for Enabled Modules
DD
LVR
—
—
5
380
15
475
µA
µA
Analog Subsystem
NOTES:
1.
VDD = 4.5 to 5.5 Vdc, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. All values shown reflect average measurements.
3. Typical values at midpoint of voltage range, 25 °C only.
4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator,
all inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on
OSC2.
5. Wait IDD is affected linearly by the OSC2 capacitance.
6. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc, OSC1 = VDD
.
General Release Specification
208
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Electrical Specifications
Electrical Specifications
Supply Current Characteristics (V = 2.7 to 3.3 Vdc)
DD
15.7 Sup p ly Curre nt Cha ra c te ristic s (VDD = 2.7 to 3.3 Vd c )
Characteristic
RUN (Analog and LVR Disabled)
Symbol
Min
Typ
Max
Unit
Internal Low-Power Oscillator at 100 kHz
Internal Low-Power Oscillator at 500 kHz
External Oscillator Running at 2.1 MHz
—
—
—
70
320
1.25
320
800
2.60
µA
µA
mA
I
I
DD
DD
WAIT (Analog and LVR Disabled)
Internal Low-Power Oscillator at 100 kHz
Internal Low-Power Oscillator at 500 kHz
External Oscillator Running at 2.1 MHz
—
—
—
20
40
0.50
65
250
1.10
µA
µA
mA
STOP (Analog and LVR Disabled)
25 °C
–40 °C to 85 °C
I
I
—
—
1
2
5
10
µA
µA
DD
DD
Incremental I for Enabled Modules
DD
LVR
—
—
5
380
15
475
µA
µA
Analog Subsystem
NOTES:
1.
VDD = 4.5 to 5.5 Vdc, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. All values shown reflect average measurements.
3. Typical values at midpoint of voltage range, 25 °C only.
4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator,
all inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on
OSC2.
5. Wait IDD is affected linearly by the OSC2 capacitance.
6. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc, OSC1 = VDD
.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
209
Electrical Specifications
Ele c tric a l Sp e c ific a tions
15.8 DC Ele c tric a l Cha ra c te ristic s (5.0 Vd c )
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage
I
I
= 10.0 µA
= –10.0 µA
V
—
—
—
0.1
—
V
OL
load
load
V
V
–0.1
OH
DD
Output High Voltage
(I
(I
= –0.8 mA) PB0:7
= –4.0 mA) PA0:5, PB4, PC0:7
V
V
–0.8
–0.8
—
—
—
—
V
V
DD
DD
load
load
V
OH
Output Low Voltage
(I
(I
(I
= 1.6 mA) PB0:7, RESET
= 10 mA) PA0:5, PB4, PC0:7
= 15 mA) PA0:5, PB4, PC0:7
—
—
—
—
—
—
0.4
0.4
1.5
load
load
load
V
OL
High Source Current
Total for All (6) PA0:5 Pins and PB4
Total for All (8) PC0:7 Pins
I
—
—
—
—
20
30
mA
mA
OH
High Sink Current
Total for All (6) PA0:5 Pins and PB4
Total for All (8) PC0:7 Pins
I
—
—
—
—
40
60
OL
Input High Voltage
PA0:5, PB0:7, PC0:7, RESET, OSC1, IRQ/V
V
0.7 x V
V
DD
V
V
IH
DD
—
—
PP
PP
Input Low Voltage
PA0:5, PB0:7, PC0:7, RESET, OSC1, IRQ/V
V
V
0.3 x V
1
IL
SS
DD
Input Current
I
I
-1
—
µA
IN
OSC1, IRQ/V
PP
Input Current
RESET (Pullup, Source)
RESET (Pulldown, Sink)
10
–6
—
—
—
—
µA
mA
IN
I/O Ports High-Z Leakage Current (Pulldowns Off)
PA0:6, PB0:7, PC0:7
I
-2
—
2
µA
µA
OZ
Input Pulldown Current
PA0:5, PB0:7, PC0:7 (V = V = 0.7 x V
)
I
IL
40
25
100
65
280
190
IN
IH
DD
PA0:5, PB0:7, PC0:7 (V = V =0.3 x V )
IN
IL
DD
NOTES:
1. +4.5 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. All values shown reflect average measurements.
3. Typical values at midpoint of voltage range, 25 °C only.
4. PC0:7 parameters only apply to MC68HC705JP7
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Electrical Specifications MOTOROLA
210
Electrical Specifications
DC Electrical Characteristics (3.0 Vdc)
15.9 DC Ele c tric a l Cha ra c te ristic s (3.0 Vd c )
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage
I
I
= 10.0 µA
= –10.0 µA
V
—
—
—
0.1
—
V
OL
load
load
V
V
V
–0.1
OH
DD
Output High Voltage
(I
(I
= –0.2 mA) PB0:7, RESET
= –2.0 mA) PA0:5, PB4, PC0:7
V
–0.8
—
—
V
V
OH
DD
load
load
Output Low Voltage
(I
(I
= 1.6 mA) PB0:7, RESET
= 5.0 mA) PA0:5, PB4, PC0:7
V
—
—
—
—
0.3
0.3
OL
load
load
High Source Current
Total for All (6) PA0:5 Pins and PB4
Total for All (8) PC0:7 Pins
I
—
—
—
—
20
30
mA
mA
OH
High Sink Current
Total for All (6) PA0:5 Pins and PB4
Total for All (8) PC0:7 Pins
I
—
—
—
—
40
60
OL
Input High Voltage
PA0:5, PB0:7, PC0:7, RESET, OSC1, IRQ/V
V
0.7 x V
—
—
—
V
DD
V
V
IH
DD
PP
PP
Input Low Voltage
PA0:5, PB0:7, PC0:7, RESET, OSC1, IRQ/V
V
V
0.2 x V
1
IL
SS
DD
Input Current
I
I
-1
µA
IN
OSC1, IRQ/V
PP
Input Current
RESET (Pullup, Source)
RESET (Pulldown, Sink)
5
–3
—
—
—
—
µA
mA
IN
I/O Ports High-Z Leakage Current (Pulldowns Off)
PA0:6, PB0:7, PC0:7
I
-2
—
2
µA
µA
OZ
Input Pulldown Current
PA0:5, PB0:7, PC0:7 (V = V = 0.7 x V
)
I
IL
10
4
25
20
75
40
DD
IH
DD
PA0:5, PB0:7, PC0:7 (V = V = 0.3 x V )
IN
IL
DD
NOTES:
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. All values shown reflect average measurements.
3. Typical values at midpoint of voltage range, 25 °C only.
4. PC0:7 parameters only apply to MC68HC705JP7
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
211
MOTOROLA
Electrical Specifications
Ele c tric a l Sp e c ific a tions
15.10 Ana log Sub syste m Cha ra c te ristic s (5.0 Vd c )
Characteristic
Symbol
Min
Max
Unit
Voltage Comparators
Input Offset Voltage
Common-Mode Range
V
—
—
15
mV
V
IO
V
V
–1.5
CMR
DD
Comparator 1 Input Impedance
Z
800
—
kΩ
IN
Comparator 2 Input Impedance
Direct Input to Comparator 2 (HOLD = 1, DHOLD = 0)
Divider Input to Comparator 2 (HOLD = 0, DHOLD = 1)
Z
Z
800
80
—
—
kΩ
kΩ
IN
IN
Input Divider Ratio (Comparator 2, HOLD = 0, DHOLD =1)
R
0.49
0.51
DIV
V
= 0 to V –1.5V
IN
DD
Analog Subsystem Internal V Offset
SS
V
20
—
40
3
mV
AOFF
Sum of comparator offset and IR drop through V
Channel Selection Multiplexer Switch Resistance
External Current Source (PB0/AN0)
SS
R
kΩ
MUX
Source Current (V
Source Current Linearity (V
Discharge Sink Current (V
= V /2)
I
I
I
85
—
1.1
113
± 1
—
µA
%FS
mA
OUT
DD
CHG
CHG
= 0 to V –1.5 Vdc)
DD
OUT
= 0.4 V)
OUT
DIS
External Capacitor (connected to PB0/AN0)
Voltage Range
Discharge Time
V
V
5
—
V –1.5
DD
V
ms/µF
µF
CAP
SS
t
10
2
DIS
Value of external ramping capacitor
C
EXT
Internal Sample and Hold Capacitor
Capacitance
C
8
13
pF
SH
Charge/Discharge Time (0 to 3.5 Vdc)
Direct Connection (HOLD = 1, DHOLD = 0)
Divided Connection (HOLD = 0, DHOLD = 1)
Temperature Diode Connection (HOLD = 1, DHOLD = 1)
Leakage Discharge Rate
t
1
2
1
—
—
—
µs
µs
µs
SHCHG
t
SHDCHG
t
SHTCHG
C
—
0.2
V/sec
SHDIS
Internal Temperature Sensing Diode
Voltage (at T = 25 °C)
Temperature Change in Voltage
V
TC
0.65
2.0
0.71
2.2
V
J
D
mV/°C
D
NOTE:
1. +4.5 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Electrical Specifications MOTOROLA
212
Electrical Specifications
Analog Subsystem Characteristics (3.0 Vdc)
15.11 Ana log Sub syste m Cha ra c te ristic s (3.0 Vd c )
Characteristic
Symbol
Min
Max
Unit
Voltage Comparators
Input Offset Voltage
Common-Mode Range
V
—
—
15
mV
V
IO
V
V
–1.5
CMR
DD
Comparator 1 Input Impedance
Z
800
—
kΩ
IN
Comparator 2 Input Impedance
Direct Input to Comparator 2 (HOLD = 1, DHOLD = 0)
Divider Input to Comparator 2 (HOLD = 0, DHOLD = 1)
Z
Z
800
80
—
—
kΩ
kΩ
IN
IN
Input Divider Ratio (Comparator 2, HOLD = 0, DHOLD =1)
R
0.49
0.51
DIV
V
= 0 to V –1.5V
IN
DD
Analog Subsystem Internal V Offset
V
10
—
30
5
mV
SS
AOFF
Multiplexer Switch Resistance
R
kΩ
MUX
External Current Source (PB0/AN0)
Source Current (V
Source Current Linearity (V
Discharge Sink Current (V
= V /2)
I
I
I
75
—
1
104
±1
—
µA
%FS
mA
OUT
DD
CHG
CHG
= 0 to V –1.5 Vdc)
DD
OUT
= 0.4 V)
OUT
DIS
External Capacitor (connected to PB0/AN0)
Voltage Range
Discharge Time
V
V
5
—
V –1.5
DD
V
ms/µF
µF
CAP
SS
t
10
2
DIS
Value of external ramping capacitor
C
EXT
Internal Sample and Hold Capacitor
Capacitance
C
8
13
pF
SH
Charge/Discharge Time (0 to 3.5 Vdc)
Direct Connection (HOLD = 1, DHOLD = 0)
Divided Connection (HOLD = 0, DHOLD = 1)
Temperature Diode Connection (HOLD = 1, DHOLD = 1)
Leakage Discharge Rate
t
1
2
1
—
—
—
µs
µs
µs
SHCHG
t
SHDCHG
t
SHTCHG
C
—
0.1
V/sec
SHDIS
Internal Temperature Sensing Diode
Voltage (at T = 25 °C)
Temperature Change in Voltage
V
TC
0.65
2.0
0.71
2.2
V
J
D
mV/°C
D
NOTE:
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
213
MOTOROLA
Electrical Specifications
Ele c tric a l Sp e c ific a tions
15.12 Control Tim ing (5.0 Vd c )
Characteristic
Symbol
Min
Max
Unit
Frequency of Oscillation (OSC)
RC Oscillator Option
Crystal Oscillator Option
—
0.1
DC
4.2
4.2
4.2
MHz
MHz
MHz
External Clock Source
f
OSC
Internal Low-Power Oscillator
Standard Product (100 kHz nominal)
Mask Option (500 kHz nominal, see Note 3)
60
300
140
700
kHz
kHz
Internal Operating Frequency, Crystal, or External Clock (f
RC Oscillator Option
Crystal Oscillator Option
/2)
OSC
—
0.05
DC
2.1
2.1
2.1
MHz
MHz
MHz
External Clock Source
f
OP
Internal Low-Power Oscillator
Standard Product (100 kHz nominal)
Mask Option (500 kHz nominal, see Note 3)
30
150
75
350
kHz
kHz
Cycle Time (1/f
)
OP
External Oscillator or Clock Source
Internal Low-Power Oscillator
476
—
ns
t
CYC
Standard Product (100 kHz nominal)
Mask Option (500 kHz nominal, see Note 3)
14.29
2.86
33.33
6.67
µs
µs
16-Bit Timer
Resolution
Input Capture (TCAP) Pulse Width
t
4.0
284
—
—
t
t
RESL
, t
CYC
ns
t
TH TL
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
t
284
see Note 2
110
—
—
—
ns
ILIH
t
ILIL
CYC
OSC1 Pulse Width (External Clock Input)
t
t
, t
ns
OH OL
Analog Subsystem Response
Voltage Comparators
Switching Time (10 mV Overdrive, Either Input)
Comparator Power-Up Delay (Bias Circuit Already Powered Up)
External Current Source (PB0/AN0)
Switching Time (I
Power-Up Delay (Bias Circuit Already Powered Up)
Bias Circuit Power-Up Delay
t
—
—
2
2
µs
µs
CPROP
CDELAY
t
t
—
—
1
2
µs
µs
ISTART
IDELAY
to I
)
DIS
RAMP
t
—
2
µs
BDELAY
NOTES:
1. +4.5 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service
routine plus 21 tCYC
.
3. The 500 kHz nominal mask option is available through special order only. Contact your local Motorola sales
representative for detailed ordering information.
General Release Specification
214
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Electrical Specifications
Electrical Specifications
Control Timing (3.0 Vdc)
15.13 Control Tim ing (3.0 Vd c )
Characteristic
Symbol
Min
Max
Unit
Frequency of Oscillation (OSC)
RC Oscillator Option
Crystal Oscillator Option
—
0.1
DC
2.1
2.1
2.1
MHz
MHz
MHz
External Clock Source
f
OSC
Internal Low-Power Oscillator
Standard Product (100 kHz nominal)
Mask Option (500 kHz nominal, see Note 3))
60
300
140
700
kHz
kHz
Internal Operating Frequency, Crystal, or External Clock (f
RC Oscillator Option
Crystal Oscillator Option
/2)
OSC
—
0.05
DC
1.05
1.05
1.05
MHz
MHz
MHz
External Clock Source
f
OP
Internal Low-Power Oscillator
Standard Product (100 kHz nominal)
Mask Option (500 kHz nominal, see Note 3))
30
150
70
350
kHz
kHz
Cycle Time (1/f
)
OP
External Oscillator or Clock Source
Internal Low-Power Oscillator
952
—
ns
t
CYC
Standard Product (100 kHz nominal)
Mask Option (500 kHz nominal, see Note 3))
14.29
2.86
33.33
6.67
µs
µs
16-Bit Timer
Resolution
Input Capture (TCAP) Pulse Width
t
4.0
284
—
—
t
t
RESL
, t
CYC
ns
t
TH TL
Interrupt Pulse Width Low (Edge-Triggered)
Interrupt Pulse Period
t
284
see Note 2
110
—
—
—
ns
ILIH
t
ILIL
CYC
OSC1 Pulse Width (External Clock Input)
t
t
, t
ns
OH OL
Analog Subsystem Response
Voltage Comparators
Switching Time (10 mV Overdrive, Either Input)
Comparator Power-Up Delay (Bias Circuit Already Powered Up)
External Current Source (PB0/AN0)
Switching Time (I
Power-Up Delay (Bias Circuit Already Powered Up)
Bias Circuit Power-Up Delay
t
—
—
2
2
µs
µs
CPROP
CDELAY
t
t
—
—
1
2
µs
µs
ISTART
IDELAY
to I
)
DIS
RAMP
t
—
2
µs
BDELAY
NOTES:
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service
routine plus 21 tCYC
.
3. The 500 kHz nominal mask option is available through special order only. Contact your local Motorola sales
representative for detailed ordering information.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
215
Electrical Specifications
Ele c tric a l Sp e c ific a tions
15.14 PEPROM a nd EPROM Prog ra m m ing Cha ra c te ristic s
Characteristic
PEPROM Programming Voltage (IRQ/V
PEPROM Programming Current (IRQ/V
PEPROM Programming Time per Bit
Symbol
Min
16.0
—
Typ
16.5
3.0
—
Max
17.0
5.0
—
Unit
V
)
V
PP
PP
PP
)
I
mA
ms
V
PP
t
t
4.0
EPGM
EPROM/MOR Programming Voltage (IRQ/V
EPROM/MOR Programming Current (IRQ/V
EPROM Programming Time per Byte
MOR Programming Time
)
V
16.0
—
16.5
3.0
—
17.0
5.0
—
PP
PP
)
I
mA
ms
ms
PP
PP
4.0
EPGM
MPGM
t
10.0
—
—
NOTE:
+4.5 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
NOTE: To program the EPROM/OTPROM, MOR or EPMSEC bits, the voltage
on V must be greater than 4.5 volts.
DD
15.15 SIOP Tim ing (VDD = 5.0 Vd c )
Characteristic
Frequency of Operation
Symbol
Min
Typ
Max
Unit
Master
Slave
f
f
0.25 x f
DC
0.25 x f
—
0.25 x f
1050
kHz
SIOP(M)
OP
OP
OP
SIOP(S)
Cycle Time
Master
Slave
t
t
4.0 x t
—
4.0 x t
—
4.0 x t
µs
SCK(M)
SCK(M)
CYC
CYC
CYC
3.8
Clock (SCK) Low Time (f = 4.2 MHz)
t
466
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
OP
SCKL
SDO Data Valid Time
SDO Hold Time
SDI Setup Time
SDI Hold Time
NOTE:
t
200
—
V
t
0
HO
t
100
100
—
S
t
—
H
1. +4.5 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Electrical Specifications MOTOROLA
216
Electrical Specifications
SIOP Timing (VDD = 3.0 Vdc)
t
SCK
t
SCKL
SCK
t
t
V
HO
MSB
BIT 1
LSB
SDO
SDI
t
S
MSB
LSB
VALID DATA
t
H
Figure 15-1. SIOP Timing Diagram
15.16 SIOP Tim ing (VDD = 3.0 Vd c )
Characteristic
Frequency of Operation
Symbol
Min
Typ
Max
Unit
Master
Slave
f
f
0.25 x f
DC
0.25 x f
—
0.25 x f
525
SIOP(M)
OP
OP
OP
kHz
SIOP(S)
Cycle Time
Master
Slave
t
t
4.0 x t
—
4.0 x t
—
4.0 x t
CYC
SCK(M)
SCK(M)
CYC
CYC
µs
1.9
Clock (SCK) Low Time (f = 4.2 MHz)
t
932
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
OP
SCKL
SDO Data Valid Time
SDO Hold Time
SDI Setup Time
SDI Hold Time
NOTE:
t
400
—
V
t
0
HO
t
200
200
—
S
t
—
H
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
217
MOTOROLA
Electrical Specifications
Ele c tric a l Sp e c ific a tions
15.17 Re se t Cha ra c te ristic s
Characteristic
Symbol
Min
Typ
Max
Unit
Low-Voltage Reset
Rising Recovery Voltage
Falling Reset Voltage
LVR Hysteresis
V
V
V
2.4
2.3
100
3.4
3.3
—
4.4
4.3
—
V
V
mV
LVRR
LVRF
LVRH
POR Recovery Voltage (see Note 2)
V
0
—
100
mV
POR
POR V Slew Rate (see Note 2)
DD
Rising (see Note 2)
Falling (see Note 2)
S
S
—
—
—
—
0.1
0.05
V/µs
VDDR
VDDF
RESET Pulse Width (when Bus Clock Active)
t
1.5
3
—
—
—
4
t
t
RL
CYC
RESET Pulldown Pulse Width
(from Internal Reset)
t
RPD
CYC
NOTE:
1. +2.7 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. By design, not tested
1
OSC1
t
RL
RESET
2
4064 or 16 t
cyc
Internal
3
Clock
Internal
Address
Bus
1FFE
1FFF
NEW PCH NEW PCL
3
Internal
Data
Bus
NEW
PCH
NEW
PCL
Op
code
3
NOTES:
1. Represents the internal gating of the OSC1 pin
2. Normal delay of 4064 t or short delay option of 16 t
CYC
CYC
3. Internal timing signal and data information not available externally
Figure 15-2. Stop Recovery Timing Diagram
General Release Specification
218
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Electrical Specifications
Electrical Specifications
Reset Characteristics
Internal
1
Reset
RESET
Pin
2
t
4064 or 16 t
cyc
RPD
Internal
3
Clock
Internal
Address
Bus
1FFF
NEW PCH NEW PCL
1FFE
3
Internal
Data
Bus
NEW
PCH
NEW
PCL
3
NOTES:
1. Represents the internal reset from low-voltage reset, illegal opcode fetch or COP watchdog timeout
2. Only if reset occurs during normal delay of 4064 t
recovery.
or short delay option of 16 t
for initial power-up or stop
CYC
CYC
3. Internal timing signal and data information not available externally
Figure 15-3. Internal Reset Timing Diagram
V
V
DD
LVRR
V
LVRF
Low
Voltage
Reset
RESET
1
Pin
2
cyc
t
4064 or 16 t
RPD
Internal
3
Clock
Internal
Address
Bus
1FFF
NEW PCH NEW PCL
1FFE
3
Internal
Data
Bus
NEW
PCH
NEW
PCL
3
NOTES:
1. RESET pin pulled down by internal device
2
Only if LVR occurs during normal delay of 4064 t
recovery.
or short delay option of 16 t
for initial power-up or stop
CYC
CYC
3
Internal timing signal and data information not available externally
Figure 15-4. Low-Voltage Reset Timing Diagram
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
219
Electrical Specifications
Ele c tric a l Sp e c ific a tions
General Release Specification
220
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Electrical Specifications
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 16. Me c ha nic a l Sp e c ific a tions
16.1 Conte nts
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
16.3 20-Pin Plastic Dual In-Line Package (Case 738) . . . . . . . . . .222
16.4 20-Pin Small Outline Integrated Circuit (Case 751D) . . . . . . .222
16.5 28-Pin Plastic Dual In-Line Package (Case 710) . . . . . . . . . .223
16.6 28-Pin Small Outline Integrated Circuit (Case 751F) . . . . . . .223
16.7 20-Pin Windowed Ceramic Integrated Circuit (Case 732) . . .224
16.8 28-Pin Windowed Ceramic Integrated Circuit (Case 733A) . .224
16.2 Introd uc tion
The MC68HC705JJ7 is available in a 20-pin plastic dual in-line package
(PDIP), a small outline integrated circuit (SOIC) package, and a 20-pin
windowed ceramic package.
The MC68HC705JP7 is available in a 28-pin plastic dual in-line package
(PDIP), a 28-pin small outline integrated circuit (SOIC) package, and a
28-pin windowed ceramic package.
The following figures show the latest packages at the time of this
publication. To make sure that you have the latest package
specifications, contact one of the following:
• Local Motorola Sales Office
• Motorola Fax Back System (Mfax™)
– Phone 1-602-244-6609
– EMAIL RMFAX0@email.sps.mot.com;
http://sps.motorola.com/mfax/
• Worldwide Web (wwweb) home page at http://motorola.com/sps/
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
MC68HC705JJ7/MC68HC705JP7 — Rev. 2.0
MOTOROLA Mechanical Specifications
General Release Specification
221
Me c ha nic a l Sp e c ific a tions
16.3 20-Pin Pla stic Dua l In-Line Pa c ka g e (Ca se 738)
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
20
1
11
10
B
3. DIMENSION
L
FORMED PARALLEL.
TO CENTER OF LEAD WHEN
4. DIMENSION
FLASH.
B
DOES NOT INCLUDE MOLD
C
L
INCHES
MIN MAX
1.010 1.070 25.66 27.17
MILLIMETERS
DIM
A
B
C
D
E
MIN MAX
0.240 0.260
0.150 0.180
0.015 0.022
0.050 BSC
0.050 0.070
0.100 BSC
6.10
3.81
0.39
6.60
4.57
0.55
-T-
SEATING
PLANE
K
M
1.27 BSC
1.77
1.27
F
E
N
G
J
2.54 BSC
0.008 0.015
0.110 0.140
0.300 BSC
0.21
2.80
0.38
3.55
G
F
J 20 PL
K
L
7.62 BSC
0.25 (0.010M)
D 20 PL
M
T B
0°
0.020 0.040
15°
0°
0.51
15°
1.01
M
N
M
M
T A
0.25 (0.010)
16.4 20-Pin Sm a ll Outline Inte g ra te d Circ uit (Ca se 751D)
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
20
11
3. DIMENSIONS
A
AND
MOLD PROTRUSION.
B
DO NOT INCLUDE
-B-
P 10 PL
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
M
0.010 (0.25M)
B
5. DIMENSION
D
DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
1
10
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
AT MAXIMUM MATERIAL CONDITION.
DIMENSION
D 20 PL
J
F
MILLIMETERS INCHES
MIN MAX MIN MAX
0.010 (0.25M)
T
A
B
S
S
DIM
A
12.65 12.95
0.499 0.510
0.292 0.299
0.093 0.104
0.014 0.019
0.020 0.035
0.050 BSC
B
7.40
2.35
0.35
0.50
7.60
2.65
0.49
0.90
C
D
F
R X 45°
1.27 BSC
G
J
0.25
0.10
0.32
0.25
7°
0.010 0.012
0.004 0.009
K
C
M
P
0°
0°
0.395 0.415
7°
10.05 10.55
0.25 0.75
-T-
SEATING
PLANE
R
0.010 0.029
M
K
G 18 PL
General Release Specification
222
MC68HC705JJ7/MC68HC705JP7 — Rev. 2.0
Mechanical Specifications MOTOROLA
Mechanical Specifications
28-Pin Plastic Dual In-Line Package (Case 710)
16.5 28-Pin Pla stic Dua l In-Line Pa c ka g e (Ca se 710)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
28
1
15
14
2. DIMENSION
WHEN FORMED PARALLEL.
3. DIMENSION DOES NOT INCLUDE
MOLD FLASH.
L
TO CENTER OF LEADS
B
B
MILLIMETERS
MIN MAX
INCHES
MIN MAX
DIM
A
B
C
D
F
36.45 37.21
13.72 14.22
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
L
A
C
3.94
0.36
1.02
5.08
0.56
1.52
N
G
H
J
2.54 BSC
0.100 BSC
0.065 0.085
0.008 0.015
0.115 0.135
1.65
0.20
2.92
2.16
0.38
3.43
J
H
G
K
L
M
K
SEATING
PLANE
15.24 BSC
0.600 BSC
F
D
0°
0.51
15°
1.02
0°
0.020 0.040
15°
M
N
16.6 28-Pin Sm a ll Outline Inte g ra te d Circ uit (Ca se 751F)
-A-
NOTES:
28
1
15
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION
PROTRUSION.
14X P
M
-B-
0.010 (0.25M)
B
A
AND
B
DO NOT INCLUDE MOLD
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
14
5. DIMENSION
D
DOES NOT INCLUDE
DAMBAR PROTRUSIONA. LLOWABLE
28X D
DAMBAR PROTRUSION SHALL BE 0.13
D
(0.005) TOTAL IN EXCESS OF
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
0.010 (0.25M)
T
S
A
S
B
R X 45°
MILLIMETERS
MIN MAX
17.80 18.05
INCHES
MIN MAX
C
DIM
A
-T-
0.701 0.711
0.292 0.299
0.093 0.104
0.014 0.019
0.016 0.035
0.050 BSC
-T-
SEATING
PLANE
B
7.40
2.35
0.35
0.41
7.60
2.65
0.49
0.90
26X G
C
D
K
F
F
G
J
1.27 BSC
0.23
0.13
0.32
0.29
8°
0.009 0.013
0.005 0.011
J
K
M
P
0°
0°
0.395 0.415
8°
10.05 10.55
0.25 0.75
R
0.010 0.029
MC68HC705JJ7/MC68HC705JP7 — Rev. 2.0
MOTOROLA Mechanical Specifications
General Release Specification
223
Me c ha nic a l Sp e c ific a tions
16.7 20-Pin Wind owe d Ce ra m ic Inte g ra te d Circ uit (Ca se 732)
NOTES:
1. LEADS WITHIN 0.010 DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
20
1
11
10
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
C
INCHES
A
DIM MIN
MAX
A
B
C
D
F
G
H
J
K
L
M
N
0.940 0.990
0.260 0.295
0.150 0.200
0.015 0.022
0.055 0.065
0.100 BSC
0.020 0.050
0.008 0.012
0.125 0.160
0.300 BSC
L
F
N
J
H
K
M
G
0
15
D
0.010 0.040
SEATING
PLANE
16.8 28-Pin Wind owe d Ce ra m ic Inte g ra te d Circ uit (Ca se 733A)
NOTES:
28
15
14
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION
4. DIMENSION
B
A
L
AND
B
TO CENTER OF LEADS WHEN
INCLUDE MENISCUS.
1
FORMED PARALLEL.
INCHES
MILLIMETERS
M
J
–A–
DIM MIN
MAX
1.490
0.605
0.240
0.022
0.065
MIN
36.45
12.70
4.06
MAX
37.84
15.36
6.09
L
A
B
C
D
F
1.435
0.500
0.160
0.015
0.050
0.38
1.27
0.55
1.65
N
C
G
J
0.100 BSC
2.54 BSC
–T–
SEATING
PLANE
0.008
0.125
0.012
0.160
0.20
3.17
0.30
4.06
K
K
L
0.600 BSC
15.24 BSC
G
M
N
0
0.020
15
0.050
0
_
0.51
15
_
1.27
_
_
F
D 28 PL
M
M
0.25 (0.010)
T A
General Release Specification
224
MC68HC705JJ7/MC68HC705JP7 — Rev. 2.0
Mechanical Specifications MOTOROLA
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 17. Ord e ring Inform a tion
17.1 Conte nts
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
17.3 MC68HC705JJ7 Order Numbers . . . . . . . . . . . . . . . . . . . . . .226
17.4 MC68HC705JP7 Order Numbers. . . . . . . . . . . . . . . . . . . . . .227
17.2 Introd uc tion
This section contains instructions for ordering the various versions of the
EPROM MCUs.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
225
Ordering Information
Ord e ring Inform a tion
17.3 MC68HC705JJ7 Ord e r Num b e rs
The following table shows the MC order numbers for the available 20-pin
package types
EPO
LPO
Freq.
(kHz)
Operating
Temperature
Range
Package
Type
Oscill.
Order Number
(1)
Type
(2)
Plastic DIP
Xtal
Xtal
Xtal
RC
RC
RC
Xtal
Xtal
Xtal
RC
RC
RC
100
100
100
100
100
100
500
500
500
500
500
500
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
MC68HC705JJ7CP
MC68HC705JJ7CDW
MC68HC705JJ7CS
MC68HRC705JJ7CP
MC68HRC705JJ7CDW
MC68HRC705JJ7CS
MC68HC705SJ7CP
MC68HC705SJ7CDW
MC68HC705SJ7CS
MC68HRC705SJ7CP
MC68HRC705SJ7CDW
MC68HRC705SJ7CS
(3)
SOIC
(4)
CERDIP
Plastic DIP
SOIC
CERDIP
Plastic DIP
SOIC
CERDIP
Plastic DIP
SOIC
CERDIP
1. Crystal/Ceramic Resonator or RC Oscillator
2. Plastic Dual In-Line Package (P, Case Outline 738)
3. Small Outline Integrated Circuit Package (DW, Case Outline 751D)
4. Windowed Ceramic Dual In-Line Package (S, Case Outline 732)
General Release Specification
226
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Ordering Information
Ordering Information
MC68HC705JP7 Order Numbers
17.4 MC68HC705JP7 Ord e r Num b e rs
The following table shows the MC order numbers for the available 28-pin
package types
EPO
LPO
Freq.
(kHz)
Operating
Temperature
Range
Package
Type
Oscill.
Order Number
(1)
Type
(2)
Plastic DIP
Xtal
Xtal
Xtal
RC
RC
RC
Xtal
Xtal
Xtal
RC
RC
RC
100
100
100
100
100
100
500
500
500
500
500
500
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
MC68HC705JP7CP
MC68HC705JP7CDW
MC68HC705JP7CS
MC68HRC705JP7CP
MC68HRC705JP7CDW
MC68HRC705JP7CS
MC68HC705SP7CP
MC68HC705SP7CDW
MC68HC705SP7CS
MC68HRC705SP7CP
MC68HRC705SP7CDW
MC68HRC705SP7CS
(3)
SOIC
(4)
CERDIP
Plastic DIP
SOIC
CERDIP
Plastic DIP
SOIC
CERDIP
Plastic DIP
SOIC
CERDIP
1. Crystal/Ceramic Resonator or RC Oscillator
2. Plastic Dual In-Line Package (P, Case Outline 710)
3. Small Outline Integrated Circuit Package (DW, Case Outline 751F)
4. Windowed Ceramic Dual In-Line Package (S, Case Outline 733A)
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
General Release Specification
227
Ordering Information
Ord e ring Inform a tion
General Release Specification
228
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
MOTOROLA
Ordering Information
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts.
Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the
design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution, P.O. Box 5405, Denver, Colorado 80217, 1-800-441-2447 or
1-303-675-2140. Customer Focus Center, 1-800-521-6274
JAPAN: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan, 81-3-5487-8488
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong, 852-26629298
Mfax™, Motorola Fax Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/;
TOUCHTONE, 1-602-244-6609; US and Canada ONLY, 1-800-774-1848
HOME PAGE: http://motorola.com/sps/
Mfax is a trademark of Motorola, Inc.
© Motorola, Inc., 1997
HC705JJ7GRS/D
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