MC68HC705K1CDW [MOTOROLA]
8-BIT, OTPROM, MICROCONTROLLER, PDSO16, SOIC-16;
| 型号： | MC68HC705K1CDW |
| 厂家： | 
MOTOROLA |
| 描述： | 8-BIT, OTPROM, MICROCONTROLLER, PDSO16, SOIC-16 可编程只读存储器 时钟 光电二极管 外围集成电路 |
| 文件： | 总140页 (文件大小：1219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC705K1/D
Rev. 2.0
HC 5
MC68HC705K1
HCMOS Mic roc ontrolle r Unit
TECHNICAL DATA
Technical Data
Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
© Motorola, Inc., 1999
Technical Data
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MC68HC705K1 — Rev. 2.0
MOTOROLA
Technical Data — MC68HC705K1
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .15
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . .31
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . .57
Section 7. Parallel Input/Output (I/O). . . . . . . . . . . . . . . .63
Section 8. Multifunction Timer. . . . . . . . . . . . . . . . . . . . .75
Section 9. EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . .83
Section 10. Personality EPROM (PEPROM) . . . . . . . . . .91
Section 11. Instruction Set. . . . . . . . . . . . . . . . . . . . . . . .99
Section 12. Electrical Specifications. . . . . . . . . . . . . . .117
Section 13. Mechanical Specifications . . . . . . . . . . . . .133
Section 13. Ordering Information . . . . . . . . . . . . . . . . .137
MC68HC705K1 — Rev. 2.0
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List of Sections
Technical Data — MC68HC705K1
Table of Contents
Section 1. General Description
1.1
1.2
1.3
1.4
1.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.6
1.6.1
V
and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DD SS
1.6.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.2.1
1.6.2.2
1.6.2.3
1.6.2.4
1.6.2.5
1.6.3
1.6.4
IRQ/V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PP
1.6.5
1.6.6
PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PB1/OSC3 and PB0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Input/Output Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .26
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2.6
2.7
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Personality EPROM/OTPROM. . . . . . . . . . . . . . . . . . . . . . . . .30
Section 3. Central Processor Unit (CPU)
3.1
3.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Section 4. Interrupts
4.1
4.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.3
4.3.1
4.3.2
Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.3.2.1
4.3.2.2
4.3.2.3
4.3.3
4.3.3.1
4.3.3.2
IRQ/V Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
PP
PA3–PA0 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . .45
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .46
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Section 5. Resets
5.1
5.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
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5.3
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Computer Operating Properly (COP) Reset. . . . . . . . . . . . .54
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Low-Voltage Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.4
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
I/O Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Multifunction Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.4.1
5.4.2
5.4.3
5.4.4
Section 6. Low-Power Modes
6.1
6.2
6.3
6.4
6.5
6.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Section 7. Parallel Input/Output (I/O)
7.1
7.2
7.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
I/O Port Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
7.4
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .65
Pulldown Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Port A External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .67
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
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7.5
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .70
Pulldown Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
7.5.1
7.5.2
7.5.3
7.5.4
Section 8. Multifunction Timer
8.1
8.2
8.3
8.4
8.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . .77
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Section 9. EPROM/OTPROM
9.1
9.2
9.3
9.4
9.5
9.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . .84
EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . . .85
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Section 10. Personality EPROM (PEPROM)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.3 PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
10.3.1 PEPROM Bit Select Register . . . . . . . . . . . . . . . . . . . . . . . .93
10.3.2 PEPROM Status and Control Register. . . . . . . . . . . . . . . . .95
10.4 PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.5 PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.6 PEPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
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Section 11. Instruction Set
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .104
11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .105
11.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .106
11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .108
11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
11.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Section 12. Electrical Specifications
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
12.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
12.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .118
12.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
12.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
12.7 Equivalent Pin Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
12.8 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .121
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12.9 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .122
12.10 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
12.11 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.12 Typical Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . .130
Section 13. Mechanical Specifications
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
13.3 Plastic Dual In-Line Package (Case 648). . . . . . . . . . . . . . . .134
13.4 Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .134
13.5 Ceramic Dual In-Line Package (Case 620) . . . . . . . . . . . . . .135
Section 13. Ordering Information
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
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List of Figures
Figure
Title
Page
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
MC68HC705K1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . .18
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . . .19
Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . . .21
3-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . . .22
2-Pin RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . .22
3-Pin RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . .23
External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . .24
2-1
2-2
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3-1
3-2
3-3
3-4
3-5
3-6
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Index Register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . .36
4-1
4-2
4-3
4-4
External Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .45
Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5-1
5-2
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6-1
Stop/Wait/Halt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
MC68HC705K1 — Rev. 2.0
MOTOROLA
Technical Data
List of Figures
11
List of Figures
Figure
Title
Page
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . . .64
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .65
Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . . .66
Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . . .69
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .70
Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . . .71
Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
8-1
8-2
8-3
8-4
Multifunction Timer Block Diagram. . . . . . . . . . . . . . . . . . . . .76
Timer Status and Control Register (TSCR) . . . . . . . . . . . . . .77
Timer Counter Register (TCNTR). . . . . . . . . . . . . . . . . . . . . .79
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9-1
9-2
9-3
EPROM Programming Register (EPROG). . . . . . . . . . . . . . .84
Programming Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . .87
10-1
10-2
10-3
Personality EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
PEPROM Bit Select Register (PEBSR) . . . . . . . . . . . . . . . . .93
PEPROM Status and Control Register (PESCR). . . . . . . . . .95
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Typical High-Side Driver Characteristics . . . . . . . . . . . . . . .123
Typical Low-Side Driver Characteristics. . . . . . . . . . . . . . . .123
Run I versus Internal Clock Frequency . . . . . . . . . . . . . .124
DD
Wait I versus Internal Clock Frequency . . . . . . . . . . . . . .124
DD
Stop I versus Temperature. . . . . . . . . . . . . . . . . . . . . . . .125
DD
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . .128
Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
12-10 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
12-11 2-Pin RC Oscillator R versus Frequency (V = 5.0 V) . . . .131
DD
12-12 3-Pin RC Oscillator R versus Frequency (V = 5.0 V) . . . .131
DD
12-13 2-Pin Oscillator R versus Frequency (V = 3.0 V) . . . . . . .132
DD
12-14 3-Pin Oscillator R versus Frequency (V = 3.0 V) . . . . . . .132
DD
Technical Data
12
MC68HC705K1 — Rev. 2.0
List of Figures
MOTOROLA
Technical Data — MC68HC705K1
List of Tables
Table
Title
Page
4-1
Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . .48
7-1
7-2
7-3
Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
PB0 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
PB1/OSC3 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
8-1
8-2
Real-Time Interrupt Rate Selection . . . . . . . . . . . . . . . . . . . .78
COP Watchdog Recommendations . . . . . . . . . . . . . . . . . . . .81
10-1
PEPROM Bit Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
11-1
11-2
11-3
11-4
11-5
11-6
11-7
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .104
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .105
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .107
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . .108
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
13-1
MC68HC705K1 Order Numbers. . . . . . . . . . . . . . . . . . . . . .137
MC68HC705K1 — Rev. 2.0
MOTOROLA
Technical Data
List of Tables
13
List of Tables
Technical Data
14
MC68HC705K1 — Rev. 2.0
MOTOROLA
List of Tables
Technical Data — MC68HC705K1
Section 1. General Description
1.1 Contents
1.2
1.3
1.4
1.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.6
1.6.1
V
and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DD SS
1.6.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.2.1
1.6.2.2
1.6.2.3
1.6.2.4
1.6.2.5
1.6.3
1.6.4
IRQ/V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PP
1.6.5
1.6.6
PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PB1/OSC3 and PB0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.2 Introduction
The MC68HC705K1 is a member of the low-cost, high-performance
M68HC05 Family of 8-bit microcontroller units (MCU). The M68HC05
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the popular M68HC05
central processor unit (CPU) and are available with a variety of
subsystems, memory sizes and types, and package types.
MC68HC705K1 — Rev. 2.0
MOTOROLA
Technical Data
General Description
15
General Description
On-chip memory of the MC68HC705K1 includes 504 bytes of erasable,
programmable read-only memory (EPROM). In packages without the
transparent window for EPROM erasure, the 504 EPROM bytes serve
as one-time programmable read-only memory (OTPROM).
1.3 Features
Features of the MCU include:
• Popular M68HC05 CPU
• Memory-mapped input/output (I/O) registers
• 504 bytes of EPROM/OTPROM, including eight user vector
locations
• 32 bytes of user random-access memory (RAM)
• 64-bit personality EPROM
• 10 bidirectional I/O pins with these features:
– Software programmable pulldown devices
– Four I/O pins with 8-mA current sinking capability
– Four I/O pins with maskable external interrupt capability
• Hardware mask and flag for external interrupts
• Fully static operation with no minimum clock speed
• On-chip oscillator with connections for:
– Crystal or ceramic resonator
– Mask-optional 2-pin or 3-pin resistor-capacitor (RC) oscillator
• Computer operating properly (COP) watchdog
• 15-bit multifunction timer with real-time interrupt circuit
• Power-saving stop, wait, halt, and data-retention modes
• 8 × 8 unsigned multiply instruction
• Illegal address reset
• Low-voltage reset
Technical Data
16
MC68HC705K1 — Rev. 2.0
General Description
MOTOROLA
General Description
Mask Options
• 16-pin plastic dual in-line package (PDIP)
• 16-pin small outline integrated circuit package (SOIC)
• 16-pin ceramic DIP (cerdip)
1.4 Mask Options
These MC68HC705K1 options are programmable in the mask option
register (MOR):
• Enabled or disabled COP watchdog
• Edge-triggered or edge- and level-triggered external interrupt pins
• Enabled or disabled port A external interrupt function
• Enabled or disabled low-voltage reset function
• Enabled or disabled STOP instruction
• Oscillator driven by crystal or ceramic resonator or oscillator
driven by RC circuit
• 2-pin RC-driven oscillator or 3-pin RC-driven oscillator
• Enabled or disabled port A and port B programmable pulldown
devices
The mask option register is an EPROM/OTPROM byte at location
$0017. Section 9. EPROM/OTPROM describes the mask option
register and the EPROM/OTPROM programming procedure.
1.5 MCU Structure
Figure 1-1 shows the structure of the MC68HC705K1 MCU.
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
General Description
17
General Description
USER EPROM/OTPROM
504 BYTES
MASK OPTION REGISTER
EPROM/OTPROM
PERSONALITY EPROM/OTPROM
64 BITS
PA7*
PA6*
PA5*
PA4*
PA3**
PA2**
PA1**
PA0**
USER RAM
32 BYTES
ARITHMETIC/LOGIC
*8-mA sink capability
CPU CONTROL
UNIT
IRQ/V
**External interrupt capability
PP
ACCUMULATOR
M68HC05
MCU
RESET
RESET
INDEX REGISTER
STACK POINTER
0
0
0
0
0
0
0
0
0
0
0 0 0 1 1 1
PROGRAM COUNTER
0
PB1/OSC3
PB0
CONDITION CODE REGISTER
1
1 1 H I N C Z
MULTIFUNCTION
TIMER
COP WATCHDOG
AND
ILLEGAL ADDRESS
DETECT
LOW-VOLTAGE
DETECT
V
DD
V
SS
OSC1
OSC2
INTERNAL
OSCILLATOR
DIVIDE
BY TWO
Figure 1-1. MC68HC705K1 Block Diagram
Technical Data
18
MC68HC705K1 — Rev. 2.0
MOTOROLA
General Description
General Description
Pin Assignments
1.6 Pin Assignments
Figure 1-2 shows the MC68HC705K1 pin assignments.
RESET
PB1/OSC3
PB0
OSC1
OSC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
SS
IRQ/V
V
PP
DD
PA0
PA1
PA2
PA3
PA7
PA6
PA5
PA4
Figure 1-2. Pin Assignments
1.6.1 V and V
DD
SS
V
and V are the power supply and ground pins. The MCU operates
SS
DD
from a single 5-volt power supply.
Very fast signal transitions occur on the MCU pins, placing high
short-duration current demands on the power supply. To prevent noise
problems, take special care to provide good power supply bypassing at
the MCU. Place bypass capacitors as close to the MCU as possible, as
Figure 1-3 shows.
V+
OSC1
V
DD
OSC2
+
C2
MCU
C1
V
SS
C1 C2
V
SS
V
DD
Figure 1-3. Bypassing Layout Recommendation
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
19
General Description
General Description
1.6.2 OSC1 and OSC2
The OSC1, OSC2, and PB1/OSC3 pins are the control connections for
the 2-pin or 3-pin on-chip oscillator. The oscillator can be driven by any
of these:
• Crystal
• Ceramic resonator
• Resistor-capacitor network
• External clock signal
The frequency of the internal oscillator is f
. The MCU divides the
OSC
internal oscillator output by two to produce the internal clock with a
frequency of f .
OP
1.6.2.1 Crystal
The circuit in Figure 1-4 shows a typical crystal oscillator circuit for an
AT-cut, parallel resonant crystal. Follow the crystal supplier’s
recommendations, as the crystal parameters determine the external
component values required to provide reliable start-up and maximum
stability. The load capacitance values used in the oscillator circuit design
should include all stray layout capacitances. To minimize output
distortion, mount the crystal and capacitors as close as possible to
the pins.
V
SS
MCU
2 MΩ
OSC1
OSC2
XTAL
V
SS
XTAL
C1 C2
C3
27 pF
C4
27 pF
V
DD
Figure 1-4. Crystal Connections
Technical Data
20
MC68HC705K1 — Rev. 2.0
MOTOROLA
General Description
General Description
Pin Assignments
NOTE: Use an AT-cut crystal and not a strip or tuning fork crystal. The MCU may
overdrive or have the wrong characteristic impedance for a strip or
tuning fork crystal.
To use the crystal-driven oscillator, the RC and PIN3 bits in the mask
option register must be clear. See 9.6 Mask Option Register. Clearing
the RC bit connects an internal 2-MΩ startup resistor between OSC1
and OSC2.
1.6.2.2 Ceramic Resonator
To reduce cost, use a ceramic resonator in place of the crystal. Use the
circuit in Figure 1-5 for a 2-pin ceramic resonator or Figure 1-6 for a
3-pin ceramic resonator, and follow the resonator manufacturer’s
recommendations. The resonator parameters determine the external
component values required for maximum stability and reliable starting.
The load capacitance values used in the oscillator circuit design should
include all stray layout capacitances. To minimize output distortion,
mount the resonator and capacitors as close as possible to the pins.
V
SS
MCU
2 MΩ
OSC1
OSC2
CER.
RES.
V
SS
CERAMIC
RESONATOR
C1 C2
C3
27 pF
C4
27 pF
V
DD
Figure 1-5. 2-Pin Ceramic Resonator Connections
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
21
General Description
General Description
V
SS
MCU
2 MΩ
OSC1
OSC2
CER.
RES.
V
SS
C1 C2
CERAMIC
RESONATOR
V
DD
Figure 1-6. 3-Pin Ceramic Resonator Connections
To use the resonator-driven oscillator, the RC bit in the mask option
register must be clear. See 9.6 Mask Option Register. Clearing the RC
bit connects an internal 2-MΩ startup resistor between OSC1 and
OSC2.
1.6.2.3 2-Pin RC Oscillator
For maximum cost reduction, use the 2-pin RC oscillator configuration
shown in Figure 1-7. The OSC2 signal is a square wave, and the signal
on OSC1 is a triangular wave. The optimum frequency for the 2-pin
oscillator configuration is 2 MHz.
V
SS
MCU
OSC1
R
C3
OSC2
R
V
SS
C3
C1 C2
V
DD
Figure 1-7. 2-Pin RC Oscillator Connections
To use the 2-pin RC oscillator configuration, the RC bit in the mask
option register must be programmed to a logic 1. Setting the RC bit
Technical Data
22
MC68HC705K1 — Rev. 2.0
General Description
MOTOROLA
General Description
Pin Assignments
disconnects the internal startup resistor. The PIN3 bit in the mask option
register must remain erased (logic 0). The PIN3 bit selects the 3-pin RC
oscillator configuration. See 9.6 Mask Option Register.
1.6.2.4 3-Pin RC Oscillator
Another low-cost option is the 3-pin RC oscillator configuration shown in
Figure 1-8. The 3-pin oscillator is more stable than the 2-pin oscillator.
The OSC2 and PB1/OSC3 signals are square waves, and the signal on
OSC1 is a triangular wave. The 3-pin RC oscillator configuration is
recommended for frequencies of 1 MHz and less.
V
SS
C3
MCU
OSC1
R
PB1/OSC3
OSC2
V
+
SS
R
C3
C1 C2
V
DD
Figure 1-8. 3-Pin RC Oscillator Connections
To use the 3-pin RC oscillator configuration, both the RC and PIN3 bits
in the mask option register must be programmed to logic 1s. See
9.6 Mask Option Register.
NOTE: In 3-pin RC oscillator configurations, the personality EPROM
(PEPROM) cannot be programmed by user software. If the voltage on
IRQ/V is raised above V , the oscillator will revert to a 2-pin oscillator
PP
DD
configuration and device operation will be disrupted.
1.6.2.5 External Clock
An external clock from another CMOS-compatible device can drive the
OSC1 input, with the OSC2 pin unconnected, as Figure 1-9 shows.
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
General Description
23
General Description
MCU
EXTERNAL
CMOS CLOCK
Figure 1-9. External Clock Connections
1.6.3 RESET
A logic 0 on the RESET pin forces the MCU to a known startup state.
See 5.3.2 External Reset for more information.
1.6.4 IRQ/V
PP
The IRQ/V pin has these functions:
PP
• Applying asynchronous external interrupt signals,
see 4.3.2 External Interrupts
• Applying the EPROM/OTPROM programming voltage,
see 9.4 EPROM/OTPROM Programming
1.6.5 PA7–PA0
PA7–PA0 are the pins of port A, a general-purpose, bidirectional I/O
port. See 7.4 Port A.
1.6.6 PB1/OSC3 and PB0
PB1/OSC3 and PB0 are the pins of port B, a general-purpose,
bidirectional I/O port. See 7.5 Port B.
Technical Data
24
MC68HC705K1 — Rev. 2.0
MOTOROLA
General Description
Technical Data — MC68HC705K1
Section 2. Memory
2.1 Contents
2.2
2.3
2.4
2.5
2.6
2.7
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Input/Output Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .26
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Personality EPROM/OTPROM. . . . . . . . . . . . . . . . . . . . . . . . .30
2.2 Introduction
2.3 Memory Map
This section describes the organization of the on-chip memory.
The central processor unit (CPU) can address 1 Kbyte of memory space.
The program counter typically advances one address at a time through
the memory, reading the program instructions and data. The erasable,
programmable read-only memory (EPROM) portion of memory holds
the program instructions, fixed data, user-defined vectors, and interrupt
service routines. The random-access memory (RAM) portion of memory
holds variable data. Input/output (I/O) registers are memory-mapped so
that the CPU can access their locations in the same way that it accesses
all other memory locations.
Figure 2-1 is a memory map of the microcontroller unit (MCU). Refer to
Figure 2-2 for a more detailed memory map of the 32-byte I/O register
section.
MC68HC705K1 — Rev. 2.0
MOTOROLA
Technical Data
Memory
25
Memory
2.4 Input/Output Section
The first 32 addresses of the memory space, $0001–$001F, are the I/O
section. These are the addresses of the I/O control registers, status
registers, and data registers. See Figure 2-2.
2.5 Random-Access Memory (RAM)
The 32 addresses from $00E0 to $00FF serve as both the user RAM and
the stack RAM. The CPU uses five RAM bytes to save all CPU register
contents before processing an interrupt. During a subroutine call, the
CPU uses two bytes to store the return address. The stack pointer
decrements during pushes and increments during pulls.
NOTE: Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
Technical Data
26
MC68HC705K1 — Rev. 2.0
Memory
MOTOROLA
Memory
Random-Access Memory (RAM)
$0000
PORT A DATA REGISTER
PORT B DATA REGISTER
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
UNUSED
UNUSED
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
UNUSED
I/O REGISTERS
32 BYTES
UNUSED
TIMER STATUS AND CONTROL REGISTER
TIMER COUNTER REGISTER
IRQ STATUS AND CONTROL REGISTER
UNUSED
$001F
$0020
UNUSED
192 BYTES
UNUSED
$00DF
$00E0
UNUSED
PEPROM BIT SELECT REGISTER
PEPROM STATUS AND CONTROL REGISTER
PULLDOWN REGISTER A
PULLDOWN REGISTER B
UNUSED
USER
RAM
STACK
RAM
32 BYTES 32 BYTES
UNUSED
UNUSED
$00FF
$0100
UNUSED
UNUSED
UNUSED
256 BYTES
MASK OPTION REGISTER
EPROM PROGRAMMING REGISTER
UNUSED
$01FF
$0200
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
TEST
USER EPROM
496 BYTES
$03F0
$03F1
$03F2
$03F3
$03F4
$03F5
$03F6
$03F7
$03F8
$03F9
COP REGISTER
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
*
TIMER VECTOR (HIGH BYTE)
TIMER VECTOR (LOW BYTE)
$03EF
$03F0
EXTERNAL INTERRUPT VECTOR (HIGH BYTE) $03FA
EXTERNAL INTERRUPT VECTOR (LOW BYTE)
$03FB
SOFTWARE INTERRUPT VECTOR (HIGH BYTE) $03FC
SOFTWARE INTERRUPT VECTOR (LOW BYTE) $03FD
TEST ROM AND
COP REGISTER
(8 BYTES)
$03F7
$03F8
USER VECTORS (EPROM)
8 BYTES
RESET VECTOR (LOW BYTE)
RESET VECTOR (LOW BYTE)
$03FE
$03FF
$03FF
Writing to bit 0 of $03F0 clears the COP watchdog.
Reading $03F0 returns ROM data.
*
Figure 2-1. Memory Map
MC68HC705K1 — Rev. 2.0
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TechnicalData
27
Memory
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Port A Data Register
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
$0000
(PORTA) Write:
See page 64.
Reset:
Read:
Unaffected by reset
0
0
0
0
0
0
PB1/
OSC3
Port B Data Register
PB0
$0001
(PORTB) Write:
See page 69.
Reset:
Unaffected by reset
$0002
$0003
Unimplemented
Unimplemented
Read:
Data Direction Register A
DDRA7 DDRA6 DDRA5 DDRA4
DDRA3
DDRA2 DDRA1 DDRA0
$0004
$0005
(DDRA) Write:
See page 65.
Reset:
Read:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Direction Register B
DDRB1 DDRB0
(DDRB) Write:
See page 70.
Reset:
0
0
0
0
0
0
0
0
$0006
$0007
Unimplemented
Unimplemented
Read: TOF
RTIF
Timer Status and Control
TOIE
RTIE
RT1
RT0
$0008
$0009
$000A
Register (TSCR) Write:
TOFR
U
RTIFR
U
See page 77.
Reset:
0
0
0
0
1
1
Read: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer Counter Register
(TCNTR) Write:
See page 79.
Reset:
Read:
0
IRQE
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IRQF
IRQ Status and Control
IRQR
U
Register (ISCR) Write:
See page 45.
Reset:
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 1 of 3)
Technical Data
28
MC68HC705K1 — Rev. 2.0
MOTOROLA
Memory
Memory
Random-Access Memory (RAM)
Addr.
$000B
↓
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Unimplemented
$000D
Unimplemented
Read:
PEPROM Bit Select Register
PEB7
0
PEB6
PEB5
PEB4
PEB3
PEB2
PEB1
PEB0
$000E
$000F
$0010
$0011
(PEBSR) Write:
See page 93.
Reset:
0
0
0
0
PEPGM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read: PEDATA
PEPRZF
PEPROM Status and Control
Register (PESCR) Write:
See page 95.
Reset:
Read:
U
1
Pulldown Register A
(PDRA) Write: PDIA7 PDIA6
PDIA5
0
PDIA4
0
PDIA3
0
PDIA2
0
PDIA1 PDIA0
See page 66.
Reset:
Read:
0
0
0
0
Pulldown Register B
(PDRB) Write:
See page 71.
0
0
0
0
0
0
0
0
0
0
0
0
PDIB1 PDIB0
Reset:
0
0
$0012
↓
Unimplemented
Unimplemented
$0016
Read:
Mask Option Register
SWPDI
PIN3
RC
SWAIT
LVRE
PIRQ
LEVEL COPEN
MPGM EPGM
$0017
$0018
(MOR) Write:
See page 87.
Reset:
Read:
Unaffected by reset
EPROM Programming
R
U
R
U
R
U
R
R
ELAT
0
Register (EPROG) Write:
See page 84.
Reset:
U
R
U
0
0
= Unimplemented
= Reserved
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 2 of 3)
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
29
Memory
Memory
Addr.
$0019
↓
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Unimplemented
$001E
Unimplemented
Read:
LVRF
0
$001F
↓
Test Register Write:
Reset:
U
U
U
U
U
U
U
U
U
U
U
Read:
COP Register
COPC
0
$03F0
(COPR) Write:
See page 54.
Reset:
U
R
U
U
= Unimplemented
= Reserved
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 3 of 3)
2.6 EPROM/OTPROM
An MCU with a quartz window has 504 bytes of erasable, programmable
ROM (EPROM). The quartz window allows EPROM erasure with
ultraviolet light. In an MCU without the quartz window, the EPROM
cannot be erased and serves as 504 bytes of one-time programmable
ROM (OTPROM). Addresses $0020–$03EF contain 496 bytes of user
EPROM/OTPROM. The eight addresses from $03F8 to $03FF are
EPROM/OTPROM locations reserved for interrupt vectors and reset
vectors.
2.7 Personality EPROM/OTPROM
An MCU with a quartz window has a 64-bit array of erasable,
programmable ROM (EPROM) to serve as a personality EPROM. The
quartz window allows EPROM erasure with ultraviolet light. In an MCU
without the quartz window, the personality EPROM cannot be erased
and serves as a 64-bit array of OTPROM.
Technical Data
30
MC68HC705K1 — Rev. 2.0
Memory
MOTOROLA
Technical Data — MC68HC705K1
Section 3. Central Processor Unit (CPU)
3.1 Contents
3.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2 Introduction
This section describes the central processor unit (CPU) registers.
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31
Central Processor Unit (CPU)
Central Processor Unit (CPU)
3.3 CPU Registers
Figure 3-1 shows the five CPU registers. CPU registers and are not part
of the memory map.
7
7
6
6
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
ACCUMULATOR (A)
INDEX
REGISTER (X)
15 14 13 12 11 10
9
0
8
0
7
1
6
1
5
1
STACK
POINTER (SP)
0
0
0
0
0
0
15 14 13 12 11 10
9
8
7
6
5
PROGRAM
COUNTER (PC)
0
0
0
0
0
0
7
1
6
1
5
1
4
3
I
2
1
0
CONDITION CODE
REGISTER (CCR)
H
N
Z
C
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 3-1. Programming Model
Technical Data
32
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Central Processor Unit (CPU)
Central Processor Unit (CPU)
CPU Registers
3.3.1 Accumulator
The accumulator (A) shown in Figure 3-2 is a general-purpose 8-bit
register. The CPU uses the accumulator to hold operands and results of
arithmetic and non-arithmetic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-2. Accumulator (A)
3.3.2 Index Register
In the indexed addressing modes, the CPU uses the byte in the index
register (X) shown in Figure 3-3 to determine the conditional address of
the operand. See 11.3.5 Indexed, No Offset, 11.3.6 Indexed, 8-Bit
Offset, and 11.3.7 Indexed, 16-Bit Offset for more information on
indexed addressing.
The 8-bit index register also can serve as a temporary data storage
location.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-3. Index Register (X)
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Central Processor Unit (CPU)
Central Processor Unit (CPU)
3.3.3 Stack Pointer
The stack pointer (SP) shown in Figure 3-4 is a 16-bit register that
contains the address of the next free location on the stack. During a
reset or after the reset stack pointer (RSP) instruction, the stack pointer
initializes to $00FF. The address in the stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
The 11 most significant bits of the stack pointer are fixed permanently at
00000000111, so the stack pointer produces addresses from $00E0 to
$00FF. If subroutines and interrupts use more than 32 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations.
An interrupt uses five locations.
Bit
15
Bit
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
1
6
1
5
1
4
1
3
1
2
1
1
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
0
1
1
1
1
= Unimplemented
Figure 3-4. Stack Pointer (SP)
Technical Data
34
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Central Processor Unit (CPU)
Central Processor Unit (CPU)
CPU Registers
3.3.4 Program Counter
The program counter (PC) shown in Figure 3-5 is a 16-bit register that
contains the address of the next instruction or operand to be fetched.
The six most significant bits of the program counter are ignored internally
and appear as 000000.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Bit
Bit
15
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
Read:
Write:
Reset:
0
0
0
0
0
0
0
Loaded with vector from $03FE and $03FF
Figure 3-5. Program Counter (PC)
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35
Central Processor Unit (CPU)
Central Processor Unit (CPU)
3.3.5 Condition Code Register
The condition code register (CCR) shown in Figure 3-6 is an 8-bit
register whose three most significant bits are permanently fixed at 111.
The condition code register contains the interrupt mask and four flags
that indicate the results of prior instructions.
Bit 7
1
6
1
5
1
4
3
I
2
1
Bit 0
C
Read:
Write:
Reset:
H
U
N
U
Z
U
1
1
1
1
U
= Unimplemented
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry bit is required for
binary-coded decimal (BCD) arithmetic operations. Reset has no
affect on the half-carry flag.
I — Interrupt Mask Flag
Setting the interrupt mask (I) disables interrupts. If an interrupt
request occurs while the interrupt mask is a logic 0, the CPU saves
the CPU registers on the stack, sets the interrupt mask, and then
fetches the interrupt vector. If an interrupt request occurs while the
interrupt mask is set, the interrupt request is latched. The CPU
processes the latched interrupt as soon as the interrupt mask is
cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a clear
interrupt mask bit (CLI), STOP, or WAIT instruction.
Technical Data
36
MC68HC705K1 — Rev. 2.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Arithmetic/Logic Unit (ALU)
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result (bit 7 in the
results is a logic 1). Reset has no effect on the negative flag.
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00. Reset has
no effect on the zero flag.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow bit. Reset
has no effect on the carry/borrow flag.
3.4 Arithmetic/Logic Unit (ALU)
The arithmetic/logic unit (ALU) performs the arithmetic and logical
operations defined by the instruction set. The binary arithmetic circuits
decode instructions and set up the ALU for the selected operation. Most
binary arithmetic is based on the addition algorithm, carrying out
subtraction as negative addition. Multiplication is not performed as a
discrete operation but as a chain of addition and shift operations within
the ALU. The multiply instruction requires 11 internal clock cycles to
complete this chain of operations.
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Central Processor Unit (CPU)
37
Central Processor Unit (CPU)
Technical Data
38
MC68HC705K1 — Rev. 2.0
MOTOROLA
Central Processor Unit (CPU)
Technical Data — MC68HC705K1
Section 4. Interrupts
4.1 Contents
4.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.3
4.3.1
4.3.2
Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.3.2.1
4.3.2.2
4.3.2.3
4.3.3
4.3.3.1
4.3.3.2
IRQ/V Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
PP
PA3–PA0 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . .45
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .46
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.2 Introduction
This section describes how interrupts temporarily change the normal
processing sequence.
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Technical Data
Interrupts
39
Interrupts
4.3 Interrupt Types
These conditions generate interrupts:
• SWI instruction (software interrupt)
• A logic 0 applied to the IRQ/V pin (external interrupt)
PP
• A logic 1 applied to one of the PA3–PA0 pins when port A external
interrupts are enabled (external interrupt)
• A timer overflow (timer interrupt)
• Expiration of the real-time interrupt period (timer interrupt)
An interrupt temporarily stops normal program execution to process a
particular event. An interrupt does not stop the execution of the
instruction in progress, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
central processor unit (CPU) registers on the stack and loads the
program counter with a user-defined vector address.
4.3.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.3.2 External Interrupts
These sources can generate external interrupts:
• IRQ/V pin
PP
• PA3–PA0 pins when port A external interrupts are enabled
Setting the I bit in the condition code register or clearing the IRQE bit in
the interrupt status and control register disables external interrupts.
Technical Data
40
MC68HC705K1 — Rev. 2.0
Interrupts
MOTOROLA
Interrupts
Interrupt Types
4.3.2.1 IRQ/V Pin
PP
An interrupt signal on the IRQ/V pin latches an external interrupt
PP
request. After completing the current instruction, the CPU tests these
bits:
• IRQ latch
• IRQE bit in the interrupt status and control register
• I bit in the condition code register
If both the IRQ latch and the IRQE bit are set, and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request. Figure 4-1 shows the logic for
external interrupts.
The IRQ/V pin is negative edge-triggered only or negative edge- and
PP
low-level-triggered, depending on the state of the LEVEL bit in the mask
option register (MOR). See 9.6 Mask Option Register.
Programming the LEVEL bit to a logic 1 selects the edge- and
level-sensitive trigger option. When LEVEL = 1:
• A falling edge or a low level on the IRQ/V pin latches an external
PP
interrupt request.
• As long as the IRQ/V is low, an external interrupt request is
PP
present, and the CPU continues to execute the interrupt service
routine. The edge- and level-sensitive trigger option allows
connection to the IRQ/V pin of multiple wired-OR interrupt
PP
sources.
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41
Interrupts
Interrupts
Programming the LEVEL bit to a logic 0 selects the edge-sensitive-only
trigger option. When LEVEL = 0:
• A falling edge on the IRQ/V pin latches an external interrupt
PP
request.
• A subsequent interrupt request can be latched only after the
voltage level on the IRQ/V pin returns to logic 1 and then falls
PP
again to logic 0.
NOTE: If the IRQ/V pin is not in use, connect it to the V pin.
PP
DD
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ/V
PP
PA3
PA2
PA1
PA0
V
DD
IRQ
LATCH
EXTERNAL
INTERRUPT
REQUEST
R
RST
IRQ VECTOR FETCH
MASK OPTION REGISTER
IRQ STATUS/CONTROL REGISTER
INTERNAL DATA BUS
Figure 4-1. External Interrupt Logic
Technical Data
42
MC68HC705K1 — Rev. 2.0
MOTOROLA
Interrupts
Interrupts
Interrupt Types
4.3.2.2 PA3–PA0 Pins
Programming the PIRQ bit in the mask option register to a logic 1
enables pins PA3–PA0 to serve as additional external interrupt sources.
See 9.6 Mask Option Register. An interrupt signal on a PA3–PA0 pin
latches an external interrupt request. After completing the current
instruction, the CPU tests these bits:
• IRQ latch
• IRQE bit in the IRQ status and control register
• I bit in the condition code register.
If both the IRQ latch and the IRQE bit are set, and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request.
The PA3–PA0 pins are edge-triggered only or both edge- and
level-triggered, depending on the state of the LEVEL bit in the MOR.
Programming the LEVEL bit to a logic 1 selects the edge- and
level-sensitive trigger option. When LEVEL = 1:
• A rising edge or a high level on a PA3–PA0 pin latches an external
interrupt request if and only if all other PA3–PA0 pins are low and
the IRQ/V pin is high.
PP
• A falling edge or a low level on the IRQ/V pin latches an external
PP
interrupt request if and only if all of the PA3–PA0 pins are low.
• As long as any PA3–PA0 pin is high or the IRQ/V pin is low, an
PP
external interrupt request is present, and the CPU continues to
execute the interrupt service routine.
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Interrupts
43
Interrupts
Programming the LEVEL bit to a logic 0 selects the edge-sensitive only
trigger option. When LEVEL = 0:
• A rising edge on a PA3–PA0 pin latches an external interrupt
request if and only if all other PA3–PA0 pins are low and the
IRQ/V pin is high.
PP
• A falling edge on the IRQ/V pin latches an external interrupt
PP
request if and only if all of the PA3–PA0 pins are low.
• A subsequent PA3–PA0 pin interrupt request can be latched only
after the voltage level of the previous PA3–PA0 interrupt signal
returns to a logic 0 and then rises again to a logic 1.
• A subsequent IRQ/V pin interrupt request can be latched only
PP
after the voltage level of the previous IRQ/V interrupt signal
PP
returns to a logic 1 and then falls again to a logic 0.
Technical Data
44
MC68HC705K1 — Rev. 2.0
Interrupts
MOTOROLA
Interrupts
Interrupt Types
4.3.2.3 IRQ Status and Control Register
The IRQ status and control register (ISCR) contains an external interrupt
mask, an external interrupt flag, and a flag reset bit. Unused bits read as
logic 0s.
Address: $000A
Bit 7
IRQE
1
6
0
0
5
0
0
4
0
0
3
2
0
0
1
Bit 0
0
Read:
Write:
Reset:
IRQF
IRQR
U
0
0
= Unimplemented
U = Unaffected
Figure 4-2. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
IRQF — External Interrupt Request Flag
The IRQF bit is a clearable, read-only flag that is set when an external
interrupt request is pending. Reset clears the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
These conditions set the IRQF bit:
a. An external interrupt signal on the IRQ/V pin
PP
b. An external interrupt signal on pin PA3, PA2, PA1, or PA0
when PA3–PA0 are enabled to serve as external interrupt
sources
The CPU clears the IRQF bit when fetching the interrupt vector.
Writing to the IRQF bit has no effect. Writing a logic 1 to the IRQR bit
clears the IRQF bit.
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45
Interrupts
IRQR — Interrupt Request Reset Bit
Writing a logic 1 to this write-only bit clears the IRQF bit. Writing a
logic 0 to IRQR has no effect. Reset has no effect on IRQR.
1 = IRQF bit cleared
0 = No effect
4.3.3 Timer Interrupts
The multifunction timer can generate these interrupts:
• Timer overflow interrupt
• Real-time interrupt
Setting the I bit in the condition code register disables all timer interrupts.
4.3.3.1 Timer Overflow Interrupt
A timer overflow interrupt request occurs if the timer overflow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. See 8.3 Timer Status and Control Register.
4.3.3.2 Real-Time Interrupt
A real-time interrupt request occurs if the real-time interrupt flag, RTIF,
becomes set while the real-time interrupt enable bit, RTIE, is also set.
See 8.3 Timer Status and Control Register.
Technical Data
46
MC68HC705K1 — Rev. 2.0
Interrupts
MOTOROLA
Interrupts
Interrupt Processing
4.4 Interrupt Processing
The CPU does these things to begin servicing an interrupt:
• Stores the CPU registers on the stack in the order shown in
Figure 4-3
• Sets the I bit in the condition code register to prevent further
interrupts
• Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $03FC and $03FD (software interrupt vector)
– $03FA and $03FB (external interrupt vector)
– $03F8 and $03F9 (timer interrupt vector)
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-3.
$00E0 (BOTTOM OF STACK)
$00E1
$00E2
•
•
•
•
•
•
UNSTACKING
ORDER
5
4
3
2
1
1
2
3
4
5
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
•
•
STACKING
ORDER
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 4-3. Interrupt Stacking Order
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Interrupts
Interrupts
Table 4-1 summarizes the reset and interrupt sources and vector
assignments.
Table 4-1. Reset/Interrupt Vector Addresses
MOR
Control
Bit
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector
Address
Function
Source
Power-on logic
RESET pin
None
None
(1)
COP watchdog
Reset
None
None
None
None
COPEN
1
$03FE–$03FF
$03FC–$03FD
(2)
Low voltage detect
Illegal address logic
LVIE
None
None
None
Software
interrupt
(SWI)
Same priority
as instruction
User code
IRQ/V pin
PP
(3)
PA3 pin
PA2 pin
PA1 pin
PIRQ
External
interrupts
3
IRQE bit
I bit
I bit
2
3
$03FA–$03FB
$03F8–$03F9
PIRQ
3
PIRQ
3
PA0 pin
TOF bit
RTIF bit
PIRQ
TOFE bit
RTIE bit
Timer
interrupts
None
1. COPEN enables the COP watchdog.
2. LVIE enables low-voltage resets.
3. PIRQ enables port A external interrupts.
NOTE: If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit.
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48
MC68HC705K1 — Rev. 2.0
Interrupts
MOTOROLA
Interrupts
Interrupt Processing
Figure 4-4 shows the sequence of events caused by an interrupt.
FROM
RESET
YES
I BIT SET?
NO
YES
YES
EXTERNAL
CLEAR IRQ LATCH
INTERRUPT?
NO
TIMER
INTERRUPT?
STACK PCL, PCH, X, A, CCR
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
NO
FETCH NEXT
INSTRUCTION
YES
YES
SWI
INSTRUCTION?
NO
RTI
UNSTACK CCR, A, X, PCH, PCL
EXECUTE INSTRUCTION
INSTRUCTION?
NO
Figure 4-4. Interrupt Flowchart
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Interrupts
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50
MC68HC705K1 — Rev. 2.0
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Interrupts
Technical Data — MC68HC705K1
Section 5. Resets
5.1 Contents
5.3
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Computer Operating Properly (COP) Reset. . . . . . . . . . . . .54
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Low-Voltage Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.4
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
I/O Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Multifunction Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.4.1
5.4.2
5.4.3
5.4.4
5.2 Introduction
This section describes the five reset sources and how they initialize the
microcontroller unit (MCU).
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Resets
5.3 Reset Types
A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user-defined reset vector address. These conditions produce a
reset:
• Initial power-up (power-on reset)
• A logic 0 applied to the RESET pin (external reset)
• Timeout of the computer operating properly (COP) watchdog
(COP reset)
• An opcode fetch from an address not in the memory map (illegal
address reset)
• V voltage below nominal 3.5 volts (low-voltage reset)
DD
5.3.1 Power-On Reset
A positive transition on the V pin generates a power-on reset. The
DD
power-on reset is strictly for power-up conditions and cannot be used to
detect drops in power supply voltage.
A 4064 t
(internal clock cycle) delay after the oscillator becomes
CYC
active allows the clock generator to stabilize. If the RESET pin is at
logic 0 at the end of 4064 t , the MCU remains in the reset condition
CYC
until the signal on the RESET pin goes to logic 1.
5.3.2 External Reset
A logic 0 applied to the RESET pin for one and one-half t
generates
CYC
an external reset. A Schmitt trigger senses the logic level at the RESET
pin.
A COP reset or an illegal address reset pulls the RESET pin low for one
internal clock cycle. A low-voltage reset pulls the RESET pin low for as
long as the low-voltage condition exists.
Technical Data
52
MC68HC705K1 — Rev. 2.0
Resets
MOTOROLA
Resets
Reset Types
MASK OPTION REGISTER
COP WATCHDOG
LOW-VOLTAGE RESET
POWER-ON RESET
IRQ/V
PP
ILLEGAL ADDRESS RESET
INTERNAL ADDRESS BUS
RESET
S
RST
TO CPU AND
SUBSYSTEMS
D
RESET
LATCH
INTERNAL
CLOCK
R
Figure 5-1. Reset Sources
NOTE: To avoid overloading some power supply designs, do not connect the
RESET pin directly to V . Use a pullup resistor of 10 kΩ or more.
DD
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Resets
Resets
5.3.3 Computer Operating Properly (COP) Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. (See 8.5 COP
Watchdog.) To clear the COP watchdog and prevent a COP reset, write
a logic 0 to bit 0 (COPC) of the COP register at location $03F0. The COP
register is a write-only register that returns the contents of a ROM
location when read.
Address: $03F0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
COPC
0
U
U
U
U
U
U
U
= Unimplemented
U = Unaffected
Figure 5-2. COP Register (COPR)
COPC — COP Clear Bit
COPC is a write-only bit. Periodically writing a logic 0 to COPC
prevents the COP watchdog from resetting the MCU. Writing a logic 1
has no effect. Reset clears the COPC bit.
5.3.4 Illegal Address Reset
An opcode fetch from an address that is not in the erasable,
programmable read-only memory (EPROM) (locations $0200–$03FF)
or the random-access memory (RAM) (locations $00E0–$00FF)
generates an illegal address reset. An illegal address reset pulls the
RESET pin low for one cycle of the internal clock.
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54
MC68HC705K1 — Rev. 2.0
Resets
MOTOROLA
Resets
Reset States
5.3.5 Low-Voltage Reset
The low-voltage reset circuit generates a reset signal if the voltage on
the V pin falls below 3.5 V (nominal). V must be set at 5 V ±10%
DD
DD
while the low-voltage reset circuit is enabled.
Programming the LVRE bit to a logic 1 enables the low-voltage reset
function. When erased, the LVRE bit in the mask option register disables
the low-voltage reset circuit. See 9.6 Mask Option Register.
A low-voltage reset pulls the RESET pin low for as long as the
low-voltage condition exists.
The state of the low-voltage reset circuit is readable in the test register
at location $001F. Bit 1 of the test register is the low-voltage reset flag
(LVRF). Regardless of the LVRE bit in the mask option register, the
low-voltage reset circuit is active in all modes except stop mode.
5.4 Reset States
This subsection describes how resets initialize the MCU.
5.4.1 CPU
A reset has these effects on the central processor unit (CPU):
• Loads the stack pointer with $FF
• Sets the I bit in the condition code register, inhibiting interrupts
• Sets the IRQE bit in the interrupt status and control register
• Loads the program counter with the user-defined reset vector from
locations $03FE and $03FF
• Clears the stop latch, enabling the CPU clock
• Clears the wait latch, waking the CPU from the wait mode
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Resets
5.4.2 I/O Port Registers
A reset has these effects on input/output (I/O) port registers:
• Clears bits DDRA7–DDRA0 in data direction register A so that
port A pins are inputs
• Clears bits PDIA7–PDIA0 in pulldown register A so that port A
pulldown devices are enabled (if the SWPDI bit in the mask option
register is programmed to a logic 0)
• Clears bits DDRB1 and DDRB0 in data direction register B so that
port B pins are inputs (if the SWPDI bit in the mask option register
is programmed to logic 0)
• Clears bits PDIB1 and PDIB0 in pulldown register B so that port B
pulldown devices are enabled
• Has no effect on port A or port B data registers
5.4.3 Multifunction Timer
A reset has these effects on the multifunction timer:
• Clears the timer status and control register
• Clears the timer counter register
5.4.4 COP Watchdog
A reset clears the COP watchdog timeout counter.
Technical Data
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Resets
Technical Data — MC68HC705K1
Section 6. Low-Power Modes
6.1 Contents
6.2
6.3
6.4
6.5
6.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
6.2 Introduction
This section describes the four low-power modes:
• Stop mode
• Wait mode
• Halt mode
• Data-retention mode
6.3 Stop Mode
If the SWAIT bit in the mask option register (MOR) is programmed to a
logic 0, the STOP instruction puts the microcontroller unit (MCU) in its
lowest power-consumption mode and has these effects on the MCU:
• Clears TOF and RTIF, the timer interrupt flags in the timer status
and control register, removing any pending timer interrupts
• Clears TOIE and RTIE, the timer interrupt enable bits in the timer
status and control register, disabling further timer interrupts
• Clears the multifunction timer counter register
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Low-Power Modes
57
Low-Power Modes
• Sets the IRQE bit in the IRQ status and control register to enable
external interrupts
• Clears the I bit in the condition code register, enabling interrupts
• Stops the internal oscillator, turning off the central processor unit
(CPU) clock and the timer clock, including the computer operating
properly (COP) watchdog
The STOP instruction does not affect any other registers or any
input/output (I/O) lines.
These conditions bring the MCU out of stop mode:
• An external interrupt signal on the IRQ/V pin — A high-to-low
PP
transition on the IRQ/V pin loads the program counter with the
PP
contents of locations $03FA and $03FB.
• An external interrupt signal on a port A external interrupt pin — If
the PIRQ bit in the mask option register is programmed to a
logic 1, a low-to-high transition on a PA3–PA0 pin loads the
program counter with the contents of locations $03FA and $03FB.
• External reset — A logic 0 on the RESET pin resets the MCU and
loads the program counter with the contents of locations $03FE
and $03FF.
When the MCU exits stop mode, processing resumes after a
stabilization delay of 4064 oscillator cycles.
6.4 Wait Mode
The WAIT instruction puts the MCU in an intermediate
power-consumption mode and has these effects on the MCU:
• Clears the I bit in the condition code register, enabling interrupts
• Sets the IRQE bit in the IRQ status and control register, enabling
external interrupts
• Stops the CPU clock, but allows the internal oscillator and timer
clock to continue to run
The WAIT instruction does not affect any other registers or any I/O lines.
Technical Data
58
MC68HC705K1 — Rev. 2.0
Low-Power Modes
MOTOROLA
Low-Power Modes
Halt Mode
These conditions restart the CPU clock and bring the MCU out of wait
mode:
• An external interrupt signal on the IRQ/V pin — A high-to-low
PP
transition on the IRQ/V pin loads the program counter with the
PP
contents of locations $03FA and $03FB.
• An external interrupt signal on a port A external interrupt pin — If
the PIRQ bit in the mask option register is programmed to a
logic 1, a low-to-high transition on a PA3–PA0 pin loads the
program counter with the contents of locations $03FA and $03FB.
• A timer interrupt — A timer overflow or a real-time interrupt request
loads the program counter with the contents of locations $03F8
and $03F9.
• A COP watchdog reset — A timeout of the COP watchdog resets
the MCU and loads the program counter with the contents of
locations $03FE and $03FF. Software can enable real-time
interrupts so that the MCU can periodically exit wait mode to reset
the COP watchdog.
• External reset — A logic 0 on the RESET pin resets the MCU and
loads the program counter with the contents of locations $03FE
and $03FF.
6.5 Halt Mode
The STOP instruction puts the MCU in halt mode if the SWAIT bit in the
mask option register is programmed to a logic 1. Halt mode is identical
to wait mode, except that a recovery delay of 1–4064 internal clock
cycles occurs when the MCU exits halt mode. When the SWAIT bit is set,
the COP watchdog cannot be inadvertently turned off by a STOP
instruction.
Figure 6-1 shows the sequence of events in stop, wait, and halt modes.
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Low-Power Modes
59
Low-Power Modes
STOP
YES
SWAIT
BIT SET?
HALT
WAIT
NO
CLEAR I BIT IN CCR
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
SET IRQE BIT IN ISCR
CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR
TURN OFF INTERNAL OSCILLATOR
YES
YES
YES
YES
YES
YES
EXTERNAL
RESET?
EXTERNAL
RESET?
YES
EXTERNAL
RESET?
NO
NO
NO
EXTERNAL
INTERRUPT?
EXTERNAL
INTERRUPT?
YES
EXTERNAL
INTERRUPT?
NO
NO
NO
YES
YES
TIMER
INTERRUPT?
TIMER
INTERRUPT?
TURN ON INTERNAL OSCILLATOR
RESET STABILIZATION TIMER
NO
NO
COP
RESET?
COP
RESET?
YES
END OF
STABILIZATION
DELAY?
NO
NO
NO
TURN ON CPU CLOCK
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
Figure 6-1. Stop/Wait/Halt Flowchart
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Low-Power Modes
Low-Power Modes
Data-Retention Mode
6.6 Data-Retention Mode
In data-retention mode, the MCU retains random-access memory (RAM)
contents and CPU register contents at V voltages as low as 2.0 Vdc.
DD
Data-retention mode allows the MCU to remain in a low
power-consumption state during which it retains data, but the CPU
cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to a logic 0.
2. Lower the V voltage. The RESET pin must remain low
DD
continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return V to normal operating voltage.
DD
2. Return the RESET pin to a logic 1.
MC68HC705K1 — Rev. 2.0
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Low-Power Modes
Low-Power Modes
Technical Data
62
MC68HC705K1 — Rev. 2.0
MOTOROLA
Low-Power Modes
Technical Data — MC68HC705K1
Section 7. Parallel Input/Output (I/O)
7.1 Contents
7.2
7.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
I/O Port Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
7.4
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . . .3
Port A External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . . .6
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .8
Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . . .8
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
7.5.1
7.5.2
7.5.3
7.5.4
7.2 Introduction
This section describes the two bidirectional input/output (I/O) ports:
• Port A
• Port B
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Parallel Input/Output (I/O)
Pa ra lle l Inp ut/ Outp ut (I/ O)
7.3 I/O Port Function
The 10 bidirectional input/output (I/O) pins form two parallel I/O ports.
Each I/O pin is programmable as an input or an output. The contents of
the data direction registers determine the data direction of each I/O pin.
All 10 I/O pins have software-programmable pulldown devices.
7.4 Port A
Port A is an 8-bit, general-purpose, bidirectional I/O port with these
features:
• Programmable pulldown devices
• 8-mA current sinking capability (pins PA7–PA4)
• External interrupt capability (pins PA3–PA0)
7.4.1 Port A Data Register
The port A data register (PORTA) contains a bit for each of the port A
pins. When a port A pin is programmed to be an output, the state of its
data register bit determines the state of the output pin. When a port A pin
is programmed to be an input, reading the port A data register returns
the logic state of the pin.
Address: $0000
Bit 7
6
5
4
3
2
1
Bit 0
PA0
Read:
Write:
Reset:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
Unaffected by reset
Figure 7-1. Port A Data Register (PORTA)
PA7–PA0 — Port A Data Bits
These read/write bits are software-programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register A. Reset has no effect on port A data.
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Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
Port A
7.4.2 Data Direction Register A
The contents of data direction register A (DDRA) determine whether
each port A pin is an input or an output. Writing a logic 1 to a DDRA bit
enables the output buffer for the associated port A pin; a logic 0 disables
the output buffer. A reset initializes all DDRA bits to logic 0s, configuring
all port A pins as inputs. If the pulldown devices are enabled, setting a
DDRA bit to a logic 1 turns off the pulldown device for that pin.
Address: $0004
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
0
0
0
0
0
0
0
0
Figure 7-2. Data Direction Register A (DDRA)
DDRA7–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears bits
DDRA7–DDRA0.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing DDRA bits from logic 0 to logic 1.
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Parallel Input/Output (I/O)
Pa ra lle l Inp ut/ Outp ut (I/ O)
7.4.3 Pulldown Register A
Programming the SWPDI bit in the mask option register to a logic 0
enables the port A and port B pulldown devices. The port A pulldown
devices sink approximately 100 µA and are under the control of the
PDIA7–PDIA0 bits in pulldown register A (PDRA).
Clearing the PDIA7–PDIA0 bits turns on the pulldown devices of the port
A pins that are configured as inputs. A pulldown device can be turned on
only when its pin is an input. When SWPDI is a logic 0, reset initializes
all port A pins as inputs with pulldown devices turned on.
Programming the SWPDI bit to a logic 1 disables the port A and port B
pulldown devices. Reset initializes all port A pins as inputs with pulldown
devices disabled when the SWPDI bit is programmed to a logic 1.
Address: $0010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write: PDIA7
Reset:
PDIA6
0
PDIA5
0
PDIA4
0
PDIA3
0
PDIA2
0
PDIA1
0
PDIA0
0
0
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA)
PDIA7–PDIA0 — Port A Pulldown Inhibit Bits 7–0
Writing logic 0s to these write-only bits turns on the port A pulldown
devices. Reading pulldown register A returns undefined data. Reset
clears bits PDIA7–PDIA0.
1 = Corresponding port A pin pulldown device turned off
0 = Corresponding port A pin pulldown device turned on
NOTE: Avoid a floating port A input by clearing its pulldown register bit before
changing its DDRA bit from logic 1 to logic 0.
Do not use read-modify-write instructions on pulldown register A.
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66
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Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
Port A
7.4.4 Port A External Interrupts
Programming the PIRQ bit in the mask option register to a logic 1
enables the PA3–PA0 pins to serve as external interrupt pins in addition
to the IRQ/V pin. The active interrupt state for the PA3–PA0 pins is a
PP
logic 1 or a rising edge. The active interrupt state for the IRQ/V pin is
PP
a logic 0 or a falling edge. The state of the LEVEL bit in the mask option
register determines whether external interrupt inputs are edge-sensitive
only or both edge- and level-sensitive.
NOTE: When testing for external interrupts, the branch if interrupt pin is high
(BIH) and branch if interrupt pin is low (BIL) instructions test the voltage
on the IRQ/V pin, not the state of the internal IRQ signal. Therefore,
PP
BIH and BIL cannot test the port A external interrupt pins.
7.4.5 Port A Logic
Figure 7-4 shows the port A I/O logic.
READ $0004
EXTERNAL
INTERRUPT
REQUEST
WRITE $0004
DATA DIRECTION
REGISTER A
BIT DDRAx
(PINS PA3–PA0)
PORT A DATA
REGISTER
BIT PAx
WRITE $0000
PAx
8-mA SINK
CAPABILITY
(PINS PA7–PA4)
READ $0000
WRITE $0010
PULLDOWN
REGISTER A
BIT PDIAx
RESET
100-µA
PULLDOWN
DEVICE
MASK OPTION REGISTER ($0017)
Figure 7-4. Port A I/O Circuit
Parallel Input/Output (I/O)
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TechnicalData
67
Pa ra lle l Inp ut/ Outp ut (I/ O)
When a port A pin is programmed as an output, reading the port bit
actually reads the value of the data latch and not the voltage on the pin
itself. When a port A pin is programmed as an input, reading the port bit
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction register bit. Table 7-1
summarizes the operations of the port A pins.
Table 7-1. Port A Pin Functions
Accesses
to PDRA
Accesses
to DDRA
Accesses
to PORTA
Pulldown
Mask
Option
Control Bits
I/O Pin
Mode
PDIAx DDRAx
Read
Write
Read/Write
Read
Pin
Write
(1)
(2)
No
No
0
1
Input, hi-z
Output
PDIA7–PDIA0 DDRA7–DDRA0
PA7–PA0
X
U
X
U
U
PDIA7–PDIA0 DDRA7–DDRA0 PA7-PA0 PA7–PA0
PDIA7–PDIA0 DDRA7–DDRA0 Pin PA7–PA0
Input,
pulldown on
Yes
0
0
Yes
Yes
Yes
0
1
1
1
0
1
Output
Input, hi-z
Output
U
U
U
PDIA7–PDIA0 DDRA7–DDRA0 PA7-PA0 PA7–PA0
PDIA7–PDIA0 DDRA7–DDRA0 Pin PA7–PA0
PDIA7–PDIA0 DDRA7–DDRA0 PA7-PA0 PA7–PA0
1. X = Don’t care
2. U = Undefined
7.5 Port B
Port B is a 2-bit, general-purpose, bidirectional I/O port with these
features:
• Programmable pulldown devices
• Oscillator output for 3-pin resistance-capacitance (RC) oscillator
configuration
7.5.1 Port B Data Register
The port B data register (PORTB) contains a bit for each of the port B
pins. When a port B pin is programmed to be an output, the state of its
data register bit determines the state of the output pin. When a port B pin
Technical Data
68
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
Port B
is programmed to be an input, reading the port B data register returns
the logic state of the pin. Reset has no effect on port B data.
Address: $0001
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
Bit 0
PB0
Read:
Write:
Reset:
PB1/
OSC3
Unaffected by reset
= Unimplemented
Figure 7-5. Port B Data Register (PORTB)
PB1/OSC3 — Port B Data Bit 1/Oscillator Output Bit
This read/write data bit is software programmable. Data direction
of PB1 bit is under the control of the DDRB1 bit in data direction
register B.
When both the RC and PIN3 bits in the mask option register are set,
PB1/OSC3 can be used as an oscillator output in the 3-pin RC
oscillator configuration. Using PB1/OSC3 as an oscillator output
affects port B in these ways:
a. Bit PB1 can be used as a read/write storage location without
affecting the oscillator. Reset has no effect on bit PB1.
b. Bit DDRB1 in data direction register B can be used as a
read/write storage location without affecting the oscillator.
Reset clears DDRB1.
c. The PB1/OSC3 pulldown device is disabled, regardless of
the state of the SWPDI bit in the mask option register.
PB0 — Port B Data Bit 0
This read/write data bit is software programmable. Data direction of
PB0 is under the control of the DDRB0 bit in data direction register B.
Bits 7–2 — Not Used
Bits 7–2 always read as logic 0s. Writes to these bits have no effect.
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
Parallel Input/Output (I/O)
69
Pa ra lle l Inp ut/ Outp ut (I/ O)
7.5.2 Data Direction Register B
The contents of data direction register B (DDRB) determine whether
each port B pin is an input or an output. Writing a logic 1 to a DDRB bit
enables the output buffer for the associated port B pin; a logic 0 disables
the output buffer. A reset initializes all DDRB bits to logic 0, configuring
all port B pins as inputs. Setting a DDRB bit to a logic 1 turns off the
pulldown device for that pin.
Address: $0005
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
Bit 0
Read:
Write:
Reset:
DDRB1 DDRB0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-6. Data Direction Register B (DDRB)
DDRB1 and DDRB0 — Data Direction Bits 1 and 0
These read/write bits control port B data direction.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Bit 7–2 — Not Used
Bits 7–2 always read as logic 0s. Writes to these bits have no effect.
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
7.5.3 Pulldown Register B
Programming the SWPDI bit in the mask option register to a logic 0
enables the port A and port B pulldown devices. The port B pulldown
devices sink approximately 100 µA and are under the control of the
PDIB1 and PDIB0 bits in pulldown register B (PDRB). Clearing PDIB1
and PDIB0 turns on the port B pulldown devices if they are configured
as inputs. A pulldown device can be turned on only when its pin is an
input. When SWPDI is a logic 0, reset initializes both port B pins as
inputs with pulldown devices turned on.
Technical Data
70
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
Port B
Programming the SWPDI bit to a logic 1 disables both of the port B
pulldown devices. Reset initializes both port B pins as inputs with
pulldown devices disabled when the SWPDI bit is programmed to a
logic 1.
Address: $0011
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
PDIB1
0
PDIB0
0
= Unimplemented
Figure 7-7. Pulldown Register B (PDRB)
PDIB1 and PDIB0 — Port B Pulldown Inhibit Bits 1 and 0
Writing logic 0s to these write-only bits turns on the port B pulldown
devices. Reading pulldown register B returns undefined data. Reset
clears PDIB1 and PDIB0.
1 = Corresponding port B pin pulldown device turned off
0 = Corresponding port B pin pulldown device turned on
Bits 7–2 — Not Used
Bits 7–2 always read as logic 0s.
Programming the SWPDI bit in the mask option register to logic 1 turns
off all port A and port B pulldown devices and disables software control
of the pulldown devices. Reset has no effect on the pulldown devices
when the SWPDI bit is set to a logic 1.
NOTE: Avoid a floating port B input by clearing its pulldown register bit before
changing its DDRB bit from logic 1 to logic 0.
Do not use read-modify-write instructions on pulldown register B.
7.5.4 Port B Logic
Figure 7-8 shows the port B I/O logic.
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
71
Parallel Input/Output (I/O)
Pa ra lle l Inp ut/ Outp ut (I/ O)
READ $0005
WRITE $0005
TO 3-PIN OSCILLATOR
DATA DIRECTION
REGISTER B
BIT DDRB1
PORT B DATA
REGISTER
BIT PB1
WRITE $0001
PB1/
OSC3
READ $0001
WRITE $0011
PULLDOWN
REGISTER B
BIT PDIB1
100-µA
PULLDOWN
DEVICE
MASK OPTION REGISTER ($0017)
READ $0005
WRITE $0005
DATA DIRECTION
REGISTER B
BIT DDRB0
PORT B DATA
REGISTER
BIT PB0
WRITE $0001
PB0
READ $0001
WRITE $0011
100-µA
PULLDOWN
DEVICE
PULLDOWN
REGISTER B
BIT PDIB0
RESET
Figure 7-8. Port B I/O Circuit
Technical Data
72
MC68HC705K1 — Rev. 2.0
MOTOROLA
Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
Port B
When a port B pin is programmed as an output, reading the port bit reads
the value of the data latch and not the voltage on the pin itself. When a
port B pin is programmed as an input, reading the port bit reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its DDR bit. Table 7-2 summarizes the operation of the
PB0 pin.
Programming the RC and PIN3 bits to logic 1 disables the PB1/OSC3
output buffer and pulldown device. The PB1/OSC3 bit becomes an
output from the 3-pin RC oscillator. The DDRB1 and PB1 bits are
available as read/write storage locations; reset clears DDRB1 but does
not affect PB1. Table 7-3 summarizes the operation of the PB1/OSC3
pin.
Table 7-2. PB0 Pin Functions
Accesses
to PDRB
Accesses
to DDRB
Accesses
to PORTB
Control Bits
PDIB0
PB0
Pin Mode
SWPDI
DDRB0
Read
Write
PDIB0
PDIB0
Read/Write
DDRB0
Read
Write
PB0
(1)
(2)
1
1
0
1
Input, hi-z
Output
Pin
X
U
X
0
U
DDRB0
PB0
PB0
Input,
pulldown on
0
0
U
PDIB0
DDRB0
Pin
PB0
0
0
0
0
1
1
1
0
1
Output
Input, hi-z
Output
U
U
U
PDIB0
PDIB0
PDIB0
DDRB0
DDRB0
DDRB0
PB0
Pin
PB0
PB0
PB0
PB0
1. X = Don’t care
2. U = Undefined
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
73
Parallel Input/Output (I/O)
Pa ra lle l Inp ut/ Outp ut (I/ O)
Table 7-3. PB1/OSC3 Pin Functions
Accesses
to PDRB
Accesses
to DDRB
Accesses
to PORTB
Control Bits
PB1/OSC3
Pin Mode
RC PIN3 SWPDI PDIB1 DDRB1
Read
Write
Read/Write
DDRB1
Read Write
(1)
(2)
0
0
1
1
X
X
0
1
Input, hi-z
Output
PDIB1
PDIB1
Pin
PB1
PB1
X
U
X
U
DDRB1
PB1
Input,
pulldown on
0
X
0
0
0
U
PDIB1
DDRB1
Pin
PB1
0
0
0
1
1
X
X
X
0
0
0
0
1
1
0
1
1
X
X
1
0
1
0
1
Output
Input, hi-z
Output
U
U
U
U
U
PDIB1
PDIB1
PDIB1
PDIB1
PDIB1
DDRB1
DDRB1
DDRB1
DDRB1
DDRB1
PB1
Pin
PB1
PB1
PB1
PB1
PB1
PB1
Pin
Input, hi-z
Output
0
PB1
Input,
pulldown on
1
0
0
0
0
U
PDIB1
DDRB1
Pin
PB1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
1
Output
Input, hi-z
Output
U
U
U
PDIB1
PDIB1
PDIB1
DDRB1
DDRB1
DDRB1
PB1
Pin
PB1
PB1
PB1
PB1
3-pin
RC oscillator
output
1
1
X
X
X
U
PDIB1
DDRB1
PB1
PB1
1. X = Don’t care
2. U = Undefined
Technical Data
74
MC68HC705K1 — Rev. 2.0
MOTOROLA
Parallel Input/Output (I/O)
Technical Data — MC68HC705K1
Section 8. Multifunction Timer
8.1 Contents
8.2
8.3
8.4
8.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . .77
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
8.2 Introduction
This section describes the operation of the multifunction timer and the
computer operating properly (COP) watchdog. Figure 8-1 shows the
organization of the timer subsystem.
MC68HC705K1 — Rev. 2.0
MOTOROLA
Technical Data
Multifunction Timer
75
Multifunction Timer
RESET
OVERFLOW
INTERNAL CLOCK
TIMER COUNTER REGISTER
÷ 4
(XTAL ÷ 2)
BITS 0–7 OF 15-STAGE
RIPPLE COUNTER
RESET
INTERRUPT
REQUEST
TIMER STATUS/CONTROL REGISTER
RTI RATE SELECT
RESET
POWER-ON
RESET (POR)
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
BITS 8–14 OF 15-STAGE RIPPLE COUNTER
COP RESET
S
Q
÷ 2
÷ 2
÷ 2
R
RESET
Figure 8-1. Multifunction Timer Block Diagram
Technical Data
76
MC68HC705K1 — Rev. 2.0
MOTOROLA
Multifunction Timer
Multifunction Timer
Timer Status and Control Register
8.3 Timer Status and Control Register
The read/write timer status and control register (TSCR) contains these
bits:
• Timer interrupt enable bits
• Timer interrupt flags
• Timer interrupt flag reset bits
• Timer interrupt rate select bits
Address: $0008
Bit 7
TOF
6
5
TOIE
0
4
RTIE
0
3
2
1
RT1
1
Bit 0
RT0
1
Read:
Write:
Reset:
RTIF
TOFR
U
RTIFR
U
0
0
= Unimplemented
U = Unaffected
Figure 8-2. Timer Status and Control Register (TSCR)
TOF — Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the
counter roll over from $FF to $00. TOF generates a timer overflow
interrupt request if TOIE is also set. Clear TOF by writing a logic 1 to
the TOFR bit. Writing to TOF has no effect. Reset clears TOF.
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected real-time interrupt
(RTI) output becomes active. RTIF generates a real-time interrupt
request if RTIE is also set. Clear RTIF by writing a logic 1 to the
RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF.
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables timer overflow interrupts. Reset clears
TOIE.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
Multifunction Timer
77
Multifunction Timer
RTIE — Real-Time Interrupt Enable Bit
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
TOFR — Timer Overflow Flag Reset
Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always
reads as a logic 0. Reset does not affect TOFR.
RTIFR — Real-Time Interrupt Flag Reset
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR
always reads as a logic 0. Reset does not affect RTIFR.
RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0
These read/write bits select one of four real-time interrupt rates, as
shown in Table 8-1. Because the selected RTI output drives the COP
watchdog, changing the real-time interrupt rate also changes the
counting rate of the COP watchdog. Reset sets RT1 and RT0,
selecting the longest COP timeout period and RTI period.
NOTE: Changing RT1 and RT0 when a COP timeout is imminent or uncertain
may cause an RTI request to be missed or an additional RTI request to
be generated. Clear the COP timer just before changing RT1 and RT0.
Table 8-1. Real-Time Interrupt Rate Selection
Number
of Cycles
to RTI
Number
of Cycles
to COP Reset
RTI
COP Timeout
RT1:RT0
(1)
(1)
Period
Period
14
17
0 0
0 1
1 0
1 1
8.2 ms
16.4 ms
32.8 ms
65.5 ms
65.5 ms
131.1 ms
262.1 ms
524.3 ms
2
2
2
= 16,384
2
2
2
= 131,072
= 262,144
= 524,288
= 1,048,576
15
18
19
= 32,768
16
= 65,536
17
20
2
= 131,072
2
1. At 2-MHz bus, 4-MHz XTAL, 0.5 µs per cycle
Technical Data
78
MC68HC705K1 — Rev. 2.0
MOTOROLA
Multifunction Timer
Multifunction Timer
Timer Counter Register
8.4 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register (TCNTR).
Address: $0009
Bit 7
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-3. Timer Counter Register (TCNTR)
Power-on clears the entire counter chain and begins clocking the
counter. After 4064 cycles, the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Each count of the timer counter register takes eight oscillator cycles or
four cycles of the internal clock.
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
Multifunction Timer
79
Multifunction Timer
8.5 COP Watchdog
Four counter stages at the end of the timer make up the mask-optional
computer operating properly (COP) watchdog. The COP watchdog is a
software error detection system that automatically times out and resets
the MCU if not cleared periodically by a program sequence. Writing a
logic 0 to bit 0 of the COP register clears the COP watchdog and
prevents a COP reset.
Address: $03F0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
COPC
0
U
U
U
U
U
U
U
= Unimplemented
U = Unaffected
Figure 8-4. COP Register (COPR)
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $03F0
returns the read-only memory (ROM) data at that address.
The COP watchdog is active in the run, wait, and halt modes of
operation if the COPEN bit in the mask option register is set.
The STOP instruction disables the COP watchdog by clearing the
counter and turning off its clock source. In applications that depend
on the COP watchdog, the STOP instruction can be disabled by
programming the SWAIT bit to a logic 1 in the mask option register. In
applications that have wait cycles longer than the COP timeout
period, the COP watchdog can be disabled by not programming the
COPEN bit to a logic 1 in the mask option register.
NOTE: If the voltage on the IRQ/V pin exceeds 2 × V , the COP watchdog
PP
DD
turns off and remains off until the IRQ/V voltage falls below 2 × V .
PP
DD
Technical Data
80
MC68HC705K1 — Rev. 2.0
MOTOROLA
Multifunction Timer
Multifunction Timer
COP Watchdog
Table 8-2 summarizes recommended conditions for enabling and
disabling the COP watchdog.
Table 8-2. COP Watchdog Recommendations
Recommended
COP Watchdog
Condition
SWAIT
Voltage on
Wait/Halt Time
(1)
IRQ/V Pin
Bit
PP
Less than 2 × VDD
Less than 2 × VDD
Less than 2 × VDD
1
1
0
Less than COP timeout period
Greater than COP timeout period
X(3)
Enabled(2)
Disabled
Disabled
Automatically
disabled
More than 2 × VDD
X
X
1. The SWAIT bit in the mask option register converts STOP instructions to HALT instruc-
tions.
2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction.
3. X = Don’t care
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
Multifunction Timer
81
Multifunction Timer
Technical Data
82
MC68HC705K1 — Rev. 2.0
MOTOROLA
Multifunction Timer
Technical Data — MC68HC705K1
Section 9. EPROM/OTPROM
9.1 Contents
9.2
9.3
9.4
9.5
9.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . .84
EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . . .85
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9.2 Introduction
This section describes how to program the 504-byte erasable,
programmable read-only memory (EPROM)/one-time programmable
read-only memory (OTPROM).
NOTE: In packages with no quartz window, the 504 bytes of EPROM function
as an OTPROM.
MC68HC705K1 — Rev. 2.0
MOTOROLA
Technical Data
83
EPROM/OTPROM
EPROM/OTPROM
9.3 EPROM Programming Register
The EPROM programming register (EPROG) contains the control bits
for programming the EPROM/OTPROM. In normal operation, the
EPROM programming register is a read-only register that contains all
logic 0s.
Address: $0018
Bit 7
6
5
4
3
2
ELAT
0
1
MPGM
0
Bit 0
EPGM
0
Read:
Write:
Reset:
R
R
R
U
R
R
U
U
R
U
U
= Reserved
U = Unaffected
Figure 9-1. EPROM Programming Register (EPROG)
ELAT — EPROM Bus Latch Bit
This read/write bit configures address and data buses for
programming the EPROM/OTPROM array. EPROM/OTPROM data
cannot be read when ELAT is set. Clearing the ELAT bit also clears
the EPGM bit. Reset clears ELAT.
1 = Address and data buses configured for EPROM/OTPROM
programming
0 = Address and data buses configured for normal operation
MPGM — Mask Option Register (MOR) Programming Bit
This read/write bit applies programming power from the IRQ/V pin
PP
to the MOR. Reset clears MPGM.
1 = MOR programming power switched on
0 = MOR programming power switched off
EPGM — EPROM Programming Bit
This read/write bit applies the voltage from the IRQ/V pin to the
PP
EPROM/OTPROM. To write the EPGM bit, the ELAT bit must already
be set. Reset clears EPGM.
1 = EPROM/OTPROM programming power switched on
0 = EPROM/OTPROM programming power switched off
Technical Data
84
MC68HC705K1 — Rev. 2.0
EPROM/OTPROM
MOTOROLA
EPROM/OTPROM
EPROM/OTPROM Programming
NOTE: Writing logic 1s to both the ELAT and EPGM bits with a single instruction
sets ELAT and clears EPGM. ELAT must be set first by a separate
instruction.
Bits 7–3 — Reserved
Bits 7–3 are factory test bits that always read as logic 0s.
9.4 EPROM/OTPROM Programming
The MC68HC705K1 does not contain built-in bootloader ROM code. To
program this device, use an external programming system such as the
M68HC705KICS evaluation module (EVM) or an M68HC705K1GANG
programmer.
Factory-provided software for programming the EPROM/OTPROM is
available through the Motorola web site at:
htt://mcu.motsps.com
The programming software copies to the 496-byte space located at
EPROM/OTPROM addresses $0200–$03EF, to the 8-byte space at
addresses $03F8–$03FF, and to the mask option register at address
$0017.
Figure 9-2 shows the circuit used to download to the on-chip
EPROM/OTPROM using the factory-provided programming software.
This sequence shows the steps in programming a byte of
EPROM/OTPROM:
1. Switch S1 powers up the MC68HC705K1.
2. Software synchronizes the external oscillator to the internal clock.
3. Switch S2 applies V to the IRQ/V pin.
PP
PP
4. Software sets the ELAT bit.
5. Software writes to an EPROM/OTPROM address.
6. Software sets the EPGM bit for a time t
programming voltage.
to apply the
EPGM
7. Software clears the ELAT bit.
NOTE: To program the EPROM/OTPROM, V must be greater than 4.5 Vdc.
DD
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
85
EPROM/OTPROM
EPROM/OTPROM
V
CC
2.2 kΩ
2.2 kΩ
V
CC
220 Ω
1
14
2
15
3
16
4
17
5
STROBE
D0
MC68HC705K1
1
16
15
14
13
12
11
10
9
RESET
PB1
OSC1
OSC2
2
3
4
5
6
7
8
PB0
V
SS
D1
INIT
D2
IRQ/V
V
DD
0.1µF
PP
PA0
PA1
PA2
PA3
PA7
PA6
PA5
PA4
V
CC
D3
D4
18
6
DIP SOCKET
19
7
20
8
D5
D6
21
9
D7
MC68HC705K1
22
10
23
11
24
12
25
13
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RESET
PB1
PB0
OSC1
OSC2
ACK
V
SS
V
DD
PA7
PA6
PA5
PA4
IRQ/V
PP
PA0
PA1
PA2
PA3
PE
0.1 µF
SOIC SOCKET
170 µH
5 V
IN5817
330 Ω
V
8
7
6
5
1
CC
4.7 Ω
10 µF
DR COL
SENSE
SW COL
SW EMIT
CAP
5 kΩ
2
3
4
S1
V
CC
+
+
COMPARE
GND
100 pF
0.1 µF
10 µF
MC34063
100 Ω
15 kΩ
1.5 kΩ
V
PP
OPTIONAL V GENERATOR
PP
S2
10 µH
0.1 µF
+
+
100 Ω
10 µF
0.1 µF
10 µF
Figure 9-2. Programming Circuit
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EPROM/OTPROM
EPROM/OTPROM
EPROM Erasing
9.5 EPROM Erasing
MCUs with windowed packages permit EPROM erasure with ultraviolet
2
light. Erase the EPROM by exposing it to 15 Ws/cm of ultraviolet light
with a wave length of 2537 angstroms. Position the ultraviolet light
source 1 inch from the window. Do not use a shortwave filter. The erased
state of an EPROM bit is a logic 0.
9.6 Mask Option Register
The mask option register (MOR) is an EPROM/OTPROM byte that
controls these options:
• Port A and port B programmable pulldown devices (enable or
disable)
• Oscillator connections (2-pin or 3-pin RC oscillator)
• Oscillator connections (RC oscillator or crystal/ceramic resonator)
• STOP instruction (enable or disable)
• Low-voltage reset (enable or disable)
• Port A external interrupt function (enable or disable)
• IRQ trigger sensitivity (edge-triggered only or both edge- and
level-triggered)
• COP watchdog (enable or disable)
The mask option register is unaffected by reset. The erased state of the
mask option register is $0000.
Address: $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
SWPDI
PIN3
RC
SWAIT
LVRE
PIRQ
LEVEL COPEN
Reset:
Erased:
Unaffected by reset
0
0
0
0
0
0
0
0
Figure 9-3. Mask Option Register (MOR)
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EPROM/OTPROM
EPROM/OTPROM
SWPDI —Software Pulldown Inhibit Bit
This EPROM bit inhibits software control of the port A and port B
pulldown devices.
1 = Software pulldown inhibited
0 = Software pulldown enabled
PIN3 — 3-Pin RC Oscillator Bit
This EPROM bit configures the on-chip oscillator as either a 3-pin
oscillator or as a 2-pin oscillator. The PIN3 bit should be cleared when
the RC bit is clear.
1 = 3-pin oscillator configured
0 = 2-pin oscillator configured
RC — RC Oscillator Bit
This EPROM bit configures the on-chip oscillator for an external RC
network.
1 = Oscillator configured for external RC network
0 = Oscillator configured for external crystal, ceramic resonator, or
clock source
SWAIT — STOP Conversion to WAIT Bit
This EPROM bit disables the STOP instruction and prevents
inadvertently turning off the COP watchdog with a STOP instruction.
When the SWAIT bit is set, a STOP instruction puts the MCU in halt
mode. Halt mode is a low-power state similar to wait mode. The
internal oscillator and timer clock continue to run, but the CPU clock
stops. When the SWAIT bit is clear, a STOP instruction stops the
internal oscillator, the internal clock, the CPU clock, and the timer
clock.
1 = STOP instruction converted to WAIT instruction
0 = STOP instruction not converted to WAIT instruction
LVRE — Low-Voltage Reset Enable Bit
This EPROM bit enables the low-voltage reset (LVR) circuit.
1 = LVR circuit enabled
0 = LVR circuit disabled
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EPROM/OTPROM
Mask Option Register
PIRQ — Port A IRQ Enable Bit
This EPROM bit enables the PA3–PA0 pins to function as external
interrupt sources.
1 = PA3–PA0 enabled as external interrupt sources
0 = PA3–PA0 not enabled as external interrupt sources
LEVEL — External Interrupt Sensitivity Bit
This EPROM bit makes the external interrupt inputs level-triggered as
well as edge-triggered.
1 = IRQ/V pin negative-edge triggered and low-level triggered;
PP
PA3–PA0 pins positive-edge triggered and high-level triggered
0 = IRQ/V pin negative-edge triggered only; PA3–PA0 pins
PP
positive-edge triggered only
COPEN — COP Watchdog Enable Bit
This EPROM bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
NOTE: In 3-pin RC oscillator configurations, the personality EPROM
(PEPROM) cannot be programmed by user software. If the voltage on
IRQ/V is raised above V , the oscillator will revert to a 2-pin oscillator
PP
DD
configuration and device operation will be disrupted.
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EPROM/OTPROM
EPROM/OTPROM
Technical Data
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EPROM/OTPROM
Technical Data — MC68HC705K1
Section 10. Personality EPROM (PEPROM)
10.1 Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.3 PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
10.3.1 PEPROM Bit Select Register . . . . . . . . . . . . . . . . . . . . . . . .93
10.3.2 PEPROM Status and Control Register. . . . . . . . . . . . . . . . .95
10.4 PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.5 PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.6 PEPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.2 Introduction
This section describes how to program the 64-bit personality erasable,
programmable read-only memory (PEPROM). Figure 10-1 shows the
structure of the PEPROM subsystem.
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Personality EPROM (PEPROM)
INTERNAL DATA BUS
PEPROM STATUS/CONTROL REGISTER
RESET
SINGLE
SENSE
AMPLIFIER
V
PP
ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
8-TO-1 COLUMN DECODER
AND MULTIPLEXER
8-TO-1 ROW DECODER
AND MULTIPLEXER
V
SWITCH
V SWITCH
PP
PP
ROW ZERO
DECODER
PEPROM STATUS/CONTROL REGISTER
INTERNAL DATA BUS
RESET
Figure 10-1. Personality EPROM
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Personality EPROM (PEPROM)
Personality EPROM (PEPROM)
PEPROM Registers
10.3 PEPROM Registers
Two input/output (I/O) registers control programming and reading of the
PEPROM:
• PEPROM bit select register (PEBSR)
• PEPROM status and control register (PESCR)
10.3.1 PEPROM Bit Select Register
The PEPROM bit select register (PEBSR) selects one of 64 bits in the
PEPROM array. Reset clears all the bits in the PEPROM bit select
register.
Address: $000E
Bit 7
PEB7
0
6
PEB6
0
5
PEB5
0
4
PEB4
0
3
PEB3
0
2
PEB2
0
1
PEB1
0
Bit 0
PEB0
0
Read:
Write:
Reset:
Figure 10-2. PEPROM Bit Select Register (PEBSR)
PEB7 and PEB6 — Not Connected to the PEPROM Array
These read/write bits are available as storage locations. Reset clears
PEB7 and PEB6.
PEB5–PEB0 — PEPROM Bit Select Bits
These read/write bits select one of 64 bits in the PEPROM as shown
in Table 10-1. Bits PEB2–PEB0 select the PEPROM row, and bits
PEB5–PEB3 select the PEPROM column. Reset clears PEB5–PEB0,
selecting the PEPROM bit in row zero, column zero.
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Personality EPROM (PEPROM)
Table 10-1. PEPROM Bit Selection
PEBSR
$00
PEPROM Bit Selected
Row 0
Row 1
Row 2
Column 0
Column 0
Column 0
$01
$02
$07
$08
$09
$0A
Row 7
Row 0
Row 1
Row 2
Column 0
Column 1
Column 1
Column 1
$0F
$10
$11
$12
Row 7
Row 0
Row 1
Row 2
Column 1
Column 2
Column 2
Column 2
$37
$38
$39
$3A
$3B
$3C
$3D
$3E
$3F
Row 7
Row 0
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Column 6
Column 7
Column 7
Column 7
Column 7
Column 7
Column 7
Column 7
Column 7
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Personality EPROM (PEPROM)
Personality EPROM (PEPROM)
PEPROM Registers
10.3.2 PEPROM Status and Control Register
The PEPROM status and control register (PESCR) controls the
PEPROM programming voltage. This register also transfers the
PEPROM bits to the internal data bus and contains a row zero flag.
Address: $000F
Bit 7
Read: PEDATA
Write:
6
0
0
5
PEPGM
0
4
0
0
3
0
0
2
0
0
1
0
0
Bit 0
PEPRZF
Reset:
U
1
= Unimplemented
U = Unaffected
Figure 10-3. PEPROM Status and Control Register (PESCR)
PEDATA — PEPROM Data Bit
This read-only bit is the state of the PEPROM sense amplifier and
shows the state of the currently selected bit. Reset does not affect the
PEDATA bit.
1 = PEPROM data logic 1
0 = PEPROM data logic 0
PEPGM — PEPROM Program Control Bit
This read/write bit controls the switches that apply the programming
voltage, V , to the selected PEPROM cell. Reset clears PEPGM.
PP
1 = Programming voltage applied
0 = Programming voltage not applied
PEPRZF — PEPROM Row Zero Flag
This read-only bit is set when the PEPROM bit select register selects
the first row (row zero) of the PEPROM array. Selecting any other row
clears PEPRZF. Monitoring PEPRZF can reduce the code needed to
access one byte of PEPROM. Reset sets PEPRZF.
1 = Row zero selected
0 = Row zero not selected
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Personality EPROM (PEPROM)
10.4 PEPROM Programming
Factory-provided software for programming the PEPROM is available
through the Motorola web site at:
htt://mcu.motsps.com
The circuit shown in Figure 9-2. Programming Circuit can be used to
program the PEPROM with the factory-provided programming software.
NOTE: To program the PEPROM, V must be greater than 4.5 Vdc.
DD
The PEPROM can also be programmed by user software with V
PP
applied to the IRQ/V pin. This sequence shows how to program each
PP
PEPROM bit:
1. Select a PEPROM bit by writing to PEBSR.
2. Set the PEPGM bit in PESCR.
3. Wait 3 ms.
4. Clear the PEPGM bit.
NOTE: While the PEPGM bit is set and V is applied to the IRQ/V pin, do not
PP
PP
access bits that are to be left unprogrammed (erased).
In 3-pin RC oscillator configurations, the PEPROM cannot be
programmed by user software. If the voltage on IRQ/V is raised above
PP
V , the oscillator will revert to a 2-pin oscillator configuration and
DD
device operation will be disrupted.
10.5 PEPROM Reading
This sequence shows how to read the PEPROM:
1. Select a bit by writing to PEBSR.
2. Read the PEDATA bit in PESCR.
3. Store the PEDATA bit in RAM or in a register.
4. Select another bit by changing PEBSR.
5. Continue reading and storing the PEDATA bits until the required
personality EPROM data is stored.
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MOTOROLA
Personality EPROM (PEPROM)
PEPROM Erasing
Reading the PEPROM is easiest when each PEPROM column contains
one byte. Selecting a row 0 bit selects the first bit, and incrementing the
PEPROM bit select register (PEBSR) selects the next row 1 bit from the
same column. Incrementing PEBSR seven more times selects the
remaining bits of the column and selects the row 0 bit of the next column,
setting the row 0 flag, PEPRZF.
A PEPROM byte that has been read can be transferred to the
personality EPROM bit select register (PEBSR) so that subsequent
reads of the PEBSR quickly yield that PEPROM byte.
10.6 PEPROM Erasing
MCUs with windowed packages permit PEPROM erasure with
2
ultraviolet light. Erase the PEPROM by exposing it to 15 Ws/cm of
ultraviolet light with a wave length of 2537 angstroms. Position the
ultraviolet light source 1 inch from the window. Do not use a shortwave
filter. The erased state of a PEPROM bit is a logic 0.
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Personality EPROM (PEPROM)
Technical Data
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Personality EPROM (PEPROM)
Technical Data — MC68HC705K1
Section 11. Instruction Set
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .104
11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .105
11.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .106
11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .108
11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
11.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
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Instruction Set
11.2 Introduction
The microcontroller unit (MCU) instruction set has 62 instructions and
uses eight addressing modes. The instructions include all those of the
M146805 CMOS Family plus one more: the unsigned multiply (MUL)
instruction. The MUL instruction allows unsigned multiplication of the
contents of the accumulator (A) and the index register (X). The
high-order product is stored in the index register, and the low-order
product is stored in the accumulator.
11.3 Addressing Modes
The central processor unit (CPU) uses eight addressing modes for
flexibility in accessing data. The addressing modes provide eight
different ways for the CPU to find the data required to execute an
instruction.
The eight addressing modes are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
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Instruction Set
Instruction Set
Addressing Modes
11.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
11.3.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
11.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
11.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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Instruction Set
11.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
11.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
11.3.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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Instruction Set
Instruction Types
11.3.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
11.4 Instruction Types
The MCU instructions fall into five categories:
• Register/memory instructions
• Read-modify-write instructions
• Jump/branch instructions
• Bit manipulation instructions
• Control instructions
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Instruction Set
11.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 11-1. Register/Memory Instructions
Instruction
Add memory byte and carry bit to accumulator
Add memory byte to accumulator
AND memory byte with accumulator
Bit test accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare accumulator
CMP
CPX
Compare index register with memory byte
Exclusive OR accumulator with memory byte
Load accumulator with memory byte
Load Index register with memory byte
Multiply
EOR
LDA
LDX
MUL
ORA
OR accumulator with memory byte
Subtract memory byte and carry bit from
accumulator
SBC
Store accumulator in memory
STA
STX
SUB
Store index register in memory
Subtract memory byte from accumulator
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Instruction Set
Instruction Types
11.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE: Do not use read-modify-write operations on write-only registers.
Table 11-2. Read-Modify-Write Instructions
Instruction
Arithmetic shift left (same as LSL)
Arithmetic shift right
Mnemonic
ASL
ASR
(1)
Bit clear
BCLR
(1)
Bit set
BSET
Clear register
CLR
COM
DEC
INC
Complement (one’s complement)
Decrement
Increment
Logical shift left (same as ASL)
Logical shift right
LSL
LSR
NEG
ROL
ROR
Negate (two’s complement)
Rotate left through carry bit
Rotate right through carry bit
Test for negative or zero
(2)
TST
1. Unlike other read-modify-write instructions, BCLR and BSET use
only direct addressing.
2. TST is an exception to the read-modify-write sequence because it
does not write a replacement value.
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Instruction Set
Instruction Set
11.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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Instruction Set
Instruction Types
Table 11-3. Jump and Branch Instructions
Instruction
Branch if carry bit clear
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if carry bit set
Branch if equal
Branch if half-carry bit clear
Branch if half-carry bit set
Branch if higher
Branch if higher or same
Branch if IRQ pin high
Branch if IRQ pin low
Branch if lower
BHS
BIH
BIL
BLO
BLS
Branch if lower or same
Branch if interrupt mask clear
Branch if minus
BMC
BMI
Branch if interrupt mask set
Branch if not equal
Branch if plus
BMS
BNE
BPL
Branch always
BRA
BRCLR
BRN
BRSET
BSR
JMP
JSR
Branch if bit clear
Branch never
Branch if bit set
Branch to subroutine
Unconditional jump
Jump to subroutine
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Instruction Set
11.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 11-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Bit clear
Branch if bit clear
Branch if bit set
Bit set
BRCLR
BRSET
BSET
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Instruction Set
Instruction Types
11.4.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 11-5. Control Instructions
Instruction
Mnemonic
CLC
CLI
Clear carry bit
Clear interrupt mask
No operation
NOP
RSP
RTI
Reset stack pointer
Return from interrupt
Return from subroutine
Set carry bit
RTS
SEC
SEI
Set interrupt mask
Stop oscillator and enable IRQ pin
Software interrupt
STOP
SWI
Transfer accumulator to index register
Transfer index register to accumulator
Stop CPU clock and enable interrupts
TAX
TXA
WAIT
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
109
Instruction Set
Instruction Set
11.5 Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 1 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
ii
dd
hh ll
ee ff
ff
ADC #opr
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
2
3
4
5
4
3
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
Add without Carry
Logical AND
A ← (A) + (M) + (C)
↕ — ↕ ↕ ↕
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM
DIR
EXT CB
IX2
IX1
IX
AB
BB
2
3
4
5
4
3
A ← (A) + (M)
↕ — ↕ ↕ ↕
DB
EB
FB
ii
dd
hh ll
ee ff
ff
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
2
3
4
5
4
3
A ← (A) (M)
— — ↕ ↕ —
dd
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
38
48
58
68
78
5
3
3
6
5
C
0
Arithmetic Shift Left (Same as LSL)
— — ↕ ↕ ↕ INH
IX1
IX
b7
b7
b0
b0
ff
dd
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
37
47
57
67
77
5
3
3
6
5
C
Arithmetic Shift Right
— — ↕ ↕ ↕ INH
IX1
IX
ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? C = 0
— — — — — REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
BCS rel
BEQ rel
BHCC rel
BHCS rel
BHI rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
25 rr
27 rr
28 rr
29 rr
22 rr
24 rr
3
3
3
3
3
3
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? C Z = 0 — — — — — REL
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL
BHS rel
Branch if Higher or Same
Technical Data
110
MC68HC705K1 — Rev. 2.0
MOTOROLA
Instruction Set
Instruction Set
Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 2 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL
2F rr
2E rr
3
3
BIL rel
Branch if IRQ Pin Low
ii
dd
hh ll
ee ff
ff
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
2
3
4
5
4
3
Bit Test Accumulator with Memory Byte
(A) (M)
— — ↕ ↕ —
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? C = 1
— — — — — REL
25 rr
23 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? C Z = 1 — — — — — REL
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
PC ← (PC) + 2 + rel ? Mn = 0 — — — — ↕
BRN rel
Branch Never
PC ← (PC) + 2 + rel ? 1 = 0
— — — — — REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
PC ← (PC) + 2 + rel ? Mn = 1 — — — — ↕
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
Set Bit n
Mn ← 1
— — — — —
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
— — — — — REL AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
— 0 — — —
INH
INH
98
9A
2
2
Clear Interrupt Mask
MC68HC705K1 — Rev. 2.0
MOTOROLA
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111
Instruction Set
Instruction Set
Table 11-6. Instruction Set Summary (Sheet 3 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
dd
ff
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
5
3
3
6
5
Clear Byte
— — 0 1 —
— — ↕ ↕ ↕
— — ↕ ↕ 1
— — ↕ ↕ ↕
— — ↕ ↕ —
— — ↕ ↕ —
ii
dd
hh ll
ee ff
ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
2
3
4
5
4
3
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
Decrement Byte
(A) – (M)
dd
ff
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
5
3
3
6
5
ii
dd
hh ll
ee ff
ff
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
2
3
4
5
4
3
(X) – (M)
dd
ff
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
5
3
3
6
5
ii
dd
hh ll
ee ff
ff
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
2
3
4
5
4
3
EXCLUSIVE OR Accumulator with Memory
Byte
A ← (A) (M)
dd
ff
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
5
3
3
6
5
Increment Byte
— — ↕ ↕ —
dd
hh ll
ee ff
ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT CC
IX2
IX1
IX
BC
2
3
4
3
2
Unconditional Jump
PC ← Jump Address
— — — — —
DC
EC
FC
Technical Data
112
MC68HC705K1 — Rev. 2.0
MOTOROLA
Instruction Set
Instruction Set
Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 4 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
dd
hh ll
ee ff
ff
JSR opr
DIR
EXT CD
IX2
IX1
IX
BD
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
— — — — —
DD
ED
FD
ii
dd
hh ll
ee ff
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
2
3
4
5
4
3
Load Accumulator with Memory Byte
A ← (M)
X ← (M)
— — ↕ ↕ —
ii
dd
hh ll
ee ff
ff
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM
DIR
EXT CE
IX2
IX1
IX
AE
BE
2
3
4
5
4
3
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
— — ↕ ↕ —
DE
EE
FE
dd
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
38
48
58
68
78
5
3
3
6
5
C
0
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
ff
dd
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
34
44
54
64
74
5
3
3
6
5
0
C
Logical Shift Right
Unsigned Multiply
— — 0 ↕ ↕ INH
b7
b0
IX1
IX
ff
1
1
MUL
X : A ← (X) × (A)
0 — — — 0
INH
42
dd
ff
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
30
40
50
60
70
5
3
3
6
5
Negate Byte (Two’s Complement)
No Operation
— — ↕ ↕ ↕ INH
IX1
IX
NOP
— — — — —
INH
9D
2
ii
dd
hh ll
ee ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT CA
IX2
IX1
IX
AA
BA
2
3
4
5
4
3
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
A ← (A) (M)
— — ↕ ↕ —
DA
EA
FA
dd
ff
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
39
49
59
69
79
5
3
3
6
5
C
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
113
Instruction Set
Instruction Set
Table 11-6. Instruction Set Summary (Sheet 5 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
dd
ff
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
36
46
56
66
76
5
3
3
6
5
C
Rotate Byte Right through Carry Bit
— — ↕ ↕ ↕ INH
b7
b0
IX1
IX
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $00FF
— — — — —
INH
9C
2
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
↕ ↕ ↕ ↕ ↕ INH
80
9
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
— — — — —
INH
81
6
ii
dd
hh ll
ee ff
ff
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
2
3
4
5
4
3
Subtract Memory Byte and Carry Bit from
Accumulator
A ← (A) – (M) – (C)
— — ↕ ↕ ↕
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
— 1 — — —
INH
INH
99
9B
2
2
Set Interrupt Mask
dd
hh ll
ee ff
ff
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
4
5
6
5
4
Store Accumulator in Memory
Stop Oscillator and Enable IRQ Pin
Store Index Register In Memory
M ← (A)
— — ↕ ↕ —
— 0 — — —
— — ↕ ↕ —
STOP
INH
8E
2
dd
hh ll
ee ff
ff
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
4
5
6
5
4
M ← (X)
ii
dd
hh ll
ee ff
ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
2
3
4
5
4
3
Subtract Memory Byte from Accumulator
A ← (A) – (M)
— — ↕ ↕ ↕
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
1
0
SWI
TAX
Software Interrupt
— 1 — — —
— — — — —
INH
INH
83
97
Transfer Accumulator to Index Register
X ← (A)
2
Technical Data
114
MC68HC705K1 — Rev. 2.0
MOTOROLA
Instruction Set
Instruction Set
Opcode Map
Table 11-6. Instruction Set Summary (Sheet 6 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
dd
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
4
3
3
5
4
Test Memory Byte for Negative or Zero
(M) – $00
— — ↕ ↕ —
ff
TXA
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
A ← (X)
— — — — —
— 0 — — —
INH
INH
9F
8F
2
2
WAIT
A
C
Accumulator
Carry/borrow flag
opr
PC
Operand (one or two bytes)
Program counter
CCR Condition code register
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
dd
Direct address of operand
dd rr
DIR
ee ff
EXT
ff
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
rel
rr
SP
X
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
H
Z
Zero flag
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
#
Immediate value
Logical AND
ii
Immediate operand byte
Logical OR
IMM
INH
IX
IX1
IX2
M
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
( )
–( )
←
?
:
↕
—
If
Concatenated with
Set or cleared
Not affected
N
n
Negative flag
Any bit
11.6 Opcode Map
See Table 11-7.
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
115
Instruction Set
Table 11-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
INH
IX1
IX
7
INH
INH
IMM
A
DIR
B
EXT
IX2
IX1
E
IX
F
MSB
LSB
MSB
LSB
0
1
2
4
5
6
8
9
C
D
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
SUB
SUB
SUB
SUB
SUB
SUB
CMP
SBC
CPX
AND
BIT
0
1
0
3
DIR 2
5
BRCLR0
DIR 2
5
BRSET1
DIR 2
5
BRCLR1
DIR 2
5
BRSET2
DIR 2
5
BRCLR2
DIR 2
5
BRSET3
DIR 2
5
BRCLR3
DIR 2
5
BRSET4
DIR 2
5
BRCLR4
DIR 2
5
BRSET5
DIR 2
5
BRCLR5
DIR 2
5
BRSET6
DIR 2
5
BRCLR6
DIR 2
5
BRSET7
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
6
RTS
INH
2
2
2
2
2
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
CMP
IX2 2
IX1 1
4
CMP
IX1 1
IX
3
BCLR0
BRN
CMP
CMP
CMP
1
2
3
3
DIR 2
5
REL
3
1
IMM 2
2
DIR 3
3
EXT 3
4
IX
3
11
5
4
BSET1
BHI
MUL
SBC
SBC
SBC
SBC
CPX
AND
BIT
SBC
CPX
AND
BIT
2
DIR 2
5
REL
3
1
5
INH
3
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
3
6
5
10
SWI
INH
BCLR1
BLS
COM
COMA
COMX
COM
COM
LSR
CPX
CPX
CPX
3
3
3
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX 1
5
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET2
BCC
LSR
LSRA
LSRX
LSR
AND
AND
AND
4
4
DIR 2
5
BCLR2 BCS/BLO
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BIT
BIT
BIT
5
5
3
DIR 2
5
REL
3
IMM 2
2
DIR 3
3
LDA
DIR 3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
5
3
3
6
5
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
ASR
LDA
LDA
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
6
6
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
IMM 2
EXT 3
5
IX2 2
6
IX1 1
5
IX
4
2
4
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
STA
7
7
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
1
1
1
1
1
1
1
INH
2
2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
CLC
EOR
EOR
EOR
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
8
8
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
DEC
SEC
ADC
ADC
ADC
9
9
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET5
BPL
DEC
DECA
DECX
DEC
CLI
SEI
ORA
ORA
ORA
A
B
C
D
E
F
A
B
C
D
E
F
3
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BCLR5
BMI
ADD
ADD
ADD
3
DIR 2
5
REL
3
INH 2
2
IMM 2
DIR 3
2
EXT 3
3
IX2 2
4
IX1 1
3
IX
2
5
3
3
6
5
BSET6
BMC
INC
INCA
INCX
INC
TST
INC
TST
RSP
INH
JMP
JMP
3
DIR 2
5
REL 2
3
DIR 1
4
INH 1
3
INH 2
3
IX1 1
5
IX
4
2
6
DIR 3
5
EXT 3
6
IX2 2
7
IX1 1
6
IX
5
2
BCLR6
BMS
TST
TSTA
TSTX
NOP
BSR
JSR
JSR
3
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
REL 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
2
BSET7
BIL
STOP
LDX
LDX
LDX
3
DIR 2
5
DIR 2
5
BCLR7
DIR 2
REL
3
BIH
REL 2
1
INH
2
WAIT
INH 1
2
2
IMM 2
DIR 3
4
EXT 3
5
STX
EXT 3
IX2 2
6
IX1 1
5
IX
4
5
3
3
6
5
BRCLR7
CLR
DIR 1
CLRA
INH 1
CLRX
INH 2
CLR
CLR
TXA
INH
STX
3
DIR 2
IX1 1
IX 1
2
DIR 3
IX2 2
IX1 1
IX
MSB
INH = Inherent
IMM = Immediate
DIR = Direct
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
MSB of Opcode in Hexadecimal
Number of Cycles
0
LSB
5
BRSET0 Opcode Mnemonic
DIR Number of Bytes/Addressing Mode
LSB of Opcode in Hexadecimal
0
EXT = Extended
3
Technical Data — MC68HC705K1
Section 12. Electrical Specifications
12.1 Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
12.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
12.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .118
12.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
12.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
12.7 Equivalent Pin Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
12.8 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .121
12.9 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .122
12.10 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
12.11 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.12 Typical Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . .130
12.2 Introduction
This section contains electrical and timing specifications.
MC68HC705K1 — Rev. 2.0
MOTOROLA
Technical Data
Electrical Specifications
117
Electrical Specifications
12.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep V and V
within the range
In
Out
V
≤ (V or V ) ≤ V . Connect unused inputs to the appropriate
In Out DD
SS
voltage level, either V or V .
SS
DD
(1)
Symbol
Value
Unit
Rating
Supply voltage
V
–0.3 to +7.0
V
DD
V
–0.3
SS
Input voltage
V
V
In
PP
I
to V +0.3
DD
V
–0.3 to
DD
EPROM programming voltage
Current drain per pin excluding
V
16.0
25
–65 to +150
mA
V
and V
DD
SS
Storage temperature range
1. Voltages referenced to VSS
T
°C
STG
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 12.8 5.0-Volt DC Electrical Characteristics and
12.9 3.3-Volt DC Electrical Characteristics for guaranteed operating
conditions.
12.4 Operating Temperature Range
(1)
Symbol
Value
T to T
Unit
Rating
(2)
Operating temperature range
MC68HC705K1P, DW, S
L
H
T
°C
A
–40 to +85
MC68HC705K1CP, CDW, CS
1. Voltages referenced to VSS
2. P = Plastic dual in-line package (PDIP)
DW = Small outline integrated circuit (SOIC)
S = Ceramic dual in-line package (cerdip)
C = Extended temperature range (–40°C to +85°C)
Technical Data
118
MC68HC705K1 — Rev. 2.0
MOTOROLA
Electrical Specifications
Electrical Specifications
Thermal Characteristics
12.5 Thermal Characteristics
Characteristic
Symbol
Value
Unit
T
Maximum junction temperature
150
°C
J
Thermal resistance
(1)
θ
MC68HC705K1P
100
140
°C/W
JA
(2)
MC68HC705K1DW
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
12.6 Power Considerations
The average chip junction temperature, T , in °C can be obtained from:
J
T = T + (P x θ )
(1)
J
A
D
JA
Where:
T = ambient temperature in °C
A
θ
= package thermal resistance, junction to ambient in °C/W
JA
P = P
+ P
I/O
D
INT
P
P
= I × V = chip internal power dissipation
CC CC
= power dissipation on input and output pins (user-determined)
INT
I/O
For most applications, P < P
and can be neglected.
I/O
INT
Ignoring P , the relationship between P and T is approximately:
I/O
D
J
K
P =
(2)
(3)
D
T + 273°C
J
Solving equations (1) and (2) for K gives:
= P x (T + 273°C) + θ x (P )
2
D
A
JA
D
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring P (at equilibrium) for a
D
known T . Using this value of K, the values of P and T can be obtained
A
D
J
by solving equations (1) and (2) iteratively for any value of T .
A
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
119
Electrical Specifications
Electrical Specifications
12.7 Equivalent Pin Loading
Figure 12-1 shows the equivalent input/output (I/O) pin loading for test
purposes.
V
DD
R2
R1
TEST POINT
C
PINS
V
R1
R2
C
DD
PA3–PA0, PB1–PB0
PA7–PA4
3.26 kΩ
470 Ω
2.38 kΩ 50 pF
2.38 kΩ 50 pF
4.5 V
PA3–PA0, PB1–PB0 3.0 V 10.91 kΩ 6.32 kΩ 50 pF
Figure 12-1. Equivalent Test Load
Technical Data
120
MC68HC705K1 — Rev. 2.0
MOTOROLA
Electrical Specifications
Electrical Specifications
5.0-Volt DC Electrical Characteristics
12.8 5.0-Volt DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
Output voltage
I
= 10.0 µA
V
—
—
—
0.1
—
V
Load
Load
OL
V
V
– 0.1
I
= –10.0 µA
V
DD
OH
Output high voltage, I
= –0.8 mA
Load
V
– 0.8
—
—
V
V
OH
DD
PA7–PA0, PB1/OSC3, PB0
Output low voltage
I
= 1.6 mA, PA3–PA0, PB1/OSC3, PB0
V
—
—
—
—
0.4
0.4
Load
Load
OL
I
= 8.0 mA, PC7–PC4
Input high voltage
V
0.7 x V
V
—
—
V
V
IH
DD
DD
PA7–PA0, PB1/OSC3, PB0, IRQ/V , RESET, OSC1
PP
Input low voltage
V
V
0.2 x V
DD
IL
SS
PA7–PA0, PB1/OSC3, PB0, IRQ/V , RESET, OSC1
PP
Supply current
(3)
—
—
2.6
0.9
—
—
mA
mA
Run
(4)
Wait
I
(5)
DD
Stop
—
—
—
200
700
1000
—
—
—
nA
nA
nA
25°C
0°C to +70°C (standard)
–40°C to +85°C (extended)
I/O ports hi-z leakage current
PA7–PA0, PB1/OSC3, PB0 (pulldown devices off)
Input pulldown current
I
—
—
±10
µA
µA
OZ
I
50
75
200
IL
PA7–PA0, PB1/OSC3, PB0 (pulldown devices on)
Input current
IRQ/V , OSC1
—
—
1.0
—
—
4.0
±1
±1
8.0
µA
µA
mA
PP
I
In
RESET (pulldown devices off)
RESET (pulldown devices on)
Capacitance
C
V
Ports (input or output)
RESET, IRQ/V
—
—
—
—
12
8
pF
Out
C
PP
In
(6)
2.8
1.0
17.0
—
3.5
2.0
17.5
5
4.5
3.0
18.0
10
V
MΩ
V
Low-voltage reset threshold
LVR
R
Oscillator internal resistor (OSC1 to OSC2)
OSC
(7)
V
Programming voltage
PP
I
Programming current
mA
PP
1. VDD = 5.0 V ±10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 4.2 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2.
4. Wait IDD measured using external square wave clock source (fOSC = 4.2 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2. VIL = 0.2 V, VIH = VDD – 0.2 V. OSC2 capacitance linearly affects wait IDD
.
5. Stop IDD measured with OSC1 = VDD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V. With low-voltage reset
enabled, stop IDD can be as high as 25 µA.
6. All MCUs guaranteed to operate at VDD = 5 V ±10%. Each MCU guaranteed to operate at its VLVR
.
7. Programming voltage measured at IRQ/VPP pin.
MC68HC705K1 — Rev. 2.0
TechnicalData
121
MOTOROLA
Electrical Specifications
Electrical Specifications
12.9 3.3-Volt DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
Output voltage
I
= 10.0 µA
V
—
—
—
0.1
—
V
Load
Load
OL
V
V
– 0.1
I
= –10.0 µA
V
DD
OH
Output high voltage, I
= –0.4 mA
Load
V
– 0.3
—
—
V
V
OH
DD
PA7–PA0, PB1/OSC3, PB0
Output low voltage
I
I
= 0.4 mA, PA3–PA0, PB1/OSC3, PB0
V
—
—
—
—
0.3
0.3
Load
Load
OL
= 3.0 mA, PC7–PC4
Input high voltage
V
0.7 x V
V
—
—
V
V
IH
DD
DD
PA7–PA0, PB1/OSC3, PB0, IRQ/V , RESET, OSC1
PP
Input low voltage
V
V
0.2 x V
DD
IL
SS
PA7–PA0, PB1/OSC3, PB0, IRQ/V , RESET, OSC1
PP
Supply current
(3)
—
—
0.7
300
—
—
mA
µA
Run
(4)
Wait
I
(5)
DD
Stop
—
—
—
50
500
1000
—
—
—
nA
nA
nA
25°C
0°C to +70°C (standard)
–40°C to +85°C (extended)
I/O ports hi-z leakage current
I
—
—
±10
µA
µA
OZ
PA7–PA0, PB1/OSC3, PB0 (pulldown devices off)
Input pulldown current
I
10
20
100
IL
PA7–PA0, PB1/OSC3, PB0 (pulldown devices on)
Input current
IRQ/V , OSC1
—
—
0.2
—
—
2.0
±1
±1
4.0
µA
µA
mA
PP
I
In
RESET (pulldown devices off)
RESET (pulldown devices on)
Capacitance
C
Ports (input or output)
—
—
—
—
12
8
pF
Out
RESET, IRQ/V
C
PP
In
R
Oscillator internal resistor (OSC1 to OSC2)
1.0
2.0
3.0
MΩ
OSC
1. VDD = 3.3 V ±10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 2.0 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2.
4. Wait IDD measured using external square wave clock source (fOSC = 2.0 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2. VIL = 0.2 V, VIH = VDD – 0.2 V. OSC2 capacitance linearly affects wait IDD
.
5. Stop IDD measured with OSC1 = VDD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V. With low-voltage reset
enabled, stop IDD can be as high as 25 µA.
Technical Data
122
MC68HC705K1 — Rev. 2.0
MOTOROLA
Electrical Specifications
Electrical Specifications
3.3-Volt DC Electrical Characteristics
V
= 5.0 V
V = 3.3 V
DD
DD
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
(NOTE 2)
(NOTE 3)
0
–1.0
–2.0
–3.0
–4.0
–5.0
0
–1.0
–2.0
–3.0
–4.0
–5.0
I
(mA)
I
(mA)
OH
OH
Notes:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V versus I curves are approximately straight lines.
2. At V
3. At V
= 5.0 V, devices are specified and tested for V ≤ 800 mV @ I = –0.8 mA.
OL OL
= 3.3 V, devices are specified and tested for V ≤ 300 mV @ I = –0.2 mA.
OL OL
DD
DD
Figure 12-2. Typical High-Side Driver Characteristics
V
= 5.0 V
V = 3.3 V
DD
DD
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
(NOTE 2)
(NOTE 3)
0
2.0
4.0
6.0
8.0
10.0
0
2.0
4.0
6.0
8.0
10.0
I
(mA)
I (mA)
OL
OL
Notes:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V versus I curves are approximately straight lines.
2. At V
3. At V
= 5.0 V, devices are specified and tested for V ≤ 400 mV @ I = 1.6 mA.
OL OL
= 3.3 V, devices are specified and tested for V ≤ 300 mV @ I = 0.4 mA.
OL OL
DD
DD
Figure 12-3. Typical Low-Side Driver Characteristics
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
123
Electrical Specifications
Electrical Specifications
T = 25°C
3.0
2.5
2.0
1.5
1.0
0.5
0
5.5 V
4.5 V
3.6 V
3.0 V
0
0.5
1.0
1.5
2.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 12-4. Run I versus Internal Clock Frequency
DD
T = 25°C
900
800
700
600
500
400
300
200
100
0
5.5 V
4.5 V
3.6 V
3.0 V
0
0.5
1.0
1.5
2.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 12-5. Wait I versus Internal Clock Frequency
DD
Technical Data
124
MC68HC705K1 — Rev. 2.0
MOTOROLA
Electrical Specifications
Electrical Specifications
3.3-Volt DC Electrical Characteristics
2500
2000
1500
1000
500
5.5 V
4.5 V
3.6 V
3.0 V
0
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 12-6. Stop I versus Temperature
DD
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
125
Electrical Specifications
Electrical Specifications
12.10 5.0-Volt Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Oscillator frequency
3-pin RC oscillator
2-pin RC oscillator
(3)
1.2
2.4
4.0
4.0
f
MHz
(3)
0.500
dc
OSC
(2)
Crystal/ceramic resonator
External clock
Internal operating frequency (f
÷ 2)
OSC
0.6
1.2
2.0
2.0
(3)
(3)
3-pin RC oscillator
2-pin RC oscillator
Crystal/ceramic resonator
External clock
f
MHz
OP
0.250
dc
(4)
2-pin RC oscillator frequency combined stability
∆f
f
= 2.0 MHz; V = 5.0 Vdc ±10%; T = –40°C to +85°C
—
—
±25
±20
%
%
OSC
OSC
OSC
DD A
f
= 2.0 MHz; V = 5.0 Vdc ±10%; T = 0°C to +40°C
DD
A
(4)
3-pin RC oscillator frequency combined stability
∆f
f
= 1.0 MHz; V = 5.0 Vdc ±10%; T = –40°C to +85°C
—
—
±15
±10
OSC
OSC
OSC
DD A
f
= 1.0 MHz; V = 5.0 Vdc ±10%; T = 0°C to +40°C
DD
A
Cycle time (1 ÷ f
)
t
500
—
—
1
ns
ms
ms
ms
OP
CYC
t
RC oscillator stabilization time
Crystal oscillator startup time
Stop recovery startup time
RESET pulse width low
RCON
t
—
100
100
—
OXON
t
—
ILCH
t
t
1.5
4.0
RL
CYC
(5)
t
t
—
Timer resolution
RESL
CYC
t
IRQ interrupt pulse width low (edge-triggered)
IRQ interrupt pulse period
250
—
ns
ILIH
(6)
t
t
—
ILIL
CYC
t
PA3–PA0 interrupt pulse width high (edge-triggered)
PA3–PA0 interrupt pulse period
250
(6)
—
ns
IHIL
t
t
—
IHIH
CYC
t
, t
OSC1 pulse width
200
10
—
ns
OH OL
(7)
t
15
ms
Programming time per byte
EPGM
1. VDD = 5.0 Vdc ±10%; VSS –0 Vdc; TA = TL to TH
2. Use only AT-cut crystals.
3. Minimum oscillator frequency with RC oscillator option is limited only by size of external R and C and leakage of external C.
4. Including processing tolerances and variations in temperature and supply voltage. Excluding tolerances of external R
and C.
5. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
6. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service
routine plus 19 tCYC
.
7. tEPGM is programming time per byte and may be accumulated during multiple programming passes.
Technical Data
126
MC68HC705K1 — Rev. 2.0
MOTOROLA
Electrical Specifications
Electrical Specifications
3.3-Volt Control Timing
12.11 3.3-Volt Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Oscillator frequency
3-pin RC oscillator
2-pin RC oscillator
(3)
1.2
2.0
2.0
2.0
f
MHz
(3)
0.500
dc
OSC
(2)
Crystal/ceramic resonator
External clock
Internal operating frequency (f
÷ 2)
OSC
0.6
1.0
1.0
1.0
(3)
(3)
3-pin RC oscillator
2-pin RC oscillator
Crystal/ceramic resonator
External clock
f
MHz
OP
0.250
dc
(4)
2-pin RC oscillator frequency combined stability
∆f
f
= 2.0 MHz; V = 3.3 Vdc ±10%; T = –40°C to +85°C
—
—
±40
±30
%
%
OSC
OSC
OSC
DD A
f
= 2.0 MHz; V = 3.3 Vdc ±10%; T = 0°C to +40°C
DD
A
(4)
3-pin RC oscillator frequency combined stability
∆f
f
= 1.0 MHz; V = 3.3 Vdc ±10%; T = –40°C to +85°C
—
—
±20
±15
OSC
OSC
OSC
DD A
f
= 1.0 MHz; V = 3.3 Vdc ±10%; T = 0°C to +40°C
DD
A
Cycle time (1 ÷ f
)
t
1000
—
—
1
ns
ms
ms
ms
OP
CYC
t
RC oscillator stabilization time
Crystal oscillator startup time
Stop recovery startup time
RESET pulse width low
RCON
t
—
100
100
—
OXON
t
—
ILCH
t
t
1.5
4.0
RL
CYC
(5)
t
t
—
Timer resolution
RESL
CYC
t
IRQ interrupt pulse width low (edge-triggered)
IRQ interrupt pulse period
250
—
ns
ILIH
(6)
t
t
—
ILIL
CYC
t
PA3–PA0 interrupt pulse width high (edge-triggered)
PA3–PA0 interrupt pulse period
250
—
ns
IHIL
t
(6)
t
—
IHIH
CYC
t
, t
OSC1 pulse width
200
—
ns
OH OL
1. VDD = 3.3 Vdc ±10%; VSS –0 Vdc; TA = TL to TH
2. Use only AT-cut crystals.
3. Minimum oscillator frequency with RC oscillator option is limited only by size of external R and C and leakage of external C.
4. Including processing tolerances and variations in temperature and supply voltage. Excluding tolerances of external R
and C.
5. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
6. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service
routine plus 19 tCYC
.
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
127
Electrical Specifications
Electrical Specifications
t
ILIL
t
IRQ/V PIN
ILIH
PP
t
IRQ
ILIH
1
.
.
.
IRQ
n
IRQ (INTERNAL)
Figure 12-7. External Interrupt Timing
OSC (NOTE 1)
RESET
t
RL
t
ILIH
IRQ/V (NOTE 2)
PP
4064 t
CYC
IRQ/V (NOTE 3)
PP
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
03FE
(NOTE 4)
03FE
03FE
03FE
03FE
03FF
RESET OR INTERRUPT
VECTOR FETCH
Notes:
1. Internal clocking from OSC1 pin.
2. Edge-triggered external interrupt mask option.
3. Edge- and level-triggered external interrupt mask option.
4. Reset vector shown as example.
Figure 12-8. Stop Mode Recovery Timing
Technical Data
128
MC68HC705K1 — Rev. 2.0
MOTOROLA
Electrical Specifications
Electrical Specifications
3.3-Volt Control Timing
V
DD
(NOTE 1)
4064 t
CYC
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
03FE
03FE
03FE
03FE
03FE
03FE
03FF
INTERNAL
DATA BUS
NEW
PCH
NEW
PCL
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 12-9. Power-On Reset Timing
INTERNAL
CLOCK
INTERNAL
03FE
03FE
03FE
03FE
03FF
NEW PC
DUMMY
NEW PC
ADDRESS BUS
NEW
PCH
NEW
PCL
OP
CODE
INTERNAL
DATA BUS
t
RL
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 12-10. External Reset Timing
MC68HC705K1 — Rev. 2.0
TechnicalData
129
MOTOROLA
Electrical Specifications
Electrical Specifications
12.12 Typical Oscillator Characteristics
Parameter
V
= 3.0 V
V
= 5.0 V
DD
Units
DD
Oscillator Type
Nominal Frequency
Frequency Variation
(Part-to-Part)
2-pin RC oscillator
3-pin RC oscillator
2 MHz
1 MHz
±12
±5
±7
±4
%
Frequency Variation
with Temperature
2-pin RC oscillator
3-pin RC oscillator
2 MHz
1 MHz
–2100
–1100
–1600
ppm/°C
–1100
Frequency Variation
with Supply Voltage
2-pin RC oscillator
3-pin RC oscillator
2 MHz
1 MHz
±1.0
±0.3
±0.2
±0.1
∆f/∆V
Cumulative Frequency
(1)
Variations
2-pin RC oscillator
3-pin RC oscillator
2 MHz
1 MHz
±36
±16
±20
±13
%
1. VDD ±10%; TA = –40°C to +85°C.
Technical Data
130
MC68HC705K1 — Rev. 2.0
MOTOROLA
Electrical Specifications
Electrical Specifications
Typical Oscillator Characteristics
T = 25°C
10 pF
20 pF
4
3
2
1
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
R (kΩ)
Figure 12-11. 2-Pin RC Oscillator R versus Frequency (V = 5.0 V)
DD
T = 25°C
10 pF
1000
20 pF
800
600
400
200
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
R (kΩ)
Figure 12-12. 3-Pin RC Oscillator R versus Frequency (V = 5.0 V)
DD
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
Electrical Specifications
131
Electrical Specifications
T = 25°C
10 pF
20 pF
4
3
2
1
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
R (kΩ)
Figure 12-13. 2-Pin Oscillator R versus Frequency (V = 3.0 V)
DD
T = 25°C
10 pF
1000
20 pF
800
600
400
200
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
R (kΩ)
Figure 12-14. 3-Pin Oscillator R versus Frequency (V = 3.0 V)
DD
Technical Data
132
MC68HC705K1 — Rev. 2.0
Electrical Specifications
MOTOROLA
Technical Data — MC68HC705K1
Section 13. Mechanical Specifications
13.1 Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
13.3 Plastic Dual In-Line Package (Case 648). . . . . . . . . . . . . . . .134
13.4 Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .134
13.5 Ceramic Dual In-Line Package (Case 620) . . . . . . . . . . . . . .135
13.2 Introduction
Package dimensions available at the time of this publication for the
MC68HC705K1 are provided in this section. The packages are:
• 16-pin plastic dual in-line package (PDIP)
• 16-pin small outline integrated circuit package (SOIC)
• 16-pin ceramic DIP (cerdip)
To make sure that you have the latest case outline specifications,
contact one of the following:
• Local Motorola Sales Office
• Motorola Mfax
– Phone 602-244-6609
– EMAIL rmfax0@email.sps.mot.com
• Worldwide Web (wwweb) at http://www.mcu.motsps.com
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
MC68HC705K1 — Rev. 2.0
MOTOROLA
Technical Data
Mechanical Specifications
133
Mechanical Specifications
13.3 Plastic Dual In-Line Package (Case 648)
-A-
16
1
9
8
B
S
INCHES
MILLIMETERS
MIN MAX
18.80 19.55
DIM
MIN
MAX
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.70
C
L
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
-T-
G
H
J
0.100 BSC
0.050 BSC
0.008
2.54 BSC
1.27 BSC
0.21
K
M
0.015
0.130
0.305
10°
0.38
3.30
7.74
10°
H
J
K
L
M
S
0.110
0.295
0°
2.80
7.50
0°
G
D
16 PL
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
13.4 Small Outline Integrated Circuit (Case 751)
-A-
16
9
MILLIMETERS
INCHES
MAX
0.411
DIM
MIN
MAX
10.45
7.60
2.65
0.49
0.90
MIN
A
B
C
D
F
10.15
7.40
2.35
0.35
0.50
0.400
0.292
0.093
0.014
0.020
-B-
8X P
0.299
0.104
0.019
0.035
M
M
B
0.010 (0.25)
1
8
G
J
1.27 BSC
0.050 BSC
0.25
0.10
0°
0.32
0.25
7°
0.010
0.004
0°
0.012
0.009
7°
J
K
M
P
D 16X
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
M
S
S
B
0.010 (0.25)
T
A
R
F
R X 45
C
-T-
M
SEATING
PLANE
G14X
K
Technical Data
134
MC68HC705K1 — Rev. 2.0
MOTOROLA
Mechanical Specifications
Mechanical Specifications
Ceramic Dual In-Line Package (Case 620)
13.5 Ceramic Dual In-Line Package (Case 620)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
B
A
A
M
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
16
1
9
8
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
B
L
INCHES
DIM MIN MAX
0.785 19.05
MILLIMETERS
MIN
MAX
19.93
7.49
A
B
C
D
E
0.750
0.240
–––
0.015
0.050 BSC
0.295
0.200
0.020
6.10
–––
16X J
5.08
0.39
0.50
M
0.25 (0.010)
T B
1.27 BSC
E
F
0.055
0.065
1.40
1.65
G
H
K
L
0.100 BSC
2.54 BSC
F
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
0.300 BSC
7.62 BSC
M
N
0
15
0.040
0
0.51
15
1.01
C
0.020
STYLE 1:
K
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
SEATING
PLANE
T
N
G
16X D
M
0.25 (0.010)
T A
MC68HC705K1 — Rev. 2.0
MOTOROLA
TechnicalData
135
Mechanical Specifications
Mechanical Specifications
Technical Data
136
MC68HC705K1 — Rev. 2.0
MOTOROLA
Mechanical Specifications
Technical Data — MC68HC705K1
Section 13. Ordering Information
13.1 Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.2 Introduction
This section contains ordering information for the available package
types.
13.3 MCU Order Numbers
Table 13-1 lists the MC order numbers.
Table 13-1. MC68HC705K1 Order Numbers
Package Type
Temperature Range
0°C to +70°C
Order Number
(1)
16-pin plastic dual in-line package (PDIP)
16-pin small outline integrated circuit (SOIC)
16-pin ceramic dual in-line package (cerdip)
MC68HC705K1P
(2)
0°C to +70°C
MC68HC705K1DW
(3)
0°C to +70°C
MC68HC705K1S
(4)
16-pin plastic dual in-line package (PDIP)
16-pin small outline integrated circuit (SOIC)
16-pin ceramic dual in-line package (cerdip)
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
MC68HC705K1CP
MC68HC705K1CDW
MC68HC705K1CS
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
3. S = Ceramic dual in-line package (cerdip)
4. C = Extended temperature range (–40°C to +85°C)
MC68HC705K1 — Rev. 2.0
Technical Data
137
MOTOROLA
Ordering Information
Ord e ring Inform a tion
Technical Data
138
MC68HC705K1 — Rev. 2.0
MOTOROLA
Ordering Information
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in
Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into
the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses,
and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use,
even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
are registered trademarks of
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution, P.O. Box 5405, Denver, Colorado 80217.
1-303-675-2140 or 1-800-441-2447. Customer Focus Center, 1-800-521-6274
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku,
Tokyo 106-8573 Japan. 81-3-3440-8573
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong. 852-26668334
Mfax™, Motorola Fax Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/;
TOUCHTONE, 1-602-244-6609; US and Canada ONLY, 1-800-774-1848
HOME PAGE: http://motorola.com/sps/
Mfax is a trademark of Motorola, Inc.
© Motorola, Inc., 1999
MC68HC705J1A/ D
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