MC68HC11A8TS_技术文档

Order this document

by MC68HC11A8TS/D

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68HC11A8

MC68HC11A1

MC68HC11A0

Technical Summary

8-Bit Microcontrollers

1 Introduction

The MC68HC11A8, MC68HC11A1, and MC68HC11A0 high-performance microcontroller units (MCUs)

are based on the M68HC11 Family. These high speed, low power consumption chips have multiplexed

buses and a fully static design. The chips can operate at frequencies from 3 MHz to dc. The three MCUs

are created from the same masks; the only differences are the value stored in the CONFIG register, and

whether or not the ROM or EEPROM is tested and guaranteed.

For detailed information about specific characteristics of these MCUs, refer to the M68HC11 Reference

Manual (M68HC11RM/AD).

1.1 Features

• M68HC11 CPU

• Power Saving STOP and WAIT Modes

• 8 Kbytes ROM

• 512 Bytes of On-Chip EEPROM

• 256 Bytes of On-Chip RAM (All Saved During Standby)

• 16-Bit Timer System

— 3 Input Capture Channels

— 5 Output Compare Channels

• 8-Bit Pulse Accumulator

• Real-Time Interrupt Circuit

• Computer Operating Properly (COP) Watchdog System

• Synchronous Serial Peripheral Interface (SPI)

• Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)

• 8-Channel, 8-Bit Analog-to-Digital (A/D) Converter

• 38 General-Purpose Input/Output (I/O) Pins

— 15 Bidirectional I/O Pins

— 11 Input-Only Pins and 12 Output-Only Pins (Eight Output-Only Pins in 48-Pin Package)

• Available in 48-Pin Dual In-Line Package (DIP) or 52-Pin Plastic Leaded Chip Carrier (PLCC)

This document contains information on a new product. Speciﬁcations and information herein are subject to change without notice.

Table 1 MC68HC11Ax Family Members

Device Number

MC68HC11A8

MC68HC11A1

MC68HC11A0

ROM

8K

0

EEPROM

RAM

256

CONFIG*

$0F

Comments

512

0

Family built around this device

ROM disabled

$0D

0

$0C

ROM and EEPROM disabled

Table 2 Ordering Information

Package

Temperature

–40°to + 85°C

CONFIG

$0F

Description

MC Order Number

MC68HC11A8P1

MC68HC11A1P

48-Pin Plastic DIP

(P suffix)

BUFFALO ROM

No ROM

–40°to + 85°C

–40°to + 105°C

–40°to + 125°C

–40°to + 85°C

–40°to + 105°C

–40°to + 125°C

–40°to + 85°C

$0D

$09

No ROM

MC68HC11A1VP

MC68HC11A1MP

MC68HCP11A1P

MC68HCP11A1VP

MC68HCP11A1MP

MC68HC11A0P

No ROM

No ROM, COP On

No ROM, No EEPROM

$09

$0C

52-Pin PLCC

(FN suffix)

–40°to + 85°C

–40°to + 105°C

–40°to + 125°C

–40°to + 85°C

–40°to + 105°C

–40°to + 125°C

–40°to + 85°C

$0F

$0D

$09

$0C

BUFFALO ROM

No ROM

MC68HC11A8FN1

MC68HC11A1FN

MC68HC11A1VFN

MC68HC11A1MFN

MC68HCP11A1FN

MC68HCP11A1VFN

MC68HCP11A1MFN

MC68HC11A0FN

No ROM

No ROM, COP On

No ROM, No EEPROM

MOTOROLA

MC68HC11A8

2

MC68HC11A8TS/D

TABLE OF CONTENTS

Section

Page

1 Introduction...............................................................................................................................................1

1.1 Features ..........................................................................................................................................1

2 Operating Modes and Memory Maps .......................................................................................................6

2.1 Memory Maps ..................................................................................................................................7

3 Resets and Interrupts .............................................................................................................................13

4 Electrically Erasable Programmable Read-Only Memory (EEPROM) ...................................................17

5 Parallel Input/Output...............................................................................................................................19

6 Serial Communications Interface (SCI) ..................................................................................................23

7 Serial Peripheral Interface (SPI).............................................................................................................29

8 Main Timer..............................................................................................................................................32

9 Pulse Accumulator..................................................................................................................................38

10 Analog-to-Digital Converter ..................................................................................................................41

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

3

XTAL

EXTAL

E

PULSE

ACCUMULATOR

COP

PA7

PAI/OC1

V

DD

SS

POWER

PA6

PA5

PA4

PA3

PA2

PA1

PA0

OSCILLATOR

OC2/OC1

OC3/OC1

OC4/OC1

OC5/OC1

IC1

IC2

IC3

TIMER

SYSTEM

IRQ

XIRQ

RESET

INTERRUPT

LOGIC

MODA/

LIR

PERIODIC

MODE

SELECT

INTERRUPT

MODB/

V

STBY

V

A/D

CONVERTER

RH

V

RL

CPU

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

SINGLE

EXPANDED CHIP

A15

A14

A13

A12

A11

A10

A9

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

256

BYTES

RAM

512

BYTES

EEPROM

SS

SCK

MOSI

MISO

PD5

PD4

PD3

PD2

A8

SPI

8

A7/D7

A6/D6

A5/D5

A4/D4

A3/D3

A2/D2

A1/D1

A0/D0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

KBYTES

ROM

TxD

SCI

PD1

PD0

RxD

R/W

AS

STRB

STRA

PARALLEL I/O

EQUIVALENT TO MC68HC24

Figure 1 MC68HC11A8 Block Diagram

MOTOROLA

MC68HC11A8

4

MC68HC11A8TS/D

XTAL

8

9

46

45

44

43

42

PE5/AN5

PE1/AN1

PE4/AN4

PE0/AN0

PB0/A8

1

PC0/A0/D0

PC1/A1/D1 10

PC2/A2/D2

PC3/A3/D3

PC4/A4/D4

PC5/A5/D5

PC6/A6/D6

PC7/A7/D7

RESET

11

12

13

14

15

16

17

18

19

20

41 PB1/A9

40

39

38

37

36

35

34

PB2/A10

PB3/A11

PB4/A12

PB5/A13

PB6/A14

PB7/A15

PA0/IC3

XIRQ

IRQ

PD0/RxD

Figure 2 52-Pin PLCC Pin Assignments

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

5

V

PA7/PAI/OC1

PA6/OC2/OC1

PA5/OC3/OC1

PA4/OC4/OC1

PA3/OC5/OC1

PA2/IC1

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

DD

2

PD5/SS

3

PD4/SCK

PD3/MOSI

PD2/MISO

PD1/TxD

PD0/RxD

IRQ

4

5

6

PA1/IC2

7

PA0/IC3

8

PB7/A15

9

XIRQ

PB6/A14

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

RESET

PB5/A13

PC7/A7/D7

PC6/A6/D6

PC5/A5/D5

PC4/A4/D4

PC3/A3/D3

PC2/A2/D2

PC1/A1/D1

PC0/A0/D0

XTAL

PB4/A12

PB3/A11

PB2/A10

PB1/A9

PB0/A8

PE0/AN0

PE1/AN1

PE2/AN2

PE3/AN3

EXTAL

V

STRB/ R/W

E

RL

V

RH

V

STRA/AS

MODA/LIR

SS

MODB/V

STBY

Figure 3 48-Pin DIP Pin Assignments

2 Operating Modes and Memory Maps

In single-chip operating mode, the MC68HC11A8 is a monolithic microcontroller without external ad-

dress or data buses.

In expanded multiplexed operating mode, the MCU can access a 64 Kbyte address space. The space

includes the same on-chip memory addresses used for single-chip mode plus external peripheral and

memory devices. The expansion bus is made up of ports B and C and control signals AS and R/W. The

address, R/W, and AS signals are active and valid for all bus cycles including accesses to internal mem-

ory locations. The following figure illustrates a recommended method of demultiplexing low-order ad-

dresses from data at port C.

MOTOROLA

MC68HC11A8

6

MC68HC11A8TS/D

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

A15

A14

A13

A12

A11

A10

A9

A8

MC54/74HC373

MC68HC11A8

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

D1

D2

D3

D4

D5

D6

D7

D8

Q1

A7

A6

A5

A4

A3

A2

A1

A0

Q2

Q3

Q4

Q5

Q6

Q7

Q8

AS

LE

OE

R/W

E

WE

D7

D6

D5

D4

D3

D2

D1

D0

Figure 4 Address/Data Demultiplexing

Special bootstrap mode allows special purpose programs to be entered into internal RAM. The boot-

loader program uses the SCI to read a 256-byte program into on-chip RAM at $0000 through $00FF.

After receiving the character for address $00FF, control passes to the loaded program at $0000.

Special test mode is used primarily for factory testing.

2.1 Memory Maps

Memory locations are the same for expanded multiplexed and single-chip modes. The on-board 256-

byte RAM is initially located at $0000 after reset. The 64-byte register block originates at $1000 after

reset. RAM and/or the register block can be placed at any other 4K boundary ($x000) after reset by writ-

ing an appropriate value to the INIT register. The 512-byte EEPROM is located at $B600 through $B7FF

after reset if it is enabled. The 8 Kbyte ROM is located at $E000 through $FFFF if it is enabled.

Hardware priority is built into the memory remapping. Registers have priority over RAM, and RAM has

priority over ROM. The higher priority resource covers the lower, making the underlying locations inac-

cessible.

In special bootstrap mode, a bootloader ROM is enabled at locations $BF40 through $BFFF.

In special test and special bootstrap modes, reset and interrupt vectors are located at $BFC0 through

$BFFF.

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

7

$0000

$1000

0000

256 BYTES RAM

(CAN BE REMAPPED TO ANY

4K PAGE BY THE INIT REGISTER)

EXT

00FF

1000

64 BYTE REGISTER BLOCK

(CAN BE REMAPPED TO ANY

4K PAGE BY THE INIT REGISTER)

103F

B600

512 BYTES EEPROM

$B600

B7FF

BF40

SPECIAL

MODE

INTERRUPT

VECTORS

BFC0

BFFF

BOOT

ROM

EXT

BFFF

E000

8K ROM

$E000

$FFFF

FFC0

FFFF

NORMAL

MODE

INTERRUPT

VECTORS

FFFF

SINGLE

CHIP

EXPANDED

MUX

SPECIAL

BOOTSTRAP

SPECIAL

TEST

Figure 5 Memory Map

MOTOROLA

MC68HC11A8

8

MC68HC11A8TS/D

Table 3 MC68HC11A8 Register and Control Bit Assignments (Sheet 1 of 2)

(The register block can be remapped to any 4K boundary.)

Bit 7

PA7

6

5

4

3

2

1

Bit 0

PA0

$1000

$1001

$1002

$1003

$1004

$1005

$1006

$1007

$1008

$1009

$100A

$100B

$100C

$100D

$100E

$100F

$1010

$1011

$1012

$1013

$1014

$1015

$1016

$1017

$1018

$1019

$101A

$101B

$101C

$101D

$101E

$101F

$1020

$1021

$1022

$1023

$1024

$1025

PA6

PA5

PA4

PA3

PA2

PA1

PORTA

Reserved

PIOC

STAF

PC7

STAI

PC6

CWOM

PC5

HNDS

PC4

OIN

PC3

PB3

PLS

PC2

PB2

EGA

PC1

INVB

PC0

PORTC

PB7

PB6

PB5

PB4

PB1

PB0

PORTB

PCL7

PCL6

PCL5

PCL4

PCL3

PCL2

PCL1

PCL0

PORTCL

Reserved

DDRC

DDC7

0

DDC6

DDC5

PD5

DDD5

PE5

FOC3

OC1M5

OC1D5

13

DDC4

PD4

DDD4

PE4

FOC4

OC1M4

OC1D4

12

DDC3

DDC2

DDC1

DDC0

PD0

DDD0

PE0

0

PD3

PD2

PD1

PORTD

0

DDD3

DDD2

DDD1

DDRD

PE7

PE6

FOC2

OC1M6

OC1D6

14

PE3

PE2

PE1

PORTE

FOC1

OC1M7

OC1D7

Bit 15

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

OM2

0

FOC5

0

CFORC

OC1M3

0

OC1M

OC1D3

0

OC1D

11

10

2

9

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

OL5

EDG3A

IC3I

IC3F

PR0

0

TCNT (High)

TCNT (Low)

TIC1 (High)

TIC1 (Low)

TIC2 (High)

TIC2 (Low)

TIC3 (High)

TIC3 (Low)

TOC1(High)

TOC1 (Low)

TOC2 (High)

TOC2 (Low)

TOC3 (High)

TOC3 (Low)

TOC4 (High)

TOC4 (Low)

TOC5 (High)

TOC5 (Low)

TCTL1

6

5

4

3

1

14

13

12

11

10

2

9

6

5

4

3

1

14

13

12

11

10

2

9

6

5

4

3

1

14

13

12

11

10

2

9

6

5

4

3

1

14

13

12

11

10

2

9

6

5

4

3

1

14

13

12

11

10

2

9

6

5

4

3

11

1

14

13

12

10

2

9

6

5

4

3

1

9

14

13

12

11

10

2

6

5

4

3

1

14

13

12

11

10

2

9

6

5

4

3

1

OL2

0

OM3

EDG1B

OC3I

OC3F

PAOVI

PAOVF

OL3

EDG1A

OC4I

OC4F

PAII

PAIF

OM4

EDG2B

OC5I

OC5F

0

OL4

EDG2A

IC1I

IC1F

0

OM5

EDG3B

IC2I

IC2F

PR1

0

TCTL2

OC1I

OC1F

TOI

OC2I

OC2F

RTII

RTIF

TMSK1

TFLG1

TMSK2

TOF

0

TFLG2

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

9

Table 3 MC68HC11A8 Register and Control Bit Assignments (Sheet 2 of 2)

(The register block can be remapped to any 4K boundary.)

Bit 7

DDRA7

Bit 7

6

5

4

PEDGE

4

3

2

1

Bit 0

RTR0

Bit 0

SPR0

0

$1026

$1027

$1028

$1029

$102A

$102B

$102C

$102D

$102E

$102F

$1030

$1031

$1032

$1033

$1034

$1035

$1038

$1039

$103A

$103B

$103C

$103D

$103E

$103F

PAEN

PAMOD

0

RTR1

PACTL

PACNT

SPCR

6

5

3

CPOL

0

2

1

SPIE

SPIF

Bit 7

SPE

DWOM

MSTR

MODF

4

CPHA

SPR1

WCOL

0

2

0

SPSR

6

5

SCP1

0

3

1

SCR1

0

Bit 0

SCR0

0

SPDR

TCLR

R8

0

T8

TCIE

TC

R6/T6

0

SCP0

M

RCKB

WAKE

TE

SCR2

0

BAUD

SCCR1

SCCR2

SCSR

TIE

RIE

RDRF

R5/T5

SCAN

5

ILIE

IDLE

R4/T4

MULT

4

RE

NF

R2/T2

CC

2

RWU

FE

R1/T1

CB

1

SBK

0

TDRE

R7/T7

CCF

Bit 7

OR

R3/T3

CD

3

R0/T0

CA

SCDR

ADCTL

ADR1

6

Bit 0

Bit 7

6

5

4

3

2

1

ADR2

Bit 7

6

5

4

3

2

1

ADR3

Bit 7

6

5

4

3

2

1

ADR4

Reserved

OPTION

COPRST

PPROG

HPRIO

INIT

ADPU

Bit 7

CSEL

6

IRQE

5

DLY

4

CME

3

0

CR1

1

CR0

Bit 0

2

ODD

EVEN

SMOD

RAM2

0

BYTE

IRV

ROW

PSEL3

REG3

DISR

NOSEC

ERASE

PSEL2

REG2

FCM

EELAT

PSEL1

REG1

FCOP

EEPGM

PSEL0

REG0

TCON

EEON

RBOOT

RAM3

TILOP

0

MDA

RAM1

OCCR

0

RAM0

CBYP

0

TEST1

CONFIG

0

NOCOP ROMON

MOTOROLA

10

MC68HC11A8

MC68HC11A8TS/D

HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous

$103C

Bit 7

6

5

4

3

PSEL3

0

2

PSEL2

1

PSEL1

0

Bit 0

PSEL0

1

RBOOT SMOD

MDA

—

IRV

—

RESET:

—

RBOOT, SMOD, and MDA reset depend on conditions at reset and can only be written in special modes

(SMOD = 1).

RBOOT — Read Bootstrap ROM

0 = Bootloader ROM disabled and not in map

1 = Bootloader ROM enabled and in map at $BF40–$BFFF

SMOD —Special Mode Select

MDA — Mode Select A

Inputs

Mode

Latched at Reset

MODB

MODA

RBOOT

SMOD

MDA

1

0

1

0

1

Single Chip

0

1

0

1

0

1

0

1

Expanded Multiplexed

Special Bootstrap

Special Test

IRV — Internal Read Visibility

0 = No internal read visibility on external bus

1 = Data from internal reads is driven out through the external data bus

PSEL3–PSEL0 — Priority Select Bits 3 through 0

Refer to 3 Resets and Interrupts.

INIT — RAM and I/O Mapping

$103D

Bit 7

RAM3

0

6

RAM2

0

5

RAM1

0

4

RAM0

0

3

REG3

0

2

REG2

0

1

REG1

0

Bit 0

REG0

1

RESET:

RAM[3:0] —256-Byte Internal RAM Map Position

RAM[3:0] determine the upper four bits of the RAM address, positioning RAM at the selected 4K bound-

ary.

REG[3:0] —64-Byte Register Block Map Position

REG[3:0] determine the upper four bits of the register address, positioning registers at the selected 4K

boundary. Register can be written only once in the first 64 cycles out of reset in normal modes, or any

time in special modes.

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

11

TEST1 — Factory Test

$103E

Bit 7

6

0

5

OCCR

0

4

CBYP

0

3

2

FCM

0

1

FCOP

0

Bit 0

TCON

0

TILOP

DISR

—

RESET:

0

Test Modes Only

TILOP — Test Illegal Opcode

OCCR — Output Condition Code Register to Timer Port

CBYP — Timer Divider Chain Bypass

DISR — Disable Resets from COP and Clock Monitor

DISR is forced to one out of reset in special test and bootstrap modes.

FCM — Force Clock Monitor Failure

FCOP — Force COP Watchdog Failure

TCON — Test Configuration Register

CONFIG — COP, ROM, EEPROM Enables

$103F

Bit 7

6

0

5

0

4

0

3

2

1

Bit 0

0

NOSEC NOCOP ROMON EEON

RESET:

—

NOTE

The bits of this register are implemented with EEPROM cells. Programming and

erasing follow normal EEPROM procedures. The erased state of CONFIG is $0F.

A new value is not readable until after a subsequent reset sequence. CONFIG can

only be programmed or erased in special modes.

NOSEC — EEPROM Security Disable

Refer to 4 Electrically Erasable Programmable Read-Only Memory (EEPROM).

NOCOP — COP System Disable

Refer to 3 Resets and Interrupts.

ROMON — ROM Enable

In single-chip mode, ROMON is forced to one out of reset.

0 = 8K ROM removed from the memory map

1 = 8K ROM present in the memory map

EEON — EEPROM Enable

0 = EEPROM is removed from the memory map

1 = EEPROM is present in the memory map

MOTOROLA

12

MC68HC11A8

MC68HC11A8TS/D

3 Resets and Interrupts

The MC68HC11A8 has three reset vectors and 18 interrupt vectors. The reset vectors are as follows:

• RESET, or Power-On

• COP Clock Monitor Fail

• COP Failure

The eight interrupt vectors service 23 interrupt sources (three non-maskable, 20 maskable). The three

non-maskable interrupt vectors are as follows:

• Illegal Opcode Trap

• Software Interrupt

• XIRQ Pin (Pseudo Non-Maskable Interrupt)

The 20 maskable interrupt sources are subject to masking by a global interrupt mask, the I bit in the

condition code register (CCR). In addition to the global I bit, all of these sources except the external

interrupt (IRQ) pin are controlled by local enable bits in control registers. Most interrupt sources in the

M68HC11 have separate interrupt vectors. For this reason, there is usually no need for software to poll

control registers to determine the cause of an interrupt. The maskable interrupt sources respond to a

fixed priority relationship, except that any one source can be dynamically elevated to the highest priority

position of any maskable source. Refer to the table of interrupt and reset vector assignments.

On-chip peripheral systems generate maskable interrupts that are recognized only if the I bit in the CCR

is clear. Maskable interrupts are prioritized according to a default arrangement, but any one source can

be elevated to the highest maskable priority position by the HPRIO register. The HPRIO register can be

written at any time, provided the I bit in the CCR is set.

For some interrupt sources, such as the parallel I/O and SCI interrupts, the flags are automatically

cleared during the course of responding to the interrupt requests. For example, the RDRF flag in the

SCI system is cleared by the automatic clearing mechanism, which consists of a read of the SCI status

register while RDRF is set, followed by a read of the SCI data register. The normal response to an

RDRF interrupt request is to read the SCI status register to check for receive errors, then to read the

received data from the SCI data register. These two steps satisfy the automatic clearing mechanism

without requiring any special instructions.

The real-time interrupt (RTI) function generates hardware interrupts at a fixed periodic rate. These hard-

ware interrupts provide a time reference signal for routines that measure real time. The routine notes

the number of times a particular interrupt has occurred and multiplies that number by the predetermined

subroutine execution time.

There are four RTI signal rates available in the MC68HC11A8. The MCU oscillator frequency and the

value of two software-accessible control bits, RTR1 and RTR0, in the pulse accumulator control register

(PACTL) determine these signal rates. Refer to 8 Main Timer for more information about PACTL.

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

13

Table 4 Interrupt and Reset Vector Assignments

Vector Address

FFC0, C1 – FFD4, D5

FFD6, D7

Interrupt Source

Reserved

CCR Mask

Local Mask

—

SCI Serial System

I Bit

• SCI Transmit Complete

• SCI Transmit Data Register Empty

• SCI Idle Line Detect

• SCI Receiver Overrun

• SCI Receive Data Register Full

SPI Serial Transfer Complete

Pulse Accumulator Input Edge

Pulse Accumulator Overflow

Timer Overflow

TCIE

TIE

ILIE

RIE

FFD8, D9

FFDA, DB

FFDC, DD

FFDE, DF

FFE0, E1

FFE3, E2

FFE4, E5

FFE6, E7

FFE8, E9

FFEA, EB

FFEC, ED

FFEE, EF

FFF0, F1

FFF2, F3

I Bit

SPIE

PAII

PAOVI

TOI

Timer Input Capture 4/Output Compare 5

Timer Output Compare 4

Timer Output Compare 3

Timer Output Compare 2

Timer Output Compare 1

Timer Input Capture 3

Timer Input Capture 2

Timer Input Capture 1

Real-Time Interrupt

I4O5I

OC4I

OC3I

OC2I

OC1I

IC3

IC2I

IC1I

RTII

Parallel I/O Handshake

IRQ

STAI

None

NOCOP

CME

None

FFF4, F5

FFF6, F7

FFF8, F9

FFFA, FB

FFFC, FD

FFFE, FF

XIRQ Pin

X Bit

None

Software Interrupt

Illegal Opcode Trap

COP Failure

COP Clock Monitor Fail

RESET

OPTION —System Configuration Options

$1039

Bit 7

ADPU

0

6

CSEL

0

5

IRQE*

0

4

DLY*

1

3

CME

0

2

0

1

CR1*

0

Bit 0

CR0*

0

RESET:

*Can be written only once in first 64 cycles out of reset in normal modes, or any time in special modes.

ADPU —A/D Converter Power-up

Refer to 10 Analog-to-Digital Converter.

CSEL —Clock Select

Refer to 10 Analog-to-Digital Converter.

IRQE — IRQ Select Edge-Sensitive Only

0 = Low logic level recognition

1 = Falling edge recognition

MOTOROLA

14

MC68HC11A8

MC68HC11A8TS/D

DLY — Enable Oscillator Start-Up Delay on Exit from STOP

0 = No stabilization delay on exit from STOP

1 = Stabilization delay enabled on exit from STOP

CME — Clock Monitor Enable

0 = Clock monitor disabled; slow clocks can be used

1 = Slow or stopped clocks cause clock failure reset

CR1, CR0 — COP Timer Rate Select

Divide

XTAL = 4.0 Mhz

Timeout

XTAL = 8.0 MHz

Timeout

XTAL = 12.0 MHz

Timeout

15

CR [1:0]

E/2

–0/+32.8 ms

–0/+16.4 ms

–0/+10.9 ms

By

0 0

0 1

1 0

1 1

1

32.768 ms

131.072 ms

524.288 ms

2.097 sec

1.0 MHz

16.384 ms

65.536 ms

262.140 ms

1.049 sec

2.0 MHz

10.923 ms

43.691 ms

174.76 ms

699.05 ms

3.0 MHz

4

16

64

E =

COPRST — Arm/Reset COP Timer Circuitry

$103A

Bit 7

6

0

5

0

4

0

3

0

2

0

1

0

Bit 0

7

0

RESET:

Write $55 to COPRST to arm COP watchdog clearing mechanism. Write $AA to COPRST to reset COP

watchdog.

HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous

$103C

Bit 7

6

5

4

3

PSEL3

0

2

PSEL2

1

PSEL1

0

Bit 0

PSEL0

1

RBOOT SMOD

MDA

—

IRV

—

RESET:

—

RBOOT — Read Bootstrap ROM Bits 7–4

Refer to 2 Operating Modes and Memory Maps.

SMOD — Special Mode Select

Refer to 2 Operating Modes and Memory Maps.

MDA — Mode Select A

Refer to 2 Operating Modes and Memory Maps.

IRV — Internal Read Visibility

Refer to 2 Operating Modes and Memory Maps.

PSEL[3:0] — Priority Select Bits 3 through 0

Can be written only while the I bit in the CCR is set (interrupts disabled). These bits select one interrupt

source to be elevated above all other I-bit related sources.

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

15

PSEL[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Interrupt Source Promoted

Timer Overflow

Pulse Accumulator Overflow

Pulse Accumulator Input Edge

SPI Serial Transfer Complete

SCI Serial System

Reserved (Default to IRQ)

IRQ

Real-Time Interrupt

Timer Input Capture 1

Timer Input Capture 2

Timer Input Capture 3

Timer Output Compare 1

Timer Output Compare 2

Timer Output Compare 3

Timer Output Compare 4

Timer Output Compare 5

CONFIG — COP, ROM, EEPROM Enables

$103F

Bit 7

6

0

5

0

4

0

3

2

1

Bit 0

0

NOSEC NOCOP ROMON EEON

RESET:

—

NOTE

The bits of this register are implemented with EEPROM cells. Programming and

erasing follow normal EEPROM procedures. The erased state of CONFIG is $0F.

A new value is not readable until after a subsequent reset sequence. CONFIG can

only be programmed or erased in special modes.

NOSEC — EEPROM Security Disable

Refer to 4 Electrically Erasable Programmable Read-Only Memory (EEPROM).

NOCOP — COP system disable

0 = COP enabled (forces reset on timeout)

1 = COP disabled (does not force reset on timeout)

ROMON — ROM Enable

Refer to 2 Operating Modes and Memory Maps.

EEON — EEPROM Enable

Refer to 2 Operating Modes and Memory Maps.

MOTOROLA

16

MC68HC11A8

MC68HC11A8TS/D

4 Electrically Erasable Programmable Read-Only Memory (EEPROM)

The 512 bytes of EEPROM in the MC68HC11A8 are located at $B600 through $B7FF. The EEON bit

in CONFIG controls the presence or absence of the EEPROM in the memory map. When EEON = 1

(erased state), the EEPROM is enabled. When EEON = 0, the EEPROM is disabled and out of the

memory map. EEON is reset to the value last programmed into CONFIG. An on-chip charge pump de-

velops the high voltage required for programming and erasing. When the E clock is less than 1 MHz,

select an internal clock. This drives the EEPROM charge pump by writing a one to the CSEL bit in the

OPTION register.

The PPROG register controls the programming and erasing of the EEPROM. To erase the EEPROM,

complete the following steps using the PPROG register:

1. Write to PPROG with the ERASE, EELAT, and appropriate BYTE and ROW bits set.

2. Write to the appropriate EEPROM address with any data. Row erase only requires a write to

any location in the row. Bulk erase is accomplished by writing to any location in the array.

3. Write to PPROG with ERASE, EELAT, EEPGM, and the appropriate BYTE and ROW bits set.

4. Delay for 10 ms or more, as appropriate.

5. Clear the EEPGM bit in PPROG to turn off the high voltage.

6. Clear the PPROG register to reconfigure the EEPROM address and data buses for normal op-

eration.

To program the EEPROM, complete the following steps using the PPROG register:

1. Write to PPROG with the EELAT bit set.

2. Write data to the desired address.

3. Write to PPROG with the EELAT and EEPGM bits set.

4. Delay for 10 ms or more, as appropriate.

5. Clear the EEPGM bit in PPROG to turn off the high voltage.

6. Clear the PPROG register to reconfigure the EEPROM address and data buses for normal op-

eration.

PPROG — EEPROM Programming Control

$103B

Bit 7

ODD

0

6

EVEN

0

5

0

4

BYTE

0

3

ROW

0

2

1

Bit 0

ERASE EELAT EEPGM

RESET:

0

ODD — Program Odd Rows in Half of EEPROM (TEST)

EVEN — Program Even Rows in Half of EEPROM (TEST)

BYTE — Byte/Other EEPROM Erase Mode

The BYTE bit overrides the ROW bit.

0 = Row or bulk erase mode is used

1 = Erase only one byte of EEPROM

ROW — Row/All EEPROM Erase Mode

The ROW bit is only valid when BYTE = 0.

0 = All 512 bytes of EEPROM are erased

1 = Erase only one 16-byte row of EEPROM

BYTE

ROW

Action

0

1

0

1

0

1

Bulk Erase (All 512 Bytes)

Row Erase (16 Bytes)

Byte Erase

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

17

ERASE — Erase/Normal Control for EEPROM

0 = Normal read or program mode

1 = Erase mode

EELAT — EEPROM Latch Control

0 = EEPROM address and data bus configured for normal reads

1 = EEPROM address and data bus configured for programming or erasing

EEPGM — EEPROM Program Command

0 = Programming or erase voltage switched off to EEPROM array

1 = Programming or erase voltage switched on to EEPROM array

CONFIG — COP, ROM, EEPROM Enables

$103F

Bit 7

6

0

5

0

4

0

3

2

1

Bit 0

0

NOSEC NOCOP ROMON EEON

RESET:

—

NOTE

The bits of this register are implemented with EEPROM cells. Programming and

erasing follow normal EEPROM procedures. The erased state of CONFIG is $0F.

A new value is not readable until after a subsequent reset sequence. CONFIG can

only be programmed or erased in special modes.

NOSEC — EEPROM Security Disable

NOSEC has no meaning unless the security mask option was specified before the MCU was manufac-

tured.

0 = Security enabled (available as a mask option on MC68HC11A8 only)

1 = Security disabled

NOCOP — COP system disable

Refer to 3 Resets and Interrupts.

ROMON — ROM Enable

Refer to 2 Operating Modes and Memory Maps.

EEON — EEPROM Enable

0 = EEPROM is removed from the memory map

1 = EEPROM is present in the memory map

MOTOROLA

18

MC68HC11A8

MC68HC11A8TS/D

5 Parallel Input/Output

The MC68HC11A8 has up to 38 input/output lines, depending on the operating mode. Port A has three

input-only pins, four output-only pins, and one bidirectional I/O pin. Port A shares functions with the tim-

er system.

Port B is an 8-bit output-only port in single-chip modes and is the high-order address in expanded

modes.

Port C is an 8-bit bidirectional port in single-chip modes and the multiplexed address and data bus in

expanded modes.

Port D is a 6-bit bidirectional port that shares functions with the serial systems.

Port E is an 8-bit input-only port that shares functions with the A/D system.

Simple and full handshake input and output functions are available on ports B and C lines in single-chip

mode. A description of the handshake functions follows.

In port B simple strobed output mode, the STRB output is pulsed for two E-clock periods each time there

is a write to the PORTB register. The INVB bit in the PIOC register controls the polarity of STRB pulses.

In port C simple strobed input mode, port C levels are latched into the alternate port C latch (PORTCL)

register on each assertion of the STRA input. STRA edge select, flag and interrupt enable bits are lo-

cated in the PIOC register. Any or all of the port C lines can still be used as general purpose I/O while

in strobed input mode.

Port C full handshake mode involves port C pins and the STRA and STRB lines. Input and output hand-

shake modes are supported, and output handshake mode has a three-stated variation. STRA is an

edge detecting input, and STRB is a handshake output. Control and enable bits are located in the PIOC

register.

In full input handshake mode, the MCU uses STRB as a “ready” line to an external system. Port C logic

levels are latched into PORTCL when the STRA line is asserted by the external system. The MCU then

negates STRB. The MCU reasserts STRB after the PORTCL register is read. A mix of latched inputs,

static inputs, and static outputs is allowed on port C, differentiated by the data direction bits and use of

the PORTC and PORTCL registers.

In full output handshake mode, the MCU writes data to PORTCL, which in turn asserts the STRB output

to indicate that data is ready. The external system reads port C (the STRB output) and asserts the STRA

input to acknowledge that data has been received.

In the three-state variation of output handshake mode, lines intended as three-state handshake outputs

are configured as inputs by clearing the corresponding DDRC bits. The MCU writes data to PORTCL

and asserts STRB. The external system responds by activating the STRA input, which forces the MCU

to drive the data in PORTCL out on all of the port C lines. This mode variation does not allow part of

port C to be used for static inputs while other port C pins are being used for handshake outputs. Refer

to the PIOC register description.

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

19

PORTA — Port A Data

$1000

Bit 7

6

5

PA5

0

4

PA4

0

3

PA3

0

2

1

Bit 0

PA0

HiZ

PA7

HiZ

PA6

0

PA2

HiZ

PA1

HiZ

RESET:

Alt. Pin

Func.:

PAI

OC2

OC1

OC3

OC1

OC4

OC1

OC5

OC1

IC1

—

IC2

—

IC3

—

And/or:

OC1

PIOC — Parallel I/O Control

$1002

Bit 7

STAF

0

6

STAI

0

5

CWOM

0

4

HNDS

0

3

OIN

0

2

PLS

U

1

EGA

1

Bit 0

INVB

1

RESET:

STAF — Strobe A Interrupt Status Flag

Set when selected edge occurs on Strobe A. Cleared by PIOC read with STAF set followed by PORTCL

read (simple strobed or full input handshake mode) or PORTCL write (output handshake mode).

STAI — Strobe A Interrupt Enable Mask

0 = STAF interrupts disabled

1 = STAF interrupts enabled

CWOM — Port C Wire-OR Mode (affects all eight port C pins)

0 = Port C outputs are normal CMOS outputs

1 = Port C outputs are open-drain outputs

HNDS — Handshake Mode

0 = Simple strobe mode

1 = Full input or output handshake mode

OIN — Output or Input Handshake Select

HNDS must be set to one for this bit to have meaning.

0 = Input handshake

1 = Output handshake

PLS — Pulse/Interlocked Handshake Operation

HNDS must be set to one for this bit to have meaning.

0 = Interlocked handshake

1 = Pulsed handshake (strobe B pulses high for two E-clock cycles)

EGA — Active Edge for Strobe A

0 = STRA falling edge selected

1 = STRA rising edge selected

INVB — Invert Strobe B

0 = Active level is logic zero

1 = Active level is logic one

MOTOROLA

20

MC68HC11A8

MC68HC11A8TS/D

Table 5 Parallel I/O Control

STAF

Clearing

Sequence

HNDS OIN

PLS

EGA

Port C

Port B

Simple

strobed

mode

Read PIOC

with STAF=1

then read

0

X

Inputs latched

into PORTCL pulses on

on any active

edge on STRA

STRB

0

1

writes to

port B

PORTCL

Full input

handshake with STAF=1

then read

Read PIOC

1

0

0 = STRB

active level

Inputs latched Normal out-

into PORTCL put port,

on any active unaffected

edge on STRA in hand-

shake

1

0

PORTCL

1 = STRB

active pulse

modes

Full output Read PIOC

handshake with STAF=1

then write to

1

0 = STRB

active level

Driven as out- Normal out-

puts if STRA at

active level,

follows DDRC

if STRA not at

active level

put port,

unaffected

in hand-

shake

0

Port C

Driven

PORTCL

1 = STRB

active pulse

1

STRA

Active Edge

Follow

DDRC

modes

Follow

DDRC

PORTC — Port C Data

$1003

Bit 7

PC7

6

5

4

3

2

1

Bit 0

PC0

PC6

PC5

PC4

PC3

PC2

PC1

S. Chip

or Boot:

PC7

0

PC6

0

PC5

0

PC4

0

PC3

0

PC2

0

PC1

0

PC0

0

RESET:

Expan.or ADDR7/ ADDR6/ ADDR5/ ADDR4/ ADDR3/ ADDR2/ ADDR1/ ADDR0/

Test:

DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

NOTE

In single chip and boot modes, port C pins reset to high impedance inputs (DDRC

registers are set to zero). In expanded and special test modes, port C is a multi-

plexed address/data bus and the port C register address is treated as an external

memory location.

PORTB — Port B Data

$1004

Bit 7

6

5

4

3

2

1

Bit 0

PB0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

S. Chip

or Boot:

PB7

0

PB6

0

PB5

0

PB4

0

PB3

0

PB2

0

PB1

0

PB0

0

RESET:

Expan.or

Test:

ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8

PORTCL — Port C Latched

$1005

Bit 7

PCL7

U

6

PCL6

U

5

PCL5

U

4

PCL4

U

3

PCL3

U

2

PCL2

U

1

PCL1

U

Bit 0

PCL0

U

RESET:

Writes affect port C pins. PORTCL is used in the handshake clearing mechanism. When an active edge

occurs on the STRA pin, port C data is latched into the PORTCL register.

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

21

DDRC — Data Direction Register for Port C

$1007

Bit 7

DDC7

0

6

DDC6

0

5

DDC5

0

4

DDC4

0

3

DDC3

0

2

DDC2

0

1

DDC1

0

Bit 0

DDC0

0

RESET:

DDC[7:0] — Data Direction Register for Port C

0 = Input

1 = Output

PORTD — Port D Data

$1008

Bit 7

6

0

5

PD5

0

4

PD4

0

3

PD3

0

2

PD2

0

1

PD1

0

Bit 0

PD0

0

RESET:

Alt. Pin

Func.:

—

SS

SCK

MOSI

MISO

TxD

RxD

DDRD — Data Direction Register for Port D

$1009

Bit 7

0

6

0

5

DDD5

0

4

DDD4

0

3

DDD3

0

2

DDD2

0

1

DDD1

0

Bit 0

DDD0

0

RESET:

0

Alt. Pin

Func.:

—

PD5/

SS

PD4/

SCK

PD3/

MOSI

PD2/

MISO

PD1/

TxD

PD0/

RxD

DDD[5:0] — Data Direction for Port D

0 = Input

1 = Output

PORTE — Port E Data

$100A

Bit 7

PE7

U

6

PE6

U

5

PE5

U

4

PE4

U

3

PE3

U

2

PE2

U

1

PE1

U

Bit 0

PE0

U

RESET:

Alt. Pin

Func.:

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

PACTL — Pulse Accumulator Control

$1026

Bit 7

DDRA7

0

6

PAEN

0

5

4

3

0

2

0

1

RTR1

0

Bit 0

RTR0

0

PAMOD PEDGE

RESET:

0

DDRA7 — Data Direction for Port A Bit 7

0 = Input

1 = Output

PAEN — Pulse Accumulator System Enable

Refer to 9 Pulse Accumulator.

PAMOD — Pulse Accumulator Mode

Refer to 9 Pulse Accumulator.

PEDGE — Pulse Accumulator Edge Control

Refer to 9 Pulse Accumulator.

RTR1, RTR0 — Real-Time Interrupt Rate

Refer to 8 Main Timer.

MOTOROLA

22

MC68HC11A8

MC68HC11A8TS/D

6 Serial Communications Interface (SCI)

The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is one

of two independent serial I/O subsystems in the MC68HC11A8. It has a standard NRZ format (one start,

eight or nine data, and one stop bit) and several baud rates available. The SCI transmitter and receiver

are independent, but use the same data format and bit rate.

TRANSMITTER

BAUD RATE

CLOCK

(WRITE ONLY)

SCDR Tx BUFFER

DDD1

10 (11) - BIT Tx SHIFT REGISTER

PIN BUFFER

AND CONTROL

PD1

TxD

H (8)

7

6

5

4

3

2

1

0

L

8

FORCE PIN

DIRECTION (OUT)

TRANSMITTER

CONTROL LOGIC

8

SCCR1 SCI CONTROL 1

SCSR INTERRUPT STATUS

8

TDRE

TIE

TC

TCIE

SCCR2 SCI CONTROL 2

SCI Rx

REQUESTS

SCI INTERRUPT

REQUEST

INTERNAL

DATA BUS

11 SCI TX BLOCK

Figure 6 SCI Transmitter Block Diagram

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

23

RECEIVER

BAUD RATE

CLOCK

DDD0

÷16

10 (11) - BIT

Rx SHIFT REGISTER

PIN BUFFER

AND CONTROL

DATA

RECOVERY

PD0

RxD

(8)

7

6

5

4

3

2

1

0

MSB

ALL ONES

DISABLE

DRIVER

RE

M

WAKEUP

LOGIC

RWU

8

SCSR SCI STATUS 1

SCDR Rx BUFFER

(READ ONLY)

SCCR1 SCI CONTROL 1

8

RDRF

RIE

IDLE

ILIE

OR

RIE

8

SCCR2 SCI CONTROL 2

SCI Tx

REQUESTS

SCI INTERRUPT

REQUEST

INTERNAL

DATA BUS

11 SCI RX BLOCK

Figure 7 SCI Receiver Block Diagram

MOTOROLA

24

MC68HC11A8

MC68HC11A8TS/D

BAUD — Baud Rate

$102B

Bit 7

6

0

5

SCP1

0

4

SCP0

0

3

RCKB

0

2

SCR2

U

1

SCR1

U

Bit 0

SCR0

U

TCLR

RESET:

0

TCLR — Clear Baud Rate Counters (TEST)

SCP1, SCP0 — SCI Baud Rate Prescaler Selects

Divide

Crystal Frequency in MHz

Internal

Clock

By

4.0 MHz

(Baud)

8.0 MHz

(Baud)

10.0 MHz

(Baud)

12.0 MHz

(Baud)

SCP[1:0]

00

01

10

11

1

3

62.50K

20.83K

15.625K

4800

125.0K

41.67K

31.25K

9600

156.25K

52.08K

38.4K

187.5K

62.5K

4

46.88K

14.42K

13

12.02K

RCKB — SCI Baud Rate Clock Check (TEST)

SCR2, SCR1, and SCR0 — SCI Baud Rate Selects

Selects receiver and transmitter bit rate based on output from baud rate prescaler stage.

Divide

Prescaler

By

Highest Baud Rate

(Prescaler Output from Previous Table)

SCP[2:0]

4800

2400

1200

600

300

150

—

9600

4800

2400

1200

600

38.4K

19.2K

9600

4800

2400

1200

600

000

001

010

011

100

101

110

111

1

2

4

8

16

32

64

128

300

150

—

300

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

25

EXTAL

XTAL

INTERNAL BUS CLOCK (PH2)

OSCILLATOR

AND

CLOCK GENERATOR

÷3

÷4

÷13

(÷4)

SCP[1:0]

1:1

0:0

0:1

1:0

E

AS

SCR[2:0]

0:0:0

÷2

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷16

SCI

TRANSMIT

BAUD RATE

(1X)

SCI

RECEIVE

BAUD RATE

(16X)

SCI BAUD GENERATOR

Figure 8 SCI Baud Rate Diagram

SCCR1 — SCI Control Register 1

$102C

Bit 7

R8

U

6

T8

U

5

0

4

M

0

3

WAKE

0

2

0

1

0

Bit 0

0

RESET:

R8 — Receive Data Bit 8

If M bit is set, R8 stores ninth bit in receive data character.

T8 — Transmit Data Bit 8

If M bit is set, T8 stores ninth bit in transmit data character.

M — Mode (Select Character Format)

0 = Start bit, 8 data bits, 1 stop bit

1 = Start bit, 9 data bits, 1 stop bit

MOTOROLA

26

MC68HC11A8

MC68HC11A8TS/D

WAKE — Wake Up by Address Mark/Idle

0 = Wake up by IDLE line recognition

1 = Wake up by address mark (most significant data bit set)

SCCR2 — SCI Control Register 2

$102D

Bit 7

TIE

0

6

TCIE

0

5

RIE

0

4

ILIE

0

3

TE

0

2

RE

0

1

RWU

0

Bit 0

SBK

0

RESET:

TIE — Transmit Interrupt Enable

0 = TDRE interrupts disabled

1 = SCI interrupt requested when TDRE status flag is set

TCIE — Transmit Complete Interrupt Enable

0 = TC interrupts disabled

1 = SCI interrupt requested if TC is set to one

RIE — Receiver Interrupt Enable

0 = RDRF and OR interrupts disabled

1 = SCI interrupt requested when RDRF flag or the OR status flag is set

ILIE — Idle Line Interrupt Enable

0 = IDLE interrupts disabled

1 = SCI interrupt requested when IDLE status flag is set

TE — Transmitter Enable

0 = Transmitter disabled

1 = Transmitter enabled

RE — Receiver Enable

0 = Receiver disabled

1 = Receiver enabled

RWU — Receiver Wake Up Control

0 = Normal SCI receiver

1 = Wake up enabled and receiver interrupts inhibited

SBK — Send Break

0 = Break generator off

1 = Break codes generated as long as SBK is set to one

SCSR — SCI Status Register

$102E

Bit 7

TDRE

1

6

TC

1

5

RDRF

0

4

IDLE

0

3

OR

0

2

NF

0

1

FE

0

Bit 0

0

RESET:

TDRE — Transmit Data Register Empty Flag

Set if transmit data can be written to SCDR; if TDRE is zero, transmit data register is busy. Cleared by

SCSR read with TDRE set followed by SCDR write.

TC — Transmit Complete Flag

Set if transmitter is idle (no data, preamble, or break transmission in progress). Cleared by SCSR read

with TC set followed by SCDR write.

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

27

RDRF — Receive Data Register Full Flag

Set if a received character is ready to be read from SCDR. Cleared by SCSR read with RDRF set fol-

lowed by SCDR read.

IDLE — Idle Line Detected Flag

Set if the RxD line is idle. IDLE flag is inhibited when RWU is set to one. Cleared by SCSR read with

IDLE set followed by SCDR read. Once cleared, IDLE is not set again until the RxD line has been active

and becomes idle again.

OR — Overrun Error Flag

Set if a new character is received before a previously received character is read from SCDR. Cleared

by SCSR read with OR set followed by SCDR read.

NF — Noise Error Flag

Set if majority sample logic detects anything other than a unanimous decision. Cleared by SCSR read

with NF set followed by SCDR read.

FE — Framing Error

Set if a zero is detected where a stop bit was expected. Cleared by SCSR read with FE set followed by

SCDR read.

SCDR — SCI Data Register

$102F

Bit 7

R7/T7

U

6

R6/T6

U

5

R5/T5

U

4

R4/T4

U

3

R3/T3

U

2

R2/T2

U

1

R1/T1

U

Bit 0

R0/T0

U

RESET:

NOTE

Receive and transmit are double buffered. Reads access the receive data buffer

and writes access the transmit data buffer.

MOTOROLA

28

MC68HC11A8

MC68HC11A8TS/D

7 Serial Peripheral Interface (SPI)

The SPI is one of two independent serial communications subsystems that allow the MCU to commu-

nicate synchronously with peripheral devices and other microprocessors. Data rates can be as high as

one half of the E-clock rate when configured as master, and as fast as the E clock when configured as

slave.

INTERNAL

MCU CLOCK

MISO

PD2

S

M

MSB

8/16-BIT SHIFT REGISTER

READ DATA BUFFER

LSB

M

S

MOSI

PD3

DIVIDER

÷2 ÷4 ÷16 ÷32

CLOCK

SPI CLOCK (MASTER)

S

SELECT

SCK

PD4

M

LOGIC

SS

PD5

MSTR

SPE

SPI CONTROL

8

SPI STATUS REGISTER

SPI CONTROL REGISTER

8

SPI INTERRUPT

REQUEST

INTERNAL

DATA BUS

11 SPI BLOCK

Figure 9 SPI Block Diagram

DDRD — Data Direction Register for Port D

$1009

Bit 7

0

6

0

5

DDD5

0

4

DDD4

0

3

DDD3

0

2

DDD2

0

1

DDD1

0

Bit 0

DDD0

0

RESET:

0

Alt. Pin

Func.:

__

PD5/

SS

PD4/

SCK

PD3/

MOSI

PD2/

MISO

PD1/

TxD

PD0/

RxD

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

29

DDD[5:0] — Data Direction for Port D

When DDRD bit 5 is zero and MSTR = 1 in SPCR, PD5/SS is a general-purpose output and mode fault

logic is disabled.

0 = Input

1 = Output

SPCR — Serial Peripheral Control Register

$1028

Bit 7

SPIE

0

6

SPE

0

5

DWOM

0

4

MSTR

0

3

CPOL

0

2

CPHA

1

SPR1

U

Bit 0

SPR0

U

RESET:

SPIE — Serial Peripheral Interrupt Enable

0 = SPI interrupts disabled

1 = SPI interrupts enabled

SPE — Serial Peripheral System Enable

0 = SPI off

1 = SPI on

DWOM — Port D Wired-OR Mode

DWOM affects all six port D pins.

0 = Normal CMOS outputs

1 = Open-drain outputs

MSTR — Master Mode Select

0 = Slave mode

1 = Master mode

CPOL, CPHA — Clock Polarity, Clock Phase

Refer to Figure 10

SCK CYCLE #

1

2

3

4

5

6

7

8

SCK (CPOL = 0)

SCK (CPOL = 1)

SAMPLE INPUT

MSB

6

5

4

3

2

1

LSB

(CPHA = 0)

DATA OUT

SAMPLE INPUT

(CPHA = 1) DATA OUT

SS (TO SLAVE)

MSB

6

5

4

3

2

1

LSB

SLAVE CPHA=1 TRANSFER IN PROGRESS

MASTER TRANSFER IN PROGRESS

3

2

4

SLAVE CPHA=0 TRANSFER IN PROGRESS

1

5

1. SS ASSERTED

2. MASTER WRITES TO SPDR

3. FIRST SCK EDGE

4. SPIF SET

5. SS NEGATED

SPI TRANSFER FORMAT 1

Figure 10 SPI Transfer Format

MOTOROLA

30

MC68HC11A8

MC68HC11A8TS/D

SPR1 and SPR0 — SPI Clock Rate Selects

E-Clock

Divide By

Frequency at

E = 2 MHz (Baud)

SPR [1:0]

00

01

10

11

2

4

1.0 MHz

500 kHz

125 kHz

62.5 kHz

16

32

SPSR — Serial Peripheral Status Register

$1029

Bit 7

SPIF

0

6

WCOL

0

5

0

4

3

0

2

0

1

0

Bit 0

MODF

0

RESET:

0

SPIF — SPI Transfer Complete Flag

Set when an SPI transfer is complete. Cleared by reading SPSR with SPIF set followed by SPDR ac-

cess.

WCOL — Write Collision

Set when SPDR is written while transfer is in progress. Cleared by SPSR with WCOL set followed by

SPDR access.

MODF — Mode Fault (A Mode Fault Terminates SPI Operation)

Set when SS is pulled low while MSTR = 1. Cleared by SPSR read with MODF set followed by SPCR

write.

SPDR — SPI Data Register

$102A

Bit 7

6

5

4

3

2

1

Bit 0

NOTE

SPI is double buffered in, single buffered out.

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

31

8 Main Timer

The main timer is based on a free-running 16-bit counter with a four-stage programmable prescaler. A

timer overflow function allows software to extend the system's timing capability beyond the counter's

16-bit range.

The timer has three channels of input capture and five channels of output compare.

Refer to the following table for a summary of crystal-related frequencies and periods.

Table 6 Timer Summary

XTAL Frequencies

4.0 MHz

1.0 MHz

1000 ns

8.0 MHz

2.0 MHz

500 ns

12.0 MHz

3.0 MHz

333 ns

Other Rates

(E)

Control

Bits

(1/E)

PR[1:0]

Main Timer Count Rates

0 0

1 count —

overflow —

1.0 µs

65.536 ms

500 ns

32.768 ms

333 ns

21.845 ms

(E/1)

16

(E/2

)

0 1

1 count —

overflow —

4.0 µs

262.14 ms

2.0 µs

131.07 ms

1.333 µs

87.381 ms

(E/4)

18

(E/2

1 0

1 count —

overflow —

8.0 µs

524.29 ms

4.0 µs

262.14 ms

2.667 µs

174.76 ms

(E/8)

19

(E/2

1 1

1 count —

overflow —

16.0 µs

1.049 s

8.0 µs

524.29 ms

5.333 µs

349.52 ms

(E/16)

20

(E/2

)

RTR[1:0]

Periodic (RTI) Interrupt Rates

13

14

15

16

0 0

0 1

1 0

1 1

8.192 ms

16.384 ms

32.768 ms

65.536 ms

4.096 ms

8.192 ms

16.384 ms

32.768 ms

2.731 ms

5.461 ms

10.923 ms

21.845 ms

(E/2

)

MOTOROLA

32

MC68HC11A8

MC68HC11A8TS/D

PRESCALER

DIVIDE BY

1, 4, 8, OR 16

TCNT (HI)

TCNT (LO)

TOI

9

MCU

E CLK

16-BIT FREE RUNNING

COUNTER

TOF

PR1

PR0

TAPS FOR RTI,

COP WATCHDOG, AND

PULSE ACCUMULATOR

INTERRUPT REQUESTS

(FURTHER QUALIFIED BY

I BIT IN CCR)

16-BIT TIMER BUS

TO PULSE

ACCUMULATOR

OC1I

FUNCTIONS

8

16-BIT COMPARATOR =

OC1F

OC2F

OC3F

PA7/OC1/

PAI

TOC1 (HI) TOC1 (LO)

BIT 7

BIT 6

FOC1

FOC2

FOC3

FOC4

FOC5

OC2I

OC3I

OC4I

I4/O5I

7

6

5

4

16-BIT COMPARATOR =

PA6/OC2/

OC1

TOC2 (HI) TOC2 (LO)

16-BIT COMPARATOR =

PA5/OC3/

OC1

BIT 5

BIT 4

BIT 3

TOC3 (HI) TOC3 (LO)

16-BIT COMPARATOR =

OC4F

OC5

PA4/OC4/

OC1

TOC4 (HI) TOC4 (LO)

16-BIT COMPARATOR =

TI4/O5 (HI) TI4/O5 (LO)

16-BIT LATCH CLK

PA3/OC5/

IC4/OC1

I4/O5F

IC4

CFORC

FORCE OUTPUT

COMPARE

I4/O5

IC1I

IC2I

IC3I

3

2

1

CLK

TIC1 (LO)

BIT 2

BIT 1

BIT 0

16-BIT LATCH

IC1F

PA2/IC1

PA1/IC2

PA0/IC3

TIC1 (HI)

CLK

16-BIT LATCH

IC2F

IC3F

TIC2 (HI)

TIC2 (LO)

CLK

16-BIT LATCH

TIC3 (HI)

TIC3 (LO)

TFLG 1

STATUS

FLAGS

TMSK 1

INTERRUPT

ENABLES

PORT A

PIN CONTROL

CAPTURE COMPARE BLOCK

Figure 11 Main Timer

NOTE: Port A pin actions are controlled by OC1M, OC1D, PACTL, TCTL1, and TCTL2 registers.

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

33

CFORC — Timer Compare Force

$100B

Bit 7

FOC1

0

6

FOC2

0

5

FOC3

0

4

FOC4

0

3

FOC5

0

2

0

1

0

Bit 0

0

RESET:

FOC5–FOC1 — Write ones to Force Compare(s)

0 = Not affected

1 = Output compare x action occurs, but OCxF flag bit not set

OC1M — Output Compare 1 Mask

$100C

Bit 7

6

5

4

3

2

0

1

0

Bit 0

OC1M7 OC1M6 OC1M5 OC1M4 OC1M3

0

RESET:

0

Set bit(s) to enable OC1 to control corresponding pin(s) of port A.

OC1D — Output Compare 1 Data

$100D

Bit 7

6

5

4

3

2

0

1

0

Bit 0

OC1D7 OC1D6 OC1D5 OC1D4 OC1D3

0

RESET:

0

If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.

TCNT — Timer Counter $100E, $100F

$100E

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

High

Low

TCNT

TCNT resets to $0000. In normal modes, TCNT is read-only.

TIC1–TIC3 — Timer Input Capture

$1010–$1015

$1010

$1011

$1012

$1013

$1014

$1015

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

9

1

9

1

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

High TIC1

Low

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

High TIC2

Low

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

High TIC3

Low

TICx not affected by reset.

MOTOROLA

34

MC68HC11A8

MC68HC11A8TS/D

TOC1–TOC5 — Timer Output Compare

$1016–$101F

$1016

$1017

$1018

$1019

$101A

$101B

$101C

$101D

$101E

$101F

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

9

1

9

1

9

1

9

1

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

High TOC1

Low

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

High TOC2

Low

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

High TOC3

Low

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

High TOC4

Low

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

High TOC5

Low

All TOCx register pairs reset to ones ($FFFF).

TCTL1 — Timer Control 1

$1020

Bit 7

OM2

0

6

OL2

0

5

OM3

0

4

OL3

0

3

OM4

0

2

OL4

0

1

OM5

0

Bit 0

OL5

0

RESET:

OM2–OM5 — Output Mode

OL2–OL5 — Output Level

OMx

OLx

Action Taken on Successful Compare

0

1

0

1

0

1

Timer disconnected from output pin logic

Toggle OCx output line

Clear OCx output line to 0

Set OCx output line to 1

TCTL2 — Timer Control 2

$1021

Bit 7

—

6

—

0

5

4

3

2

1

Bit 0

EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A

RESET:

0

Table 7 Timer Control Configuration

EDGxB

EDGxA

Configuration

Capture disabled

0

1

0

1

0

1

Capture on rising edges only

Capture on falling edges only

Capture on any edge

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

35

TMSK1 — Timer Interrupt Mask 1

$1022

Bit 7

OC1I

0

6

OC2I

0

5

OC3I

0

4

OC4I

0

3

OC5I

0

2

IC1I

0

1

IC2I

0

Bit 0

IC3I

0

RESET:

OC1I–OC5I — Output Compare x Interrupt Enable

If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested.

IC1I–IC3I — Input Capture x Interrupt Enable

If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested.

NOTE

Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable

the corresponding interrupt sources.

TFLG1 — Timer Interrupt Flag 1

$1023

Bit 7

OC1F

0

6

OC2F

0

5

OC3F

0

4

OC4F

0

3

OC5F

0

2

IC1F

0

1

IC2F

0

Bit 0

IC3F

0

RESET:

Clear flags by writing a one to the corresponding bit position(s).

OC1F–OC5F — Output Compare x Flag

Set each time the counter matches output compare x value.

IC1F–IC3F — Input Capture x Flag

Set each time a selected active edge is detected on the ICx input line.

TMSK2 — Timer Interrupt Mask 2

$1024

Bit 7

TOI

0

6

RTII

0

5

PAOVI

0

4

PAII

0

3

0

2

0

1

PR1

0

Bit 0

PR0

0

RESET:

TOI — Timer Overflow Interrupt Enable

0 = TOF interrupts disabled

1 = Interrupt requested when TOF is set to one

RTII — Real-Time Interrupt Enable

0 = RTIF interrupts disabled

1 = Interrupt requested when RTIF is set to one

PAOVI — Pulse Accumulator Overflow Interrupt Enable

Refer to 9 Pulse Accumulator.

PAII — Pulse Accumulator Input Edge Interrupt Enable

Refer to 9 Pulse Accumulator.

NOTE

Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable

the corresponding interrupt sources.

PR1 and PR0 — Timer Prescaler Select

In normal modes, PR1 and PR0 can only be written once, and the write must be within 64 cycles after

reset. Refer to Table 6 for specific timing values.

MOTOROLA

36

MC68HC11A8

MC68HC11A8TS/D

PR[1:0]

0 0

Prescaler

1

4

0 1

1 0

8

1 1

16

TFLG2 — Timer Interrupt Flag 2

$1025

Bit 7

TOF

0

6

RTIF

0

5

PAOVF

0

4

3

0

2

0

1

0

Bit 0

PAIF

0

RESET:

0

Clear flags by writing a one to the corresponding bit position(s).

TOF — Timer Overflow Flag

Set when TCNT changes from $FFFF to $0000.

RTIF — Real-Time (Periodic) Interrupt Flag

Set periodically. Refer to RTR[1:0] bits in PACTL register.

PAOVF — Pulse Accumulator Overflow Interrupt Flag

Refer to 9 Pulse Accumulator.

PAIF — Pulse Accumulator Input Edge Interrupt Flag

Refer to 9 Pulse Accumulator.

PACTL — Pulse Accumulator Control

$1026

Bit 7

DDRA7

0

6

PAEN

0

5

4

3

0

2

0

1

RTR1

0

Bit 0

RTR0

0

PAMOD PEDGE

RESET:

0

DDRA7 — Data Direction for Port A Bit 7

Refer to 5 Parallel Input/Output.

PAEN — Pulse Accumulator Enable

Refer to 9 Pulse Accumulator.

PAMOD — Pulse Accumulator Mode Select

Refer to 9 Pulse Accumulator.

PEDGE — Pulse Accumulator Edge Select

Refer to 9 Pulse Accumulator.

RTR [1:0] — Real-Time Interrupt (RTI) Rate

Table 8 Real-Time Interrupt Rates

RTR[1:0]

Divide E By

XTAL = 4.0 MHz

XTAL = 8.0 MHz

XTAL = 12.0 MHz

13

14

15

16

0 0

8.19 ms

4.096 ms

8.192 ms

16.384 ms

32.768 ms

2.0 MHz

2.731 ms

2

0 1

1 0

1 1

16.38 ms

32.77 ms

65.54 ms

1.0 MHz

5.461 ms

10.923 ms

21.845 ms

3.0 MHz

E =

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

37

9 Pulse Accumulator

The MC68HC11A8 has an 8-bit counter that can be configured to operate as a simple event counter or

for gated time accumulation, depending on the PAMOD bit in the PACTL register. The pulse accumu-

lator counter can be read or written at any time.

The port A bit 7 I/O pin can be configured as a clock in event counting mode, or as a gate signal to en-

able a free-running clock (E divided by 64) in gated time accumulation mode.

Table 9 Pulse Accumulator Timing

Common XTAL Frequencies

Selected Crystal

4.0 MHz

1.0 MHz

1000 ns

8.0 MHz

2.0 MHz

500 ns

12.0 MHz

3.0 MHz

333 ns

CPU Clock

Cycle Time

(E)

(1/E)

Pulse Accumulator (in Gated Mode)

6

1 count —

overflow —

64.0 µs

16.384 ms

32.0 µs

8.192 ms

21.33 µs

5.461 ms

(E/2 )

14

(E/2

)

PAOVI

PAOVF

1

INTERRUPT

REQUESTS

PAII

PAIF

2

E ÷ 64 CLOCK

(FROM MAIN TIMER)

TMSK2 INT ENABLES

TFLG2 INTERRUPT STATUS

PAI EDGE

DISABLE

FLAG SETTING

PAEN

OVERFLOW

PACNT 8-BIT COUNTER

MCU PIN

CLOCK

2 1

MUX

:

PA7/

PAI/

OC1

INPUT BUFFER

AND

EDGE DETECTOR

ENABLE

DATA

BUS

OUTPUT

BUFFER

PAEN

FROM

MAIN TIMER

OC1

FROM

DDRA7

PACTL CONTROL

INTERNAL

DATA BUS

PULSE ACC BLOCK

Figure 12 Pulse Accumulator System Block Diagram

MOTOROLA

38

MC68HC11A8

MC68HC11A8TS/D

TMSK2 — Timer Interrupt Mask 2

$1024

Bit 7

TOI

0

6

RTII

0

5

PAOVI

0

4

PAII

0

3

0

2

0

1

PR1

0

Bit 0

PR0

0

RESET:

TOI — Timer Overflow Interrupt Enable

Refer to 8 Main Timer.

RTII — Real-Time Interrupt Enable

Refer to 8 Main Timer.

PAOVI — Pulse Accumulator Overflow Interrupt Enable

0 = PAOVF interrupts disabled

1 = Interrupt requested when RTIF is set to one

PAII — Pulse Accumulator Input Edge Interrupt Enable

0 = PAIF interrupts disabled

1 = Interrupt requested when PAIF is set to one

PR1, PR0 — Timer Prescaler Select

Refer to 8 Main Timer.

NOTE

Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable

the corresponding interrupt sources.

TFLG2 — Timer Interrupt Flag 2

$1025

Bit 7

TOF

0

6

RTIF

0

5

PAOVF

0

4

PAIF

0

3

0

2

0

1

0

Bit 0

0

RESET:

Clear flags by writing a one to the corresponding bit position(s).

TOF — Timer Overflow Flag

Refer to 8 Main Timer.

RTIF — Real-Time Interrupt Flag

Refer to 8 Main Timer.

PAOVF — Pulse Accumulator Overflow Flag

Set when PACNT changes from $FF to $00.

PAIF — Pulse Accumulator Input Edge Flag

Set each time a selected active edge is detected on the PAI input line.

PACTL — Pulse Accumulator Control

$1026

Bit 7

DDRA7

0

6

PAEN

0

5

4

3

0

2

0

1

RTR1

0

Bit 0

RTR0

0

PAMOD PEDGE

RESET:

0

DDRA7 — Data Direction for Port A Bit 7

Refer to 5 Parallel Input/Output.

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

39

PAEN — Pulse Accumulator System Enable

0 = Pulse Accumulator disabled

1 = Pulse Accumulator enabled

PAMOD — Pulse Accumulator Mode

0 = Event counter

1 = Gated time accumulation

PEDGE — Pulse Accumulator Edge Control

PAMOD

PEDGE

Action on Clock

0

1

0

1

0

1

PAI falling edge increments the counter

PAI rising edge increments the counter

A zero on PAI inhibits counting

A one on PAI inhibits counting

RTR1 and RTR0 — Real-Time Interrupt (RTI) Rate

Refer to 8 Main Timer.

PACNT — Pulse Accumulator Counter

$1027

Bit 7

0

6

0

5

0

4

0

3

0

2

0

1

0

Bit 0

0

RESET:

Can be read and written.

MOTOROLA

40

MC68HC11A8

MC68HC11A8TS/D

10 Analog-to-Digital Converter

The A/D converter system uses an all capacitive charge redistribution technique to convert analog sig-

nals to digital values. The MC68HC11A8 A/D system is an 8-channel, 8-bit, multiplexed-input, succes-

sive-approximation converter and is accurate to ±1 least significant bit (LSB). It does not require

external sample and hold circuits because of the type of charge redistribution technique used.

Dedicated lines V and V provide the reference supply voltage inputs. Refer to the A/D converter

RH

RL

block diagram.

A multiplexer allows the single A/D converter to select one of 16 analog signals, as shown in the ADCTL

register description.

PE0

AN0

V

RH

8-BIT CAPACITIVE DAC

WITH SAMPLE AND HOLD

PE1

AN1

V

RL

PE2

AN2

SUCCESSIVE APPROXIMATION

REGISTER AND CONTROL

PE3

AN3

RESULT

ANALOG

MUX

PE4

AN4

PE5

AN5

INTERNAL

DATA BUS

PE6

AN6

PE7

AN7

ADCTL A/D CONTROL

RESULT REGISTER INTERFACE

ADR1 A/D RESULT 1

ADR2 A/D RESULT 2

ADR3 A/D RESULT 3

ADR4 A/D RESULT 4

EA9 A/D BLOCK

Figure 13 A/D Converter Block Diagram

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

41

E CLOCK

MSB

4

CYCLES

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

2

CYC

12 E CYCLES

CYC CYC CYC CYC CYC CYC CYC END

SAMPLE ANALOG INPUT

SUCCESSIVE APPROXIMATION SEQUENCE

CONVERT FIRST

CONVERT SECOND

CHANNEL, UPDATE

ADR2

CONVERT THIRD

CHANNEL, UPDATE

ADR3

CONVERT FOURTH

CHANNEL, UPDATE

ADR4

CHANNEL, UPDATE

ADR1

0

32

64

96

128 — E CYCLES

A/D CONVERSION TIM

Figure 14 A/D Conversion Sequence

DIFFUSION/POLY

COUPLER

ANALOG

INPUT

*

+ ~20V

– ~0.7V

+ ~12V

– ~0.7V

≤ 4 KΩ

< 2 pF

~ 20 pF

400 nA

JUNCTION

LEAKAGE

DAC

CAPACITANCE

DUMMY N-CHANNEL

OUTPUT DEVICE

INPUT

PROTECTION

DEVICE

V

RL

* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.

ANALOG INPUT PIN

Figure 15 Electrical Model of an Analog Input Pin (Sample Mode)

ADCTL — A/D Control/Status

$1030

Bit 7

CCF

U

6

0

5

SCAN

U

4

MULT

U

3

CD

U

2

CC

U

1

CB

U

Bit 0

CA

U

RESET:

CCF — Conversions Complete Flag

Set after an A/D conversion cycle. Cleared when ADCTL is written.

SCAN — Continuous Scan Control

0 = Do four conversions and stop

1 = Convert four channels in selected group continuously

MULT — Multiple Channel/Single Channel Control

0 = Convert single channel selected

1 = Convert four channels in selected group

MOTOROLA

42

MC68HC11A8

MC68HC11A8TS/D

CD–CA — Channel Select D through A

Table 10 A/D Converter Channel Assignments

Channel Select Control Bits

Channel

Signal

AN0

Result in ADRx if

MULT = 1

ADR1

CD

0

CC

0

CB

0

CA

0

1

AN1

ADR2

0

1

0

AN2

ADR3

0

1

AN3

ADR4

0

1

0

AN4*

ADR1

0

1

0

1

AN5*

ADR2

0

1

0

AN6*

ADR3

0

1

AN7*

ADR4

1

0

X

0

X

0

Reserved

ADR1–ADR4

ADR1

1

V

**

RH

1

0

1

0

1

V

ADR2

ADR3

ADR4

RL

(V )/2**

RH

Reserved**

* Not available in 48-pin package

**Used for factory testing

ADR1–ADR4 — A/D Results

$1031–$1034

Bit 7

6

5

4

3

2

1

Bit 0

$1031

$1032

$1033

$1034

1

Bit 0

ADR1

ADR2

ADR3

ADR4

Table 11 Analog Input to 8-Bit Result Translation Table

Bit 7

50%

6

5

4

3

2

1

Bit 0

(1)

25%

12.5%

6.25%

3.12%

1.56%

0.78%

0.39%

%

(2)

2.500

1.250

0.625

0.3125

0.1562

0.0781

0.0391

0.0195

Volts

(1)

(2)

% of V –V

V

= 0.0 V; V = 5.0 V

RL RH

RH

RL

OPTION — System Configuration Options

$1039

Bit 7

ADPU

0

6

CSEL

0

5

IRQE*

0

4

DLY*

1

3

CME

0

2

0

1

CR1*

0

Bit 0

CR0*

0

RESET:

*Can be written only once in first 64 cycles out of reset in normal modes, or any time in special modes.

ADPU — A/D Power Up

0 = A/D Converter powered down

1 = A/D Converter powered up

CSEL — Clock Select

0 = A/D and EEPROM use system E clock

1 = A/D and EEPROM use internal RC clock

MC68HC11A8

MC68HC11A8TS/D

MOTOROLA

43

IRQE — IRQ Select Edge Sensitive Only

Refer to 3 Resets and Interrupts.

DLY — Enable Oscillator Start-Up Delay on Exit from STOP

Refer to 3 Resets and Interrupts.

CME — Clock Monitor Enable

Refer to 3 Resets and Interrupts.

CR1, CR0 — COP Timer Rate Select

Refer to 3 Resets and Interrupts.

MOTOROLA

44

MC68HC11A8

MC68HC11A8TS/D

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different

applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not

convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in

systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of

the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such

unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola and B are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:

USA/EUROPE: Motorola Literature Distribution;

P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447

MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609

INTERNET: http://Design-NET.com

JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki,

6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315

HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298

M

MC68HC11A8TS/D


型号：	MC68HC11A8TS
厂家：	MOTOROLA
描述：	8-Bit Microcontrollers 8位微控制器微控制器
文件：	总45页 (文件大小：287K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC68HC11A8TS [MOTOROLA]

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