MC44725VFU [MOTOROLA]
Digital Video Encoder; 数字视频编码器
| 型号： | MC44725VFU |
| 厂家： | 
MOTOROLA |
| 描述： | Digital Video Encoder |
| 文件： | 总39页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
MC44724
MC44725
Digital Video Encoder
RGB Output Support
HCMOS Technology
The MC44724 and MC44725 are Digital Video Encoders (DVE).
They convert ITU-601/656 standard 4:2:2 Bit-Paralellel data into
analog composite video, S-Video or Y/Cb/Cr or R/G/B in PAL
and NTSC formats. They accept the multiplexed ((CB,Y,CR)Y)
signals from digital sources such as MPEG decoders and can act as
a sync generator master. All video processing is done digitally and
requires no external adjustment.
Specifically designed for digital satellite, digital cable decoders
and multimedia terminals.
VFU SUFFIX
64 VQFP
(0.5mm Pitch)
• World Wide Operation (PAL-BDGHI, PAL-N,PAL-M, NTSC-M)
• SMPTE 170M / ITU - R 624 composite video output
• Programmable Color Sub-carrier Frequencies
• Analog Horizontal, Vertical, Frame or Composite Sync Outputs
• Sync Extraction From Digital Input Data (SAV, EAV)
• Sync Polarity and Horizontal Phase Control
• Master or Slave Sync (H/Vsync, H/Fsync, ITU-R656 Slave) Operation
• Interlaced or Non-Interlaced Support
• 625/50 or 525/60 ITU-601/656 two 8-bit or 16-bit ((CB,Y,CR)Y) Digital Input
• Luma 2X / Chroma 4X Oversampling Filtering
• External VBI Information Data Input (such as TeleText Information Data)
• Selectable Two sets of Signals within (CVBS/Y/C) or (Y/Cb/Cr) or (R/G/B)
• Six Analog Outputs Through 10-bit DACs
• Easily programmed via Serial Bus ( I2C or SPI Bus)
• 2 Hardware I2C Chip Addresses
• Closed-Caption, CGMS and WSS Information data Insertion
• MACROVISION ver. 7.01 Anti-Copy Signal Insertion(MC44724 Only)
• On Chip Color - bar Generator
• +3.3V Power Supply or +3.3V(Digital)/+5V(Analog) Power Supply
The MC44724 device is protected by U.S. patent number 4,631,603,4,577,216 and 4,819,098
and other intellectual property rights. The use of Macrovision's copy protection technology in the
device must be authorized by Macrovision and is intended for home and other limited pay-per-
view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or
disassembly is prohibited.
No. 1
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Pin Assignment]
1
2
CVBS / Cb / B1
CVBS / Cb / B1
EXT
TVIN
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CVBS / Cb / B1 Vdd
Y / G1
3
DVIN0
DVIN1
DVIN2
DVIN3
DVIN4
DVIN5
DVIN6
DVIN7
DVss
4
5
Y / G1
6
Y / G1 Vdd
7
C / Cr / R1
MC44724
MC44725
C / Cr /R1
8
9
C / Cr / R1 Vdd
10
11
12
13
14
15
16
DAVss
Ibias1
DVdd
VReff1
DAVdd
SEL
SCL/SCK
SDA/SI
SO
VReff2
Ibias2
NC
No. 2
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Pin Descriptions]
PIN
NAME
I/O
DESCRIPTIONS
1
2
3
4
5
6
7
8
9
CVBS/Cb/B1
CVBS/Cb/B1
CVBS/Cb/B1Vdd
Y/G1
O
O
Analog composite video signal output or Cb or B signal output current drive(positive)
Analog composite video signal output or Cb or B signal output current drive(negative)
Power Supply for CVBS / Cb / B DAC circuit
Analog luminance or G signal output current drive(positive)
Analog luminance or G signal output current drive(negative)
Power Supply for Y / G DAC circuit
Analog chrominance signal output or Cr or R signal output current drive(positive)
Analog chrominance signal output or Cr or R signal output current drive(negative)
Power Supply for C / Cr /R DAC circuit
O
O
Y/G1
Y/G1Vdd
C/Cr/R1
C/Cr/R1
C/Cr/R1Vdd
DAVss
O
O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39~46
47
48
49
50
51
Ground for DAC circuit
Ibias1
Vref1
DAVdd
Vref2
Ibias2
O
Reference current for the 3 DACs1
Reference full scale voltage for the 3 DACs1
Power Supply for the DACs
Reference full scale voltage for the 3 DACs2
Reference current for the 3 DACs2
No Connect to pin
Analog composite video signal output or Cb or B signal output current drive(positive)
Analog composite video signal output or Cb or B signal output current drive(negative)
Power Supply for CVBS / Cb / B DAC circuit
Analog luminance or G signal output current drive(positive)
Analog luminance or G signal output current drive(negative)
Power Supply for Y / G DAC circuit
Analog chrominance signal output or Cr or R signal output current drive(positive)
Analog chrominance signal output or Cr or R signal output current drive(negative)
Power Supply for C / Cr /R DAC circuit
I2C chip address select { 0 : 40(hex)/41(hex) 1 : 1D(hex )/1E(hex) }
TEST pin(Ground)
O
NC
CVBS/Cb/B2
CVBS/Cb/B2
CVBS/Cb/B2Vdd
Y/G2
O
O
O
O
Y/G2
Y/GVdd
C/Cr/R2
C/Cr/R2
C/Cr/R2Vdd
ChipA
TEST
DVss
CLOCK
DVdd
Reset
PAL/NTSC
SO
SDA/SI
SCL/SCK
SEL
DVdd
DVss
DVIN7~0
TVIN
EXT
F/Vsync
Hsync
DATST
O
O
I
I
Ground for Digital circuit
27MHz clock input
Power Supply for Digital circuit
Reset signal, active LOW
I
I
NTSC/PAL select . This pin active only Reset time. (NTSC : Low PAL : High )
z(O) If SPI mode, serial data output / If I2C mode, connect to Ground
I/O(I) Serial data input, Open drain output / If SPI mode, serial data input
I
(I) Connect to Ground / If SPI mode, this pin is chip select
Power Supply for Digital circuit
Serial clock
Ground for Digital circuit
I/O Multiplexed 4:2:2 data(CCIR Rec656/601) input (1)
I/O TEST data input
I/O Csync/Frame sync output, or external VBI information input
I/O Frame sync or Vertical sync input/output
I/O Horizontal sync input/output
I
MUX swith in 8-bit X 2 Multiplexed 4:2:2 data(CCIR Rec656/601) input (1) and (2), or
for D/A converter test
52~55
TP8~5
I/O 8-bit Multiplexed 4:2:2 data(CCIR Rec656/601) input (2), or Multiplexed Cr/Cb data
(CCIR Rec656/601) input in 16-bit input mode, or Test data input/output (TP8 : MSB)
Ground for Digital circuit
56
DVss
57
58~61
DVdd
TP4~1
Power Supply for Digital circuit
I/O Multiplexed 4:2:2 data(CCIR Rec656/601) input (2), or Multiplexed Cr/Cb data
(CCIR Rec656/601) input in 16-bit input mode, or Test data input/output (TP1 : LSB)
I/O Test data inout/output
62
63
64
TP0
DLVdd
DLVss
Power Supply D/A Converter Digital circuit
Ground for D/A Coverter Digital circuit
No.
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MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Block Diagram]
ChipA
Y/G1Vdd
copy
protection
DVdd
DVdd
bus
Sync_generator
CVBS/Cb/B1Vdd
C/Cr/R1Vdd
BG
DVss
DVss
CGMS,
WSS_gen
Y/G1
CC_gen
0
0
0
Y/G1
CVBS/Cb/B1
CVBS/Cb/B1
C/Cr/R1
C/Cr/R1
H,V
0
off_set
Y
DVIN [7 : 0]
demux
0
0
0
Cb
Cr
Modulator
TVIN
Vref1
Ibias1
TP [8 : 1]
TP [0]
subcarrier
gen
Y/G2
Y/G2
0
0
RGB matrix
CVBS/Cb/B2
CVBS/Cb/B2
0
C/Cr/R2
C/Cr/R2
Vref2
clock
Reset
Ibias2
bus
DAVdd
DAVss
TEST
I2C / SPI
PAL/NTSC
MC44724/5
I2C/SPI chip-address
40/41(hex)
1D/1E(hex)
No. 4
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Function Descriptions]
Clock
27.0Mhz is necessary. This signal on the clock pin needs to be active before the reset pin is de-asserted.
( see figures 1 and 2 )
Reset Procedure
RESET is a level sensitive input pin. Driving the RESET pin low causes a DVE reset. The 27Mhz DVE
clock signal must be active before RESET is released. De-asserting reset will latch the status of the PAL/
NTSC, TVIN and SEL pins.
The PAL/NTSC pin determines the default values for the DVE control registers. The default register
values have been chosen so that standard PAL or NTSC video will appear at the DAC outputs immediately
when a valid input digital video data stream is present.
The value on the SEL pins determine the default serial communication mode. If Low, the DVE use I2C bus
operation. If High, the DVE use 4-wired SPI operation.
After reset, the VBI signals (Closed-Caption, CGMS and WSS ) are disabled.
(see page --- for sub-address register descriptions.)
Fig 1 : DVIN Data Input Timing
Input Clock 27MHz
50%
Tds
Input Data
DVIN0~7
Tdh
Fig 2 : Sync Data Output Timing
Clock 27MHz
Td
Td
Output Data
TP0~8
Output data
H/VF sync
No. 5
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Input Data Format
The input digital video is in accord with the ITU-R Rec.656 and SMPTE 125M standards. It is an two 8-bit
or 16-bit multiplexed 4:2:2 ((CB,Y,CR)Y) data stream. Samples are latched on the rising edge of the clock
signal. Data is input on pins DVIN[ 7 : 0 ] and TP[ 8 : 1 ]
(see figures 3 and 4 for sub-address register descriptions.)
Video Timing / Sync Generator
The DVE outputs PAL-B,D,G,H,I, PAL-N, PAL-M or NTSC-M standard video signals.
The DVE sync generator can be operated in two modes, master or slave.
In master mode, the DVE generates all the correct Horizontal and Vertical or Frame sync signals
internally, or it is output Csync signal through the EXT pin(C/Fsync).
In slave mode, the DVE derives the sync signals from the Bit-Parallel input data stream Start Active
Video (SAV) and End Active Video (EAV) data packet information. Sync signals are output on the
Hsync and F/Vsync or EXT pins and can be programmed for positive or negative polarity. The phase of
Hsync can also be controlled.
Also, the DVE allows more two slave modes. One is H/Vsync slave, and the aother is H/Fsync slave
mode.
Vertical Blanking corresponds to the following lines.
625/50 624-22 311-335 ITU-R line numbering
525/60 1-19 264-282 SMPTE line numbering
(see figures 3,4,5,6,7,8,9,10, and 11 for sub-address register descriptions.)
70(hex){[1:0]=01}
Fig 3 : Digital Input Timing(525/60 system) in Master Mode
Hsync phase
sub-address71[2:0]
-3T delay
+4T delay
Hsync polarity
Hsync
clock
sub-address71[5]
T
128T
1440T
244T
8-bit input mode
Cb718
00 00
Y718 Cr718 Y719
Cb0
FF
00 00 XY
Y0 Cr0 Y1 Cb2 Y2
DVIN0~7
FF
INVALID
16-bit input mode
Y718
Y719
Y2
Y0
Y1
DVIN0~7
INVALID
INVALID
Cb718
Cr718
Cr718
Cb2
Cr2
Cb0
Cr0
TP1~8
or
Cr0
Cb718
Cb0
No. 6
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
70(hex){[1:0]=01}
Fig 4 : Digital Input Timing(625/50 system) in Master Mode
Hsync phase
sub-address71[2:0]
-3T delay
+4T delay
Hsync polarity
Hsync
clock
sub-address71[5]
T
128T
1440T
264T
8-bit input mode
Cb718
00 00
Y718 Cr718
Y719 FF
Cb0
00 00 XY
Y0
Y1
Y2
Cr0
Cb2
FF
DVIN0~7
INVALID
16-bit input mode
Y718
Y719
Y2
Y0
Y1
DVIN0~7
INVALID
INVALID
Cb718
Cr718
Cr718
Cb718
Cb2
Cr2
Cb0
Cr0
TP1~8
or
Cr0
Cb0
Fig 5 : Sync Timing::525/60 Interlaced System in Master Mode
sub-address71[7] =0
Fsync polarity
sub-address71[3]
Fsync
Vsync
Vsync polarity
sub-address71[4]
Hsync
CSYNC
524 525
1
2
3
4
5
6
7
8
9
10
11
21
22
23
Fsync
Vsync
Hsync
CSYNC
261 262 263 264 265 266 267 268 269 270 271 272 273
283 284 285
No. 7
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
sub-address71[7] =0
Fig 6 : Sync Timing::625/50 Interlaced System in Master Mode
Fsync polarity
sub-address71[3]
Fsync
Vsync polarity
sub-address71[4]
Vsync
Hsync
CSYNC
21
22
23
621 622 623 624 625
1
2
3
4
5
6
7
8
9
Fsync
Vsync
Hsync
CSYNC
334 335
309 310 311 312 313 314 315 316 317 318 319 320 321
Fig 7 : Sync Timing::525/60 Non-interlaced System in Master Mode
sub-address71[7] =1
Fsync polarity
sub-address71[3]
Fsync
Vsync
Vsync polarity
sub-address71[4]
Hsync
CSYNC
261 262
1
2
3
4
5
6
7
8
9
10
11
21
22
23
sub-address71[7] =1
Fig 8 : Sync Timing::625/50 Non-interlaced System in Master Mode
Fsync polarity
sub-address71[3]
Fsync
Vsync polarity
sub-address71[4]
Vsync
Hsync
CSYNC
21
22
23
9
308 309 310 311 312
1
2
3
4
5
6
7
8
No. 8
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 9 : Analog Sync Timing::Rise and fall
0.148uS
27.04uS
0.148uS
4.74uS
NTSC
PAL
2.37uS
29.41uS
63.56uS
0.222uS
4.74uS
0.222uS
27.26uS
2.37uS
29.63uS
64.00uS
Fig 10 : Sync Timing::525/60 Interlaced System in Slave Mode
sub-address71[1:0] =10, 11
Odd field
Fsync polarity
sub-address71[4]
Fsync
Vsync
Vsync polarity
sub-address71[5]
Hsync
Internal Hsync
reset counter
Hsync Delay
sub-address 7A[7:0], 71[3:0]
CSYNC
3
4
5
6
7
Even field
Fsync
Vsync
Hsync
CSYNC
266
267
268
269
No. 9
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
sub-address71[1:0] =10, 11
Fig 11 : Sync Timing::625/50 Interlaced System in Slave Mode
Odd field
Fsync polarity
sub-address71[4]
Fsync
Vsync
Vsync polarity
sub-address71[5]
Hsync
Internal Hsync
reset counter
Hsync Delay
sub-address 7A[7:0], 71[3:0]
CSYNC
625
1
2
3
4
Even field
Fsync
Vsync
Hsync
CSYNC
313
314
315
316
No.
10
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Chroma / Luma Encoding
The DVE de-multiplexes the 4:2:2 digital video data stream.
The de-multiplexed Y or Luma samples are interpolated (2X oversampled) at the clock rate. Offset
compensation is then added, next any VBI signals consisting of Closed-Caption, CGMS and WSS are
added to the appropriate lines, then finally composite sync pulses are added to the Luma signal.
(see figure 12.)
De-multiplexed component color CB and CR samples are interpolated (4X oversampled) at the clock rate.
Interpolating simplifies the output filter and allows more accurate encoding. The DVE generates the
necessary subcarrier color frequency for PAL or NTSC encoding from the 27Mhz system clock. This
color subcarrier is then modulated by the base band component color CB and CR signals to create the
video Chroma signal. (see figure 13.)
A 7.5 IRE pedestal is added for the 60Hz field rate. This can be added for the 50Hz field rate through
serial bus control. (see sub-address register descriptions)
CVBS and S-VIDEO or YCbCr or RGB Outputs
The internal digital video signals drive 10-bit D/A converters. Converter outputs are bi-directional current
sources where the current is proportional to the digital data with reference to the IBIAS reference current. The
pins CVBS/Cb/B, Y/G and C/Cr/R are the respective composite, Luma and Chroma or Y/Cb/Cr or R/G/B signal
current source pins. Also, each DACs can drive 75ohm load register.
User can select 2 sets of signals within above 3 sets.
(see "Application Diagram" and "sub-address register descriptions".)
Bias Current Gain
DACs can be switched off through serial bus control to reduce power consumption. Both outputs of unused
DACs should be connected to ground through a resister to avoid charge buildup.
No. 11
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 12 : Luminance Output Range
470
420
340
290
212
162
82
32
32
Digital Y input code(16~235)
525/60 and 625/50 system
100%amplitude,100%saturation color bar
code
1023
IRE
100
670
620
89
540
70
59
490
412
41
30
362
11
7.5
0
282
232
232
200
-40
12
0
Analog Y output level(525/60 system)
100%amplitude,100%saturation color bar
code
1023
IRE
670
620
100
89
540
490
70
59
412
362
41
30
282
11
0
232
232
-43
44
0
Analog Y output level(625/50 system)
100%amplitude,100%saturation color bar
12
No.
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 13 : Chrominance Output Range
480
480
444
404
332
292
256
256
256
256
220
180
108
68
32
32
Digital Cb-input code(16~240)
525/60 and 625/50 system
100%amplitude,100%saturation color bar
Digital Cr-input code(16~240)
525/60 and 625/50 system
100%amplitude,100%saturation color bar
code
1023
IRE
63
59
45
Å }30
Å }32
Å }32
Å }22
Å }30
Å }22
Å }11
20
0
511
-20
-45
-59
-63
0
Analog C output level(525/60 system)
100%amplitude,100%saturation color bar
code
1023
IRE
Å }30
Å }32
67
63
48
Å }32
Å }30
Å }22
Å }22
Å }11
21.5
0
511
-21.5
-48
-63
-67
0
Analog C output level(625/50 system)
100%amplitude,100%saturation color bar
No. 13
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 14 : RGB Output Range for 525/60 system
code
1023
IRE
670
100
7.5
0
232
200
12
-40
0
Analog R output level(525/60 system)
100%amplitude,100%saturation color bar
code
IRE
1023
670
100
232
7.5
0
200
12
-40
0
Analog G output level(525/60 system)
code
1023
100%amplitude,100%saturation color bar
IRE
100
670
7.5
0
232
200
-40
12
0
Analog B output level(525/60 system)
100%amplitude,100%saturation color bar
Transformation
a) R = Y + 1.371 (Cr-128)
b) G = Y - 0.698 (Cr - 128) - 0.336 (Cb - 128)
c) B = Y +1.732 (Cb - 128)
No. 14
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 15 : RGB Output Range for 625/50 system
code
1023
IRE
670
100
232
0
44
-43
0
Analog R output level(625/50 system)
100%amplitude,100%saturation color bar
code
IRE
1023
670
100
232
0
44
-43
0
Analog G output level(625/50 system)
code
1023
100%amplitude,100%saturation color bar
IRE
670
100
232
0
-43
44
0
Analog B output level(625/50 system)
100%amplitude,100%saturation color bar
Transformation
a) R = Y + 1.371 (Cr-128)
b) G = Y - 0.698 (Cr - 128) - 0.336 (Cb - 128)
c) B = Y +1.732 (Cb - 128)
No. 15
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Copy Generation Managment System (CGMS) Encoding
CGMS signals can be encoded by the DVE onto output video line 20 (525 / 60 for Japan).
CGMS identification signals also identify and control the TV screen presentation mode - wide screen,
letterbox and or normal -16:9 or 4:3.
(see figures 18 for sub-address register descriptions.)
Closed-Caption Encoding
Closed-Captioned or Extended Data Service signals can be encoded by the DVE onto output video line 21/284
(NTSC) and line 22/335 (PAL). The CC data is input through the serial bus interface. Two 8-bit byte data pairs
are encoded for each field. There are four registers for holding the data - two bytes per field. The serial data is
7bit US-ASCII MSB first, proceeded by an odd parity bit. Total 8-bits. (P-7-6-5-4-3-2-1-0)
The DVE automatically generates the required clock run in and start bit for CC encoding. (see figure 16.)
When Closed-Captioning is enabled, the system micro processor (uP) should update the CC data once each
frame. The system uP should also write NULL characters when there is no CC data to encode. It is also
recommended to write CC data only to the inactive frame. Field1 and Field2 data are double-buffered by the
Frame sync falling edge of previous Frame, updating Frame 2 data during Frame1 display and Frame1 data
during Frame2 display.
(see figures 20 for sub-address register descriptions.)
Wide Screen Signalling (WSS) Encoding
WSS signals can be encoded by the DVE onto output video line 23 (625 / 50 for Europe).
WSS identification signals also identify and control the TV screen presentation mode - wide screen,
letterbox and or normal -16:9 or 4:3.
(see figures19 for sub-address register descriptions.)
No. 16
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Serial Control Bus
Control of the DVE device is accomplished through the I2C-Bus or SPI serial bus.
In I2C mode, pins SDA and SCL are the respective data and clock signals. Device address can be
40(hex)/41(hex) or 1E(hex)/1F(hex) . Slave address is chosen at reset by the state of the ChipA pin
signal { 0 : 40(hex)/41(hex), 1 : 1E(hex)/1F(hex) }
Sub-address register read and write operations are documented in the following section.
In SPI mode, pins SO, SI, SCK and SEL are the respective data input, output, serial clock and chip
select signals. Register read and write operations are documented in the following section.
TM
MACROVISION Copy Protection
When enabled, the Luma and Chroma signals are modified according to the MACROVISIONTM copy
protection process for Pay Per View (PPV) applications revision 7.01 dated Sep 6th , 1996.
Enabling and control is through the serial control bus.
No parts will be sent to the customer until the customer provides MOTOROLA with written confirmation of
a license, non-disclosure or waiver from MACROVISIONTM
.
If your customer would NOT like to use this feature or customer do NOT have an agreement of the copy
protection with MACROVISION, and then you should recommend the MC44723FT (no copy guard part).
No. 17
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 16-a : I2C-BUS Interface Write operation Timing
SCL
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
SDA
ACK
ACK
Start
chip address(write)
Sub-address
SCL
SDA
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
ACK
ACK
Data 1
Data N
Stop
Fig 16-b : I2C-BUS Interface Read operation Timing
SCL
D7
MSB
D6
D5
D4
D3
D2
D1
D0
D7
MSB
D6
D5
D4
D3
D2
D1
D0
SDA
LSB
LSB
ACK
ACK
Stop
Start
chip address(write)
Sub-address
SCL
SDA
D7
MSB
D6
D5
D4
D3
D2
D1
D0
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
LSB
ACK by MCU
chip address(Read)
ACK
Data 1
Start
SCL
D7
MSB
D6
D5
D4
D3
D2
D1
D0
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
SDA
LSB
ACK by MCU
Stop
ACK by MCU
Data 2
Data N
No. 18
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 17-a : SPI-BUS Interface Write operation Timing
SEL
SCK
x
x
D7
MSB
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
LSB
D7
MSB
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
LSB
SI
SO
(Don't
care)
x
x
x
x
MSB
LSB
MSB
LSB
Start
Write Command
Sub-address
SEL
SCK
SI
D7
MSB
D6
x
D5
x
D4
D3
x
D2
x
D1
D0
D7
MSB
D6
x
D5
x
D4
D3
D2
x
D1
x
D0
LSB
LSB
SO
(Don't
care)
MSB
x
x
x
x
x
x
x
LSB
MSB
LSB
Data 1
Data N
No. 19
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Fig 17-b : SPI-BUS Interface Read operation Timing
SEL
SCK
x
x
D7
MSB
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
D7
MSB
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
SI
LSB
LSB
SO
(Don't
care)
x
x
x
x
MSB
LSB
MSB
LSB
Start
Write Command
Sub-address
Stop
SEL
SCK
x
x
D7
MSB
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
x
x
x
x
x
x
x
x
SI
LSB
MSB
LSB
x
x
D7
MSB
D6
D5
D4
D3
D2
D1
D0
SO
MSB
LSB
LSB
Read Command
Data 1
Start
SEL
SCK
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SI
MSB
LSB
MSB
LSB
D7
MSB
D6
D5
D4
D3
D2
D1
D0
D7
MSB
D6
D5
D4
D3
D2
D1
D0
SO
LSB
LSB
Data 2
Data N
Stop
No. 20
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Specifications]
Maximum Ratings
DC Supply Voltage
Vdd
Vin
Vout
Iout
Pd
-0.5 ~ +7.0
-1.5 ~ Vdd+1.5
-0.5 ~ Vdd+1.5
25
750
-65 ~ +150
V
V
V
mA
mW
Å é
Input Voltage, All Inputs
Output Voltage, All Outputs
DC Output Current, per Pin
Power Dissipation
Storage Temperature
Tstg
Electrical Characteristics
Characteristic
Power Supply Voltage(Analog Blocks)
DAVDD
Power Supply Voltage(Digital Blocks)
DVDD
Symbol Min
AVDD 3.1
4.75
Typ
3.3
5.0
3.3
Max
3.5
5.25
3.5
Unit
V
DVDD 3.1
V
Supply Current(Analog Blocks)
Supply Current(Digital Blocks)
Operating Temperature
AIcc
DIcc
Ta
-
-
0
30
170
-
-
-
70
mA
mA
Å é
DAC Blocks Characteristics(Power Supply 3.3V,Ta=25Å é Å }3Å é )
Characteristics
Resolution
Symbol Min
Typ
-
Max
10
Unit
Bit
Other
-
-
Integral Non-Linearity
INL
DNL
Vyo
Vyfs 0.85
Vyzs
-
-
-
-
Å }4.0 LSB
Å }2.0 LSB
Vref = 1.1V
Vref = 1.1V
Vref = 1.5V
Differential Non-Linearity
Analog Output Voltage
Full Scale Output Voltage
Zero Scale Output Voltage
External Load Resistance
0.85
1.00
1.00
0.0
1.15
1.15
0.1
-
Vp-p
V
V
-
75
RL
120
É
DAC Blocks Characteristics(Power Supply 5.0V,Ta=25Å é Å }3Å é )
Characteristics
Resolution
Symbol Min
Typ
-
Max
10
Unit
Bit
Other
-
-
Integral Non-Linearity
INL
-
-
Å }4.0 LSB
Vref = 1.5V
Differential Non-Linearity
Analog Output Voltage
Full Scale Output Voltage
Zero Scale Output Voltage
External Load Resistance
DNL
Vyo
Vyfs
Vyzs
RL
-
-
-
-
-
Å }2.0 LSB
Vref = 1.5V
Vref = 2V
Vref = 2V
1.5
1.5
0.0
240
2.0
2.0
0.1
-
Vp-p
V
V
75
É
No. 21
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Specifications]
Clock Blocks Characteristics
Characteristic
Clock Rate
Clock Duty Cycle
Symbol
fc
Dty
Min
-
45
Typ
27.0
50
Max
-
55
Unit
MHz
Å ì
Digital Blocks Electrical Characteristics(Power Supply 3.3V,Ta=25Å é Å }3Å é )
Characteristics
Input Voltage HIGH
LOW
Output Voltage HIGH
(2.0mA) LOW
Symbol Min
Typ
-
-
-
Max
Unit
V
V
V
V
ViH
ViL
2.0
-
-
0.8
-
VoH 2.4
VoL
-
-
0.4
Input Leakage Current
Iin
-
Å }2.5
Å }20
-
-
20
20
-
-
5
5
27
É
É
A
A
Hi-Z Leakage Current
Input Capacitance
Load Capacitance
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
Data delay
Ioz
Cin
CL
Tds
Tdh
Tr
-
-
-
4
5
-
-
-
-
-
-
-
pF
pF
nS
nS
nS
nS
nS
-
-
-
Tf
Td
IIC/SPI-BUS Blocks Characteristics(Power Supply 3.3V,Ta=25Å é Å }3Å é )
Characteristics
Input Voltage LOW
Input Voltage High
Input Current
SDA Output Voltage (IOM=3mA)
Output Current (during acknowledge)
Symbol Å @Min
Typ
0.8
-
Å }10
0.4
-
Max
V
V
É
V
Unit
VILM
VIHM
VIM
-
2.3
-
-
-
-
-
-
A
VOM
IOM
-
3
mA
50Å
50Å
Clock
Tdh
valid
Tds
Tf
Tr
Input Data
not valid
not valid
No. 22
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[I2C-BUS Slave Address 40(hex)/41(hex) or 1E(hex)/1F(hex)]
<I2C-Bus Format>
WRITE MODE
S
Slave Address
40(hex) or 1E(hex)
DATA 0
--------
A
Sub Address
A
A
DATA N
A P
if more than 1byte DATA is transmitted,
then auto-increment of the Sub Address is performed
S
Start condition
Slave Address
A
Sub Address
DATA 0
DATA N
P
40(hex) or 1E(hex)
Acknowledge, generated by the slave
Sub address byte
First data byte
continued data byte(Sub Address is auto increment)
Stop condition
READ MODE
S
Slave Address
A
Sub Address N A P
Slave receiver
--------- AM P
DATA N + 1 AM
AM
40(hex) or 1E(hex)
then
S
Slave Address
41(hex) or 1F(hex)
Slave transmitter
A
DATA N
S
Start condition
Slave Address
A
Sub Address N
DATA N
DATA N + 1
AM
Slave receiver is act transmitter is ad
Acknowledge, generated by the slave
Sub Address byte
DATA byte of Register N
DATA byte of Register N + 1 (address auto-increment)
Acknowledge, generated by the micro controller
Stop condition (When Last AM must be '1' )
P
No. 23
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[SPI-BUS]
<SPI-Bus Format>
WRITE MODE
Write Command
40(hex) or 1E(hex)
DATA 0
--------
S
Sub Address
DATA N
P
if more than 1byte DATA is transmitted,
then auto-increment of the Sub Address is performed
S
Chip select on ( Hi to Lo)
Write Command 40(hex) or 1E(hex)
Sub Address
DATA 0
DATA N
P
Sub address byte
First data byte
continued data byte(Sub Address is auto increment)
Chip select off (Lo to Hi)
READ MODE
Write Command
S
P
Sub Address N
Slave receiver
40(hex) or 1E(hex)
then
S
Read Command
Slave transmitter
---------
P
DATA N
DATA N + 1
41(hex) or 1F(hex)
S
Chip select on (Hi to Lo)
Sub Address byte set
Sub Address N
Read Command
DATA N
DATA N + 1
P
41(hex) or 1F(hex)
DATA byte of Register N
DATA byte of Register N + 1 (address auto-increment)
Chip select off (Lo to Hi)
No. 24
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[Register Mapping and Description]
Sub-address 70 : Variable I/O Switch (write/read)
MSB
LSB
EXTsync
SW
F/Vsync
SW
M/S
mode1
M/S
mode0
color bar
select
self-SW
VBLK SW
bs-off
Register 70
default : 0000_0001(bin)
bs - off
: color burst control switch On/Off
0 : color burst ON (default)
1 : color burst OFF
self - SW
: internal self H/V counter reset switch On / Off
0 : self counter reset OFF (default)
1 : self counter reset ON
Note : this mode is ONLY valid at when 70h[1: 0] is "10(bin)" or "11(bin)".
color bar select : color bar select
Luma Chroma
0 : color bar
1 : color bar
100%
100%
100%
75%
VBLK SW
: Vertical Blanking Mask Enabale switch On-Off
0 : reject VBI information data in vertical blanking period (default)
1 : through VBI information data in vertical blanking period
EXTsync SW
F/Vsync SW
: Composite sync/Flame sync output switch
0 : Frame sync output (default)
1 : compsite sync output
: Flame sync /Vertical sync output switch
0 : Vertical sync output (default)
1 : Frame sync output
M/S sync mode1 : Master or Slave sync mode
M/S sync mode0 00 : 656 slave or H/V master mode
01 : 656 slave mode(no H/Vsync output) (defalt)
10 : Fsync/Hsync slave mode
11 : Vsync/Hsync slave mode
No. 25
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 71 : Sync control (write/read)
MSB
LSB
v-polarity f-polarity h- delay2 h-delay1 h-delay0
h-polarity
non-inter VBI SW
Register 71
default : 0000_0100(bin)
non-inter
VBI SW
h-polarity
v-polarity
f-polarity
: non-interlaced mode select
0 : interlace mode (default)
1 : non-interlace mode
: vertical blanking information signal input control switch on EXT pin
0 : VBI input Off (default)
1 : VBI input On
: polarity of Hsync
0 : negative (default)
1 : positive
: polarity of Vsync
0 : negative (default)
1 : positive
: polarity of Fsync
0 : field1 (odd) = low level (default)
1 : field1 (odd) = high level
h-delay2
h-delay1
h-delay0
: delay on Hsync with referance to DVIN data in Master mode
000: + 4 clock delay
001: + 3 clock delay
010: + 2 clock delay
011: + 1 clock delay
100: + 0 clock delay
101: - 1 clock delay
110: - 2 clock delay
111: - 3 clock delay
Note : this h-delay can be also related with 7A[7:0] register and can
delay totally +2023 clock delay in H/V or H/Fsynnc slave mode.
No. 26
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 72 : PAL/NTSC setup (write / read)
MSB
LSB
PAL/
EXT I/O
SW
PAL/
NTSC2
phase-set
TEST
setup75 625/525
color bar
Register 72
NTSC1
default : 0000_1000(bin) NTSC (If "PAL/NTSC" pin is LOW level)
0000_0101(bin) PAL
phase-set
: color sub-currier phase syncronization
0 : free running (default)
1 : 1 phase reset/8 field and 1 phase reset/4 flam
TSET
: for test, should be "0"
EXT I/O SW
: Input/Output switch on EXT pin
0 : VBI input(default)
1 : Csync or Flame sync output
color bar
: internal color bar genarator control
0 : nomal operation (default)
1 : color bar genarator On
(need to set color bar mode on sub-address 70[5]. )
setup75
: Setup level for Luminance
0 : setup level for luminunce = 0IRE
1 : setup level for luminunce = 7.5IRE
625/525 : control line mode
0 : 525 lines / 60 Hz mode
1 : 625 lines / 50 Hz mode
PAL/NTSC2
PAL/NTSC1
: subcarrier control
00 : NTSC(M)
01 : PAL (BDGHI)
10 : PAL (M)
11 : PAL (N)
No. 27
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 73: Vertical Blanking Information Luma (Y) Level (write only)
MSB
LSB
Register 73
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
default : 1000_0000(bin)
Sub-address 74: Vertical Blanking Information Chroma (U) Level (write only)
MSB
LSB
Register 74
U7
U6
U5
U4
U3
U2
U1
U0
default : 79(dec)
(NTSC)
157(dec) (PAL)
Sub-address 75: Vertical Blanking Information Chroma (V) Level (write only)
MSB
LSB
Register 75
V2
V1
V0
V7
V6
V5
V4
V3
default : 128(dec) (NTSC)
107(dec) (PAL)
No. 28
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 76 : signal control 1(write only)
MSB
LSB
dac sw0
Luma
Cr
Cb
CVBS dac C dac
Y dac
dac sw1
Register 76
default : 0000_0000(bin)
Cr
Cb
: Cr/Cb signal control
0 : Cr, Cb On (default)
1 : chrominance Off
Luma
: luminance control
0 : luminance On (default)
1 : luminance Off
CVBSdac
Cdac
Ydac
: D/A converter (1) output On-Off control
0 : CVBS/Cb/BDAC1, C/Cr/RDAC1, Y/GDAC1 output On (default)
1 : CVBS/Cb/BDAC1, C/Cr/RDAC1, Y/GDAC1 output Off
dac sw1
dac sw0
: 1~9-pin's D/A converter output signal control
01 or 11 : R/G/B output On
10 : Y/Cr/Cb output On
00 : Y/C/CVBS output On
Sub-address 77 : signal control 2 (write only )
MSB
LSB
dac sw3
B
R
B dac
R dac
G
G dac
dac sw4
Register 77
default : 0000_0001(bin)
B
R
G
: B/R/G signal control
0 : B/R/G signal On (default)
1 : B/R/G signal Off
Bdac
Rdac
Gdac
: D/A converter (2) output On-Off control
0 : CVBS/Cb/BDAC2, C/Cr/RDAC2, Y/GDAC2 output On (default)
1 : CVBS/Cb/BDAC2, C/Cr/RDAC2, Y/GDAC2 output Off
dac sw4
dac sw3
: 17~25-pin's D/A converter (2) output signal control
01 or 11 : R/G/B output On (default)
10 : Y/Cr/Cb output On
00 : Y/C/CVBS output On
29
No.
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 78~79 : Sub-carrier phase control (write only)
MSB
LSB
sc-ph2
sc-ph9
sc-ph8
sc-ph6
sc-ph5
sc-ph4
sc-ph3
sc-ph1
sc-ph7
Register 78
default : 0000_0000(bin)
MSB
LSB
sc-ph0
-
-
-
-
-
-
Register 79
default : 0000_0000(bin)
sc-ph9
sc-ph8
sc-ph7
sc-ph6
sc-ph5
sc-ph4
sc-ph3
sc-ph2
sc-ph1
sc-ph0
: sub-currier phase control
0000_0000 : sub-currier phase 0 degree (default)
to
1111_1111 : sub-currier phase 359 degree
Sub-address 7A : Hsync delay control (write only)
MSB
LSB
H-delay3
H-dela10 H-delay9
H-delay6 H-delay5 H-delay4
H-delay8
H-delay7
Register 7A
default : 0000_0000(bin)
h-delay10
: delay on Hsync with reference to DVIN data
0000_0000_000 : Hsync delay 0 delay
to
h-delay9
h-delay8
h-delay7
h-delay6
h-delay5
h-delay4
h-delay3
1111_1111_000 : Hsync delay +255 delay
Note : this h-delay can be also related with 71[3:0] register and can
delay totally +2023 delay(1111_1111_111) in H/V or H/ Fsync
slave mode.
No. 30
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 7B : Digital Video Input Select Control (write only)
MSB
LSB
16-bit
Cr_tmg1
Cr _tmg 2
-
-
Cb _tmg 2 Cb_tmg1
Y_tmg
Register 7B
input mode
default : 0000_0000(bin)
Cr/Cb_tmg2
Cr/Cb_tmg1
: Cr/Cb clock timing delay in 16-bit Digital Input Mode
00 : Cr clock delay 0 clock (default)
01 : Cr clock delay +1 clock
10 : Cr clock delay +2 clock
11 : Cr clock delay +3 clock
Y_tmg
: Y clock timing delay in 16-bit Digital Input Mode
0 : Y clock delay 0 clock (default)
1 : Y clock delay +1 clock
16-bit
input mode
: 16-bit Multiplexed CbYCrY Digital Video Input mode
0 : 8-bit CbYCrY Digital Video Input mode (default)
1 : 16-bit CbYCrY Digital Video Input mode
No.
31
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 7C : signal control 3(write only)
MSB
LSB
R/B CGMS
G CGMS RGB bf CbCr bf croma bf
Ysync
G sync
R/B sync
Register 7C
default : 0000_0000(bin)
Y sync
: Y sync Signal On/Off (Y/Cb/Cr mode only)
0 : Y sync On (default)
1 : Y sync Off
R/B sync
G sync
: R/B sync signal On/Off
0 : R/B sync Off (default)
1 : R/B sync On
: G sync signal On/Off
0 : G sync Off (default)
1 : G sync On
R/B CGMS
G CGMS
RGB bf
CbCr bf
Croma
: R/B CGMS data Insertion On/Off
0 : CGMS data On
1 : CGMS data off
: G CGMS data Insertion On/Off
0 : CGMS data On
1 : CGMS data off
: RGB burst level On/Off
0 : RGB bf data On
1 : RGB bf data off
: CbCr burst On/Off
0 : Cb/Cr bf data On
1 : Cb/Cr bf data off
: Croma burst On/Off
0 : Croma bf data On
1 : Croma bf data off
Sub-address 7D~7E : Vsync delay control (write only)
MSB
LSB
V-delay2
V-delay7
V-delay9 V-delay8
V-delay6 V-delay5 V-delay4 V-delay3
Register 7D
default : 0000_0000(bin)
MSB
LSB
V-delay0
-
-
-
-
-
-
V-delay1
Register 7E
default : 0000_0000(bin)
No. 32
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
V-delay9
V-delay8
V-delay7
V-delay6
V-delay5
V-delay4
V-delay3
V-delay2
V-delay1
V-delay0
: delay on Vsync with reference to DVIN data in slave mode
0000_0000_000 : Vsync delay 0 delay
to
1111_1111_111 : Hsync delay +1023 delay
No. 33
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
NTSC only
Sub-address 80~82: CGMS characters for Field1(Line20)/Field2(Line283) (write only)
MSB
LSB
vid112 vid111
b2 b1
Register 80
vid118
b8
vid117
b7
vid116
b6
vid115
b5
vid114
b4
vid113
b3
MSB
MSB
LSB
Register 81
Register 82
vid128
b16
vid127
b15
vid126
b14
vid125
b13
vid124
b12
vid123
b11
vid122 vid121
b9
b10
LSB
vid134
b20
vid133
b19
vid132
b18
vid131
b17
XX
XX
XX
XX
49.1Å }0.5É
11.2Å }0.6É
2.235É
70IRE
0IRE
Ref b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b12 b14 b16 b18 b20
b13 b15 b17 b19
b11
-40IRE
Fig 18 : CGMS wave form
PAL only
Sub-address 80~81: WSS characters for Line23 (write only)
MSB
LSB
Register 80
wss7
wss6
wss5
wss4
b5
wss3
wss2
b3
wss1
b2
wss0
b1
b8
b7
b6
b4
MSB
LSB
Register 81
-
-
wss13
b14
wss12
b13
wss11
b12
wss10
b11
wss9
b10
wss8
b9
b16
b15
End of
horizontal
blanking
internal
500mV+-5%
10.5É
11.0É s+-0.25É
27.4É
38.4É
44.5É
Fig 19 : WSS wave form
34
No.
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 83~84 :closed caption characters/extended data for Field1(Line21) (write)
default 1000_0000
First byte to Encode
MSB
LSB
LSB
Register 83
ccp118 ccb117
ccb116 ccb115
ccb114
b4
ccb113
b3
ccb112
b2
ccb111
b1
parity
b7
b6
b5
Second byte to Encode
MSB
ccp128
parity
ccb125
b5
ccb127
b7
ccb126
b6
ccb124
b4
ccb123
b3
ccb122
b2
ccb121
b1
Register 84
Sub-address 85~86 :closed cation character/extended data for Field2(Line284)
First byte to Encode
MSB
LSB
Register 85
ccp218 ccb217
ccb216
b6
ccb215
b5
ccb214
b4
ccb213
b3
ccb212
b2
ccb211
b1
parity
b7
Second byte to Encode
MSB
LSB
ccb221
b1
Register 86
ccp228
parity
ccb225
b5
ccb227
b7
ccb226
b6
ccb224
b4
ccb223
b3
ccb222
b2
4.15Å }0.1É
10.50Å }0.5É
33.764É
12.91É
50IRE
50IRE
0IRE
0IRE
p
a
r
i
t
p b b b b b b b
a 1 2 3 4 5 6 7
b b b b b b b
1 2 3 4 5 6 7
r
i
CHARACTER1
CHARACTER2
-40IRE
t
y
y
Fig 20 : Closed caption wave form
sub-address 83 & 84 and 85 & 86 (previous frame data)
are double-buffered by Flame sync falling edge
Field 1
Fsync
Field 2
Fig 21 : Closed caption data update timing
No. 35
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 87 :Closed caption/CGMS
MSB
LSB
-
CGMS
CC2_flag CC1_flag CC_null
WSS
CC2
CC1
Register 87
default 00h
CC2_flag : Closed Caption Status Flag for field2/field1
CC1_flag : 00 : Automatically set to " 11 " at when 2-byte Closed
Caption data are written, and then will be cleared to "00"
when the data is send to doubled buffer
CC_null : Automatically set the null code when the data is send to doubled
buffer
0 : Keep data registers
1 : Automatically set the null code
WSS
: WSS information data insertion On-Off
0 : WSS information data insertion Off
1 : WSS information data insertion On
CGMS : CGMS information data insertion On-Off
0 : CGMS information data insertion Off
1 : CGMS information data insertion On
CC2
: closed caption/extended data for field2 encoding On-Off
0 : closed caption/extended data for field2 encoding Off
1 : closed caption/extended data for field2 encoding On
CC1
: closed caption/extended data for field1 encoding
0 : closed caption/extended data for field1 encoding Off
1 : closed caption/extended data for field1 encoding On
No. 36
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
I2C-BUS Slave Receiver Sub-address map
77h[7:5]
[4:2]
[1:0]
B/R/G signal control (default 0: On)
D/A converter(2) output On/Off control(default 0: On)
D/A converter(2) output signal control(default 0X: On)
70h:[7]
[6]
[5]
[4]
[3]
[2]
[1:0]
71h:[7]
burst control (default 0:on)
self counter reset switch (default 0:off)
color bar select (defalut 0:Luma 100% Chroma 100%)
vertical blanking switch(default 0:off)
EXT pin output mode select (Csync:1, Flame sync:0)
F/Vsync select(default 0:Vsync)
Master/Slave mode select(default 01:656_slave)
interlaced / non-interlaced
78h[7:0]
79h[1:0]
79h[7:2]
sub-currier phase control(default 00h)
sub-currier phase control(default 00)
n.a.
7A[7:0]
hsync-delay control
(default 0:interlaced)
(In slave mode, is valid with 71h[2:0] register)
n.a
Cr/Cb clock timing delay in 16-bit digital input mode
(default 00: clock delay 0)
Y clock timing delay in 16-bit digital input mode
(default 0: clock delay 0)
16-bit multiplexed CbYCrYdigital video input mode
(default 0: 8-bit YCrCb digital video input mode)
Ysync signal On/Off(YCrCb mode only)(default 0: On)
R/Bsync signal On/Of(default 0: Off)
Gsync signal On/Of(default 0: Off)
R/B CGMS data insertion On/Of(default 0: On)
G CGMS data insertion On/Of(default 0: On)
RGB/CbCr burst On/Off(default 0: On)
Chroma burst On/Off(default 0: On)
[6]
[5]
[4]
[3]
VBI input control on EXT pin (default 0:off)
horizontal sync polarity (default 0)
vertical sync polarity (default 0)
flame sync polarity (default 0)
hsync delay control (default 100:0 clock delay)
(In slave mode can use with 7A[7:0])
sub-currier phase syncronaiation(default 0)
Test mode (default 0:off)
EXT I/O switch(defalt 1:cysnc output)
color bar generate(default 0:off)
setup level control(default 1:7.5IRE)
625lines50Hz/525Lines60Hz
7B[7:6]
[5:2]
[1]
[0]
[2:0]
72h:[7]
[6]
[5]
[4]
[3]
7C[7]
[6]
[5]
[4]
[3]
[2]
(default set PAL/NTSC pin)
PAL/NTSC (default set PAL/NTSC pin)
00:NTSC/M
[2:1]
[0]
[1:0]
01:PAL/BGHL
(10:PAL/M) (11:PAL/N)
7D[7:0]
delay on Vsync with reference to DVIN data in slave
mode
n.a
73h[7:0]
74h[7:0]
75h[7:0]
76h[7]
[6]
Y_register(default 80h)
7E[7:2]
[1:0]
U_register(default 79d:ntsc/157d:PAL)
V_register(default 128d:ntsc/107d:PAL)
Cr on/off (default 0:on)
delay on Vsync with reference to DVIN data in slave
mode
Cb on/off (default 0:on)
80~82h
80~81h
83h[7:0]
84h[7:0]
85h[7:0]
86h[7:0]
87h[7:6]
[5]
CGMS characters for field1(line20)/field2(line283)
WSS characters for field1(line23)
CC character1(line21) (default 'h80)
CC character2(line21) (default 'h80)
CC character1(line284) (default 'h80)
CC character2(line284) (default 'h80)
Closed Caption Status Flag for field2
Automatic set to null code(Closed Caption data)
n.a.
[5]
Luma on/off(default 0:on)
(default 0: on)
CVBS dac/Cdac/Ydac on/off(default 0: on)
D/A converter output signal control
(default 00 : CBVS/Y/C output)
[4:2]
[1:0]
[4]
[3]
[2]
WSS information data insetion on/off (default 0: off)
CGMS on/off (default 0: off)
[1]
CC closed caption/extended data for field2 encoding
(default 0: off)
[0]
CC closed caption/extended data for field1 encoding
(default 0: off)
<<<<<<<< M-BUS Format >>>>>>
** WRITE MODE **
S | Slave_address(W) | A | Sub_address | A | Data0 | A | ... | DataN | A | P
S
Start condition
Slave_address
42(hex) or 1C(hex)
A
Acknowledge generated by me
Sub_address register
First data
Sub_address
Data0
DataN
P
Continued data(address is auto incremented)
Stop condition
<<<<<<<< SPI-Bus Format >>>>>>
** WRITE MODE **
S | Write Command | Sub_address | Data0 | ... | DataN | P
S
Chip select on (High to Low)
42(hex) or 1C(hex)
Sub_address byte
Write Command
Sub_address
Data0
First data
DataN
P
Continued data byte(address is auto incremented)
Chip select off (Low to High)
No.37
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
[ Appr ica t ion Dia gr a
DVdd
DLVdd
47uF
47uF
0.01uF
0.01uF
CVBS
1
CVBS / Cb / B1
EXT
TVIN
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
M PEG
DECODER
75
CVBS / Cb / B1
CVBS / Cb / B1 Vdd
Y / G1
2
3
0.01u
47uF
75
75
DVIN0
DVIN1
DVIN2
DVIN3
DVIN4
DVIN5
DVIN6
DVIN7
DVss
Y
C
4
75
75
5
Y / G1
0.01u
47uF
6
Y / G1 Vdd
C / Cr / R1
C / Cr /R1
C / Cr / R 1Vdd
7
MC44724
MC44725
8
75
9
47uF
10
11
12
13
14
15
16
DAVss
Ibias1
0.01u
2k
1k
750
DVdd
VReff1
DAVdd
SEL
47uF
0.01u
SCL/SCK
SDA/SI
SO
VReff2
Ibias2
0.01u
750
NC
2k
1k
I f
NTSC sy st em = "
0.01u
else PAL sy st em = "
100k
10uF
clock
No. 38
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Package
HD
D
Det ail A
L1
L
min
-
max
1.70
0.15
A
A1
A2
b
0.05
1.40TYP
0.18
0.10
9.90
9.90
0.27
0.20
10.1
10.1
c
D
E
Detail A
e
0.50
HD
HE
L
11.80
11.80
12.20
12.20
ZD or ZE
b
e
0.50TYP
L1
0.80
1.20
10
0
-
É
y
0.10
ZD
ZE
1.25TYP
1.25TYP
unit : m
39
No.
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.
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