MC14XXXBDW [MOTOROLA]
BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER; BCD至七段锁存器/解码器/驱动器
| 型号： | MC14XXXBDW |
| 厂家： | 
MOTOROLA |
| 描述： | BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER |
| 文件： | 总9页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14511B BCD–to–seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode devices
and NPN bipolar output drivers in a single monolithic structure. The circuit
provides the functions of a 4–bit storage latch, an 8421 BCD–to–seven
segment decoder, and an output drive capability. Lamp test (LT), blanking
(BI), and latch enable (LE) inputs are used to test the display, to turn–off or
pulse modulate the brightness of the display, and to store a BCD code,
respectively. It can be used with seven–segment light–emitting diodes
(LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts
either directly or indirectly.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
Applications include instrument (e.g., counter, DVM, etc.) display driver,
computer/calculator display driver, cockpit display driver, and various clock,
watch, and timer uses.
DW SUFFIX
SOIC
CASE 751G
•
•
•
•
•
•
•
•
•
•
Low Logic Circuit Power Dissipation
High–Current Sourcing Outputs (Up to 25 mA)
Latch Storage of Code
Blanking Input
Lamp Test Provision
Readout Blanking on all Illegal Input Combinations
Lamp Intensity Modulation Capability
Time Share (Multiplexing) Facility
Supply Voltage Range = 3.0 V to 18 V
Capable of Driving Two Low–power TTL Loads, One Low–power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
MC14XXXBD
Plastic
Ceramic
SOIC
SOIC
T
= – 55° to 125°C for all packages.
A
PIN ASSIGNMENT
B
C
1
2
16
15
V
DD
f
a
LT
BI
3
4
5
6
7
8
14
13
12
11
10
9
g
a
b
c
•
•
Chip Complexity: 216 FETs or 54 Equivalent Gates
Triple Diode Protection on all Inputs
f
g
b
e
c
LE
D
d
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Rating
DC Supply Voltage
Symbol
Value
Unit
V
A
d
e
V
DD
– 0.5 to + 18
V
SS
Input Voltage, All Inputs
V
in
– 0.5 to V
DD
+0.5
V
DISPLAY
DC Current Drain per Input Pin
Operating Temperature Range
Power Dissipation per Package†
Storage Temperature Range
I
10
mA
C
T
A
– 55 to + 125
500
0
1
2
3
4
5
6
7
8
9
P
D
mW
C
TRUTH TABLE
T
– 65 to + 150
25
stg
Inputs
Outputs
LE BI LT
D
X
X
C
B
X
X
A
X
X
a
1
0
b
1
0
c
1
0
d
1
0
e
1
0
f
g
Display
8
Maximum Output Drive Current
(Source) per Output
I
mA
OHmax
X
X
X
0
0
1
X
X
1
0
1
0
Blank
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
1
0
0
0
0
0
1
1
0
1
2
3
Maximum Continuous Output Power
(Source) per Output ‡
P
50
mW
OHmax
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
0
4
5
6
7
‡P
= I
(V
– V )
OH
OHmax OH DD
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
8
9
Blank
Blank
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Blank
Blank
Blank
Blank
1
1
1
X
X
X
X
*
*
X = Don’t Care
* Depends upon the BCD code previously applied when LE = 0
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
5.0
10
15
4.1
9.1
14.1
—
—
—
4.1
9.1
14.1
4.57
9.58
14.59
—
—
—
4.1
9.1
14.1
—
—
—
Vdc
Vdc
“1” Level
“0” Level
OH
V
in
= 0 or V
DD
Input Voltage #
(V = 3.8 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 8.8 or 1.0 Vdc)
O
(V = 13.8 or 1.5 Vdc)
O
V
Vdc
Vdc
“1” Level
Source
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
(V = 0.5 or 3.8 Vdc)
O
(V = 1.0 or 8.8 Vdc)
O
(V = 1.5 or 13.8 Vdc)
O
Output Drive Voltage
V
OH
(I
OH
(I
OH
(I
OH
(I
OH
(I
OH
(I
OH
= 0 mA)
5.0
10
15
4.1
—
3.9
—
3.4
—
—
—
—
—
—
—
4.1
—
3.9
—
3.4
—
4.57
4.24
4.12
3.94
3.70
3.54
—
—
—
—
—
—
4.1
—
3.5
—
3.0
—
—
—
—
—
—
—
= 5.0 mA)
= 10 mA)
= 15 mA)
= 20 mA)
= 25 mA)
(I
OH
(I
OH
(I
OH
(I
OH
(I
OH
(I
OH
= 0 mA)
9.1
—
9.0
—
8.6
—
—
—
—
—
—
—
9.1
—
9.0
—
8.6
—
9.58
9.26
9.17
9.04
8.90
8.70
—
—
—
—
—
—
9.1
—
8.6
—
8.2
—
—
—
—
—
—
—
Vdc
Vdc
= 5.0 mA)
= 10 mA)
= 15 mA)
= 20 mA)
= 25 mA)
14.1
—
14
—
13.6
—
—
—
—
—
—
—
14.1
—
14
—
13.6
—
14.59
14.27
14.18
14.07
13.95
13.70
—
—
—
—
—
—
14.1
—
13.6
—
13.2
—
—
—
—
—
—
—
(I
OH
(I
OH
(I
OH
(I
OH
(I
OH
(I
OH
= 0 mA)
= 5.0 mA)
= 10 mA)
= 15 mA)
= 20 mA)
= 25 mA)
Output Drive Current
I
mAdc
OL
(V
OL
(V
OL
(V
OL
= 0.4 V)
= 0.5 V)
= 1.5 V)
Sink
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
pF
in
Input Capacitance
Quiescent Current
C
—
5.0
7.5
—
in
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
DD
(Per Package) V = 0 or V
in DD
,
I
= 0 µA
out
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
I
T
5.0
10
15
I
T
I
T
I
T
= (1.9 µA/kHz) f + I
= (3.8 µA/kHz) f + I
= (5.7 µA/kHz) f + I
µAdc
DD
DD
DD
(C = 50 pF on all outputs, all
L
buffers switching)
#Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ V
2.0 Vdc min @ V
2.5 Vdc min @ V
= 5.0 Vdc
= 10 Vdc
= 15 Vdc
DD
DD
DD
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
–3
I (C ) = I (50 pF) + 3.5 x 10 (C – 50) V
DD
f
T
L
T
L
where: I is in µA (per package), C in pF, V
in Vdc, and f in kHz is input frequency.
T
L
DD
MC14511B
362
MOTOROLA CMOS LOGIC DATA
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
V
Vdc
DD
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise Time
t
ns
TLH
THL
PLH
t
t
t
= (0.40 ns/pF) C + 20 ns
= (0.25 ns/pF) C + 17.5 ns
= (0.20 ns/pF) C + 15 ns
5.0
10
15
—
—
—
40
30
25
80
60
50
TLH
TLH
TLH
L
L
L
Output Fall Time
t
ns
ns
t
t
t
= (1.5 ns/pF) C + 50 ns
= (0.75 ns/pF) C + 37.5 ns
= (0.55 ns/pF) C + 37.5 ns
5.0
10
15
—
—
—
125
75
65
250
150
130
THL
THL
THL
L
L
L
Data Propagation Delay Time
t
t
t
t
= (0.40 ns/pF) C + 620 ns
= (0.25 ns/pF) C + 237.5 ns
= (0.20 ns/pF) C + 165 ns
L
5.0
10
15
—
—
—
640
250
175
1280
500
350
PLH
PLH
PLH
L
L
t
t
t
= (1.3 ns/pF) C + 655 ns
L
t
t
5.0
10
15
—
—
—
720
290
200
1440
580
400
PHL
PHL
PHL
PHL
= (0.60 ns/pF) C + 260 ns
L
= (0.35 ns/pF) C + 182.5 ns
L
ns
Blank Propagation Delay Time
PLH
5.0
I0
15
—
—
—
600
200
150
750
300
220
t
t
t
= (0.30 ns/pF) C + 585 ns
L
PLH
PLH
PLH
= (0.25 ns/pF) C + 187.5 ns
L
= (0.15 ns/pF) C + 142.5 ns
L
t
t
5.0
10
15
—
—
—
485
200
160
970
400
320
t
t
t
= (0.85 ns/pF) C + 442.5 ns
L
PHL
PHL
PHL
PHL
= (0.45 ns/pF) C + 177.5 ns
L
= (0.35 ns/pF) C + 142.5 ns
L
ns
Lamp Test Propagation Delay Time
PLH
5.0
10
15
—
—
—
313
125
90
625
250
180
t
t
t
= (0.45 ns/pF) C + 290.5 ns
L
PLH
PLH
PLH
= (0.25 ns/pF) C + 112.5 ns
L
= (0.20 ns/pF) C + 80 ns
L
t
5.0
10
15
—
—
—
313
125
90
625
250
180
t
t
t
= (1.3 ns/pF) C + 248 ns
L
PHL
PHL
PHL
PHL
= (0.45 ns/pF) C + 102.5 ns
L
= (0.35 ns/pF) C + 72.5 ns
L
Setup Time
t
5.0
10
15
100
40
30
—
—
—
—
—
—
ns
ns
ns
su
Hold Time
t
5.0
10
15
60
40
30
—
—
—
—
—
—
h
Latch Enable Pulse Width
t
5.0
10
15
520
220
130
260
110
65
—
—
—
WL
* The formulas given are for the typical characteristics only.
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; how-
ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high-impedance circuit. A destructive high current mode may occur if V and V
are not constrained to the range V
≤ (V or
in out
SS
in
V ) ≤ V .
out DD
Due to the sourcing capability of this circuit, damage can occur to the device if V
is applied, and the outputs are shorted to
DD
V and are at a logical 1 (See Maximum Ratings).
SS
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
or V ).
DD
SS
MOTOROLA CMOS LOGIC DATA
MC14511B
363
Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective C loads.
L
20 ns
20 ns
V
V
V
DD
SS
OH
90%
50%
1
A, B, AND C
10%
2f
50% DUTY CYCLE
50%
ANY OUTPUT
V
OL
Figure 1. Dynamic Power Dissipation Signal Waveforms
20 ns
INPUT C
20 ns
V
DD
90%
50%
10%
V
V
SS
t
t
PHL
PLH
OH
90%
10%
50%
OUTPUT g
V
OL
t
t
THL
TLH
(a) Inputs D and LE low, and Inputs A, B, BI and LT high.
20 ns
V
V
DD
90%
50%
LE
10%
SS
t
h
t
su
V
DD
50%
INPUT C
V
V
SS
OH
OUTPUT g
V
OL
(b) Input D low, Inputs A, B, BI and LT high.
20 ns
20 ns
V
V
DD
90%
50%
LE
10%
SS
t
WL
(c) Data DCBA strobed into latches.
Figure 2. Dynamic Signal Waveforms
MC14511B
364
MOTOROLA CMOS LOGIC DATA
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT
V
V
DD
DD
COMMON
ANODE LED
COMMON
CATHODE LED
≈
1.7 V
≈
1.7 V
V
SS
V
SS
INCANDESCENT READOUT
FLUORESCENT READOUT
V
V
V
DD
DD
DD
**
DIRECT
(LOW BRIGHTNESS)
FILAMENT
SUPPLY
V
SS
V
V
OR APPROPRIATE
SS
SS
VOLTAGE BELOW V
.
SS
(CAUTION: Maximum working voltage = 18.0 V)
GAS DISCHARGE READOUT
LIQUID CRYSTAL (LCD) READOUT
EXCITATION
(SQUARE WAVE,
APPROPRIATE
VOLTAGE
V
V
TO V )
V
DD
SS
DD
DD
1/4 OF MC14070B
V
V
SS
SS
**Afilamentpre–warmresistorisrecommendedtoreducefilament
thermal shock and increase the effective cold resistance of the
filament.
Direct dc drive of LCD’s not recommended for life of
LCD readouts.
MOTOROLA CMOS LOGIC DATA
MC14511B
365
LOGIC DIAGRAM
BI 4
13 a
12 b
A 7
11 c
10 d
B 1
9 e
15 f
14 g
C 2
LT 3
D 6
V
V
= PIN 16
= PIN 8
DD
SS
LE 5
MC14511B
366
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
0.25 (0.010)
G
0.300 BSC
7.62 BSC
M
S
T
B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MOTOROLA CMOS LOGIC DATA
MC14511B
367
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
–B–
8X P
M
M
0.010 (0.25)
B
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
1
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
J
16X D
M
S
S
0.010 (0.25)
T
A
B
F
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
10.15
7.40
2.35
0.35
0.50
MAX
10.45
7.60
2.65
0.49
0.90
MIN
MAX
0.411
0.299
0.104
0.019
0.035
0.400
0.292
0.093
0.014
0.020
R X 45
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
M
SEATING
14X G
K
PLANE
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
MC14511B
368
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