MC14648BCL [MOTOROLA]
Hex Non-Inverting 3-State Buffer; 六角非反相三态缓冲器
| 型号： | MC14648BCL |
| 厂家： | 
MOTOROLA |
| 描述： | Hex Non-Inverting 3-State Buffer |
| 文件： | 总6页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14503B is a hex non–inverting buffer with 3–state outputs, and a
high current source and sink capability. The 3–state outputs make it useful in
common bussing applications. Two disable controls are provided. A high
level on the Disable A input causes the outputs of buffers 1 through 4 to go
into a high impedance state and a high level on the Disable B input causes
the outputs of buffers 5 and 6 to go into a high impedance state.
P SUFFIX
PLASTIC
CASE 648
•
•
3–State Outputs
TTL Compatible — Will Drive One TTL Load Over Full Temperature
Range
D SUFFIX
SOIC
CASE 751B
•
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Two Disable Controls for Added Versatility
Pin for Pin Replacement for MM80C97 and 340097
ORDERING INFORMATION
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
– 0.5 to + 18.0
DD
V , V
T
= – 55° to 125°C for all packages.
A
Input or Output Voltage (DC or Transient)
Input Current (DC or Transient), per Pin
Output Current (DC or Transient), per Pin
Power Dissipation, per Package†
Storage Temperature
– 0.5 to V
DD
+ 0.5
V
in out
I
in
± 10
mA
mA
mW
C
I
± 25
out
TRUTH TABLE
P
D
500
Appropriate
Disable
T
stg
– 65 to + 150
260
In
Input
Out
T
L
Lead Temperature (8–Second Soldering)
C
n
n
0
0
0
1
0
1
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
1
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
X
High
Impedance
CIRCUIT DIAGRAM
X = Don’t Care
ONE OF TWO/FOUR BUFFERS
V
DD
LOGIC DIAGRAM
15
12
*IN
n
OUT
DISABLE B
IN 5
n
11
OUT 5
14
2
13
3
IN 6
IN 1
IN 2
IN 3
IN 4
OUT 6
OUT 1
OUT 2
OUT 3
OUT 4
*DISABLE
*INPUT
V
SS
TO OTHER BUFFERS
4
5
* Diode protection on all inputs (not shown)
6
7
10
9
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
1
DISABLE A
voltages to this high-impedance circuit. For proper operation, V and
in
V
V
= PIN 16
= PIN 8
V
out
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
DD
SS
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
SS DD
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= V
DD
Input Voltage
(V = 3.6 or 1.4 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 7.2 or 2.8 Vdc)
O
(V = 11.5 or 3.5 Vdc)
O
“1” Level
Source
Sink
V
Vdc
IH
(V = 1.4 or 3.6 Vdc)
O
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
(V = 2.8 or 7.2 Vdc)
O
(V = 3.5 or 11.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
OH
(V
OH
(V
OH
(V
OH
(V
OH
= 2.5 Vdc)
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
4.5
5.0
5.0
10
– 4.3
– 5.8
– 1.2
– 3.1
– 8.2
—
—
—
—
—
– 3.6
– 4.8
– 1.02
– 2.6
– 6.8
– 5.0
– 6.1
– 1.4
– 3.7
– 14.1
—
—
—
—
—
– 2.5
– 3.0
– 0.7
– 1.8
– 4.8
—
—
—
—
—
15
(V
OL
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
4.5
5.0
10
2.2
2.6
6.5
—
—
—
—
1.8
2.1
5.5
2.1
2.3
6.2
25
—
—
—
—
1.2
1.3
3.8
—
—
—
—
mAdc
OL
15
19.2
16.1
11.2
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
1.0
2.0
4.0
—
—
—
0.002
0.004
0.006
1.0
2.0
4.0
—
—
—
30
60
120
µAdc
µAdc
Q
Total Supply Current**†
I
5.0
10
15
I
I
I
= (2.5 µA/kHz) f + I
= (6.0 µA/kHz) f + I
= (10 µA/kHz) f + I
T
T
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs)
L
T
(All outputs switching,
50% Duty Cycle)
Three–State Output Leakage
Current
I
15
—
± 0.1
—
± 0.0001
± 0.1
—
± 3.0
µAdc
TL
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
DD
– V ) in volts, f in kHz is input frequency, and k = 0.006.
SS
T
L
MOTOROLA CMOS LOGIC DATA
MC14503B
327
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
All Types
V
DD
V
CC
Characteristic
Symbol
Unit
Typ #
Max
Output Rise Time
t
ns
TLH
THL
PLH
PHL
PHZ
t
t
t
= (0.5 ns/pF) C + 20 ns
= (0.3 ns/pF) C + 8.0 ns
= (0.2 ns/pF) C + 8.0 ns
5.0
10
15
45
23
18
90
45
35
TLH
TLH
TLH
L
L
L
Output Fall Time
t
ns
ns
ns
t
t
t
= (0.5 ns/pF) C + 20 ns
= (0.3 ns/pF) C + 8.0 ns
= (0.2 ns/pF) C + 8.0 ns
5.0
10
15
45
23
18
90
45
35
THL
THL
THL
L
L
L
Turn–Off Delay Time, all Outputs
t
t
t
t
t
= (0.3 ns/pF) C + 60 ns
= (0.15 ns/pF) C + 27 ns
= (0.1 ns/pF) C + 20 ns
5.0
10
15
75
35
25
150
70
50
PLH
PLH
PLH
L
L
L
Turn–On Delay Time, all Outputs
t
t
t
= (0.3 ns/pF) C + 60 ns
= (0.15 ns/pF) C + 27 ns
= (0.1 ns/pF) C + 20 ns
5.0
10
15
75
35
25
150
70
50
PHL
PHL
PHL
L
L
L
3–State Propagation Delay Time
Output “1” to High Impedance
t
5.0
10
15
75
40
35
150
80
70
ns
ns
ns
ns
Output “0” to High Impedance
High Impedance to “1” Level
High Impedance to “0” Level
t
5.0
10
15
80
40
35
160
80
70
PLZ
PZH
t
5.0
10
15
65
25
20
130
50
40
t
5.0
10
15
100
35
25
200
70
50
PZL
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
PIN ASSIGNMENT
DIS A
IN 1
1
2
16
15
V
DD
DIS B
OUT 1
IN 2
3
4
5
6
7
8
14
13
12
11
10
9
IN 6
OUT 6
IN 5
OUT 2
IN 3
OUT 5
IN 4
OUT 3
V
OUT 4
SS
MC14503B
328
MOTOROLA CMOS LOGIC DATA
DISABLE
INPUT
20 ns
20 ns
V
V
DD
90%
V
DD
16
50%
INPUT
10%
SS
INPUT
t
t
PLH
PHL
PULSE
GENERATOR
OUTPUT
V
OH
OL
90%
50%
OUTPUT
10%
V
C
L
SS
V
t
t
THL
TLH
t
t
PHL
PLH
Figure 1. Switching Time Test Circuit and Waveforms
(t
, t
, t
, and t )
TLH THL PHL
PLH
DISABLE INPUT
DISABLE INPUT
t
, t
CIRCUIT
PULSE
GENERATOR
PULSE
GENERATOR
PLZ PZL
V
V
DD
DD
t
, t
CIRCUIT
INPUT
16
PHZ PZH
16
8
1 k
OUTPUT
INPUT
OUTPUT
1 k
C
L
C
L
V
V
SS
SS
8
20 ns
20 ns
10%
V
V
DD
90%
50%
DISABLE INPUT
SS
t
t
PLZ
PZL
V
OH
90%
10%
90%
OUTPUT FOR t
OUTPUT FOR t
, t
CIRCUIT
CIRCUIT
PZH PZL
≈
V
+ 0.05 V
– 0.15 V
OL
t
t
PZH
PHZ
≈
V
OH
, t
PHZ PLZ
10%
V
OL
Figure 2. 3–State AC Test Circuit and Waveforms
(t , t , t , t
)
PLZ PHZ PZH PZL
MOTOROLA CMOS LOGIC DATA
MC14503B
329
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J 16 PL
G
0.300 BSC
7.62 BSC
M
S
0.25 (0.010)
T B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MC14503B
330
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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MC14503B/D
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