MC14069 [MOTOROLA]
Hex Inverter; 六反相器
MOTOROLA 
SEMICONDUCTOR TECHNICAL DATA
The MC14069UB hex inverter is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure.
These inverters find primary use where low power dissipation and/or high
noise immunity is desired. Each of the six inverters is a single stage to
minimize propagation delays.
L SUFFIX
CERAMIC
CASE 632
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
P SUFFIX
PLASTIC
CASE 646
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs (see Page 5–2)
Pin–for–Pin Replacement for CD4069UB
•
•
•
Meets JEDEC UB Specifications
D SUFFIX
SOIC
CASE 751A
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
ORDERING INFORMATION
V
DD
– 0.5 to + 18.0
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
I , I
in out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
T
A
= – 55° to 125°C for all packages.
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
T
stg
– 65 to + 150
260
PIN ASSIGNMENT
T
Lead Temperature (8–Second Soldering)
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
IN 1
OUT 1
IN 2
1
2
3
4
14
13
12
11
V
DD
IN 6
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
OUT 6
IN 5
OUT 2
LOGIC DIAGRAM
CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
IN 3
5
6
10
9
OUT 5
IN 4
OUT 3
1
3
5
9
2
V
DD
V
7
8
OUT 4
V
V
= PIN 14
= PIN 7
SS
DD
SS
4
6
8
INPUT*
OUTPUT
11
13
10
12
V
SS
* Double diode protection on all
inputs not shown.
20 ns
20 ns
V
DD
V
DD
90%
14
OUTPUT
50%
10%
INPUT
PULSE
GENERATOR
V
V
SS
INPUT
t
t
PLH
PHL
C
L
7
V
OH
90%
50%
10%
SS
OUTPUT
V
OL
t
t
TLH
THL
Figure 1. Switching Time Test Circuit and Waveforms
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
Max
V
Vdc
DD
Characteristic
Symbol
Unit
Min
Max
Min
Max
Min
Output Voltage
“0” Level
“1” Level
“0” Level
V
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
OL
V
in
= V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0
Input Voltage
(V = 4.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.0
2.0
2.5
—
—
—
2.25
4.50
6.75
1.0
2.0
2.5
—
—
—
1.0
2.0
2.5
O
(V = 9.0 Vdc)
O
(V = 13.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 Vdc)
O
5.0
10
15
4.0
8.0
12.5
—
—
—
4.0
8.0
12.5
2.75
5.50
8.25
—
—
—
4.0
8.0
12.5
—
—
—
(V = 1.0 Vdc)
O
(V = 1.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
µAdc
ns
DD
Total Supply Current**†
(Dynamic plus Quiescent,
I
T
5.0
10
15
I
I
I
= (0.3 µA/kHz) f + I /6
DD
T
T
T
= (0.6 µA/kHz) f + I /6
DD
Per Gate) (C = 50 pF)
= (0.9 µA/kHz) f + I /6
DD
L
Output Rise and Fall Times**
t
,
TLH
(C = 50 pF)
t
5.0
10
15
—
—
—
—
—
—
—
—
—
100
50
40
200
100
80
—
—
—
—
—
—
L
THL
t
t
t
, t
= (1.35 ns/pF) C + 33 ns
= (0.60 ns/pF) C + 20 ns
= (0.40 ns/pF) C + 20 ns
L
TLH THL
L
L
, t
TLH THL
, t
TLH THL
Propagation Delay Times**
(C = 50 pF)
t
t
,
ns
PLH
L
PHL
t
t
t
, t
= (0.90 ns/pF) C + 20 ns
= (0.36 ns/pF) C + 22 ns
= (0.26 ns/pF) C + 17 ns
5.0
10
15
—
—
—
—
—
—
—
—
—
65
40
30
125
75
55
—
—
—
—
—
—
PLH PHL
L
L
L
, t
PLH PHL
, t
PLH PHL
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
DD
– V ) in volts, f in kHz is input frequency, and k = 0.002.
SS
T
L
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautionsmust be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, V and V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
be left open.
should be constrained to the range V
≤ (V or V ) ≤ V
.
in out
SS
in
out
DD
or V ). Unused outputs must
SS
DD
MC14069UB
2
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
1
9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
7
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.280
0.200
0.020
0.065
MIN
19.05
6.23
3.94
0.39
1.40
MAX
19.94
7.11
5.08
0.50
1.65
0.750
0.245
0.155
0.015
0.055
–T–
SEATING
PLANE
K
F
G
J
K
0.100 BSC
2.54 BSC
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
G
N
M
D 14 PL
0.25 (0.010)
J 14 PL
0.25 (0.010)
L
M
N
0.300 BSC
7.62 BSC
0
15
0
15
M
S
T
A
M
S
T
B
0.020
0.040
0.51
1.01
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
ISSUE L
14
8
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
1
7
4. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
C
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
0
10
0
10
0.015
0.039
0.39
1.01
H
G
D
M
MOTOROLA CMOS LOGIC DATA
MC14069UB
3
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE F
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
7
–B–
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
DIM
A
B
C
D
F
G
J
K
M
P
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
0.337
0.150
0.054
0.014
0.016
–T–
SEATING
PLANE
J
M
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T
B
A
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
R
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in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
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MC14069UB/D
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