MC14052BCPDS [MOTOROLA]
Differential Multiplexer, 1 Func, 4 Channel, CMOS, PDIP16;
| 型号： | MC14052BCPDS |
| 厂家： | 
MOTOROLA |
| 描述： | Differential Multiplexer, 1 Func, 4 Channel, CMOS, PDIP16 解复用器 开关 复用器或开关 信号电路 |
| 文件： | 总9页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC14051B, MC14052B, and MC14053B analog multiplexers are
digitally–controlled analog switches. The MC14051B effectively implements
an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a
Triple SPDT. All three devices feature low ON impedance and very low OFF
leakage current. Control of analog signals up to the complete supply voltage
range can be achieved.
L SUFFIX
CERAMIC
CASE 620
•
•
•
•
Triple Diode Protection on Control Inputs
Switch Function is Break Before Make
Supply Voltage Range = 3.0 Vdc to 18 Vdc
P SUFFIX
PLASTIC
CASE 648
Analog Voltage Range (V
DD
– V ) = 3.0 to 18 V
EE
Note: V
must be
V
EE
SS
•
•
•
•
•
Linearized Transfer Characteristics
Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical
Pin–for–Pin Replacement for CD4051, CD4052, and CD4053
For 4PDT Switch, See MC14551B
D SUFFIX
SOIC
CASE 751B
For Lower R
ON
CMOS Devices
, Use the HC4051, HC4052, or HC4053 High–Speed
ORDERING INFORMATION
MAXIMUM RATINGS*
Symbol
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
Parameter
Value
Unit
V
DD
DC Supply Voltage (Referenced to V ,
EE
V
≥ V
)
– 0.5 to + 18.0
V
SS
EE
T
= – 55° to 125°C for all packages.
A
V , V
in out
Input or Output Voltage (DC or Transient)
(Referenced to V for Control Inputs and
SS
for Switch I/O)
V
EE
– 0.5 to V
DD
+ 0.5
V
I
in
Input Current (DC or Transient),
per Control Pin
± 10
mA
mA
mW
C
I
Switch Through Current
± 25
sw
P
Power Dissipation. per Package†
Storage Temperature
500
D
T
stg
– 65 to + 150
260
T
L
Lead Temperature (8–Second Soldering)
C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:“P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
MC14051B
MC14052B
MC14053B
8–Channel Analog
Multiplexer/Demultiplexer
Dual 4–Channel Analog
Multiplexer/Demultiplexer
Triple 2–Channel Analog
Multiplexer/Demultiplexer
6
11
INHIBIT
A
B
C
X0
X1
X2
X3
X4
6
10
9
12
14
15
11
1
5
INHIBIT
A
B
X0
X1
X2
X3
Y0
Y1
6
11
INHIBIT
A
B
C
X0
X1
14
15
X
Y
CONTROLS
CONTROLS
CONTROLS
X
Y
13
10
9
13
14
15
10
9
12
13
2
COMMONS
OUT/IN
COMMONS
OUT/IN
X
3
SWITCHES
IN/OUT
SWITCHES
IN/OUT
Y0
Y1
Z0
COMMON
OUT/IN
SWITCHES
IN/OUT
12
1
1
5
3
Z
4
5
2
4
X5
X6
X7
2
4
Y2
Y3
3
Z1
V
V
V
= PIN 16
= PIN 8
= PIN 7
V
V
V
= PIN 16
= PIN 8
= PIN 7
V
DD
= PIN 16
= PIN 8
= PIN 7
DD
SS
EE
DD
SS
EE
V
SS
EE
V
Note: Control Inputs referenced to V , Analog Inputs and Outputs reference to V . V
SS EE EE
must be ≤ V
.
SS
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS
– 55 C
25 C
Typ #
125 C
Characteristic
Symbol
V
DD
Test Conditions
Unit
Min
Max
Min
Max
Min
Max
SUPPLY REQUIREMENTS (Voltages Referenced to V
)
EE
– 3.0 ≥ V
Power Supply Voltage
Range
V
DD
—
3.0
18
3.0
—
18
3.0
18
V
V
DD
≥ V
SS
EE
Quiescent Current Per
Package
I
5.0
10
15
Control Inputs:
= V or V
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µA
DD
V
in
,
V
SS DD
Switch I/O:V
EE
, and
I/O
V
DD
∆V
500 mV**
= 25 C only (The
A
switch
Total Supply Current
(Dynamic Plus
Quiescent, Per Package
I
5.0
10
15
T
µA
D(AV)
(0.07 µA/kHz) f + I
(0.20 µA/kHz) f + I
(0.36 µA/kHz) f + I
DD
DD
DD
channel component,
Typical
(V – V )/R , is
in out on
not included.)
CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to V
)
SS
Low–Level Input Voltage
High–Level Input Voltage
V
5.0
10
15
R
= per spec,
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
V
V
IL
IH
in
on
= per spec
I
off
V
5.0
10
15
R
= per spec,
on
= per spec
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
I
off
Input Leakage Current
Input Capacitance
I
15
—
V
in
= 0 or V
DD
—
—
± 0.1
—
—
±0.00001 ± 0.1
—
—
1.0
—
µA
C
—
5.0
7.5
pF
in
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to V
)
EE
Recommended
Peak–to–Peak Voltage
Into or Out of the Switch
V
—
—
—
Channel On or Off
Channel On
0
0
V
0
0
—
V
0
0
V
V
PP
I/O
DD
DD
DD
Recommended Static or
Dynamic Voltage Across
the Switch** (Figure 5)
∆V
switch
600
—
600
300
—
mV
Output Offset Voltage
ON Resistance
V
OO
V
in
= 0 V, No Load
—
—
—
10
—
—
µV
R
5.0
10
15
∆V
500 mV**,
IH
—
—
—
800
400
220
—
—
—
250
120
80
1050
500
280
—
—
—
1200
520
300
Ω
on
switch
= V or V
V
in
IL
(Control), and V
=
in
0 to V
DD
(Switch)
∆ON Resistance Between
Any Two Channels in the
Same Package
∆R
5.0
10
15
—
—
—
70
50
45
—
—
—
25
10
10
70
50
45
—
—
—
135
95
65
Ω
on
Off–Channel Leakage
Current (Figure 10)
I
off
15
V
= V or V
—
± 100
—
± 0.05
± 100
—
±1000 nA
in IL IH
(Control) Channel to
Channel or Any One
Channel
Capacitance, Switch I/O
C
C
—
—
Inhibit = V
—
—
—
10
—
—
—
pF
pF
I/O
O/I
DD
DD
Capacitance, Common O/I
Inhibit = V
(MC14051B)
(MC14052B)
(MC14053B)
—
—
—
—
—
—
—
—
—
60
32
17
—
—
—
—
—
—
—
—
—
Capacitance, Feedthrough
(Channel Off)
C
—
—
Pins Not Adjacent
Pins Adjacent
—
—
—
—
—
—
0.15
0.47
—
—
—
—
—
—
pF
I/O
#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
* For voltage drops across the switch (∆V ) > 600 mV ( > 300 mV at high temperature), excessive V current may be drawn, i.e. the
switch
DD
DD
current out of the switch may contain both V and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.)
MC14051B MC14052B MC14053B
2
MOTOROLA CMOS LOGIC DATA
ELECTRICAL CHARACTERISTICS* (C = 50 pF, T = 25 C) (V
V
SS
unless otherwise indicated)
L
A
EE
V
– V
Vdc
Typ #
All Types
DD
EE
Characteristic
Symbol
Max
Unit
Propagation Delay Times (Figure 6)
t
, t
ns
PLH PHL
Switch Input to Switch Output (R = 10 kΩ)
MC14051
L
t
t
t
, t
= (0.17 ns/pF) C + 26.5 ns
= (0.08 ns/pF) C + 11 ns
L
= (0.06 ns/pF) C + 9.0 ns
L
5.0
10
15
35
15
12
90
40
30
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
MC14052
ns
ns
ns
t
t
t
, t
= (0.17 ns/pF) C + 21.5 ns
= (0.08 ns/pF) C + 8.0 ns
L
= (0.06 ns/pF) C + 7.0 ns
L
5.0
10
15
30
12
10
75
30
25
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
MC14053
t
t
t
, t
= (0.17 ns/pF) C + 16.5 ns
5.0
10
15
25
8.0
6.0
65
20
15
PLH PHL
L
, t
= (0.08 ns/pF) C + 4.0 ns
L
PLH PHL
, t
PLH PHL
= (0.06 ns/pF) C + 3.0 ns
L
Inhibit to Output (R = 10 kΩ, V
EE
= V
)
t
t
, t
,
L
SS
PHZ PLZ
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level
MC14051B
, t
PZH PZL
5.0
10
15
350
170
140
700
340
280
MC14052B
MC14053B
5.0
10
15
300
155
125
600
310
250
ns
ns
ns
5.0
10
15
275
140
110
550
280
220
Control Input to Output (R = 10 kΩ, V
= V
)
t
, t
L
EE
SS
PLH PHL
MC14051B
5.0
10
15
360
160
120
720
320
240
MC14052B
5.0
10
15
325
130
90
650
260
180
ns
ns
MC14053B
5.0
10
15
300
120
80
600
240
160
Second Harmonic Distortion
—
10
0.07
—
%
(R = 10KΩ, f = 1 kHz) V = 5 V
L
in
PP
Bandwidth (Figure 7)
BW
10
17
—
MHz
(R = 1 kΩ, V = 1/2 (V –V ) p–p, C = 50pF
L
in DD EE
L
20 Log (V /V ) = – 3 dB)
out in
Off Channel Feedthrough Attenuation (Figure 7)
= 1KΩ, V = 1/2 (V – V ) p–p
—
10
– 50
—
dB
R
L
in DD EE
f
f
f
= 4.5 MHz — MC14051B
= 30 MHz — MC14052B
= 55 MHz — MC14053B
in
in
in
Channel Separation (Figure 8)
—
—
10
10
– 50
75
—
—
dB
(R = 1 kΩ, V = 1/2 (V –V ) p–p,
L
in DD EE
f
in
= 3.0 MHz
Crosstalk, Control Input to Common O/I (Figure 9)
mV
(R = 1 kΩ, R = 10 kΩ
1
L
Control t
= t
= 20 ns, Inhibit = V )
TLH THL
SS
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautionsmust be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, V and V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V , V , or V ). Unused outputs
must be left open.
should be constrained to the range V
≤ (V or V ) ≤ V .
in out
SS
in out DD
SS EE
DD
MOTOROLA CMOS LOGIC DATA
MC14051B MC14052B MC14053B
3
V
DD
V
V
DD
DD
IN/OUT
OUT/IN
V
EE
V
DD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
CONTROL
V
EE
Figure 1. Switch Circuit Schematic
16
V
TRUTH TABLE
DD
Control Inputs
Select
INH
A 11
B 10
6
BINARY TO 1–OF–8
DECODER WITH
INHIBIT
LEVEL
CONVERTER
ON Switches
Inhibit
C*
B
A
MC14051B MC14052B
MC14053B
C
9
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
X0
X1
X2
X3
Y0
Y1
Y2
Y3
X0
X1
X2
X3
Z0 Y0 X0
Z0 Y0 X1
Z0 Y1 X0
Z0 Y1 X1
8
V
7
V
SS
EE
X0 13
X1 14
X2 15
X3 12
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
X4
X5
X6
X7
Z1 Y0 X0
Z1 Y0 X1
Z1 Y1 X0
Z1 Y1 X1
3 X
X4
X5
1
5
X6
X7
2
4
1
x
x
x
None
None
None
* Not applicable for MC14052
x = Don’t Care
Figure 2. MC14051B Functional Diagram
16
V
DD
16
V
DD
INH
6
BINARY TO 1–OF–4
DECODER WITH
INHIBIT
LEVEL
CONVERTER
INH
A 11
B 10
6
A 10
BINARY TO 1–OF–2
DECODER WITH
INHIBIT
LEVEL
CONVERTER
B
9
C
9
8
V
7
V
EE
SS
X0 12
X1 14
X2 15
X3 11
8
V
7
V
EE
SS
13 X
X0 12
X1 13
14 X
15 Y
Y0
Y1
Y2
Y3
1
5
2
4
Y0
Y1
Z0
Z1
2
1
5
3
3
Y
4
Z
Figure 3. MC14052B Functional Diagram
Figure 4. MC14053B Functional Diagram
MC14051B MC14052B MC14053B
4
MOTOROLA CMOS LOGIC DATA
TEST CIRCUITS
ON SWITCH
LOAD
CONTROL
SECTION
OF IC
A
B
C
PULSE
GENERATOR
V
out
V
C
INH
R
L
L
SOURCE
V
V
V
V
DD
EE
EE DD
Figure 5. ∆V Across Switch
Figure 6. Propagation Delay Times,
Control and Inhibit to Output
A, B, and C inputs used to turn ON or OFF
the switch under test.
R
L
A
B
A
C
B
C
ON
V
out
INH
C
L
= 50 pF
R
V
L
SS
OFF
INH
V
out
= 50 pF
V
R
L
C
in
L
V
– V
2
DD
EE
V
– V
2
DD
EE
V
in
Figure 7. Bandwidth and Off–Channel
Feedthrough Attenuation
Figure 8. Channel Separation
(Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST
V
DD
V
EE
A
B
C
CONTROL
SECTION
OF IC
OTHER
CHANNEL(S)
V
V
V
out
EE
R
INH
C = 50 pF
L
DD
L
R1
V
V
EE
COMMON
DD
Figure 9. Crosstalk, Control Input to
Common O/I
Figure 10. Off Channel Leakage
NOTE: See also Figures 7 and 8 on Page 6–51.
MOTOROLA CMOS LOGIC DATA
MC14051B MC14052B MC14053B
5
V
DD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 k
RANGE
Ω
X–Y
V
DD
PLOTTER
V
= V
SS
EE
Figure 11. Channel Resistance (R ) Test Circuit
ON
TYPICAL RESISTANCE CHARACTERISTICS
350
300
350
300
250
200
150
250
200
150
100
T
= 125°C
A
T
= 125°C
A
100
25°C
25°C
–55
°C
–55
°
C
50
0
50
0
–10 –8.0 –6.0 –4.0 –2.0
0
0.2
4.0
6.0
8.0
10
–10 –8.0 –6.0 –4.0 –2.0
0
0.2
4.0
6.0
8.0
10
V
, INPUT VOLTAGE (VOLTS)
V , INPUT VOLTAGE (VOLTS)
in
in
Figure 12. V
DD
= 7.5 V, V
EE
= – 7.5 V
Figure 13. V
DD
= 5.0 V, V = – 5.0 V
EE
350
300
700
600
T
= 25°C
A
250
200
150
100
500
400
300
200
V
= 2.5 V
DD
T
= 125
°C
5.0 V
A
7.5 V
25
°C
50
0
100
0
–55
°
C
–10 –8.0 –6.0 –4.0 –2.0
0
0.2
4.0
6.0
8.0
10
–10 –8.0 –6.0 –4.0 –2.0
0
0.2
4.0
6.0
8.0
10
V
, INPUT VOLTAGE (VOLTS)
V
, INPUT VOLTAGE (VOLTS)
in
in
Figure 15. Comparison at 25°C, V
= –V
EE
Figure 14. V
DD
= 2.5 V, V = – 2.5 V
EE
DD
PIN ASSIGMENT
MC14052B
MC14051B
MC14053B
X4
X6
1
2
16
15
V
Y0
Y2
1
2
16
15
V
DD
Y1
Y0
1
2
16
15
V
Y
X
DD
X2
DD
X2
X
X7
3
4
5
6
7
8
14
13
12
11
10
9
X1
X0
X3
A
Y
Y3
3
4
5
6
7
8
14
13
12
11
10
9
X1
X
Z1
Z
3
4
5
6
7
8
14
13
12
11
10
9
X1
X0
A
X5
Y1
X0
X3
A
Z0
INH
INH
INH
V
B
V
V
B
EE
EE
EE
V
C
V
B
V
C
SS
SS
SS
MC14051B MC14052B MC14053B
6
MOTOROLA CMOS LOGIC DATA
APPLICATIONS INFORMATION
Figure A illustrates use of the on–chip level converter de-
tailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control sig-
above V
and/or below V
are anticipated on the analog
EE
DD
channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.
nal is used to directly control a 9 V
analog signal.
p–p
The digital control logic levels are determined by V
and
volt-
DD
SS
V
. The V
voltage is the logic high voltage; the V
SS
age is logic low. For the example, V
DD
= + 5 V = logic high at
The absolute maximum potential difference between V
DD
= GND = 0 V = logic low.
DD
is 18.0 V. Most parameters are specified up to 15 V
the control inputs; V
and V
SS
The maximum analog signal level is determined by V
EE
which is the recommended maximum difference between
and V
DD
voltage determines the maximum recom-
and V . The V
mended peak above V . The V
maximum swing below V . For the example, V
5 V maximum swing above V ; V
V
.
EE
EE
DD
DD
Balanced supplies are not required. However, V
voltage determines the
must
SS
EE
SS
= + 10 V,
– V
=
be greater than or equal to V . For example, V
SS
DD
SS
EE
DD
– 3 V is acceptable. See the Table
– V
= 5 V maximum
V
= + 5 V, and V
EE
SS SS
EE
SS
below.
swing below V . The example shows a ± 4.5V signal which
SS
allows a 1/2 volt margin at each peak. If voltage transients
+5 V
–5 V
V
V
V
EE
DD
SS
+
4.5 V
9 V
p–p
SWITCH
I/O
9 V
p–p
ANALOG SIGNAL
COMMON
O/I
GND
MC14051B
MC14052B
MC14053B
ANALOG SIGNAL
+5 V
–
4.5 V
EXTERNAL
CMOS
DIGITAL
0–TO–5 V DIGITAL
CONTROL SIGNALS
INHIBIT,
A, B, C
CIRCUITRY
Figure A. Application Example
V
DD
V
DD
D
D
X
X
X
ANALOG
I/O
COMMON
O/I
D
D
X
V
EE
V
EE
Figure B. External Germanium or Schottky Clipping Diodes
POSSIBLE SUPPLY CONNECTIONS
Control Inputs
Logic High/Logic Low
In Volts
V
V
V
EE
In Volts
Maximum Analog Signal Range
In Volts
DD
SS
In Volts
In Volts
+ 8
0
0
– 8
+ 8/0
+ 5/0
+ 8 to – 8 = 16 V
p–p
+ 5
– 12
0
+ 5 to – 12 = 17 V
p–p
+ 5
0
+ 5/0
+ 5 to 0 = 5 V
p–p
+ 5
0
– 5
+ 5/0
+ 5 to – 5 = 10 V
p–p
+ 10
+ 5
– 5
+ 10/ + 5
+ 10 to – 5 = 15 V
p–p
MOTOROLA CMOS LOGIC DATA
MC14051B MC14052B MC14053B
7
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J 16 PL
G
0.300 BSC
7.62 BSC
M
S
0.25 (0.010)
T B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MC14051B MC14052B MC14053B
8
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
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