MB084CJ00TASN60 [MOTOROLA]
EDO DRAM Module, 4MX8, 60ns, MOS, SIMM-30;
| 型号： | MB084CJ00TASN60 |
| 厂家： | 
MOTOROLA |
| 描述： | EDO DRAM Module, 4MX8, 60ns, MOS, SIMM-30 动态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by 5VEDOU8S/D
SEMICONDUCTOR
TECHNICAL DATA
4M x 8
5 V, EDO, Unbuffered
MM
4 Megabyte
•
•
•
•
•
JEDEC–Standard 30–Lead Single–In–Line Memory Module (SIMM)
Single 5 V Power Supply, TTL–Compatible Inputs and Outputs
Extended Data Out (EDO)
RAS–Only Refresh, CAS Before RAS Refresh, Hidden Refresh
4MB: 2048 Cycle Refresh: 32 ms (Max)
PART NUMBERS (See Last Page for Definitions)
Organization
60
4M x 8
MB084CJ00TASN60
MB084CT00TASN60
TSOP 30–LEAD SIMM
CASE 839D–01
KEY TIMING PARAMETERS
Speed
t
(ns)
t
(ns)
t
(ns)
t
(ns)
t
(ns)
RC
RAC
CAC
AA
EPC
BACK VIEW
FRONT VIEW
60
104
60
17
30
25
ADDITIONAL PARAMETERS
1
Standby Power
Dissipation (mW) (Max)
Active Power
Dissipation
(mW) (Max)
Configuration
Speed
TTL
CMOS
4MB
60
1210
22
11
30
2/25/97
Motorola, Inc. 1997
4M x 8 5 V EDO U
PIN ASSIGNMENTS
Pin
1
Name
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Name
DQ4
A8
V
CC
2
CAS
DQ0
A0
3
A9
4
A10
DQ5
W
5
A1
6
DQ1
A2
7
V
SS
8
A3
DQ6
NC
9
V
SS
PIN NAMES
10
11
12
13
14
15
DQ2
A4
DQ7
NC
A0 – A10 . . . . . . . . . . . . . . . . . Address Inputs
DQ0 – DQ7 . . . . . . . . . . . . . Data Input/Output
CAS . . . . . . . . . . . . . Column Address Strobe
RAS . . . . . . . . . . . . . . . . Row Address Strobe
W . . . . . . . . . . . . . . . . . . . . . . Read/Write Input
A5
RAS
NC
DQ3
A6
V
V
. . . . . . . . . . . . . . . . . . . . . . Power (+ 5 V)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
CC
SS
NC
NC . . . . . . . . . . . . . . . . . . . . . . No Connection
A7
V
CC
FUNCTIONAL BLOCK DIAGRAM
A0 – A10
A0 – A10
W
W
DQ0 – DQ3
DQ
CAS
CAS
RAS
RAS
V
V
SS
CC
A0 – A10
W
DQ4 – DQ7
DQ
CAS
RAS
V
V
SS
CC
V
CC
V
SS
5VEDOU8S
2
MOTOROLA DRAM
4M x 8 5 V EDO
U
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol
Power Supply Voltage
Voltage Relative to V
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
Value
Unit
V
V
– 0.5 to + 7
– 0.5 to + 7
CC
V , V
in out
V
SS
(For Any Pin Except V
)
CC
Data Output Current per DQ Pin
Power Dissipation
I
50
1.8
mA
W
out
P
D
Operating Temperature Range
Storage Temperature Range
T
0 to + 70
– 55 to + 150
°C
°C
A
T
stg
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5 V ± 10% V, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS (All Voltages Referenced to V
)
SS
Parameter
Symbol
Min
4.5
Typ
5
Max
5.5
0
Unit
Supply Voltage (Operating Voltage Range)
V
CC
V
V
SS
0
0
Logic High Voltage, All Inputs
Logic Low Voltage, All Inputs
V
2.4
—
—
—
—
—
—
V
CC
+ 0.5
V
V
IH
V
– 0.5*
– 20
– 10
2.4
0.8
20
10
—
IL
Input Leakage Current (V
≤ V ≤ V
in
)
I
µA
µA
V
SS
CC
lkg(I)
Output Leakage Current (CAS at Logic 1, V
SS
≤ V
out
≤ V
)
I
lkg(O)
CC
Output High Voltage (I
= – 5 mA)
V
OH
OH
Output Low Voltage (I
= 4.2 mA)
V
OL
—
0.4
V
OL
* – 2.0 V at pulse widths ≤ 20 ns.
DC CHARACTERISTICS AND SUPPLY CURRENTS (All Voltages Referenced to V
)
SS
4MB
Characteristic
Symbol
Unit
Notes
Min
—
Max
220
4
V
V
V
Power Supply Current
(t
= t
Min) 60
I
I
I
mA
mA
mA
1, 2
CC
CC
CC
RC RC
CC1
Power Supply Current (Standby) (RAS = CAS = V
)
—
IH
CC2
CC3
Power Supply Current
(t
= t
Min) 60
Min) 60
—
220
1, 2
1, 2
RC RC
During RAS Only Refresh Cycles
V
Power Supply Current
CC
During EDO Cycle
(t
= t
I
—
190
mA
EPC EPC
CC4
V
V
Power Supply Current (Standby) (RAS = CAS = V
Power Supply Current
– 0.2 V)
I
I
—
—
2
mA
mA
CC
CC
CC5
(t = t
RC RC
Min) 60
220
1
CC
CC6
During CAS Before RAS Refresh Cycle
NOTES:
1. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
2. Column address can be changed once or less while RAS = V and CAS = V
.
IL
IH
5VEDOU8S
3
MOTOROLA DRAM
4M x 8 5 V EDO U
CAPACITANCE (f = 1.0 MHz, T = 25°C, V
= 5 V, Periodically Sampled Rather Than 100% Tested)
A
CC
Input Capacitance
Symbol
Max
20
Unit
pF
Addresses
WE
C
C
C
C
in
in
in
in
24
pF
RAS
24
pF
CAS
24
pF
DQ
C
17
pF
out
NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I ∆t/∆V.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5 V ± 10%, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
ALL DEVICES: READ, WRITE, AND READ–WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbol
60
Parameter
Random Read or Write Cycle Time
Unit
ns
Notes
Std
Alt
Min
104
—
Max
—
t
t
5
RELREL
RC
Access Time from RAS
t
t
t
60
ns
6, 7,
11, 12
RELQV
RAC
Access Time from CAS
t
—
—
17
30
ns
ns
6, 8,
11
CELQV
CAC
Access Time from Column Address
t
t
6, 9,
12
AVQV
AA
Access Time from Precharge CAS
CAS to Output in Low–Z
Output Buffer and Turn–Off Delay
Transition Time (Rise and Fall)
RAS Precharge Time
RAS Pulse Width
t
t
t
—
0
35
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
CEHQV
CPA
t
t
CELQX
CLZ
t
0
15
10, 16
1
CEHQZ
OFF
t
T
t
T
1
50
t
t
40
60
10
40
10
14
12
—
REHREL
RELREH
CELREH
RELCEH
CELCEH
RP
t
t
t
t
t
10 k
—
RAS
RSH
CSH
RAS Hold Time
t
t
CAS Hold Time
—
CAS Pulse Width
t
10 k
45
CAS
RAS to CAS Delay Time
RAS to Column Address Delay Time
NOTES:
t
t
11
12
RELCEL
RCD
t
t
30
RELAV
RAD
(continued)
1. V (min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V
IH IL IH
.
IL
2. An initial pause of 200 µs is required after power–up followed by 8 RAS cycles before proper device operation is guaranteed. If using the
internal refresh counter, a minimum of 8 CAS before RAS refresh cycles, instead of 8 RAS only refresh cyces are required.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between V and V (or between V and V ) in a monotonic manner.
IH
IL
IL
IH
4. AC measurements t = 5.0 ns.
T
5. The specification for t
(min), t
(min), and t
(min) is used only to indicate cycle time at which proper operation over the full
RC
RWC
EPC
temperature range (0°C ≤ T ≤ 70°C) is ensured.
6. Measured with a current load equivalent to 2 TTL (– 200 µA, + 4 mA) loads and 100 pF with the data output trip points set at V
A
= 2.0 V
OH
and V
= 0.8 V.
OL
7. Assumes that t
8. Assumes that t
9. Assumes that t
≤ t
(max).
(max).
(max).
RCD RCD
≥ t
RCD RCD
≥ t
RAD RAD
10. t
(max), t
(max), and t
(max) define the time at which the output achieves the open circuit condition and is not referenced
OFF
REZ
WEZ
to output voltage levels.
11. Operation within the t
(max) limit ensures that t
(max) limit, then access time is controlled exclusively by t .
RCD
(max) limit ensures that t
(max) can be met. t
RCD
(max) is specified as a reference point only; if t
RCD
RAC
RCD
RAD
is greater than the specified t
CAC
12. Operation within the t
(max) can be met. t (max) is specified as a reference point only; if t
RAD
RAD
is greater than the specified t
RAC
(max), then access time is controlled exclusively by t
.
RAD
AA
5VEDOU8S
MOTOROLA DRAM
4
4M x 8 5 V EDO
U
ALL DEVICES: READ, WRITE, AND READ–WRITE CYCLES (continued)
Symbol
60
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Std
Alt
Min
5
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32
—
—
—
—
—
—
100 k
—
—
—
15
15
—
CAS to RAS Precharge Time
CAS Precharge Time
t
t
t
CEHREL
CRP
t
10
0
CEHCEL
CP
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
t
t
AVREL
ASR
RAH
t
t
10
0
RELAX
t
t
AVCEL
CELAX
AVREH
ASC
CAH
t
t
t
10
30
0
Column Address to RAS Lead Time
Read Command Setup Time
t
t
RAL
RCS
RCH
RRH
t
WHCEL
CEHWX
REHWX
Read Command Hold Time Referenced to CAS
Read Command Hold Time Referenced to RAS
Write Command Hold Time Referenced to CAS
Write Command Pulse Width
t
t
t
t
0
13
13
0
t
t
10
10
10
10
0
CELWH
WCH
t
t
WP
WLWH
WLREH
WLCEH
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data In Setup Time
t
t
t
RWL
CWL
t
t
t
14
14
DVCEL
DS
Data In Hold Time
t
t
10
—
0
CELDX
DH
Refresh Period
t
t
RFSH
RVRV
Write Command Setup Time
t
t
15
WLCEL
WCS
CAS Setup Time for CAS Before RAS Refresh
CAS Hold Time for CAS Before RAS Refresh
RAS Precharge to CAS Active Time
CAS Precharge Time for CAS Before RAS Counter Test
RAS Hold Time from CAS Precharge (EDO)
RAS Pulse Width (EDO)
t
t
5
CELCEL
RELCEH
REHCEL
CEHCEL
CSR
t
t
t
t
10
5
CHR
t
RPC
t
20
35
60
60
25
5
CPT
t
t
RHCP
CEHREH
t
t
RASP
RELREH
RAS to Next CAS Delay (EDO)
EDO Cycle Time
t
t
RNCD
RELCEL
CELCEL
t
t
EPC
Output Data Hold Time
t
t
CELQZ
COH
Output Buffer Turn–Off Delay from RAS
Output Buffer Turn–Off Delay from W
t
t
0
10, 16
10
REHQZ
REZ
WEZ
WED
t
t
0
WLQZ
WLDV
W to Data Delay
NOTES:
t
t
15
10. Either t
RRH
or t
must be satisfied for a read cycle.
RCH
11. These parameters are referenced to CAS leading edge in write cycles.
12. t , t , t , t , and t are not restrictive operating parameters. They are included in the data sheet as electrical
WCS RWD CWD AWD
characteristics only; if t ≥ t
CPWD
(min), the cycle is a write cycle and the data out pin will remainopencircuit(highimpedance)throughout
WCS WCS
the entire cycle. If this condition is not satisfied, the condition of the data out (at access time) is indeterminate.
13. If RAS goes high before CAS goes high, the open circuit condition is controlled by CAS going high (t ). If CAS goes high before RAS
OFF
goes high, the open circuit condition is controlled by RAS going high (t
14. To avoid bus contention and potential damage to the module, RAS0 and RAS1 may not be active low simultaneously. Similarly, RAS2
and RAS3 may not be simultaneously active low.
).
REZ
5VEDOU8S
5
MOTOROLA DRAM
4M x 8 5 V EDO U
TIMING DIAGRAMS
READ CYCLE
t
RC
t
RP
V
IH
t
RAS
RAS
V
IL
t
CSH
t
t
t
t
CRP
RSH
CAS
CRP
RCD
t
V
V
IH
IL
CAS
t
RAD
ASC
t
RAL
t
t
t
ASR
t
CAH
RAH
ROW
V
V
IH
IL
COLUMN
ADDRESS
ADDRESSES
ADDRESS
t
RCH
t
RRH
t
RCS
V
V
IH
IL
W
t
AA
t
t
CAC
OFF
t
RAC
V
OH
DQ
HIGH–Z
VALID DATA OUT
V
OL
t
CLZ
WRITE CYCLE
t
RC
t
RP
V
V
t
IH
IL
RAS
RAS
t
CSH
t
t
t
t
CRP
RCD
RSH
CAS
CRP
t
V
V
IH
IL
CAS
t
RAH
t
RAL
t
t
t
ASP
ASC
CAH
V
V
IH
IL
ROW
ADDRESS
COLUMN
ADDRESS
ADDRESSES
t
RAD
t
CWL
t
t
WCS
WCH
t
WP
V
V
IH
IL
W
t
RWL
t
t
DS
DH
VALID DATA IN
V
V
IH
IL
HIGH–Z
DQ
5VEDOU8S
6
MOTOROLA DRAM
4M x 8 5 V EDO
U
EXTENDED DATA OUT READ CYCLE
t
RP
t
RASP
V
IH
RAS
CAS
t
RNCD
V
IL
t
t
t
EPC
EPC
RSH
RHCP
t
t
RCD
t
t
t
CRP
CP
CRP
t
t
t
CAS
CAS
CAS
V
IH
t
RAH
V
IL
t
RAD
t
CP
t
CSH
t
RAL
t
ASC
t
t
ASC
ASC
t
t
CAH
t
t
CAH
CAH
ASR
V
IH
ROW
COLUMN 1
COLUMN 2
COLUMN N
ADDRESSES
V
IL
t
RCH
t
RCS
V
IH
W
V
IL
t
t
t
t
RRH
AA
AA
AA
t
t
CPA
CPA
t
t
t
t
t
CAC
RAC
CAC
REZ
t
CAC
OFF
t
t
COH
CLZ
V
OH
DQ
D
1
D
2
D
N
out
out
out
V
OL
EXTENDED DATA OUT WRITE CYCLE
t
RP
t
RASP
V
IH
RAS
CAS
V
IL
t
t
t
EPC
EPC
RSH
t
t
t
CP
RCD
CP
t
CRP
t
t
t
t
CAS
CRP
CAS
CAS
V
IH
t
RAH
V
IL
t
t
RAL
CSH
t
t
t
ASC
ASC
ASC
t
t
t
CAH
CAH
CAH
t
ASR
V
IH
ROW
COLUMN 1
COLUMN 2
COLUMN N
ADDRESSES
V
IL
t
t
t
CWL
CWL
CWL
t
RAD
t
RWL
t
t
WCS
WCS
t
WCS
t
t
WCH
WCH
t
WCH
t
t
t
WP
WP
WP
V
IH
W
V
IL
t
t
t
DH
DH
DH
t
t
t
DS
DS
DS
V
OH
DQ
D
1
D
2
D
N
in
in
in
V
OL
5VEDOU8S
7
MOTOROLA DRAM
4M x 8 5 V EDO U
EXTENDED DATA OUT READ WRITE MIXED CYCLE
t
RASP
t
RP
t
V
CSH
IH
RAS
V
IL
t
t
t
EPC
t
t
CRP
EPC
EPC
CRP
t
t
t
t
CP
CP
CP
CP
t
RCD
t
t
t
t
CAS
t
CAS
CAS
CAS
CAS
V
IH
CAS
t
V
RAD
RAH
IL
t
t
t
ASC
t
t
ASC
ASC
ASC
t
t
CAH
ASR
t
t
t
CAH
t
CAH
t
CAH
CAH
ASC
V
IH
ADDRESSES
COL. 1
COL. 2
COL. 3
t
COL. 4
COL. N
ROW
ROW
V
IL
t
RCS
RCH
V
IH
W
V
IL
t
WCS
t
WCH
t
t
t
CPA
CPA
CPA
t
DH
t
t
t
t
CAC
CAC
CAC
CAC
t
DS
t
AA
t
t
AA
t
AA
AA
t
V
IH
t
RAC
CLZ
D
4
t
in
V
IL
t
t
t
WED
REZ
COH
COH
DQ
t
t
CLZ
WEZ
V
OH
D
1
D
2
D
out
3
D
N
out
out
out
V
OL
5VEDOU8S
8
MOTOROLA DRAM
4M x 8 5 V EDO
U
RAS ONLY REFRESH CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
CAS
t
t
RPC
CRP
V
V
IH
IL
t
RAH
t
ASR
V
V
ROW
ADDRESS
IH
IL
ADDRESSES
NOTE: W = H or L.
DQ = Open.
CAS BEFORE RAS REFRESH CYCLE
t
RC
t
t
RAS
RP
V
IH
RAS
t
CSR
RPC
V
IL
t
t
CP
t
CHR
t
V
IH
CAS
V
IL
t
WRP
WRH
V
IH
W
V
IL
t
OFF
V
OH
DQ
HIGH–Z
V
OL
NOTE: Addresses = H or L.
W must be as shown to avoid switching into component test mode.
5VEDOU8S
9
MOTOROLA DRAM
4M x 8 5 V EDO U
HIDDEN REFRESH CYCLE (READ)
t
t
RC
RC
t
t
RP
t
RAS
RP
t
RAS
V
IH
RAS
V
IL
t
t
t
RCD
RSH
CHR
t
CRP
V
IH
CAS
t
CRP
t
CAH
V
t
IL
RAD
t
ASC
t
ASR
V
IH
COLUMN
ADDRESSES
ROW
V
IL
t
RAH
t
t
RRH
RCS
V
IH
W
V
IL
t
AA
t
t
REZ
CAC
t
OFF
t
CLZ
V
OH
DQ
DATA OUT
V
OL
t
RAC
5VEDOU8S
10
MOTOROLA DRAM
4M x 8 5 V EDO
U
HIDDEN REFRESH CYCLE (WRITE)
t
t
RC
RC
t
t
t
RP
RAS
RP
t
RAS
V
V
IH
RAS
CAS
V
IL
t
t
t
t
CRP
t
RCD
RSH
CHR
CRP
IH
V
IL
t
RAD
t
t
RAH
CAH
t
t
ASC
ASR
V
IH
COLUMN
ADDRESSES
ROW
V
IL
t
WCH
t
WCS
t
WP
V
IH
W
V
IL
t
t
DH
DS
V
OH
DQ
DATA IN
V
OL
CAS BEFORE RAS REFRESH COUNTER TEST READ CYCLE
t
RP
t
RAS
V
IH
RAS
CAS
V
IL
t
CHR
t
t
t
t
CRP
CSR
CPT
RSH
CAS
t
V
IH
V
IL
t
RAL
t
CAH
t
ASC
V
IH
ADDRESSES
COLUMN
V
IL
t
t
RRH
t
RCS
RCH
V
IH
W
V
IL
t
t
t
CAC
OFF
t
AA
REZ
V
OH
DATA OUT
DQ
V
OL
t
CLZ
5VEDOU8S
11
MOTOROLA DRAM
4M x 8 5 V EDO U
CAS BEFORE RAS REFRESH COUNTER TEST WRITE CYCLE
t
RP
t
RAS
V
V
V
IH
RAS
CAS
V
IL
t
CHR
t
t
t
t
CRP
CSR
RSH
CAS
CPT
t
IH
V
IL
t
RAL
t
CAH
t
ASC
IH
ADDRESSES
COLUMN
V
IL
t
RWL
t
CWL
t
WCS
t
WCH
V
IH
W
V
IL
t
DH
t
DS
V
IH
DATA IN
DQ
V
IL
5VEDOU8S
12
MOTOROLA DRAM
4M x 8 5 V EDO
U
DEVICE INITIALIZATION
WRITE CYCLE
The user can write to the DRAM with either a write or an
EDO mode write cycle. The write mode is discussed here,
while EDO mode write operations are covered in a separate
section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
On power–up, an initial pause of 200 µs is required for the
internal substrate generator to establish the correct bias volt-
age. This must be followed by a minimum of eight active
cycles of the row address strobe (clock) to initialize all dy-
namic nodes within the module. During an extended inactive
state (greater than 32 ms), a wake up sequence of eight ac-
tive cycles is necessary to ensure proper operation.
(V ). Write mode is distinguished by the active transition of
IL
W, with respect to CAS. Minimum active time t
RAS
apply to write mode, as in
and t
, and precharge time t
CAS
RP
ADDRESSING THE RAM
the read mode.
A write cycle is characterized by W active transition at
minimum time t before CAS active transition. Data in
The address pins on the device are time multiplexed at the
beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two
separate address fields. A total of 22 address bits, 11 rows
and 11 columns, will decode one of the word locations in the
device. RAS active transition is followed by CAS active tran-
WCS
(DQ) is referenced to CAS in a write cycle. RAS and CAS
clocks must stay active for t and t , respec-
RWL
CWL
tively, after the start of the write operation to complete the
cycle.
sition (active = V , t
minimum) for all read or write
EDO MODE CYCLES
IL RCD
cycles. The delay between RAS and CAS active transitions,
referred to as the multiplex window, gives a system design-
er flexibility in setting up the external addresses into the
RAM.
The external CAS signal is ignored until an internal RAS
signal is available. This “gate” feature on the external CAS
clock enables the internal CAS line as soon as the row
EDO mode allows fast successive data operations at all
column locations on a selected row of the module. Read ac-
cess time in EDO mode (t
) is typically half the regular
CAC
. EDO mode operation consists
RAS clock access time, t
RAC
of keeping RAS active while toggling CAS between V and
IH
. The row is latched by RAS active transition, while each
V
IL
CAS active transition allows selection of a new column loca-
tion on the row.
An EDO mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing require-
ments for the first cycle are met, CAS transitions to inactive
address hold time (t
) specification is met (and defines
RAH
minimum). The multiplex window can be used to absorb
t
RCD
skew delays in switching the address bus from row to column
addresses and in generating the CAS clock.
There are three other variations in addressing the module:
RAS–only refresh cycle, CAS before RAS refresh cycle,
and page mode. All three are discussed in separate sections
that follow.
for minimum t , while RAS remains low (V ). The second
CP IL
CAS active transition while RAS is low initiates the first EDO
mode cycle (t ). Either a read or write operation can be
EPC
performed in an EDO mode cycle, subject to the same con-
ditions as in normal operation (previously described). These
operations can be intermixed in consecutive EDO mode
cycles and performed in any order. The maximum number of
READ CYCLE
The DRAM may be read with either a “normal” random
read cycle or an EDO read cycle. The normal read cycle is
outlined here, while the EDO mode cycle is discussed in a
separate section.
consecutive EDO mode cycles is limited by t
mode operation is ended when RAS transitions to inactive,
coincident with or following CAS inactive transition.
. EDO
RASP
The normal read cycle begins as described in ADDRESS-
ING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (W) input level must be
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to
degrade with time and temperature. Each bit must be peri-
odically refreshed (recharged) to maintain the correct bit
high (V ), t
to enable read mode.
(minimum) before the CAS active transition,
IH RCS
Both the RAS and CAS clocks trigger a sequence of
events that are controlled by several delayed internal clocks.
The internal clocks are linked in such a manner that the read
access time of the device is independent of the address mul-
tiplex window. CAS controls read access time: CAS must be
state. Bits require refresh every t
.
RFSH
This is accomplished by cycling through the row
addresses in sequence within the specified refresh time. All
the bits on a row are refreshed simultaneously when the row
is addressed. Distributed refresh implies a row refresh every
15.6 µs. Burst refresh, a refresh of all rows consecutively,
active before or at t
maximum to guarantee valid data
RCD
(access time from RAS active transition).
out (DQ) at t
RAC
maximum is exceeded, read access time is
must be performed every t
.
RFSH
If the t
RCD
determined by the CAS clock active transition (t
A normal read or write operation to the RAM will refresh all
the bits associated with the particular row decodes. Three
other methods of refresh, RAS–only refresh, CAS before
RAS refresh, and hidden refresh are available on this
device for greater system flexibility.
).
CAC
The RAS and CAS clocks must remain active for a mini-
mum time of t and t , respectively, to complete the
RAS
read cycle. W must remain high throughout the cycle, and for
time t or t after RAS or CAS inactive transition,
CAS
RRH
RCH
respectively, to maintain the data at that bit location. Once
RAS transitions to inactive, it must remain inactive for a mini-
RAS–Only Refresh
mum time of t
the next active cycle.
to precharge the internal device circuitry for
RAS–only refresh consists of RAS transition to active,
latching the row address to be refreshed, while CAS remains
RP
5VEDOU8S
13
MOTOROLA DRAM
4M x 8 5 V EDO U
high (V ) throughout the cycle. An external counter is
IH
CAS BEFORE RAS REFRESH COUNTER TEST
employed to ensure that all rows are refreshed within the
specified limit.
The internal refresh counter of the device can be tested
with a CAS before RAS refresh counter test. This refresh
counter test is performed with read and write operations.
During this test, the internal refresh counter generates the
row address, while the external address input supplies the
column address. The entire array is refreshed after complet-
ing one cycle for every column, as indicated by the check
data written in each row. See CAS before RAS refresh
counter test cycle timing diagram.
CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS
active before RAS. This clock order activates an internal
refresh counter that generates the row address to be
refreshed. External address lines are ignored during the au-
tomatic refresh cycle. The output buffer remains at the same
state it was in during the previous cycle (hidden refresh).
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:
1. Write 0s into all memory cells (normal write mode).
2. Select a column address, and read 0 out of the cell by
performing CAS before RAS refresh counter test,
read cycle. Repeat this operation for every column.
3. Select a column address, and write 1 into the cell by per-
forming CAS before RAS refresh counter test, write
cycle. Repeat this operation for every column.
4. Read 1s (normal read mode), which were written at step
three.
Hidden Refresh
Hidden refresh allows refresh cycles to occur while main-
taining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for
t
and back to active, starts the hidden refresh. This is
RP
essentially the execution of a CAS before RAS refresh from a
cycle in progress (see Figure 1). W is subject to the same
conditions with respect to RAS active transition (to prevent
test mode cycle) as in CAS before RAS refresh.
5. Repeat steps one through four using complement data.
CAS BEFORE RAS
REFRESH CYCLE
CAS BEFORE RAS
REFRESH CYCLE
MEMORY CYCLE
RAS
CAS
VALID DATA OUT
DQ
HIGH–Z
Figure 1. Hidden Refresh Cycle
5VEDOU8S
14
MOTOROLA DRAM
4M x 8 5 V EDO
U
PACKAGE DIMENSIONS
4M x 8 (4MB)
30–LEAD SIMM
CASE 839A–01
-Y-
R
NOTES:
Q
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TABS TO BE ELECTRICALLY CONNECTED BOTH
SIDES OF CARD.
4. DIMENSION E INCLUDES PLATING AND/OR
METALIZATION.
5. CONTACT ZONE MUST BE FREE OF HOLES.
0.08 (0.003)
A
B
COMPONENT AREA
V
-Z-
N
E
G
U
P
P
INCHES
MILLIMETERS
W
DIM
A
B
C
D
E
MIN
MAX
3.505
0.555
0.208
0.075
0.053
0.055
MIN
88.78
13.85
–––
MAX
89.02
14.09
5.28
C
M
3.495
0.545
–––
0.065
0.047
0.045
DETAIL X
1.66
1.20
1.15
1.90
1.34
1.39
S
0.25 (0.010)
Z Y
-D-
F
G
H
L
M
N
P
Q
R
S
U
V
0.100 BSC
2.54 BSC
S
–––
0.080
0.075
0.128
0.045
0.123
0.245
0.005
3.229
0.395
0.100
0.010
–––
0.085
0.138
–––
0.127
0.255
0.015
3.239
0.405
–––
–––
2.04
1.91
3.26
1.15
3.13
6.23
0.13
82.02
10.04
2.54
0.25
–––
2.15
3.50
–––
3.22
6.47
0.38
82.27
10.28
–––
S
S
F
0.25 (0.010)
D
NOTE 5
F
L
S
H
DETAIL X
60 PL
W
TSOP 30–LEAD SIMM
CASE 839D–01
NOTES:
Y
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. PADS TO BE ELECTRICALLY CONNECTED BOTH
SIDES OF CARD.
4. DIMENSION E INCLUDES PLATING AND/OR
METALIZATION.
5. CONTACT ZONE MUST BE FREE OF HOLES.
Q
0.003 (0.08)
A
B
Z
COMPONENT AREA
V
R
N
C
E
G
U
P
P
INCHES
MILLIMETERS
W
DIM
A
B
C
D
E
MIN
MAX
3.505
0.605
0.110
0.075
0.053
0.055
MIN
88.78
15.11
–––
MAX
89.02
15.37
2.79
M
3.495
0.595
–––
0.065
0.047
0.045
SEE DETAIL J
1.66
1.20
1.15
1.90
1.34
1.39
D
F
0.010 (0.25)
Z
Y
G
H
L
M
N
P
Q
R
S
U
V
0.100 BSC
2.54 BSC
F
0.010 (0.25)
Z Y
–––
0.080
0.075
0.128
0.045
0.123
0.245
0.005
3.229
0.395
0.100
0.010
–––
0.085
0.138
–––
0.127
0.255
0.015
3.239
0.405
–––
–––
2.04
1.91
3.26
1.15
3.13
6.23
0.13
82.02
10.04
2.54
0.254
–––
2.15
3.50
–––
3.22
6.47
0.38
82.27
10.28
–––
S
NOTE 5
F
L
S
H
DETAIL J
APPLIES 60 PL
W
5VEDOU8S
15
MOTOROLA DRAM
4M x 8 5 V EDO U
ORDERING INFORMATION
(Order by Full Part Number)
M
B
08 X
X
X
XX X X X
X
XX
Motorola Memory Prefix
Speed (60 = 60 ns)
Extended Data Out (EDO)
Width
Pad Metal (N = Tin–Lead, G = Gold)
S = SIMM
Depth
Board Type/Revision (A, B)
Fab
Component Die Rev
C–Revision—4M x 4
Data Characters
Component Package (T = TSOP, J = SOJ)
00 = Commercial, Unbuffered, 5 V
Module, x4 DRAM–Based,
Square Refresh
Full Part Numbers — MB084CJ00TASN60
MB084CT00TASN60
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado, 80217. 303–675–2140 or 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
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5VEDOU8S/D
◊
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