DSPB56L007FJ50 [MOTOROLA]
Digital Signal Processor;
| 型号： | DSPB56L007FJ50 |
| 厂家： | 
MOTOROLA |
| 描述： | Digital Signal Processor |
| 文件： | 总83页 (文件大小：597K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by:
DSP56007/D
DSP56007
SYMPHONY AUDIO DSP FAMILY
24-BIT DIGITAL SIGNAL PROCESSORS
Motorola designed the Symphony family of high-performance, programmable Digital Signal
Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic,
ATRAC, and Lucasfilm Home THX processing. Software for these applications is licensed by
Motorola for integration into products like audio/ video receivers, televisions, and automotive
sound systems with such user-developed features as digital equalization and sound field
processing. The DSP56007 is an MPU-style general purpose DSP, composed of an efficient 24-bit
Digital Signal Processor core, program and data memories, various peripherals optimized for
audio, and support circuitry. As illustrated in Figure 1, the DSP56000 core family compatible
DSP is fed by program memory, two independent data RAMs and two data ROMs, a Serial
Audio Interface (SAI), Serial Host Interface (SHI), External Memory Interface (EMI), dedicated
I/ O lines, on-chip Phase Lock Loop (PLL), and On-Chip Emulation (OnCE ) port. The
DSP56007 has significantly more on-chip memory than the DSP56004.
ˇ
16-Bit Bus
24-Bit Bus
4
9
5
29
General
Purpose
Input/
Serial
Serial
External
Audio
Interface
(SAI)
Host
Interface
(SHI)
Memory
Interface
(EMI)
X Data
Memory*
Program
Memory*
Y Data
Memory*
Output
PAB
Address
Generation
Unit
24-Bit
DSP56000
Core
XAB
YAB
GDB
PDB
XDB
YDB
Internal
Data
Bus
Switch
TM
OnCE Port
Program
Address
Generator
Program
Decode
Controller
Data ALU
24 × 24 + 56 → 56-Bit MAC
Two 56-Bit Accumulators
Interrupt
Control
Clock
PLL
Gen.
Program Control Unit
Refer to Table 1 for memory configurations.
4
*
3
4
IRQA, IRQB, NMI, RESET
AA0248
Figure 1 DSP56007 Block Diagram
©1996, 1997 MOTOROLA, INC.
TABLE OF CONTENTS
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SECTION 5
SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . .1-1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
FOR TECHNICAL ASSISTANCE:
Telephone:
Email:
1-800-521-6274
dsphelp@dsp.sps.mot.com
http:/ / www.motorola-dsp.com
Internet:
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET pin is
active when low.)
Means that a high true (active high) signal is high or that a low true (active low) signal
is low
Means that a high true (active high) signal is low or that a low true (active low) signal
is high
Signal/Symbol
Logic State
Signal State
Voltage
PIN
PIN
PIN
PIN
True
False
True
False
Asserted
Deasserted
Asserted
V / V
IL
OL
OH
OH
OL
V
V
/ V
/ V
IH
IH
Deasserted
V / V
IL
Note:
Values for V , V , V , and V are defined by individual product specifications.
OH
IL
OL
IH
ii
DSP56007/D
MOTOROLA
DSP56007
Features
FEATURES
Digital Signal Processing Core
•
•
Efficient, object code compatible with the 24-bit DSP56000 core family engine
Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at
88 MHz
•
•
•
•
•
•
•
•
•
•
Highly parallel instruction set with unique DSP addressing modes
Two 56-bit accumulators including extension byte
Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles
56-bit addition/ subtraction in 1 instruction cycle
Fractional and integer arithmetic with support for multiprecision arithmetic
Hardware support for block floating-point Fast Fourier Transforms (FFT)
Hardware nested DO loops
Zero-overhead fast interrupts (2 instruction cycles)
Four 24-bit internal data buses and three 16-bit internal address buses for
simultaneous accesses to one program and two data memories
•
Fabricated in high-density CMOS
Memory
•
•
On-chip modified Harvard architecture, which permits simultaneous accesses
to program and two data memories
Bootstrap loading from Serial Host Interface or External Memory Interface
Table 1 Memory Configuration (Word width is 24 bits)
Mode
PE
Program
X Data
Y Data
Bootstrap
ROM
ROM
RAM
ROM
RAM
ROM
RAM
0
1
6400
5120
None
1024
512
512
1024
1024
512
512
2176
1152
52
52
MOTOROLA
DSP56007/D
iii
DSP56007
Features
Peripheral and Support Circuits
•
Serial Audio Interface (SAI) includes two receivers and three transmitters,
master or slave capability, implementation of I S, Sony, and Matsushita audio
2
protocols; and two sets of SAI interrupt vectors
•
•
Serial Host Interface (SHI) features single master capability, 10-word receive
FIFO, and support for 8-, 16-, and 24-bit words
External Memory Interface (EMI), implemented as a peripheral supporting:
–
Page-mode DRAMs (one or two chips): 64 K × 4, 256 K × 4,
and 4 M × 4 bits
–
–
–
SRAMs (one to four): 256 K × 8 bits
Data bus may be 4 or 8 bits wide
Data words may be 8, 12, 16, 20, or 24 bits wide
•
Four dedicated, independent, programmable General Purpose Input/ Output
(GPIO) lines
•
•
•
On-chip peripheral registers memory mapped in data memory space
Three external interrupt request pins
On-Chip Emulation (OnCE) port for unobtrusive, processor speed-
independent debugging
•
Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer
for the core clock
•
•
•
Power-saving Wait and Stop modes
Fully static, HCMOS design for operating frequencies down to DC
80-pin plastic Quad Flat Pack surface-mount package; 14 × 14 × 2.20 mm
(2.15–2.45 mm range); 0.65 mm lead pitch
•
•
Complete pinout compatibility between DSP56009, DSP56004,
DSP56004ROM, and DSP56007 for easy upgrades
5 V power supply
iv
DSP56007/D
MOTOROLA
DSP56007
Product Documentation
PRODUCT DOCUMENTATION
Table 2 lists the documents that provide a complete description of the DSP56007 and
are required to design properly with the part. Documentation is available from a local
Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature
Distribution Center, or through the Motorola DSP home page on the Internet (the
source for the latest information).
Table 2 DSP56007 Documentation
Document Name
Description of Content
Order Number
DSP56000 Family
Manual
DSP56000 core family architecture and the 24-bit DSP56KFAMUM/ AD
core processor and instruction set
DSP56007 User’s
Manual
Memory, peripherals, and interfaces
DSP56007UM/ AD
DSP56007 Technical
Data
Electrical and timing specifications,
and pin and package descriptions
DSP56007/ D
MOTOROLA
DSP56007/D
v
DSP56007
Product Documentation
vi
DSP56007/D
MOTOROLA
SECTION 1
SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
The DSP56007 input and output signals are organized into the nine functional
groups, as shown in Table 1-1. The individual signals are illustrated in Figure 1-1.
Table 1-1 DSP56007 Functional Group Signal Allocations
Functional Group
Number of Signals
Detailed Description
Power (V
)
9
13
3
Table 1-2
Table 1-3
Table 1-4
CC
Ground (GND)
Phase Lock Loop (PLL)
External Memory Interface (EMI)
29
Table 1-5 and
Table 1-6
Interrupt and Mode Control
Serial Host Interface (SHI)
Serial Audio Interface (SAI)
4
5
9
Table 1-7
Table 1-8
Table 1-9 and
Table 1-10
General Purpose Input/ Output (GPIO)
On-Chip Emulation (OnCE) port
Total
4
4
Table 1-11
Table 1-12
80
MOTOROLA
DSP56007/D
1-1
Signal/Connection Descriptions
Signal Groupings
Power Inputs
DSP56007
V
CCP
3
2
V
CCQ
MOSI/HA0
V
CCA
V
V
CCD
SS/HA2
MISO/SDA
SCK/SCL
HREQ
Port B
Serial Host
Interface
2
CCS
Ground
GND
P
3
4
GND
Q
GND
A
D
2
3
GND
GND
Port C
Serial Audio
Interface
S
WSR
PCAP
PINIT
SCKR
PLL
Rec0
Rec1
SDI0
SDI1
EXTAL
WST
SCKT
SDO0
SDO1
SDO2
15
8
MA0–MA14
MD0–MD7
Tran0
Tran1
Tran2
MA15/MCS3
MA16/MCS2/MCAS
MA17/MCS1/MRAS
MCS0
Port A
External Memory
Interface
4
GPIO
GPIO0–GPIO3
MWR
MRD
DSCK/OS1
DSI/OS0
DSO
MODC/NMI
Mode/Interrupt
Control
MODB/IRQB
MODA/IRQA
RESET
OnCE™
Port
Reset
DR
80 signals
AA0249G
Figure 1-1 DSP56007 SIgnals
1-2
DSP56007/D
MOTOROLA
Signal/Connection Descriptions
Power
POWER
Table 1-2 Power Inputs
Power Name
Description
V
V
V
V
V
PLL Power—V
provides isolated power for the Phase Lock Loop (PLL). The
CCP
CCQ
CCA
CCD
CCS
CCP
voltage should be well-regulated and the input should be provided with an
extremely low impedance path to the V power rail.
CC
Quiet Power—V
provides isolated power for the internal processing logic. This
CCQ
input must be tied externally to all other chip power inputs. The user must provide
adequate external decoupling capacitors.
Address Bus Power—V
I/ O drivers. This input must be tied externally to all other chip power inputs. The
user must provide adequate external decoupling capacitors.
provides isolated power for sections of the address bus
CCA
Data Bus Power—V
provides isolated power for sections of the data bus I/ O
CCD
drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors.
Serial Interface Power—V
provides isolated power for the SHI and SAI. This
CCS
input must be tied externally to all other chip power inputs. The user must provide
adequate external decoupling capacitors.
GROUND
Table 1-3 Grounds
Ground Name
Description
GND
PLL Ground—GND is ground dedicated for PLL use. The connection should be
P
P
provided with an extremely low-impedance path to ground. V
should be
CCP
bypassed to GND by a 0.47 µF capacitor located as close as possible to the chip
P
package.
GND
GND
GND
GND
Quiet Ground—GND provides isolated ground for the internal processing logic.
This connection must be tied externally to all other chip ground connections. The
user must provide adequate external decoupling capacitors.
Q
A
D
S
Q
Address Bus Ground—GND provides isolated ground for sections of the address
A
bus I/ O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Data Bus Ground—GND provides isolated ground for sections of the data bus I/ O
D
drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Serial Interface Ground—GND provides isolated ground for the SHI and SAI. This
S
connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
MOTOROLA
DSP56007/D
1-3
Signal/Connection Descriptions
Clock and PLL signals
CLOCK AND PLL SIGNALS
Note: While the PLL on this DSP is identical to the PLL described in the DSP56000
Family Manual, two of the signals have not been implemented externally.
Specifically, there is no PLOCK signal or CKOUT signal available. Therefore,
the internal clock is not directly accessible and there is no external indication
that the PLL is locked. These signals were omitted to reduce the number of
pins and allow this DSP to be put in a smaller, less expensive package.
Table 1-4 Clock and PLL Signals
State
during
Reset
Signal
Name
Signal
Type
Signal Description
EXTAL
Input
Input
External Clock/Crystal—This input should be connected to an
external clock source. If the PLL is enabled, this signal is
internally connected to the on-chip PLL. The PLL can multiply
the frequency on the EXTAL pin to generate the internal DSP
clock. The PLL output is divided by two to produce a four-phase
instruction cycle clock, with the minimum instruction time being
two PLL output clock periods. If the PLL is disabled, EXTAL is
divided by two to produce the four-phase instruction cycle clock.
PCAP
Input
Input
PLL Filter Capacitor—This input is used to connect a high-
quality (high “Q” factor) external capacitor needed for the PLL
filter. The capacitor should be as close as possible to the DSP with
heavy, short traces connecting one terminal of the capacitor to
PCAP and the other terminal to V
. The required capacitor
CCP
value is specified in Table 2-6 on page 2-6.
Note:
When short lock time is critical, low dielectric absorption
capacitors such as polystyrene, polypropylene, or teflon are
recommended.
If the PLL is not used (i.e., it remains disabled at all times), there is
no need to connect a capacitor to the PCAP pin. It may remain
unconnected, or be tied to either V or GND.
cc
PINIT
Input
Input
PLL Initialization (PINIT)—During the assertion of hardware
reset, the value on the PINIT line is written into the PEN bit of the
PCTL register. When set, the PEN bit enables the PLL by causing
it to derive the internal clocks from the PLL voltage controlled
oscillator output. When the bit is cleared, the PLL is disabled and
the DSP’s internal clocks are derived from the clock connected to
the EXTAL signal. After hardware RESET is deasserted, the
PINIT signal is ignored.
1-4
DSP56007/D
MOTOROLA
Signal/Connection Descriptions
External Memory Interface (EMI)
EXTERNAL MEMORY INTERFACE (EMI)
Table 1-5 External Memory Interface (EMI) Signals
Signal
Type
State during
Reset
Signal Name
Signal Description
MA0–MA14
Output
Output
Table 1-6 Memory Address Lines 0–14—The MA0–MA10 lines provide
the multiplexed row/ column addresses for DRAM accesses.
Lines MA0–MA14 provide the non-multiplexed address lines
0–14 for SRAM accesses.
MA15
Table 1-6 Memory Address Line 15 (MA15)—This line functions as the
non-multiplexed address line 15.
MCS3
MA16
Memory Chip Select 3 (MCS3)—For SRAM accesses, this line
functions as memory chip select 3.
Output
Table 1-6 Memory Address Line 16 (MA16)—This line functions as the
non-multiplexed address line 16 or as memory chip select 2 for
SRAM accesses.
MCS2
Memory Chip Select 2 (MCS2)—For SRAM access, this line
functions as memory chip select 2.
MCAS
Memory Column Address Strobe (MCAS)—This line
functions as the Memory Column Address Strobe (MCAS)
during DRAM accesses.
MA17
MCS1
MRAS
Output
Table 1-6 Memory Address Line 17 (MA17)—This line functions as the
non-multiplexed address line 17.
Memory Chip Select 1 (MCS1)—This line functions as chip
select 1 for SRAM accesses.
Memory Row Address Strobe (MRAS)—This line also
functions as the Memory Row Address Strobe during DRAM
accesses.
MCS0
MWR
MRD
Output
Output
Output
Table 1-6 Memory Chip Select 0—This line functions as memory chip
select 0 for SRAM accesses.
Table 1-6 Memory Write Strobe—This line is asserted when writing to
external memory.
Table 1-6 Memory Read Strobe—This line is asserted when reading
external memory.
MOTOROLA
DSP56007/D
1-5
Signal/Connection Descriptions
External Memory Interface (EMI)
Table 1-5 External Memory Interface (EMI) Signals (Continued)
Signal
Type
State during
Reset
Signal Name
Signal Description
MD0–MD7
Bidi-
rectional
Tri-stated Data Bus—These signals provide the bidirectional data bus for
EMI accesses. They are inputs during reads from external
memory, outputs during writes to external memory, and tri-
stated if no external access is taking place. If the data bus width
is defined as four bits wide, only signals MD0–MD3 are active,
while signals MD4–MD7 remain tri-stated. While tri-stated,
MD0–MD7 are disconnected from the pins and do not require
external pull-ups.
.
Table 1-6 EMI States during Reset and Stop States
Operating Mode
Signal
Hardware Reset Software Reset Individual Reset
Stop Mode
MA0–MA14
MA15
Driven High
Driven High
Previous State
Driven High
Previous State
Previous State
Previous State
Previous State
MCS3
MA16
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Previous State
Previous State
MCS2
Driven High
Driven High
Driven High
Driven High
MCAS:
DRAM refresh disabled
DRAM refresh enabled
Driven High
Driven High
Driven High
Driven High
Driven High
Driven Low
Driven High
Driven High
MA17
MCS1
Driven High
Driven High
Driven High
Driven High
Previous State
Driven High
Previous State
Driven High
MRAS:
DRAM refresh disabled
DRAM refresh enabled
Driven High
Driven High
Driven High
Driven High
Driven High
Driven Low
Driven High
Driven High
MCS0
MWR
MRD
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
Driven High
1-6
DSP56007/D
MOTOROLA
Signal/Connection Descriptions
Interrupt and Mode Control
INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the DSP’s operating mode as it comes
out of hardware reset and receives interrupt requests from external sources after
reset.
Table 1-7 Interrupt and Mode Control Signals
Signal
Type
State during
Reset
Signal Name
Signal Description
MODA
Input
Input (MODA) Mode Select A—This input signal has three functions:
•
•
•
to work with the MODB and MODC signals to select
the DSP’s initial operating mode,
to allow an external device to request a DSP
interrupt after internal synchronization, and
to turn on the internal clock generator when the DSP
is in the Stop processing state, causing the DSP to
resume processing.
MODA is read and internally latched in the DSP when the
processor exits the Reset state. The logic state present on the
MODA, MODB, and MODC pins selects the initial DSP
operating mode. Several clock cycles after leaving the Reset
state, the MODA signal changes to the external interrupt
request IRQA. The DSP operating mode can be changed by
software after reset.
IRQA
External Interrupt Request A (IRQA)—The IRQA input is a
synchronized external interrupt request. It may be
programmed to be level-sensitive or negative-edge-
triggered. When the signal is edge-triggered, triggering
occurs at a voltage level and is not directly related to the fall
time of the interrupt signal. However, as the fall time of the
interrupt signal increases, the probability that noise on IRQA
will generate multiple interrupts also increases.
While the DSP is in the Stop mode, asserting IRQA gates on
the oscillator and, after a clock stabilization delay, enables
clocks to the processor and peripherals. Hardware reset
causes this input to function as MODA.
MOTOROLA
DSP56007/D
1-7
Signal/Connection Descriptions
Interrupt and Mode Control
Table 1-7 Interrupt and Mode Control Signals (Continued)
Signal
Type
State during
Reset
Signal Name
Signal Description
MODB
Input
Input (MODB) Mode Select B—This input signal has two functions:
•
•
to work with the MODA and MODC signals to select
the DSP’s initial operating mode, and
to allow an external device to request a DSP
interrupt after internal synchronization.
MODB is read and internally latched in the DSP when the
processor exits the Reset state. The logic state present on the
MODA, MODB, and MODC pins selects the initial DSP
operating mode. Several clock cycles after leaving the Reset
state, the MODB signal changes to the external interrupt
request IRQB. The DSP operating mode can be changed by
software after reset.
External Interrupt Request B (IRQB)—The IRQB input is a
synchronized external interrupt request. It may be
IRQB
programmed to be level-sensitive or negative-edge-
triggered. When the signal is edge-triggered, triggering
occurs at a voltage level and is not directly related to the fall
time of the interrupt signal. However, as the fall time of the
interrupt signal increases, the probability that noise on IRQB
will generate multiple interrupts also increases. Hardware
reset causes this input to function as MODB.
1-8
DSP56007/D
MOTOROLA
Signal/Connection Descriptions
Interrupt and Mode Control
Table 1-7 Interrupt and Mode Control Signals (Continued)
Signal
Type
State during
Reset
Signal Name
Signal Description
MODC
Input,
edge-
Input (MODC) Mode Select C—This input signal has two functions:
triggered
•
•
to work with the MODA and MODB signals to select
the DSP’s initial operating mode, and
to allow an external device to request a DSP
interrupt after internal synchronization.
MODC is read and internally latched in the DSP when the
processor exits the Reset state. The logic state present on the
MODA, MODB, and MODC pins selects the initial DSP
operating mode. Several clock cycles after leaving the Reset
state, the MODC signal changes to the Non-Maskable
Interrupt request, NMI. The DSP operating mode can be
changed by software after reset.
NMI
Non-Maskable Interrupt Request—The NMI input is a
negative-edge-triggered external interrupt request. This is a
level 3 interrupt that can not be masked out. Triggering
occurs at a voltage level and is not directly related to the fall
time of the interrupt signal. However, as the fall time of the
interrupt signal increases, the probability that noise on NMI
will generate multiple interrupts also increases. Hardware
reset causes this input to function as MODC.
RESET
input
active
RESET—This input causes a direct hardware reset of the
processor. When RESET is asserted, the DSP is initialized and
placed in the Reset state. A Schmitt-trigger input is used for
noise immunity. When the reset signal is deasserted, the initial
DSP operating mode is latched from the MODA, MODB, and
MODC signals. The DSP also samples the PINIT signal and
writes its status into the PEN bit of the PLL Control Register.
When the DSP comes out of the Reset state, deassertion
occurs at a voltage level and is not directly related to the rise
time of the RESET signal. However, the probability that
noise on RESET will generate multiple resets increases with
increasing rise time of the RESET signal.
For proper hardware reset to occur, the clock must be active,
since a number of clock ticks are required for proper
propagation of the hardware Reset state.
MOTOROLA
DSP56007/D
1-9
Signal/Connection Descriptions
Serial Host Interface (SHI)
SERIAL HOST INTERFACE (SHI)
The Serial Host Interface (SHI) has five I/ O signals, which may be configured to
2
operate in either SPI or I C mode. Table 1-8 lists the SHI signals.
Table 1-8 Serial Host Interface (SHI) signals
State
during
Reset
Signal
Type
Signal Name
Signal Description
SCK
Input or
Output
Tri-stated
SPI Serial Clock (SCK)—The SCK signal is an output
when the SPI is configured as a master, and a Schmitt-
trigger input when the SPI is configured as a slave. When
the SPI is configured as a master, the SCK signal is
derived from the internal SHI clock generator. When the
SPI is configured as a slave, the SCK signal is an input,
and the clock signal from the external master
synchronizes the data transfer. The SCK signal is ignored
by the SPI if it is defined as a slave and the Slave Select
(SS) signal is not asserted. In both the master and slave
SPI devices, data is shifted on one edge of the SCK signal
and is sampled on the opposite edge where data is stable.
Edge polarity is determined by the SPI transfer protocol.
2
SCL
Input or
Output
I C Serial Clock (SCL)—SCL carries the clock for bus
2
transactions in the I C mode. SCL is a Schmitt-trigger
input when configured as a slave, and an open-drain
output when configured as a master. SCL should be
connected to V through a pull-up resistor. The
CC
maximum allowed internally generated bit clock
Fosc
Fosc
frequency is
/
for the SPI mode and
/ for the
4
6
2
I C mode where F is the clock on EXTAL. The
osc
maximum allowed externally generated bit clock
Fosc
Fosc
frequency is
/
for the SPI mode and
/ for the
3
5
2
I C mode. This signal is tri-stated during hardware reset,
software reset, or individual reset (no need for external
pull-up in this state).
1-10
DSP56007/D
MOTOROLA
Signal/Connection Descriptions
Serial Host Interface (SHI)
Table 1-8 Serial Host Interface (SHI) signals (Continued)
State
during
Reset
Signal
Type
Signal Name
Signal Description
MISO
Input or
Output
Tri-stated
SPI Master-In-Slave-Out (MISO)—When the SPI is
configured as a master, MISO is the master data input
line. The MISO signal is used in conjunction with the
MOSI signal for transmitting and receiving serial data.
This signal is a Schmitt-trigger input when configured
for the SPI Master mode, an output when configured for
the SPI Slave mode, and tri-stated if configured for the
SPI Slave mode when SS is deasserted.
2
2
SDA
Input or
Output
I C Serial Data and Acknowledge (SDA)—In I C mode,
SDA is a Schmitt-trigger input when receiving and an
open-drain output when transmitting. SDA should be
connected to V through a pull-up resistor. SDA carries
CC
2
the data for I C transactions. The data in SDA must be
stable during the high period of SCL. The data in SDA is
only allowed to change when SCL is low. When the bus
is free, SDA is high. The SDA line is only allowed to
change during the time SCL is high in the case of Start
and Stop events. A high-to-low transition of the SDA line
while SCL is high is an unique situation, and is defined
as the Start event. A low-to-high transition of SDA while
SCL is high is an unique situation, and is defined as the
Stop event.
Note:
This line is tri-stated during hardware reset, software
reset, or individual reset (no need for external pull-up
in this state).
MOSI
Input or
Output
Tri-stated
SPI Master-Out-Slave-In (MOSI)—When the SPI is
configured as a master, MOSI is the master data output
line. The MOSI signal is used in conjunction with the
MISO signal for transmitting and receiving serial data.
MOSI is the slave data input line when the SPI is
configured as a slave. This signal is a Schmitt-trigger
input when configured for the SPI Slave mode.
2
HA0
Input
I C Slave Address 0 (HA0)—This signal uses a Schmitt-
2
trigger input when configured for the I C mode. When
2
configured for I C Slave mode, the HA0 signal is used to
form the slave device address. HA0 is ignored when the
2
SHI is configured for the I C Master mode.
Note:
This signal is tri-stated during hardware reset,
software reset, or individual reset (no need for
external pull-up in this state).
MOTOROLA
DSP56007/D
1-11
Signal/Connection Descriptions
Serial Host Interface (SHI)
Table 1-8 Serial Host Interface (SHI) signals (Continued)
State
during
Reset
Signal
Type
Signal Name
Signal Description
SS
Input
Tri-stated
SPI Slave Select (SS)—This signal is an active low
Schmitt-trigger input when configured for the SPI
mode. When configured for the SPI Slave mode, this
signal is used to enable the SPI slave for transfer.
When configured for the SPI Master mode, this
signal should be kept deasserted. If it is asserted
while configured as SPI master, a bus error
condition will be flagged.
2
I C Slave Address 2 (HA2)—This signal uses a
HA2
Input
2
Schmitt-trigger input when configured for the I C
2
mode. When configured for the I C Slave mode, the
HA2 signal is used to form the slave device address.
2
HA2 is ignored in the I C Master mode. If SS is
deasserted, the SHI ignores SCK clocks and keeps
the MISO output signal in the high-impedance
state.
Note:
This signal is tri-stated during hardware reset,
software reset, or individual reset (no need for
external pull-up in this state).
HREQ
Input or
Output
Tri-stated
Host Request—This signal is an active low Schmitt-
trigger input when configured for the Master mode, but
an active low output when configured for the Slave
mode. When configured for the Slave mode, HREQ is
asserted to indicate that the SHI is ready for the next data
word transfer and deasserted at the first clock pulse of
the new data word transfer. When configured for the
Master mode, HREQ is an input and when asserted by
the external slave device, it will trigger the start of the
data word transfer by the master. After finishing the data
word transfer, the master will await the next assertion of
HREQ to proceed to the next transfer.
Note:
This signal is tri-stated during hardware, software,
individual reset, or when the HREQ[1:0] bits (in the
HCSR) are cleared (no need for external pull-up in this
state).
1-12
DSP56007/D
MOTOROLA
Signal/Connection Descriptions
Serial Audio Interface (SAI)
SERIAL AUDIO INTERFACE (SAI)
The SAI is composed of separate receiver and transmitter sections.
SAI Receiver Section
Table 1-9 Serial Audio Interface (SAI) Receiver signals
Signal
Name
Signal
Type
State during
Reset
Signal Description
SDI0
Input
Tri-stated
Tri-stated
Tri-stated
Serial Data Input 0—While in the high impedance
state, the internal input buffer is disconnected from
the pin and no external pull-up is necessary. SDI0 is
the serial data input for receiver 0.
Note:
This signal is high impedance during hardware or
software reset, while receiver 0 is disabled
(R0EN = 0), or while the DSP is in the Stop state.
SDI1
Input
Serial Data Input 1—While in the high impedance
state, the internal input buffer is disconnected from
the pin and no external pull-up is necessary. SDI1 is
the serial data input for receiver 1.
Note:
This signal is high impedance during hardware or
software reset, while receiver 1 is disabled
(R1EN = 0), or while the DSP is in the Stop state.
SCKR
Input or
Output
Receive Serial Clock—SCKR is an output if the
receiver section is programmed as a master, and a
Schmitt-trigger input if programmed as a slave. While
in the high impedance state, the internal input buffer
is disconnected from the pin and no external pull-up is
necessary.
Note:
SCKR is high impedance if all receivers are
disabled (individual reset) and during hardware or
software reset, or while the DSP is in the Stop state.
MOTOROLA
DSP56007/D
1-13
Signal/Connection Descriptions
Serial Audio Interface (SAI)
Table 1-9 Serial Audio Interface (SAI) Receiver signals (Continued)
Signal
Name
Signal
Type
State during
Reset
Signal Description
WSR
Input or
Output
Tri-stated
Word Select Receive (WSR)—WSR is an output if the
receiver section is configured as a master, and a
Schmitt-trigger input if configured as a slave. WSR is
used to synchronize the data word and to select the
left/ right portion of the data sample.
Note:
WSR is high impedance if all receivers are disabled
(individual reset), during hardware reset, during
software reset, or while the DSP is in the Stop state.
While in the high impedance state, the internal
input buffer is disconnected from the signal and no
external pull-up is necessary.
1-14
DSP56007/D
MOTOROLA
Signal/Connection Descriptions
Serial Audio Interface (SAI)
SAI Transmitter Section
Table 1-10 Serial Audio Interface (SAI) Transmitter signals
State
during
Reset
Signal
Name
Signal
Type
Signal Description
SDO0
SDO1
SDO2
SCKT
Output
Output
Output
Driven
High
Serial Data Output 0 (SDO0)—SDO0 is the serial output for
transmitter 0. SDO0 is driven high if transmitter 0 is disabled,
during individual reset, hardware reset, and software reset,
or when the DSP is in the Stop state.
Driven
High
Serial Data Output 1 (SDO1)—SDO1 is the serial output for
transmitter 1. SDO1 is driven high if transmitter 1 is disabled,
during individual reset, hardware reset and software reset, or
when the DSP is in the Stop state.
Driven
High
Serial Data Output 2 (SDO2)—SDO2 is the serial output for
transmitter 2. SDO2 is driven high if transmitter 2 is disabled,
during individual reset, hardware reset and software reset, or
when the DSP is in the Stop state.
Input or
Output
Tri-stated
Serial Clock Transmit (SCKT)—This signal provides the
clock for the SAI. SCKT can be an output if the transmit
section is configured as a master, or a Schmitt-trigger input if
the transmit section is configured as a slave. When the SCKT
is an output, it provides an internally generated SAI transmit
clock to external circuitry. When the SCKT is an input, it
allows external circuitry to clock data out of the SAI.
Note:
SCKT is high impedance if all transmitters are disabled
(individual reset), during hardware reset, software reset, or
while the DSP is in the Stop state. While in the high
impedance state, the internal input buffer is disconnected
from the pin and no external pull-up is necessary.
WST
Input or
Output
Tri-stated
Word Select Transmit (WST)—WST is an output if the
transmit section is programmed as a master, and a Schmitt-
trigger input if it is programmed as a slave. WST is used to
synchronize the data word and select the left/ right portion of
the data sample.
Note:
WST is high impedance if all transmitters are disabled
(individual reset), during hardware or software reset, or
while the DSP is in the Stop state. While in the high
impedance state, the internal input buffer is disconnected
from the pin and no external pull-up is necessary.
MOTOROLA
DSP56007/D
1-15
Signal/Connection Descriptions
General Purpose I/O
GENERAL PURPOSE I/O
Table 1-11 General Purpose I/ O (GPIO) Signals
Signal
Name
Signal
Type
State during
Reset
Signal Description
GPIO0–
GPIO3
Standard
Output,
Open-drain
Output, or
Input
Disconnected
GPIO lines can be used for control and handshake
functions between the DSP and external circuitry.
Each GPIO line can be configured individually as
disconnected, open-drain output, standard output,
or an input.
Note:
Hardware reset or software reset configures all
the GPIO lines as disconnected (external
circuitry connected to these pins may need pull-
ups until the pins are configured for operation).
ON-CHIP EMULATION (OnCETM) PORT
There are four signals associated with the OnCE port controller and its serial
interface.
Table 1-12 On-Chip Emulation Port Signals
Signal
Name
Signal
Type
State during
Reset
Signal Description
DSI
Input
Output,
Debug Serial Input (DSI)—The DSI signal is the signal
Driven Low through which serial data or commands are provided to the
OnCE port controller. The data received on the DSI signal
will be recognized only when the DSP has entered the
Debug mode of operation. Data must have valid TTL logic
levels before the serial clock falling edge. Data is always
shifted into the OnCE port Most Significant Bit (MSB) first.
OS0
Output
Operating Status 0 (OS0)—When the DSP is not in the Debug
mode, the OS0 signal provides information about the DSP
status if it is an output and used in conjunction with the OS1
signal. When switching from output to input, the signal is
tri-stated.
Note:
If the OnCE port is in use, an external pull-down resistor
should be attached to the DSI/ OS0 signal. If the OnCE
port is not in use, the resistor is not required.
1-16
DSP56007/D
MOTOROLA
Signal/Connection Descriptions
TM
On-Chip Emulation (OnCE ) Port
Table 1-12 On-Chip Emulation Port Signals (Continued)
Signal
Name
Signal
Type
State during
Reset
Signal Description
DSCK
Input
Output,
Debug Serial Clock (DSCK)—The DSCK/ OS1 signal,
Driven Low when an input, is the signal through which the serial clock
is supplied to the OnCE port. The serial clock provides
pulses required to shift data into and out of the OnCE port.
Data is clocked into the OnCE port on the falling edge and
is clocked out of the OnCE port on the rising edge.
OS1
Output
Operating Status 1 (OS1)—If the OS1 signal is an output
and used in conjunction with the OS0 signal, it provides
information about the DSP status when the DSP is not in the
Debug mode. The debug serial clock frequency must be no
greater than 1/ 8 of the processor clock frequency. The
signal is tri-stated when it is changing from input to output.
Note:
If the OnCE port is in use, an external pull-down resistor
should be attached to the DSCK/ OS1 pin. If the OnCE
port is not in use, the resistor is not required.
DSO
Output
Driven High Debug Serial Output (DSO)—The DSO line provides the
data contained in one of the OnCE port controller registers
as specified by the last command received from the
command controller. The Most Significant Bit (MSB) of the
data word is always shifted out of the OnCE port first. Data
is clocked out of the OnCE port on the rising edge of DSCK.
The DSO line also provides acknowledge pulses to the
external command controller. When the DSP enters the
Debug mode, the DSO line will be pulsed low to indicate
that the OnCE port is waiting for commands. After
receiving a read command, the DSO line will be pulsed low
to indicate that the requested data is available and the
OnCE port is ready to receive clock pulses in order to
deliver the data. After receiving a write command, the DSO
line will be pulsed low to indicate that the OnCE port is
ready to receive the data to be written; after the data is
written, another acknowledge pulse will be provided.
Note:
During hardware reset and when idle, the DSO line is
held high.
MOTOROLA
DSP56007/D
1-17
Signal/Connection Descriptions
TM
On-Chip Emulation (OnCE ) Port
Table 1-12 On-Chip Emulation Port Signals (Continued)
Signal
Name
Signal
Type
State during
Reset
Signal Description
DR
Input
Input
Debug Request (DR)—The debug request input provides a
means of entering the Debug mode of operation. This signal,
when asserted (pulled low), will cause the DSP to finish the
current instruction being executed, to save the instruction
pipeline information, to enter the Debug mode, and to wait
for commands to be entered from the debug serial input line.
While the DSP is in the Debug mode, the user can reset the
OnCE port controller by asserting DR, waiting for an
acknowledge pulse on DSO, and then deasserting DR. It
may be necessary to reset the OnCE port controller in cases
where synchronization between the OnCE port controller
and external circuitry is lost. Asserting DR when the DSP is
in the Wait or the Stop mode, and keeping it asserted until
an acknowledge pulse in the DSP is produced, puts the DSP
into the Debug mode. After receiving the acknowledge
pulse, DR must be deasserted before sending the first OnCE
port command. For more information, see Methods Of
Entering The Debug Mode in the DSP56000 Family
Manual.
Note:
If the OnCE port is not in use, an external pull-up resistor
should be attached to the DR line.
1-18
DSP56007/D
MOTOROLA
SECTION 2
SPECIFICATIONS
INTRODUCTION
The DSP56007 is fabricated in high density CMOS with Transistor-Transistor Logic
(TTL) compatible inputs and outputs.
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting
against damage due to high static voltage or
electrical fields; however, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either GND or V ).
CC
Note: In the calculation of timing requirements, adding a maximum value of one
specification to a minimum value of another specification does not yield a
reasonable sum. A maximum specification is calculated using a worst case
variation of process parameter values in one direction. The minimum
specification is calculated using the worst case for the same parameters in the
opposite direction. Therefore, a “maximum” value for a specification will
never occur in the same device that has a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that
can never exist.
MOTOROLA
DSP56007/D
2-1
Specifications
Thermal characteristics
Table 2-1 Maximum Ratings (GND = 0 V )
dc
Rating
Symbol
Value
Unit
Supply Voltage
V
–0.3 to +7.0
V
V
CC
All Input Voltages
V
(GND – 0.25) to (V + 0.25)
IN
CC
Current Drain per Pin excluding V and GND
I
10
mA
CC
Operating Temperature Range:
T
J
•
•
50 and 66 MHz
88 MHz
–40 to +125
–40 to +110
°C
°C
Storage Temperature
T
–55 to +125
°C
STG
THERMAL CHARACTERISTICS
Table 2-2 Thermal Characteristics
3
4
Characteristic
Symbol
QFP Value
QFP Value
Unit
1
Junction-to-ambient thermal resistance
R
or θ
or θ
61.5
11.8
2.7
37
—
—
˚C/ W
˚C/ W
˚C/ W
θJA
JA
JC
2
Junction-to-case thermal resistance
R
θJC
Thermal characterization parameter
Ψ
JT
Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal-single-sided
Printed Circuit Board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment
and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111)
2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-
88, with the exception that the cold plate temperature is used for the case temperature.
3. These are measured values. See note 1 for test board conditions.
4. These are measured values; testing is not complete. Values were measured on a non-standard
four-layer thermal test board (two internal planes) at one watt in a horizontal configuration.
2-2
DSP56007/D
MOTOROLA
Specifications
DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-3 DC Electrical Characteristics
50 MHz
66 MHz
88 MHz
Unit
Characteristics
Symbol
Min Typ Max Min Typ Max Min Typ Max
Supply voltage
Input high voltage
V
4.75 5.0 5.25 4.75 5.0 5.25 4.75 5.0 5.25
V
CC
•
•
•
EXTAL
RESET
MODA, MODB,
MODC
SHI inputs
V
V
V
4.0
2.5
3.5
—
—
—
V
V
V
4.0
2.5
3.5
—
—
—
V
V
V
4.0
2.5
3.5
—
—
—
V
V
V
V
V
V
IHC
IHR
IHM
CC
CC
CC
CC
CC
CC
CC
CC
CC
1
•
•
V
0.7 ×
—
—
V
V
0.7 ×
—
—
V
V
0.7 ×
—
—
V
V
V
V
IHS
CC
CC
CC
CC
CC
CC
V
V
V
CC
CC
CC
All other inputs
V
2.0
2.0
2.0
IH
Input low voltage
•
•
EXTAL
MODA, MODB,
MODC
V
–0.5
–0.5
—
—
0.4
2.0
–0.5
–0.5
—
—
0.4
2.0
–0.5
–0.5
—
—
0.4
2.0
V
V
ILC
V
ILM
1
•
•
SHI inputs
V
–0.5
–0.5
—
—
0.3 × –0.5
—
—
0.3 × –0.5
—
—
0.3 ×
V
V
ILS
V
V
V
CC
CC
CC
All other inputs
V
0.8
–0.5
–1
0.8
–0.5
–1
0.8
1
IL
Input leakage current
I
IN
•
EXTAL, RESET,
MODA, MODB,
MODC, DR
–1
—
1
—
1
—
µA
•
Other Input Pins
(@ 2.4 V/ 0.4 V)
–10
–10
2.4
—
—
—
—
—
10
10
—
0.4
–10
–10
2.4
—
—
—
—
—
10
10
—
0.4
–10
–10
2.4
—
—
—
—
—
10
10
—
0.4
µA
µA
V
High impedance (off-state)
input current (@ 2.4 V / 0.4 V)
I
TSI
Output high voltage
V
OH
(I
= –0.4 mA)
OH
Output low voltage
(I = 3.2 mA)
V
V
OL
OL
SCK/ SCL I = 6.7 mA
OL
MISO/ SDA I = 6.7 mA
OL
HREQ I = 6.7 mA
OL
Internal Supply Current
4
4
4
•
•
•
Normal mode
Wait mode
Stop mode
I
—
—
—
80 105
14
5
—
—
—
110 130
18
5
—
—
—
147 169
24
5
mA
mA
µA
CCI
I
25
110
30
110
33
110
CCW
2
I
CCS
MOTOROLA
DSP56007/D
2-3
Specifications
AC Electrical Characteristics
Table 2-3 DC Electrical Characteristics (Continued)
50 MHz
66 MHz
88 MHz
Characteristics
Symbol
Unit
Min Typ Max Min Typ Max Min Typ Max
PLL supply current
—
—
0.7
10
1.1
—
—
—
1.0
10
1.5
—
—
—
1.3
10
2.2
—
mA
pF
3
Input capacitance
C
IN
Notes: 1. The SHI inputs are: MOSI/ HA0, SS/ HA2, MISO/ SDA, SCK/ SCL, and HREQ.
2. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signals are
disabled during Stop state.
3. Periodically sampled and not 100% tested
4. Maximum values are derived using the methodology described in Section 4. Actual maximums are
application dependent and may vary widely from these numbers.
AC ELECTRICAL CHARACTERISTICS
The timing waveforms in the AC Electrical Characteristics are tested with a V
IL
maximum of 0.5 V and a V minimum of 2.4 V for all pins, except EXTAL, RESET,
IH
MODA, MODB, MODC, and SHI pins (MOSI/ HA0, SS/ HA2, MISO/ SDA, SCK/
SCL, HREQ). These pins are tested using the input levels set forth in the DC Electrical
Characteristics. AC timing specifications that are referenced to a device input signal
are measured in production with respect to the 50% point of the respective input
signal’s transition. DSP56007 output levels are measured with the production test
machine V and V
reference levels set at 0.8 V and 2.0 V, respectively.
OL
OH
All output delays are given for a 50 pF load unless otherwise specified.
For load capacitance greater than 50 pF, the drive capability of the output pins
typically decreases linearly:
1. At 1.5 ns per 10 pF of additional capacitance at all output pins except
MOSI/ HA0, MISO/ SDA, SCK/ SCL, HREQ
2. At 1.0 ns per 10 pF of additional capacitance at output pins MOSI/ HA0,
MISO/ SDA, SCK/ SCL, HREQ (in SPI mode only)
2-4
DSP56007/D
MOTOROLA
Specifications
Internal Clocks
INTERNAL CLOCKS
For each occurrence of T , T , T , or I , substitute with the numbers in Table 2-4.
CYC
C
H
L
Table 2-4 Internal Clocks
Characteristics
Internal Operation Frequency
Symbol
Expression
f
—
Internal Clock High Period
• with PLL disabled
T
H
ET
H
• with PLL enabled and MF ≤ 4
(Min) 0.48 × T
(Max) 0.52 × T
C
C
• with PLL enabled and MF > 4
(Min) 0.467 × T
(Max) 0.533 × T
C
C
Internal Clock Low Period
• with PLL disabled
• with PLL enabled and MF ≤ 4
T
T
L
ET
L
(Min) 0.48 × T
(Max) 0.52 × T
(Min) 0.467 × T
C
C
• with PLL enabled and MF > 4
C
C
(Max) 0.533 × T
Internal Clock Cycle Time
Instruction Cycle Time
(DF / MF) × ET
C
C
I
2 × T
C
CYC
EXTERNAL CLOCK (EXTAL PIN)
The DSP56007 system clock is externally supplied via the EXTAL pin. Timings shown
in this document are valid for clock rise and fall times of 3 ns maximum.
Table 2-5 External Clock (EXTAL Pin)
50 MHz
66 MHz
88 MHz
No.
Characteristics
Sym.
Unit
MHz
ns
Min Max Min
Max Min Max
— Frequency of External Clock (EXTAL Pin) Ef
0
50
0
66
0
88
1
1
External Clock Input High—EXTAL Pin
• with PLL disabled
ET
H
9.3
∞
7.1
∞
5.3
∞
(46.7%–53.3% duty cycle)
• with PLL enabled
8.5 235500 6.4 235500 4.8 235500 ns
(42.5%–57.5% duty cycle)
MOTOROLA
DSP56007/D
2-5
Specifications
Phase Lock Loop (PLL) Characteristics
Table 2-5 External Clock (EXTAL Pin) (Continued)
50 MHz
66 MHz
88 MHz
No.
Characteristics
Sym.
Unit
Min Max Min
Max Min Max
1
2
External Clock Input Low—EXTAL Pin
• with PLL disabled
ET
L
9.3
∞
7.1
∞
5.4
∞
ns
(46.7%–53.3% duty cycle)
• with PLL enabled
8.5 235500 6.4 235500 4.8 235500 ns
(42.5%–57.5% duty cycle)
1
3
External Clock Cycle Time
• with PLL disabled
• with PLL enabled
ET
I
C
20
∞
15.15
∞
11.4
∞
ns
20 409600 15.15 409600 11.4 409600 ns
1
4
Instruction Cycle Time = I = 2 × T
cyc
C
cyc
• with PLL disabled
40
∞
30.3
∞
22.7
∞
ns
• with PLL enabled
40 819200 30.3 819200 22.7 819200 ns
Note:
1. External Clock Input High and External Clock Input Low are measured at 50% of the input transition.
EXTAL
1
2
ET
ET
H
L
3
ET
C
4
AA0250
Figure 2-1 External Clock Timing
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table 2-6 Phase Lock Loop (PLL) Characteristics
Characteristics
Expression
Min
Max
Unit
1
VCO frequency when PLL enabled
PLL external capacitor
MF × Ef
10
f
MHz
1
MF × C
PCAP
(PCAP pin to V
)
@ MF ≤ 4
@ MF > 4
MF × 340
MF × 380
MF × 480
MF × 970
pF
pF
CCP
Note:
1. Cpcap is the value of the PLL capacitor (connected between PCAP pin and V
) for MF = 1.
CCP
The recommended value for Cpcap is 400 pF for MF ≤ 4 and 540 pF for MF > 4.
The maximum VCO frequency is limited to the internal operation frequency, defined in Table 2-4.
2-6
DSP56007/D
MOTOROLA
Specifications
RESET, Stop, Mode Select, and Interrupt Timing
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (C = 50 pF + 2 TTL Loads)
L
No.
Characteristics
Min
Max
Unit
10 Minimum RESET assertion width:
•
•
PLL disabled
PLL enabled
25 × T
2500 × ET
—
—
ns
ns
C
1
C
14 Mode Select Setup Time
15 Mode Select Hold Time
21
0
—
—
—
ns
ns
ns
16 Minimum Edge-triggered Interrupt Request Assertion
Width
13
16a Minimum Edge-triggered Interrupt Request
Deassertation Width
13
—
—
ns
ns
18 Delay from IRQA, IRQB, NMI Assertion to GPIO Valid
Caused by First Interrupt Instruction Execution
12 × T + T
C
H
22 Delay from General Purpose Output Valid to Interrupt
Request Deassertation for Level Sensitive Fast
2
Interrupts—If Second Interrupt Instruction is:
•
•
Single Cycle
Two Cycles
T – 31
ns
L
(2 × T ) + T – 31 ns
C
L
25 Duration of IRQA Assertion for Recovery from Stop State
12
—
ns
27 Duration for Level Sensitive IRQA Assertion to ensure
interrupt service (when exiting “STOP”)
•
•
Stable External Clock, OMR Bit 6 = 1
Stable External Clock, PCTL Bit 17 = 1
6 × T + T
—
—
ns
ns
C
L
12
Note:
1. This timing requirement is sensitive to the quality of the external PLL capacitor connected to the PCAP
pin. For capacitor values less than or equal to 2 nF, asserting RESET according to this timing requirement
will ensure proper processor initialization for capacitors with a deltaC/ C less than 0.5%. (This is typical
for ceramic capacitors.) For capacitor values greater than 2 nF, asserting RESET according to this timing
requirement will ensure proper processor initialization for capacitors with a deltaC/ C less than 0.01%.
(This is typical for Teflon, polystyrene, and polypropylene capacitors.) However, capacitors with values
greater than 2 nF with a deltaC/ C greater than 0.01% may require longer RESET assertion to ensure
proper initialization.
2. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timing 22 applies to
prevent multiple interrupt service. To avoid these timing restrictions, the Negative Edge-triggered
mode is recommended when using fast interrupts. Long interrupts are recommended when using
Level-sensitive mode.
VIHR
RESET
10
AA0251
Figure 2-2 Reset Timing
MOTOROLA
DSP56007/D
2-7
Specifications
RESET, Stop, Mode Select, and Interrupt Timing
RESET
VIHR
14
15
V
V
IH
IHM
MODA, MODB
MODC
IRQA, IRQB,
NMI
V
V
IL
ILM
AA0252
Figure 2-3 Operating Mode Select Timing
IRQA, IRQB,
NMI
16
IRQA, IRQB,
NMI
16A
AA0253
Figure 2-4 External Interrupt Timing (Negative Edge-triggered)
General
Purpose
I/O
(Output)
18
22
IRQA
IRQB
NMI
General Purpose I/O
AA0254
AA0255
AA0256
Figure 2-5 External Level-sensitive Fast Interrupt Timing
25
IRQA
Figure 2-6 Recovery from Stop State Using IRQA
27
IRQA
Figure 2-7 Recovery from Stop State Using IRQA Interrupt Service
2-8
DSP56007/D
MOTOROLA
Specifications
External Memory Interface (EMI) DRAM Timing
EXTERNAL MEMORY INTERFACE (EMI) DRAM TIMING
(C = 50 pF + 2 TTL Loads)
L
Table 2-8 External Memory Interface (EMI) DRAM Timing
50 MHz
66 MHz
88 MHz
Timing
Mode
No.
Characteristics
Symbol
Expression
Unit
Min Max Min Max Min Max
41 Page Mode Cycle Time
t
slow
fast
4 × T
3 × T
80
60
—
—
61
46
—
—
45.5
34.1
—
—
ns
ns
PC
C
C
42 RAS or RD Assertion to
Data Valid
t
,
slow
fast
7 × T – 16
—
—
124
84
—
—
90
60
—
—
63.5 ns
40.8 ns
RAC
C
t
5 × T – 16
GA
C
43 CAS Assertion to Data
Valid
T
slow
fast
3 × T – 10
—
—
50
30
—
—
35
20
—
—
24.1 ns
12.7 ns
CAC
C
2 × T – 10
C
44 Column Address Valid
to Data Valid
t
slow 3 ×T + T – 7
—
—
63
43
—
—
46
30
—
—
32.8 ns
21.4 ns
AA
C
L
fast
2 × T + T –
C L
7
45 CAS Assertion to Data
Active
T
0
0
—
0
—
0
—
ns
CLZ
46 RAS Assertion Pulse
t
slow
fast
3 ×T –11
+ n × 4 × T
209
149
—
—
156
110
—
—
114
—
—
ns
ns
RASP
C
1
Width
(Page Mode Access
Only)
C
2 × T –11
79.9
C
+ n × 3 ×T
C
47 RAS Assertion Pulse
Width
t
slow
fast
7 × T – 11 129
—
—
95
65
—
—
68.5
45.8
—
—
ns
ns
RAS
C
5 × T – 11
89
C
(Single Access Only)
48 RAS or CAS
Deassertation to RAS
Assertion
t
T
,
slow
fast
5 × T – 5
95
55
—
—
70
40
—
—
51.8
29.1
—
—
ns
ns
RP
C
3 × T – 5
CRP
C
49 CAS Assertion Pulse
Width
T
t
slow
fast
3 × T – 10
50
30
—
—
35
20
—
—
24.1
12.7
—
—
ns
ns
CAS
C
2 × T – 10
C
50 Last CAS Assertion to
RAS Deassertation
(Page Mode Access
Only)
slow
fast
3 × T – 15
45
25
—
—
30
15
—
—
19.1
7.7
—
—
ns
ns
RSH
C
2 × T – 15
C
51
T
T
,
slow
fast
7 × T – 15 125
—
—
91
61
—
—
64.5
41.8
—
—
ns
ns
RAS or WR Assertion to
CAS Deassertation
CSH
C
5 × T – 15
85
CWL
C
52 RAS Assertion to CAS
Assertion
t
slow
fast
4 ×T – 13
67
47
—
—
47
32
—
—
32.5
21.1
—
—
ns
ns
RCD
RAD
C
3 × T – 13
C
53 RAS Assertion to
Column Address Valid
t
slow
3 ×T + T – 57
—
40
—
26.8
—
ns
C
H
13
fast
2 ×T + T – 37
—
25
—
15.4
—
ns
C
H
13
MOTOROLA
DSP56007/D
2-9
Specifications
External Memory Interface (EMI) DRAM Timing
Table 2-8 External Memory Interface (EMI) DRAM Timing (Continued)
50 MHz
66 MHz
88 MHz
Timing
Mode
No.
Characteristics
Symbol
Expression
T – 5
Unit
Min Max Min Max Min Max
54 CAS Deassertation Pulse
Width
T
15
4
—
—
10
2
—
—
6.4
0.1
—
—
ns
CP
C
(Page Mode Access
Only)
55 Row Address Valid to
RAS Assertion
t
T – 6
ns
ASR
L
(Row Address Setup
Time)
56 RAS Assertion to ROW
Address Not Valid
(Row Address Hold
Time)
t
slow 3 × T + T – 56
—
—
39
24
—
—
25.8
14.4
—
—
ns
ns
RAH
C
H
14
fast
2 × T + T – 36
C
H
14
57 Column Address Valid
to CAS Assertion
(Column Address Setup
Time)
t
T – 6
4
—
2
—
0.1
—
ns
ASC
L
58 CAS Assertion to
Column Address Not
Valid
T
T
slow 3 × T + T – 56
—
—
39
24
—
—
25.8
14.4
—
—
ns
ns
CAH
C
H
14
fast
2 × T + T – 36
C
H
(Column Address Hold
Time)
14
59
slow 7 × T + T – 136
—
—
100
54
—
—
71.2
37.1
—
—
ns
ns
Last CAS Assertion to
Column Address Not
Valid (Column Address
Hold Time)
CAH
C
H
14
fast
4 × T + T – 76
C
H
14
60 RAS Assertion to
Column Address Not
Valid
t
slow 7 × T + T – 136
—
—
100
69
—
—
71.2
48.5
—
—
ns
ns
AR
C
H
14
fast
5 × T + T – 96
C
H
14
61 Column Address Valid
to RAS Deassertation
t
slow 3 × T + T – 63
—
—
46
30
—
—
32.8
21.2
—
—
ns
ns
RAL
C
L
fast
7
43
2 × T + T –
C
L
7
62 CAS, RAS, RD, or WR
Deassertation to WR or
RD Assertion
t
t
,
slow
fast
5 × T – 11
89
49
—
—
65
35
—
—
45.8
23.1
—
—
ns
ns
RCH
C
3 × T – 11
RRH
C
63 CAS or RD
Deassertation to Data
Not Valid
t
,
0
0
—
0
—
0
—
ns
OFF
t
GZ
(Data Hold Time)
2-10
DSP56007/D
MOTOROLA
Specifications
External Memory Interface (EMI) DRAM Timing
Table 2-8 External Memory Interface (EMI) DRAM Timing (Continued)
50 MHz
66 MHz
88 MHz
Timing
Mode
No.
Characteristics
Symbol
Expression
Unit
Min Max Min Max Min Max
64 Random Read or Write
Cycle Time (Single
Access Only)
t
slow
fast
12 × T
240
98.8
—
—
182
121
—
—
136.4
91.0
—
—
ns
ns
RC
C
8 × T
C
65 WR Deassertation to
CAS Assertion
t
slow
fast
9 × T – 11 169
—
—
125
80
—
—
91.3
57.2
—
—
ns
ns
RCS
C
6 × T – 11 109
C
66 CAS Assertion to WR
Deassertation
t
slow
fast
3 × T – 13
47
27
—
—
32
17
—
—
21.1
9.7
—
—
ns
ns
WCH
C
2 × T – 13
C
67 Data Valid to CAS
Assertion
t
T – 6
4
—
2
—
0.1
—
ns
DS
L
(Data Setup Time)
68 CAS Assertion to Data
Not Valid (Data Hold
Time)
t
slow 3 × T + T – 56
—
—
39
24
—
—
25.8
14.4
—
—
ns
ns
DH
C
H
14
fast
2 × T + T – 36
C
H
14
69 RAS Assertion to Data
Not Valid
t
t
slow 7 × T + T – 136
—
—
100
69
—
—
71.2
48.5
—
—
ns
ns
DHR
C
H
14
fast
5 × T + T – 96
C
H
14
70 WR Assertion to CAS
Assertion
slow
fast
4 × T – 14
66
46
—
—
47
31
—
—
31.4
20.1
—
—
ns
ns
WCS
C
3 × T – 14
C
71 WR Assertion Pulse
Width (Single Cycle
Only)
t
slow
fast
7 × T – 9
131
91
—
—
97
67
—
—
70.5
47.8
—
—
ns
ns
WP
C
5 × T – 9
C
72
t
slow
fast
7 × T – 15 125
—
—
91
61
—
—
64.5
41.8
—
—
ns
ns
RAS Assertion to WR
Deassertation
WCR
C
5 × T – 15
85
C
(Single Cycle Only)
73 WR Assertion to Data
Active
slow 3 × T + T – 57
—
—
40
25
—
—
26.8
15.4
—
—
ns
ns
C
H
13
fast
2 × T + T – 37
C
H
13
74 RD or WR Assertion to
RAS Deassertation
t
t
,
slow
fast
7 × T – 13 127
—
—
93
63
—
—
66.5
43.8
—
—
ns
ns
ROH
C
5 × T – 13
87
RWL
C
(Single Cycle Only)
Note:
1. n is the number of successive accesses. n = 2, 3, 4, or 6.
MOTOROLA
DSP56007/D
2-11
Specifications
External Memory Interface (EMI) DRAM Timing
48
48
47
74
64
MRAS
52
50
49
65
MCAS
55
53
59
60
Row Address
56
Last Column Address
MA0–MA10
MWR
57
62
44
61
43
MRD
42
63
45
Data In
MD0–MD7
AA0257
Figure 2-8 DRAM Single Read Cycle
2-12
DSP56007/D
MOTOROLA
Specifications
External Memory Interface (EMI) DRAM Timing
48
46
48
60
50
MRAS
65
41
54
54
52
49
49
49
MCAS
51
61
55
53
58
58
59
Row Address
Col. Address
Col. Address
Last Column Address
MA0–MA10
56
57
62
44
57
44
57
MWR
MRD
44
43
43
43
42
63
63
63
45
45
45
Data In
Data In
Data In
MD0–MD7
AA0263
Figure 2-9 DRAM Page Mode Read Cycle
MOTOROLA
DSP56007/D
2-13
Specifications
External Memory Interface (EMI) DRAM Timing
64
48
47
48
MRAS
74
52
50
49
65
MCAS
55
61
60
53
59
Row Address
Column Address
MA0–MA10
56
70
57
66
62
72
MWR
MRD
71
69
68
67
73
MD0–MD7
Data Out
AA0264
Figure 2-10 DRAM Single Write Cycle
2-14
DSP56007/D
MOTOROLA
Specifications
External Memory Interface (EMI) DRAM Timing
48
46
48
60
50
MRAS
65
41
54
54
52
49
49
49
MCAS
51
61
55
53
58
58
59
MA0–MA10
Row Address
Col. Address
Col. Address
Last Column Address
56
70
66
57
57
62
57
MWR
MRD
69
68
68
67
67
73
68
67
Data Out
Data Out
Data Out
MD0–MD7
AA0265
Figure 2-11 DRAM Page Mode Write Cycle
MOTOROLA
DSP56007/D
2-15
Specifications
External Memory Interface (EMI) DRAM Refresh Timing
EXTERNAL MEMORY INTERFACE (EMI) DRAM REFRESH TIMING
(C = 50pF + 2 TTL Loads)
L
Table 2-9 External Memory Interface (EMI) DRAM Refresh Timing
50 MHz
66 MHz
88 MHz
Timing
Mode
No.
Characteristics
Sym.
Exp.
Unit
Min Max Min Max Min Max
81
t
slow
fast
6 × T – 7 113
—
—
84
—
—
—
61.2
—
—
—
ns
ns
RAS Deassertation to
RAS Assertion
RP
C
1
4 × T – 7
73
C
82 CAS Deassertation to
CAS Assertion
T
slow
fast
5 × T – 7
93
53
—
—
71
—
—
—
49.8
—
—
—
ns
ns
CPN
C
1
3 × T – 7
C
83 Refresh Cycle Time
t
slow
fast
13 × T
260
180
—
—
197 — 147.7
—
—
ns
ns
RC
C
1
9 × T
—
—
—
C
84 RAS Assertion Pulse
Width
t
slow
fast
7 × T – 9 131
—
—
97
—
—
—
70.5
—
—
—
ns
ns
RAS
C
1
5 × T – 9
91
C
85 RAS Deassertation to
RAS Assertion for
t
slow
fast
5 × T – 5
95
55
—
—
70
—
—
—
51.8
—
—
—
ns
ns
RP
C
1
3 × T – 5
C
2
Refresh Cycle
86 CAS Assertion to RAS
Assertion on Refresh
Cycle
T
T
T – 7
13
—
8
—
4.4
—
ns
CSR
C
87 RAS Assertion to CAS
Deassertation on
slow
fast
7 × T – 15 125
—
—
91
—
—
—
64.5
—
—
—
ns
ns
CHR
RPC
OFF
C
1
5 × T – 15 85
C
Refresh Cycle
88 RAS Deassertation to
CAS Assertion on a
Refresh Cycle
t
t
slow
5 × T – 11 89
—
—
65
—
—
—
45.8
—
—
—
ns
ns
C
1
fast
3 × T – 11 49
C
89 CAS Deassertation to
Data Not Valid
0
0
—
0
—
0
—
ns
Note:
1. Fast mode is not available for operating frequencies above 50 MHz.
2. This happens when a Refresh Cycle is followed by an Access Cycle.
2-16
DSP56007/D
MOTOROLA
Specifications
External Memory Interface (EMI) SRAM Timing
83
81
84
87
85
MRAS
88
82
MCAS
86
89
MD0–MD7
Data In
AA0266
Figure 2-12 CAS before RAS Refresh Cycle
EXTERNAL MEMORY INTERFACE (EMI) SRAM TIMING
(C = 50pF + 2 TTL Loads)
L
Table 2-10 External Memory Interface (EMI) SRAM Timing
50 MHz 66 MHz 88 MHz
Min Max Min Max Min Max
No.
Characteristics
Symbol
t , t
Expression
Unit
91
4 × T – 11 +
69
—
50
—
34.5
—
ns
Address Valid and CS
Assertion Pulse Width
RC WC
C
Ws × T
C
92 Address Valid to RD or WR
Assertion
t
T + T – 13
17
35
29
4
—
—
—
—
55
25
—
10
23
19
2
—
—
—
—
38
15
—
4.4
17.7
11.7
0.1
—
—
—
—
—
ns
ns
ns
ns
AS
C
L
93 RD or WR Assertion Pulse
Width
t
2 × T – 5 +
WP
C
Ws × T
C
94 RD or WR Deassertation to
RD or WR Assertion
—
2 × T – 11
C
95 RD or WR Deassertation to
Address not Valid
t
T – 6
WR
H
96 Address Valid to Input Data
Valid
t
, t
3 × T + T –15 +
—
—
0
—
—
0
24.8 ns
AA AC
C
L
Ws × T
C
97 RD Assertion to Input Data
Valid
t
2 × T – 15 +
—
7.7
—
ns
ns
OE
C
Ws × T
C
98 RD Deassertation to Data
Not Valid (Data Hold Time)
t
0
0
OHZ
MOTOROLA
DSP56007/D
2-17
Specifications
External Memory Interface (EMI) SRAM Timing
Table 2-10 External Memory Interface (EMI) SRAM Timing
50 MHz 66 MHz 88 MHz
Min Max Min Max Min Max
No.
Characteristics
Symbol
, t
Expression
Unit
ns
99 Address Valid to WR
Deassertation
T
3 × T + T –14 + 56
—
—
—
39
18
2
—
—
—
25.8
12.0
0.1
—
—
—
9.7
CW AW
C
L
Ws × T
C
100 Data Setup Time to WR
Deassertation
t
(t
)
T + T – 5 +
25
4
ns
DS DW
C
L
Ws × T
C
101 Data Hold Time from WR
Deassertation
t
T – 6
ns
DH
H
102 WR Assertion to Data Valid
103 WR Deassertation to Data
—
—
T + 4
—
—
14
20
—
—
12
18
—
—
ns
H
T + 10
15.7 ns
H
1
high impedance
104 WR Assertion to Data
Active
—
T – 6
4
—
2
—
0.1
—
ns
H
Note:
1. This value is periodically sampled and not 100% tested.
MA0–MA14
MA15/MCS3
91
MA16/MCS2/MCAS
MA17/MCS1/MRAS
MCS0
92
95
94
93
RD
94
98
WR
97
96
Data In
MD0–MD7
AA0267
Figure 2-13 SRAM Read Cycle
2-18
DSP56007/D
MOTOROLA
Specifications
External Memory Interface (EMI) SRAM Timing
MA0–MA14
MA15/MCS3
91
MA16/MCS2/MCAS
MA17/MCS1/MRAS
MCS0
99
95
93
92
WR
94
94
RD
100
102
103
Data Out
MD0–MD7
104
101
AA0268
Figure 2-14 SRAM Write Cycle
MOTOROLA
DSP56007/D
2-19
Specifications
Serial Audio Interface (SAI) Timing
SERIAL AUDIO INTERFACE (SAI) TIMING
(C = 50pF + 2 TTL Loads)
L
Table 2-11 Serial Audio Interface (SAI) Timing
50 MHz 66 MHz 81 MHz
Min Max Min Max Min Max
No.
Characteristics
Mode
Expression
Unit
111 Minimum Serial Clock Cycle = master
(min) slave
4 × T
80
65
—
—
61
51
—
—
45.5
39.1
—
—
ns
ns
C
t
3 × T + 5
SAICC
C
112 Serial Clock High Period
113 Serial Clock Low Period
114 Serial Clock Rise/ Fall Time
master 0.5 × t
– 8
32
23
—
—
22
18
—
—
14.7
13.7
—
—
ns
ns
SAICC
slave
0.35 × t
SAICC
master 0.5 × t
– 8
32
23
—
—
22
18
—
—
14.8
13.7
—
—
ns
ns
SAICC
slave
0.35 × t
SAICC
master
slave
8
—
—
8
10
—
—
8
8
—
—
8.0 ns
5.9 ns
0.15 × t
SAICC
115 Data In Valid to SCKR edge
(Data In Set-up Time)
master
slave
26
4
26
4
—
—
26
4
—
—
26
4
—
—
ns
ns
116 SCKR Edge to Data In Not
Valid (Data In Hold Time)
master
slave
0
14
0
14
—
—
0
14
—
—
0
14
—
—
ns
ns
117 SCKR Edge to Word Select Out master
Valid (WSR Out Delay Time)
20
12
12
—
12
12
20
—
—
—
12
12
20
—
—
—
12
12
20
—
—
ns
ns
ns
118 Word Select In Valid to SCKR
Edge (WSR In Set-up Time)
slave
119 SCKR Edge to Word Select In
Not Valid (WSR In Hold Time)
slave
121 SCKT Edge to Data Out Valid
(Data Out Delay Time)
master
13
40
T + 34
—
—
—
13
40
44
—
—
—
13
40
41
—
—
—
13
40
39.7 ns
ns
ns
1
slave
2
slave
H
122 SCKT Edge to Word Select Out master
Valid (WST Out Delay Time)
19
12
12
—
12
12
19
—
—
—
12
12
19
—
—
—
12
12
19
—
—
ns
ns
ns
123 Word Select In Valid to SCKT
Edge (WST In Set-up Time)
slave
124 SCKT Edge to Word Select In
Not Valid (WST In Hold Time)
slave
Note:
1. When the Frequency Ratio between Parallel and Serial clocks is 1:4 or greater
2. When the Frequency Ratio between Parallel and Serial clocks is 1:3 – 1:4
2-20
DSP56007/D
MOTOROLA
Specifications
Serial Audio Interface (SAI) Timing
111
112
113
114
114
114
113
SCKR
(RCKP = 1)
111
114
SCKR
(RCKP = 0)
112
115
116
SDI0–SDI1
(Data Input)
Valid
119
118
WSR
(Input)
Valid
117
WSR
(Output)
AA0269
Figure 2-15 SAI Receiver Timing
MOTOROLA
DSP56007/D
2-21
Specifications
Serial Audio Interface (SAI) Timing
111
112
113
114
114
114
114
113
112
SCKT
(T KP = 1)
C
111
SCKT
(T KP = 0)
C
121
SDO0–SDO2
(Data Output)
124
123
WST
(Input)
Valid
122
WST
(Output)
AA0270
Figure 2-16 SAI Transmitter Timing
2-22
DSP56007/D
MOTOROLA
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
SERIAL HOST INTERFACE (SHI) SPI PROTOCOL TIMING
(C = 50 pF; V
= 0.7 × V , V = 0.3 × V
)
CC
L
IHS
CC
ILS
Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing
50 MHz
66 MHz
88 MHz
Filter
Mode
No.
Characteristics
Mode
Expression
Unit
Min Max Min Max Min Max
Tolerable Spike Width
on Clock or Data In
bypassed
narrow
wide
—
—
—
0
20
100
—
—
—
0
20
100
—
—
—
0
20
100 ns
ns
ns
141 Minimum Serial Clock
Cycle = t (min)
SPICC
For frequency below 33
1
MHz
master bypassed
4 × T
—
—
—
—
—
—
ns
C
For frequency above 33
1
MHz
bypassed
narrow
wide
6 × T
1000
2000
3 × T
120
1000
2000
60
—
—
—
—
—
—
—
—
—
91
1000
2000
45
—
—
—
—
—
—
—
—
—
68.2
1000
2000
34.1
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
2
CPHA = 0, CPHA = 1
slave bypassed
narrow
wide
slave bypassed
narrow
C
3 × T + 25
85
70
59.1
C
CPHA = 1
3 × T + 85
145
139
491
1082
130
124
476
1067
119.1
113.1
465.1
1056.1
C
3 × T + 79
C
3 × T + 431
C
wide
3 × T + 1022
C
142 Serial Clock High Period master
0.5 × t
–10
50
—
35
—
24.1
—
ns
SPICC
2
CPHA = 0, CPHA = 1
slave bypassed
T + 8
28
51
63
70
246
541
—
—
—
—
—
—
23
46
58
63
239
534
—
—
—
—
—
—
19.4
42.4
54.4
57.0
233.0
528.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
C
narrow
wide
slave bypassed
narrow
T + 31
C
CPHA = 1
T + 43
C
T + T + 40
C
H
T + T + 216
C
H
wide
T + T + 511
C
H
143 Serial Clock Low Period master
0.5 × t
–10
50
—
35
—
24.1
—
ns
SPICC
2
CPHA = 0, CPHA = 1
slave bypassed
T + 8
28
51
63
70
246
541
—
—
—
—
—
—
23
46
58
63
239
534
—
—
—
—
—
—
19.4
42.4
54.4
57.0
233.0
528.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
C
narrow
wide
slave bypassed
narrow
T + 31
C
CPHA = 1
T + 43
C
T + T + 40
C
H
T + T + 216
C
H
wide
T + T + 511
C
H
144 Serial Clock Rise/ Fall
Time
master
slave
10
2000
—
—
10
2000
—
—
10
2000
—
—
10
ns
2000 ns
MOTOROLA
DSP56007/D
2-23
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued)
50 MHz
66 MHz
88 MHz
Filter
Mode
No.
Characteristics
Mode
Expression
T + T + 35
Unit
Min Max Min Max Min Max
146 SS Assertion to First
SCK Edge CPHA = 0
slave bypassed
narrow
wide
slave bypassed
narrow
65
65
65
6
0
0
—
—
—
—
—
—
58
58
58
6
—
—
—
—
—
—
52.0
52.0
52.0
6
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
C
H
T + T + 35
C
H
T + T + 35
C H
CPHA = 1
6
0
0
0
0
0
0
wide
147 Last SCK Edge to SS Not slave bypassed
T + 6
26
90
217
2
66
193
—
—
—
—
—
—
21
85
212
2
66
193
—
—
—
—
—
—
17.4
81.4
208.4
2
66
193
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
C
Asserted
CPHA = 0
CPHA = 1
narrow
wide
slave bypassed
narrow
T + 70
C
T + 197
C
3
2
66
193
wide
148 Data In Valid to SCK
Edge (Data In Set-up
Time)
master bypassed
0
0
—
—
0
22
—
—
0
25.6
—
—
ns
ns
narrow MAX {(37 –T ), 0} 17
C
MAX {(52 –T ), 0}
C
wide
0
32
—
37
—
40.6
—
ns
MAX {(38 –T ), 0}
C
slave bypassed MAX {(53 –T ), 0}
0
18
—
—
0
23
—
—
0
26.6
—
—
ns
ns
C
narrow
wide
33
—
38
—
41.6
—
ns
149 SCK Edge to Data In Not master bypassed
2 × T + 17
57
58
68
57
58
68
—
—
—
—
—
—
47
48
58
47
48
58
—
—
—
—
—
—
39.7
40.7
50.7
39.7
40.7
50.7
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
C
Valid
(Data In Hold Time)
narrow
wide
2 × T + 18
C
2 × T + 28
C
slave bypassed
narrow
2 × T + 17
C
2 × T + 18
C
wide
2 × T + 28
C
150 SS Assertion to Data Out slave
Active
4
4
—
4
—
4
—
24
41
214 ns
504 ns
41
214 ns
504 ns
57.0 ns
233 ns
528 ns
ns
ns
ns
151 SS Deassertation to Data slave
24
—
24
—
24
—
4
high impedance
152 SCK Edge to Data Out
Valid (Data Out Delay
Time)
master bypassed
41
214
504
41
214
504
—
—
—
—
—
—
—
—
—
41
214
504
41
214
504
70
—
—
—
—
—
—
—
—
—
41
214
504
41
214
504
63
—
—
—
—
—
—
—
—
—
narrow
wide
2
CPHA = 0, CPHA = 1
slave bypassed
narrow
ns
wide
CPHA = 1
slave bypassed
narrow
T + T + 40
C H
T + T + 216
246
541
239
534
C
H
wide
T + T + 511
C H
2-24
DSP56007/D
MOTOROLA
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued)
50 MHz
66 MHz
88 MHz
Filter
Mode
No.
Characteristics
Mode
Expression
Unit
Min Max Min Max Min Max
153 SCK Edge to Data Out
Not Valid
master bypassed
narrow
wide
slave bypassed
narrow
0
57
163
0
57
163
0
57
163
0
57
163
—
—
—
—
—
—
0
57
163
0
57
163
—
—
—
—
—
—
0
57
163
0
57
163
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
(Data Out Hold Time)
wide
154 SS Assertion to Data Out slave
Valid CPHA = 0
T + T + 35
—
65
—
58
—
52.0 ns
C
H
157 First SCK Sampling
Edge to HREQ Output
Deassertation
slave bypassed 3 × T + T + 32
—
—
—
102
279
577
—
—
—
85
262
560
—
—
—
71.8 ns
248.8 ns
546.8 ns
C
H
narrow 3 × T + T + 209
C
H
wide
3 × T + T + 507
C H
158 Last SCK Sampling Edge slave bypassed 2 × T + T + 6
56
—
—
—
44
101
207
—
—
—
34.4
91.4
197.4
—
—
—
ns
ns
ns
C
H
to HREQ Output Not
narrow
2 × T + T + 63 113
C
H
Deasserted
wide
2 × T + T + 169 219
C
H
CPHA = 1
159 SS Deassertation to
HREQ Output Not
Deasserted
slave
2 × T + T + 7
57
45
35.4
ns
C
H
CPHA = 0
160 SS Deassertation Pulse
Width CPHA = 0
slave
T + 4
24
106
0
—
—
—
19
82
0
—
—
—
15.4
62.8
0
—
—
—
ns
ns
ns
C
161 HREQ In Assertion to
First SCK Edge
master
0.5 × t
+
SPICC
2 × T + 6
C
162 HREQ In Deassertation master
to Last SCK Sampling
0
Edge (HREQ In Set-up
Time) CPHA = 1
163 First SCK Edge to HREQ master
In Not Asserted
0
0
—
0
—
0
—
ns
(HREQ In Hold Time)
Note:
1. For an Internal Clock frequency below 33 MHz, the minimum permissible Internal Clock to Serial Clock frequency
ratio is 4:1. For an Internal Clock frequency above 33 MHz, the minimum permissible Internal Clock to Serial
Clock frequency ratio is 6:1.
2. In CPHA = 1 mode, the SPI slave supports data transfers at t
= 3 × T , if the user assures that the HTX is
SPICC
C
written at least T ns before the first edge of SCK of each word.In CPHA = 1 mode, the SPI slave supports data
C
transfers at t
SCK of each word.
= 3 × T , if the user assures that the HTX is written at least T ns before the first edge of
SPICC
C
C
3. When CPHA = 1, the SS line may remain active low between successive transfers.
4. Periodically sampled, not 100% tested
5. Refer to the DSP56007 User’s Manual for a detailed description of how to use the different filtering
modes.
MOTOROLA
DSP56007/D
2-25
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
SS
(Input)
143
142
141
141
144
144
144
144
SCK (CPOL = 0)
(Output)
142
143
SCK (CPOL = 1)
(Output)
148
149
148
149
MISO
(Input)
MSB
Valid
LSB
Valid
152
MSB
153
MOSI
(Output)
LSB
161
163
HREQ
(Input)
AA0271
Figure 2-17 SPI Master Timing (CPHA = 0)
2-26
DSP56007/D
MOTOROLA
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
SS
(Input)
143
142
141
142
143
144
144
144
144
SCK (CPOL = 0)
(Output)
141
SCK (CPOL = 1)
(Output)
148
148
149
149
MISO
(Input)
MSB
Valid
LSB
Valid
152
153
MOSI
(Output)
MSB
LSB
161
162
163
HREQ
(Input)
AA0272
Figure 2-18 SPI Master Timing (CPHA = 1)
MOTOROLA
DSP56007/D
2-27
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
SS
(Input)
143
142
141
141
147
144
144
144
144
160
SCK (CPOL = 0)
(Input)
146
154
142
143
SCK (CPOL = 1)
(Input)
152
153
153
151
LSB
150
MISO
(Output)
MSB
148
148
149
149
MSB
Valid
MOSI
(Input)
LSB
Valid
157
159
HREQ
(Output)
AA0273
Figure 2-19 SPI Slave Timing (CPHA = 0)
2-28
DSP56007/D
MOTOROLA
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
SS
(Input)
143
141
147
142
144
144
144
SCK (CPOL = 0)
(Input)
146
142
144
143
152
SCK (CPOL = 1)
(Input)
152
153
151
150
MISO
(Output)
MSB
LSB
148
148
149
149
MSB
Valid
LSB
Valid
MOSI
(Input)
157
158
HREQ
(Output)
AA0274
Figure 2-20 SPI Slave Timing (CPHA = 1)
MOTOROLA
DSP56007/D
2-29
Specifications
2
Serial Host Interface (SHI) I C Protocol Timing
SERIAL HOST INTERFACE (SHI) I2C PROTOCOL TIMING
(V
(V
= 0.7 × V , V = 0.3 × V
)
CC
IHS
CC
ILS
= 0.8 × V , V
= 0.2 × V
)
CC
OHS
CC
OLS
(R (min) = 1.5 kΩ)
P
2
Table 2-13 SHI I C Protocol Timing
2
Standard I C
(C = 400 pF, R = 2 kΩ, 100 kHz)
L
P
All frequencies
No.
Characteristics
Symbol
Unit
Min
Max
—
Tolerable Spike Width on SCL or SDA
Filters Bypassed
—
—
—
0
20
100
ns
ns
ns
Narrow Filters Enabled
Wide Filters Enabled
171 Minimum SCL Serial Clock Cycle
172 Bus Free Time
t
t
10.0
4.7
4.7
4.0
4.7
4.0
—
—
—
—
—
—
—
1.0
0.3
—
—
3.4
—
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
SCL
BUF
173 Start Condition Set-up Time
174 Start Condition Hold Time
175 SCL Low Period
t
SU;STA
t
HD;STA
t
LOW
176 SCL High Period
t
HIGH
177 SCL and SDA Rise Time
178 SCL and SDA Fall Time
179 Data Set-up Time
t
r
t
—
f
t
250
0.0
—
SU;DAT
180 Data Hold Time
t
t
HD;DAT
VD;DAT
182 SCL Low to Data Out Valid
183 Stop Condition Set-up Time
t
4.0
SU;STO
Note: Refer to the DSP56007 User’s Manual for a detailed description of how to use the different filtering
modes.
2-30
DSP56007/D
MOTOROLA
Specifications
Serial Host Interface (SHI) I C Protocol Timing
2
2
The Programmed Serial Clock Cycle, t
, is specified by the value of the HDM5–
I CCP
HDM0 and HRS bits of the HCKR (SHI Clock control Register).
2
The expression for t
is:
I CCP
tI2CCP = [Tc × 2 × (HDM[5:0] + 1) × (7 × (1 – HRS) + 1)]
where
•
HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divide-by-
eight prescaler is operational. When HRS is set, the prescaler is bypassed.
•
HDM5–HDM0 are the Divider Modulus Select bits.
•
A divide ratio from 1 to 64 (HDM5–HDM0 = 0 to $3F) may be selected.
2
In I C mode, you may select a value for the Programmed Serial Clock Cycle from
6 × T
(HDM5–HDM0 = 2, HRS = 1)
to
C
1024 × T
(HDM5–HDM0 = $3F, HRS = 0).
C
2
The DSP56007 provides an improved I C bus protocol. In addition to supporting the
2
2
100 kHz I C bus protocol, the SHI in I C mode supports data transfers at up to 1000
kHz. The actual maximum frequency is limited by the bus capacitances (C ),the pull-
L
up resistors (R ), (which affect the rise and fall time of SDA and SCL, (see table
P
below)), and by the input filters.
Consideration for programming the SHI Clock Control Register (HCKR)—Clock
Divide Ratio: the master must generate a bus free time greater than T172 slave when
2
operating with a DSP56007 SHI I C slave.
The table below describes a few examples:
Table 2-14 Considerations for Programming the SHI Clock control Register (HCKR)
Conditions to be Considered
Resulting Limitations
Master
Slave
Oper-
ating
Freq.
Min.
Perm-
Master
Filter
Mode
Slave
Filter
Mode
Maximum
I C Serial
Frequency
Oper-
ating
Freq.
T172
Slave
T172
Master
2
Bus Load
issible
2
t
I CCP
C = 50 pF, 88 MHz 88 MHz Bypassed Bypassed 36 ns
56 × T
60 × T
66 × T
41 ns
66 ns
103 ns
1010 kHz
825 kHz
634 kHz
L
C
R = 2 kΩ
Narrow
Wide
Narrow 60 ns
Wide 95 ns
P
C
C
MOTOROLA
DSP56007/D
2-31
Specifications
Serial Host Interface (SHI) I C Protocol Timing
2
Example: for C = 50 pF, R = 2 kΩ, f = 88 MHz, Bypassed Filter mode: The master,
L
P
2
when operating with a DSP56007 SHI I C slave with an 88 MHz operating frequency,
must generate a bus free time greater than 36 ns (T172 slave). Thus, the minimum
2
permissible t
is 56 × T which gives a bus free time of at least 41 ns (T172 master).
C
I CCP
2
This implies a maximum I C serial frequency of 1010 kHz.
In general, bus performance may be calculated from the C and R of the bus, the
L
P
Input Filter modes and operating frequencies of the master and the slave. Table 2-15
contains the expressions required to calculate all relevant performance timing for a
given C and R .
L
P
2
Table 2-15 SHI Improved I C Protocol Timing
2
Improved I C (C = 50 pF, R = 2 kΩ)
L
P
2
3
4
50 MHz
66 MHz
88 MHz
U
n
i
Filter
Mode
No.
Char.
Sym. Mode
Expression
Min Max Min Max Min Max
t
— Tolerable Spike
Width on SCL or
SDA
bypassed
narrow
wide
0
20
100
—
—
—
0
20
100
—
—
—
0
20
100
—
—
—
0
ns
20 ns
100 ns
2
171 SCL Serial Clock
Cycle
t
master bypassed
narrow
t
+ 3 × T + 1050
—
—
—
—
—
—
1007
1225
1591
478
—
—
—
—
—
—
981
1199
1557
461
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
SCL
I CCP
C
72 + t
r
2
t
t
+ 3 × T + 1263
I CCP
C
245 + t
wide
+ 3 ×rT + 1593
2
I CCP
C
535 + t
r
bypassed
slave
4 × T + T +
500
694
976
C
H
172 + t
r
narrow
4 × T + T +
672
655
C
H
366 + t
r
wide
4 × T + T +
954
937
C
H
648 + t
r
2
172 Bus Free Time
t
master bypassed
narrow
0.5 × t
0.5 × t
0.5 × t
–
–
–
60
80
—
—
—
46
68
—
—
—
38.2
60.9
95
—
—
—
ns
ns
ns
BUF
I CCP
42 – t
r
2
I CCP
42 – t
r
2
wide
100
102
I CCP
42 – t
r
slave
slave
bypassed
narrow
wide
2 × T + 11
51
75
110
—
—
—
41
65
100
—
—
—
33.7
57.7
92.7
—
—
—
ns
ns
ns
C
2 × T + 35
C
2 × T + 70
C
173 Start Condition
Set-up Time
t
bypassed
narrow
wide
12
50
150
12
50
150
—
—
—
12
50
150
—
—
—
12
50
150
—
—
—
ns
ns
ns
SU;STA
2-32
DSP56007/D
MOTOROLA
Specifications
Serial Host Interface (SHI) I C Protocol Timing
2
2
Table 2-15 SHI Improved I C Protocol Timing (Continued)
2
Improved I C (C = 50 pF, R = 2 kΩ)
L
P
2
3
4
50 MHz
66 MHz
88 MHz
U
n
i
Filter
Mode
No.
Char.
Sym. Mode
Expression
Min Max Min Max Min Max
t
2
174 Start Condition
Hold Time
t
master bypassed
narrow
0.5 × t
0.5 × t
0.5 × t
+
332
352
372
—
—
—
318
340
378
—
—
—
310
333
367
—
—
—
ns
ns
ns
HD;STA
I CCP
12 – t
f
2
+
+
I CCP
12 – t
f
2
wide
I CCP
12 – t
f
slave
bypassed 2 × T + T + 21 71
—
—
—
59
138
238
—
—
—
49.4
128
228
—
—
—
ns
ns
ns
C
H
narrow
2 × T + T + 100 150
C
H
wide
2 × T + T + 200 250
C
H
2
175 SCL Low Period
176 SCL High Period
177 SCL Rise Time
t
master bypassed
narrow
0.5 × t
+
+
+
338
358
378
352
—
—
—
—
—
—
324
346
384
—
—
—
—
—
—
316
339
373
—
—
—
ns
ns
ns
LOW
I CCP
18 – t
f
2
0.5 × t
I CCP
18 – t
f
2
wide
0.5 × t
I CCP
18 – t
2 × T + 74 + t
2 × T + 286 + t 564
f
slave
bypassed
narrow
wide
342
554
854
335
534
847
—
—
—
ns
ns
ns
C
r
C
r
2 × T + 586 + t 864
C
r
2
t
master bypassed 0.5 × t
+ 2 × 379
—
—
—
375
523
773
—
—
—
360
507
754
—
—
—
ns
ns
ns
HIGH
I CCP
T + 19
C
2
narrow
wide
0.5 × t
+
544
776
49
I CCP
2 × T + 144
C
2
0.5 × t
+
I CCP
2 × T + 356
2 × T + T – 1
2 × T + T + 18 68
C
slave
bypassed
narrow
wide
—
—
—
37
56
68
—
—
—
27.4
46.4
58.4
—
—
—
ns
ns
ns
C
H
C
H
2 × T + T + 30 80
C
H
t
t
r
f
1
Output
1.7 × R ×
(C + 20)
—
—
238
—
—
238
—
—
238 ns
2000 ns
P
L
Input
2000
2000
2000
178 SCL Fall Time
1
Output
20 + 0.1 ×
(C – 50)
—
—
20
—
—
20
—
—
20 ns
L
Input
2000
2000
2000
2000 ns
179 Data Set-up Time t
bypassed
narrow
wide
T + 8
28
80
94
—
—
—
23
75
89
—
—
—
19.4
71.4
85.4
—
—
—
ns
ns
ns
SU;DAT
C
T + 60
C
T + 74
C
MOTOROLA
DSP56007/D
2-33
Specifications
Serial Host Interface (SHI) I C Protocol Timing
2
2
Table 2-15 SHI Improved I C Protocol Timing (Continued)
2
Improved I C (C = 50 pF, R = 2 kΩ)
L
P
2
3
4
50 MHz
66 MHz
88 MHz
U
n
i
Filter
Mode
No.
Char.
Sym. Mode
Expression
Min Max Min Max Min Max
t
180 Data Hold Time
t
bypassed
narrow
wide
0
0
0
0
0
0
—
—
—
0
0
0
—
—
—
0
0
0
—
—
—
ns
ns
ns
HD;DAT
182 SCL Low to Data t
Out Valid
bypassed
narrow
wide
2 × T + 71 + t
—
—
—
349
522
813
—
—
—
339
512
803
—
—
—
332 ns
505 ns
796 ns
VD;DAT
C
r
2 × T + 244 + t
C
r
r
2 × T + 535 + t
C
2
183 Stop Condition
Set-up Time
t
master bypassed
narrow
0.5 × t
+
381
459
613
—
—
—
359
440
592
—
—
—
346
427
575
—
—
—
ns
ns
ns
SU;STO
I CCP
T + T + 11
C
H
2
0.5 × t
+
I CCP
T + T + 69
C
H
2
wide
0.5 × t
+
I CCP
T + T + 183
C
H
slave
bypassed
narrow
wide
11
50
150
11
50
150
—
—
—
11
50
150
—
—
—
11
50
150
—
—
—
ns
ns
ns
184 HREQ In
Deassertation to
Last SCL Edge
(HREQ In Set-up
Time)
master bypassed
narrow
0
0
0
0
0
0
—
—
—
0
0
0
—
—
—
0
0
0
—
—
—
ns
ns
ns
wide
186 First SCL
Sampling Edge
to HREQ Output
Deassertation
slave
slave
bypassed 3 × T + T + 32
—
—
—
102
279
577
—
—
—
85
262
560
—
—
—
72 ns
249 ns
547 ns
C
H
narrow
3 × T + T + 209
C
H
wide
3 × T + T + 507
C
H
187 Last SCL Edge to
HREQ Output
bypassed
narrow
wide
2 × T + T + 6
56
—
—
—
44
101
207
—
—
—
34.4
91.4
197.4
—
—
—
ns
ns
ns
C
H
2 × T + T + 63 113
C
H
Not Deasserted
2 × T + T + 169 219
C
H
2
188 HREQ In
Assertion to First
SCL Edge
master bypassed
narrow
t
t
t
+ 2 × T + 6 726
—
—
—
688
733
809
—
—
—
665
711
779
—
—
—
ns
ns
ns
I CCP
2
I CCP
2
C
+ 2 × T + 6 766
C
wide
+ 2 × T + 6 846
I CCP
C
189 First SCL Edge
to HREQ In Not
Asserted (HREQ
In Hold Time)
master
0
0
—
0
—
0
—
ns
2-34
DSP56007/D
MOTOROLA
Specifications
Serial Host Interface (SHI) I C Protocol Timing
2
2
Table 2-15 SHI Improved I C Protocol Timing (Continued)
2
Improved I C (C = 50 pF, R = 2 kΩ)
L
P
2
3
4
50 MHz
66 MHz
88 MHz
U
n
i
Filter
Mode
No.
Char.
Sym. Mode
Expression
Min Max Min Max Min Max
t
Note:
1. C is in pF, R is in kΩ, and result is in ns.
L
P
2
2. A t
of 34 × T (the maximum permitted for the given bus load) was used for the calculations in the
I CCP
C
Bypassed Filter mode.
A t
Narrow Filter mode.
A t
2
of 36 × T (the maximum permitted for the given bus load) was used for the calculations in the
I CCP
C
2
of 40 × T (the maximum permitted for the given bus load) was used for the calculations in the Wide
I CCP
C
Filter mode.
2
3. A t
of 43 × T (the maximum permitted for the given bus load) was used for the calculations in the
I CCP
C
Bypassed Filter mode.
A t
Narrow Filter mode.
A t
2
of 46 × T (the maximum permitted for the given bus load) was used for the calculations in the
I CCP
C
2
of 51 × T (the maximum permitted for the given bus load) was used for the calculations in the Wide
I CCP
C
Filter mode.
2
4. A t
of 56 × T (the maximum permitted for the given bus load) was used for the calculations in the
I CCP
C
Bypassed Filter mode.
A t
Narrow Filter mode.
A t
2
of 60 × T (the maximum permitted for the given bus load) was used for the calculations in the
I CCP
C
2
of 66 × T (the maximum permitted for the given bus load) was used for the calculations in the Wide
I CCP
C
Filter mode.
5. Refer to the DSP56007 User’s Manual for a detailed description of how to use the different filtering
modes.
171
173
176
175
SCL
SDA
177
180
178
172
179
MSB
LSB
ACK
Stop
Stop
Start
174
188
186
182
183
187
189
184
HREQ
AA0275
2
Figure 2-21 I C Timing
MOTOROLA
DSP56007/D
2-35
Specifications
General Purpose I/O (GPIO) Timing
GENERAL PURPOSE I/O (GPIO) TIMING
(C = 50 pF + 2 TTL Loads)
L
Table 2-16 GPIO Timing
50/66/88 MHz
No.
Characteristics
Expression
Unit
Min
Max
201 EXTAL Edge to GPIO Out Valid (GPIO Out Delay Time)
26
2
—
2
26
—
ns
ns
202 EXTAL Edge to GPIO Out Not Valid (GPIO Out Hold
Time)
203 GPIO In Valid to EXTAL Edge (GPIO In Set-up Time)
204 EXTAL Edge to GPIO In Not Valid (GPIO In Hold Time)
10
6
10
6
—
—
ns
ns
EXTAL
(Input)
(Note 1)
201
202
GPIO(0:3)
(Output)
203
204
GPIO(0:3)
(Input)
Valid
Note: 1. Valid when the ratio between EXTAL frequency and internal clock frequency equals 1
AA0276
Figure 2-22 GPIO Timing
2-36
DSP56007/D
MOTOROLA
Specifications
On-Chip Emulation (OnCE ) Timing
ON-CHIP EMULATION (OnCE ) TIMING
(C = 50 pF + 2 TTL Loads)
L
Table 2-17 OnCE Timing
50/66/88 MHz
Unit
No.
Characteristics
Min
Max
40
40
—
—
—
—
42
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
230
231
DSCK Low
DSCK High
232
233
234
235
236
237
238
239
240
241
DSCK Cycle Time
200
DR Asserted to DSO (ACK) Asserted
DSCK High to DSO Valid
5 T
C
—
3
DSCK High to DSO Invalid
DSI Valid to DSCK Low (Set-up)
DSCK Low to DSI Invalid (Hold)
Last DSCK Low to OS0–OS1, ACK Active
DSO (ACK) Asserted to First DSCK High
DSO (ACK) Assertion Width
15
3
3 T + T
C
L
2 T
C
4 T + T – 3
5 T + 7
C
H
C
DSO (ACK) Asserted to OS0–OS1 High
—
0
1
Impedance
242
243
244
OS0–OS1 Valid to EXTAL Transition #2
EXTAL Transition #2 to OS0–OS1 Invalid
T – 21
—
—
—
ns
ns
ns
C
0
Last DSCK Low of Read Register to First DSCK
High of Next Command
7 T + 10
C
245
246
Last DSCK Low to DSO Invalid (Hold)
3
—
ns
ns
DR Assertion to EXTAL Transition #2 for Wake
Up from WAIT State
10
T – 10
C
247
EXTAL Transition #2 to DSO After Wake Up from
WAIT State
17 T
—
ns
C
MOTOROLA
DSP56007/D
2-37
Specifications
On-Chip Emulation (OnCE ) Timing
Table 2-17 OnCE Timing (Continued)
50/66/88 MHz
No.
Characteristics
Unit
Min
Max
248
DR Assertion Width
•
•
to recover from WAIT
to recover from WAIT and enter Debug
mode
15
12 T – 15
ns
ns
C
13 T + 15
—
C
249
DR Assertion to DSO (ACK) Valid (Enter Debug
mode) After Asynchronous Recovery from WAIT
State
17 T
—
ns
C
2
250A DR Assertion Width to Recover from STOP
• Stable External Clock, OMR Bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17 = 1
15
15
15
65548 T + T
ns
ns
ns
C
L
20 T + T
C
L
L
13 T + T
C
250B DR Assertion Width to Recover from STOP and
2
enter Debug mode
• Stable External Clock, OMR Bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17 = 1
65549 T + T
—
—
—
ns
ns
ns
C
L
L
21 T + T
C
L
L
14 T + T
C
251
DR Assertion to DSO (ACK) Valid (Enter Debug
2
mode) After Recovery from STOP State
• Stable External Clock, OMR Bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17 = 1
65553 T + T
—
—
—
ns
ns
ns
C
25 T + T
C
L
L
18 T + T
C
Note:
1. Maximum T
L
2. Periodically sampled, not 100% tested
246
246
230
DSCK
(input)
231
232
AA0277
Figure 2-23 DSP56007 OnCE Serial Clock Timing
2-38
DSP56007/D
MOTOROLA
Specifications
On-Chip Emulation (OnCE ) Timing
DR
(Input)
233
240
DSO
(Output)
ACK
AA0278
Figure 2-24 DSP56007 OnCE Acknowledge Timing
DSCK
(Input)
(Last)
(OS1)
DSO
(Output)
(ACK)
(OS0)
236
237
238
DSI
(Input)
(Note 1)
Note: 1. High Impedance, external pull-down resistor
AA0279
Figure 2-25 DSP56007 OnCE Data I/O to Status Timing
DSCK
(Input)
(Last)
(Note 1)
(OS0)
234
235
245
DSO
(Output)
Note: 1. High Impedance, external pull-down resistor
AA0280
Figure 2-26 DSP56007 OnCE Read Timing
239
OS1
(Output)
(Note 1)
241
(DSCK Input)
240
DSO
(Output)
(DSO Output)
(DSI Input)
OS0
(Output)
(Note 1)
241
236
237
Note: 1. High Impedance, external pull-down resistor
AA0281
Figure 2-27 DSP56007 OnCE Data I/O Status Timing
MOTOROLA
DSP56007/D
2-39
Specifications
On-Chip Emulation (OnCE ) Timing
EXTAL
(Note 2)
242
OS0–OS1
(Output)
(Note 1)
243
Note: 1. High Impedance, external pull-down resistor
2. Valid when the ratio between EXTAL frequency and clock frequency equals 1
AA0282
Figure 2-28 DSP56007 OnCE EXTAL to Status Timing
DSCK
(Input)
(Next Command)
244
AA0283
Figure 2-29 DSP56007 OnCE DSCK Next Command After Read Register Timing
T0, T2
T1, T3
248
EXTAL
DR
(Input)
246
247
DSO
(Output)
AA0284
Figure 2-30 Synchronous Recovery from WAIT State
248
DR
(Input)
249
DSO
(Output)
AA0285
Figure 2-31 Asynchronous Recovery from WAIT State
2-40
DSP56007/D
MOTOROLA
Specifications
On-Chip Emulation (OnCE ) Timing
250
DR
(Input)
251
DSO
(Output)
AA0286
Figure 2-32 Asynchronous Recovery from STOP State
MOTOROLA
DSP56007/D
2-41
Specifications
On-Chip Emulation (OnCE ) Timing
2-42
DSP56007/D
MOTOROLA
SECTION 3
PACKAGING
PIN-OUT AND PACKAGE INFORMATION
This section provides information about the available packages for this product,
including diagrams of the package pinouts and tables describing how the signals
described in Section 1 are allocated. The DSP56007 is available in an 80-pin Quad
Flat Pack (QFP) package.
MOTOROLA
DSP56007/D
3-1
Packaging
Pin-out and Package Information
QFP Package Description
Top and bottom views of the QFP package are shown in Figure 3-1 and Figure 3-2
with their pin-outs.
41
61
V
DR
MD7
MD6
MD5
MD4
CCS
MODC/NMI
MODB/IRQB
MODA/IRQA
RESET
(Top View)
MISO/SDA
GND
D
GND
MD3
S
V
MD2
MD1
CCP
PCAP
GND
V
P
CCD
PINIT
MD0
GND
GND
Q
D
V
GPIO3
CCQ
EXTAL
SCK/SCL
MA0
GPIO2
GPIO1
GPIO0
MA1
MRD
Orientation Mark
MA2
MA3
GND
MWR
MA17/MCS1/MRAS
MA16/MCS2/MCAS
21
A
1
Note: An OVERBAR indicates the signal is asserted when the
voltage = ground (active low). To simplify locating the pins,
each fifth pin is shaded in the illustration.
Figure 3-1 Top View
3-2
DSP56007/D
MOTOROLA
Packaging
Pin-out and Package Information
41
61
DR
V
CCS
MD7
MD6
MD5
MD4
GND
MD3
MD2
MD1
V
MODC/NMI
MODB/IRQB
MODA/IRQA
RESET
(Bottom View)
MISO/SDA
D
GND
S
V
CCP
PCAP
GNDP
PINIT
CCD
MD0
GND
GPIO3
GPIO2
GPIO1
GPIO0
MRD
MWR
MA17/MCS1/MRAS
MA16/MCS2/MCAS
GND
D
Q
V
CCQ
EXTAL
SCK/SCL
MA0
MA1
MA2
MA3
GND
Orientation Mark
21
A
1
Note: An OVERBAR indicates the signal is asserted when the
voltage = ground (active low). To simplify locating the pins,
each fifth pin is shaded in the illustration.
Figure 3-2 Bottom View
MOTOROLA
DSP56007/D
3-3
Packaging
Pin-out and Package Information
Table 3-1 DSP56007 Pin Identification by Pin Number
Pin #
Signal Name
GND
Pin #
28
Signal Name
Pin #
55
Signal Name
WSR
1
V
CCQ
A
2
MCS0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GND
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
SDI1
Q
3
MA15/ MCS3
MA14
PINIT
GND
SDI0
4
DSO
P
5
MA13
PCAP
DSI/ OS0
DSCK/ OS1
DR
6
V
V
CCP
CCA
7
MA12
GND
S
8
GND
MISO/ SDA
RESET
MD7
A
9
V
MD6
CCQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
MODA/ IRQA
MODB/ IRQB
MODC/ NMI
MD5
Q
MA11
MA10
MA9
MD4
GND
MD3
MD2
MD1
D
V
CCS
MA8
MOSI/ HA0
SS/ HA2
HREQ
GND
MA7
A
V
CCD
V
GND
MD0
GND
CCA
S
MA6
MA5
MA4
GND
MA3
MA2
MA1
MA0
SDO2
SDO1
SDO0
D
GPIO3
GPIO2
GPIO1
GPIO0
MRD
V
A
CCS
SCKT
WST
SCKR
MWR
GND
MA17/ MCS1/
MRAS
Q
26
27
SCK/ SCL
EXTAL
53
54
V
80
MA16/ MCS2/
MCAS
CCQ
GND
S
3-4
DSP56007/D
MOTOROLA
Packaging
Pin-out and Package Information
Table 3-2 DSP56007 Pin Identification by Signal Name
Signal Name
Pin #
Signal Name
Pin #
Signal Name
Pin #
DR
DSCK
DSI
61
60
59
58
27
1
MA5
MA6
19
18
16
14
13
12
11
7
MRD
MWR
NMI
OS0
77
78
39
59
60
32
30
36
26
51
49
26
35
57
56
47
46
45
42
6
MA7
DSO
MA8
EXTAL
MA9
OS1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MA10
MA11
MA12
MA13
MA14
MA15
MA16
MA17
MCAS
MCS0
MCS1
MCS2
MCS3
MD0
PCAP
PINIT
RESET
SCK
A
A
A
A
D
D
P
8
15
21
66
72
31
10
29
52
34
44
54
76
75
74
73
41
42
43
37
38
25
24
23
22
20
5
4
SCKR
SCKT
SCL
3
80
79
80
2
SDA
Q
Q
Q
SDI0
SDI1
SDO0
SDO1
SDO2
SS
GND
GND
GND
79
80
3
S
S
S
GPIO0
GPIO1
GPIO2
GPIO3
HA0
71
69
68
67
65
64
63
62
35
37
38
39
41
79
MD1
V
V
V
CCA
CCA
CCD
MD2
17
70
33
9
MD3
MD4
V
CCP
CCQ
CCQ
CCQ
HA2
MD5
V
V
V
HREQ
IRQA
IRQB
MA0
MD6
28
53
40
48
55
50
MD7
MISO
MODA
MODB
MODC
MOSI
MRAS
V
V
CCS
CCS
MA1
WSR
WST
MA2
MA3
MA4
MOTOROLA
DSP56007/D
3-5
Packaging
Pin-out and Package Information
Table 3-3 DSP56007 Power Supply Pins
Pin #
Signal Name
Circuit Supplied
Address Bus Buffers
6
V
CCA
17
1
GND
A
D
Q
8
15
21
70
66
72
9
V
Data Bus Buffers
Internal Logic
CCD
GND
V
CCQ
28
53
10
29
52
33
31
40
48
34
44
54
GND
V
PLL
CCP
GND
P
S
V
Serial Ports
CCS
GND
3-6
DSP56007/D
MOTOROLA
Packaging
Pin-out and Package Information
L
60
41
61
40
B
P
B
-A-
-B-
L
B
V
-A,B,D-
DETAIL A
DETAIL A
21
80
F
1
20
-D-
A
M
S
S
S
0.20
0.05
C
A-B
A-B
D
D
A-B
J
N
S
H
S
M
0.20
D
M
E
M
S
S
0.20
C
A-B
D
DETAIL C
SECTION B-B
C
DATUM
-H-
PLANE
0.01
-C-
SEATING
PLANE
H
M
G
CASE 841B-01
ISSUE O
MILLIMETERS
DIM
A
B
C
D
E
MIN
13.90
13.90
2.15
MAX
14.10
14.10
2.45
U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
0.22
0.38
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
2.00
0.22
2.40
0.33
F
BOTTOM OF THE PARTING LINE.
T
G
H
J
K
L
M
N
P
0.65 BSC
4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT
-
0.25
0.23
0.95
DATUM PLANE -H-.
DATUM
PLANE
5. DIMENSIONS S AND V TO BE DETERMINED AT
0.13
0.65
-H-
R
SEATING PLANE -C-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
12.35 BSC
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
PER SIDE. DIMENSIONS A AND B DO
55
0.13
105
0.17
INCLUDE MOLD MISMATCH AND ARE DETERMINED
0.325 BSC
AT DATUM PLANE -H-.
Q
R
S
05
0.13
16.95
0.13
05
16.95
0.35
75
0.30
17.45
-
7. DIMENSION D DOES NOT INCLUDE DAMBAR
K
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
Q
W
T
X
U
V
W
X
-
17.45
0.45
DETAIL C
1.6 REF
Figure 3-3 80-pin Quad Flat Pack (QFP) Mechanical Information
MOTOROLA
DSP56007/D
3-7
Packaging
Ordering Drawings
ORDERING DRAWINGS
Complete mechanical information regarding DSP56007 packaging is available by
facsimile through Motorola's Mfax™ system. Call the following number to obtain
information by facsimile:
(602) 244-6591
The Mfax automated system requests the following information:
•
The receiving facsimile telephone number including area code or country
code
•
The caller’s Personal Identification Number (PIN)
Note: For first time callers, the system provides instructions for setting up a PIN,
which requires entry of a name and telephone number.
•
The type of information requested:
–
–
–
–
Instructions for using the system
A literature order form
Specific part technical information or data sheets
Other information described by the system messages
A total of three documents may be ordered per call.
The DSP56007 80-pin QFP package mechanical drawing is referenced as 841B-01.
3-8
DSP56007/D
MOTOROLA
SECTION 4
DESIGN CONSIDERATIONS
THERMAL DESIGN CONSIDERATIONS
An estimation of the chip junction temperature, T , in °C can be obtained from the
J
equation:
Equation 1: TJ = TA + (PD × RθJA
)
Where:
T = ambient temperature ˚C
A
R
= package junction-to-ambient thermal resistance ˚C/ W
θJA
P = power dissipation in package
D
Historically, thermal resistance has been expressed as the sum of a junction-to-case
thermal resistance and a case-to-ambient thermal resistance:
Equation 2: RθJA = RθJC + RθCA
Where:
R
R
R
= package junction-to-ambient thermal resistance ˚C/ W
= package junction-to-case thermal resistance ˚C/ W
= package case-to-ambient thermal resistance ˚C/ W
θJA
θJC
θCA
R
is device-related and cannot be influenced by the user. The user controls the
θJC
thermal environment to change the case-to-ambient thermal resistance, R
. For
θCA
example, the user can change the air flow around the device, add a heat sink, change
the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change
the thermal dissipation capability of the area surrounding the device on a PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow
is dissipated through the case to the heat sink and out to the ambient environment.
For ceramic packages, in situations where the heat flow is split between a path to the
case and an alternate path through the PCB, analysis of the device thermal
performance may need the additional modeling capability of a system level thermal
simulation tool.
MOTOROLA
DSP56007/D
4-1
Design Considerations
Thermal Design Considerations
The thermal performance of plastic packages is more dependent on the temperature
of the PCB to which the package is mounted. Again, if the estimations obtained from
do not satisfactorily answer whether the thermal performance is adequate, a
R
θJA
system level model may be appropriate.
A complicating factor is the existence of three common ways for determining the
junction-to-case thermal resistance in plastic packages:
•
•
•
To minimize temperature variation across the surface, the thermal resistance
is measured from the junction to the outside surface of the package (case)
closest to the chip mounting area when that surface has a proper heat sink.
To define a value approximately equal to a junction-to-board thermal
resistance, the thermal resistance is measured from the junction to where the
leads are attached to the case.
If the temperature of the package case (T ) is determined by a thermocouple,
T
the thermal resistance is computed using the value obtained by the equation
(T – T )/ P .
J
T
D
As noted above, the junction-to-case thermal resistances quoted in this data sheet are
determined using the first definition. From a practical standpoint, that value is also
suitable for determining the junction temperature from a case thermocouple reading
in forced convection environments. In natural convection, using the junction-to-case
thermal resistance to estimate junction temperature from a thermocouple reading on
the case of the package will estimate a junction temperature slightly hotter than
actual temperature. Hence, the new thermal metric, Thermal Characterization
Parameter or Ψ , has been defined to be (T – T )/ P . This value gives a better
JT
J
T
D
estimate of the junction temperature in natural convection when using the surface
temperature of the package. Remember that surface temperature readings of
packages are subject to significant errors caused by inadequate attachment of the
sensor to the surface and to errors caused by heat loss to the sensor. The
recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.
4-2
DSP56007/D
MOTOROLA
Design Considerations
Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate logic voltage level (e.g., either GND or V ).
CC
Use the following list of recommendations to assure correct DSP operation:
•
•
Provide a low-impedance path from the board power supply to each V
pin on the DSP, and from the board ground to each GND pin.
CC
Use at least four 0.01–0.1 µF bypass capacitors positioned as close as
possible to the four sides of the package to connect the V power source
CC
to GND.
•
Ensure that capacitor leads and associated printed circuit traces that
connect to the chip V and GND pins are less than 0.5 in per capacitor
CC
lead.
•
•
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers
for V and GND.
CC
Because the DSP output signals have fast rise and fall times, PCB trace
lengths should be minimal. This recommendation particularly applies to
the address and data buses as well as the IRQA, IRQB, and NMI pins.
Maximum Printed Circuit Board (PCB) trace lengths on the order of
6 inches are recommended.
•
•
Consider all device loads as well as parasitic capacitance due to PCB
traces when calculating capacitance. This is especially critical in systems
with higher capacitive loads that could create higher transient currents in
the V and GND circuits.
CC
All inputs must be terminated (i.e., not allowed to float) using CMOS
levels, except as noted in Section 1.
•
•
Take special care to minimize noise levels on the V
and GND pins.
CCP P
If multiple DSP56007 devices are on the same board, check for cross-talk
or excessive spikes on the supplies due to synchronous operation of the
devices.
MOTOROLA
DSP56007/D
4-3
Design Considerations
Power Consumption Considerations
POWER CONSUMPTION CONSIDERATIONS
Power dissipation is a key issue in portable DSP applications. Some of the factors
which affect current consumption are described in this section. Most of the current
consumed by CMOS devices is Alternating Current (AC), which is charging and
discharging the capacitances of the pins and internal nodes.
Current consumption is described by the formula:
Equation 3: I = C × V × f
where:
C = node/ pin capacitance in farads
V = voltage swing
f = frequency of node/ pin toggle in hertz
Example 4-1 Current Consumption
For an I/ O pin loaded with 50 pF capacitance, operating at 5.25 V, and with a 88 MHz clock,
toggling at its maximum possible rate (22 MHz), the current consumption is:
Equation 4: I = 50 × 10–12 × 5.25 × 22 × 106 = 5.78mA
The Maximum Internal Current (I max) value reflects the typical possible
CCI
switching of the internal buses on best-case operation conditions, which is not
necessarily a real application case. The Typical Internal Current (I
) value
CCItyp
reflects the average switching of the internal buses on typical operating conditions.
For applications that require very low current consumption:
•
•
•
•
•
Minimize the number of pins that are switching.
Minimize the capacitive load on the pins.
Connect the unused inputs to pull-up or pull-down resistors.
Disable unused peripherals.
Disable unused pin activity.
4-4
DSP56007/D
MOTOROLA
Design Considerations
Power Consumption Considerations
Current consumption test code:
org
p:RESET
jmp
MAIN
org
p:MAIN
movep #$180000,x:$FFFD
move
move
move
move
nop
#0,r0
#0,r4
#$00FF,m0
#$00FF,m4
rep
#256
move
rep
r0,x:(r0)+
#256
mov
clr
r4,y:(r4)+
a
move
rep
l:(r0)+,a
#30
mac
x0,y0,a
x:(r0)+,x0
y:(r4)+,y0
move
jmp
a,p:(r5)
TP1
TP1
nop
jmp
MAIN
MOTOROLA
DSP56007/D
4-5
Design Considerations
Power-Up Considerations
POWER-UP CONSIDERATIONS
To power-up the device properly, ensure that the following conditions are met:
•
Stable power is applied to the device according to the specifications in Table
2-3 (DC Electrical Characteristics).
•
•
The external clock oscillator is active and stable.
RESET is asserted according to the specifications in Table 2-7 (Reset, Stop,
Mode Select, and Interrupt Timing).
•
The following input pins are driven to valid voltage levels: DR, PINIT,
MODA, MODB, and MODC.
Care should be taken to ensure that the maximum ratings for all input voltages obey
the restrictions on Table 2-1 (Maximum Ratings), at all phases of the power-up
procedure. This may be achieved by powering the external clock, hardware reset, and
mode selection circuits from the same power supply that is connected to the power
supply pins of the chip.
At the beginning of the hardware reset procedure, the device might consume
significantly more current than the specified typical supply current. This is because of
contentions among the internal nodes being affected by the hardware reset signal
until they reach their final hardware reset state.
4-6
DSP56007/D
MOTOROLA
SECTION 5
ORDERING INFORMATION
Consult a Motorola Semiconductor sales office or authorized distributor to determine
product availability and to place an order.
Table 5-1 Ordering Information
Supply
Voltage
Frequency
(MHz)
Part
Package Type
Pin Count
Order Number
1
2
DSPB56007
5 V
Quad Flat Pack
(QFP)
80
50
66
88
50
66
88
DSPB56007FJ50
DSPB56007FJ66
DSPB56007FJ88
DSPE56007FJ50
DSPE56007FJ66
DSPE56007FJ88
DSPE56007
5 V
Quad Flat Pack
(QFP)
80
Note:
1. The DSPB56007 includes a generic factory-programmed ROM and may be used for RAM-based
applications. For additional information on future part development, or to request specific ROM-
based support, call your local Motorola Semiconductor sales office or authorized distributor.
2. The DSPE56007 includes factory-programmed ROM containing support for Dolby Pro Logic and
Lucasfilm THX applications. This part can be used only be customers licensed for Dolby Pro Logic
and Lucasfilm THX. To request specific support for this chip, call your local Motorola Semiconductor
sales office or authorized distributor.
MOTOROLA
DSP56007/D
5-1
OnCE, Mfax, and Symphony are trademarks of Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may
be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights
of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support life, or for any other application in which the
failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer
purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/Europe/Locations Not Listed:
Asia/Pacific:
Japan:
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P.O. Box 5405
Denver, Colorado 80217
303-675-2140
Motorola Semiconductors H.K. Ltd.
8B Tai Ping Industrial Park
51 Ting Kok Road
Tai Po, N.T., Hong Kong
852-26629298
Nippon Motorola Ltd.
Tatsumi-SPD-JLDC
6F Seibu-Butsuryu-Center
3-14-2 Tatsumi Koto-Ku
Tokyo 135, Japan
1 (800) 441-2447
81-3-3521-8315
Technical Resource Center:
1 (800) 521-6274
Mfax™:
RMFAX0@email.sps.mot.com
TOUCHTONE (602) 244-6609
US & Canada ONLY (800) 774-1848
Internet:
http://www.motorola-dsp.com
DSP Helpline
dsphelp@dsp.sps.mot.com
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