DSP56300AD_技术文档

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Technical Data

DSP56362/D

Rev. 3, 02/2004

24-Bit Audio Digital

Signal Processor

Motorola designed the DSP56362 to support digital audio applications requiring digital audio compression

and decompression, sound field processing, acoustic equalization, and other digital audio algorithms. The

DSP56362 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable

CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the

Motorola Symphony™ DSP family, as shown in Figure 1. This design provides a two-fold performance

increase over Motorola’s popular Symphony family of DSPs while retaining code compatibility. Significant

architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct

memory access (DMA). The DSP56362 offers 100 million instructions per second (MIPS) using an internal

100 MHz clock at 3.3 V.

2

16

12

5

Program RAM/

Instruction

Cache

3072 × 24

Program ROM

30K × 24

Bootstrap ROM

X Data

RAM

5632 × 24

ROM

6144 × 24

Host

Interface

DAX

(SPDIF)

Triple

Timer

SHI

ESAI

Y Data

RAM

5632 × 24

ROM

6144 × 24

Memory

Expansion

Area

192 × 24

Peripheral

Expansion Area

YAB

18

Address

External

Address

Bus

XAB

PAB

DAB

Generation

Unit

Address

Switch

Six Channel

DMA Unit

DRAM/SRAM

Bus

24-Bit

DSP56300

Core

11

Interface

&

Control

I - Cache

Control

DDB

YDB

XDB

PDB

GDB

External

Data Bus

Switch

24

Internal

Data

Bus

Data

Switch

Power

EXTAL

Clock

Generator

Mngmnt.

Data ALU

6

Program

Interrupt

Controller

Program

Decode

Controller

Program

Address

Generator

+

→

56-bit MAC

24

×

24 56

JTAG

OnCE

Two 56-bit Accumulators

56-bit Barrel Shifter

PLL

CLKOUT

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

PINIT/NMI

AA0456G

Figure 1 DSP56362 Block Diagram

This document contains information on a new product. Specifications and information herein are subject to change without notice.

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SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

PACKAGING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

POWER CONSUMPTION BENCHMARK. . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

IBIS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INDEX-I

FOR TECHNICAL ASSISTANCE:

Telephone:

1-800-521-6274

Email:

dsphelp@dsp.sps.mot.com

http://www.motorola-dsp.com

Internet:

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

“asserted”

“deasserted”

Examples:

Used to indicate a signal that is active when pulled low (For example, the RESET

pin is active when low.)

Means that a high true (active high) signal is high or that a low true (active low)

signal is low

Means that a high true (active high) signal is low or that a low true (active low)

signal is high

Signal/Symbol

Logic State

Signal State

Voltage*

True

False

True

Asserted

Deasserted

Asserted

V_IL/V_OL

V_IH/V_OH

V_IL/V_OL

False

Deasserted

Note:

*Values for V_IL, V_OL, V_IH, and V_OHare defined by individual product specifications.

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OVERVIEW

FEATURES

•

Multimode, multichannel decoder software functionality

–

Dolby Digital and Pro Logic

MPEG2 5.1

DTS

Bass management

Digital audio post-processing capabilities

–

3D Virtual surround sound

Lucasfilm THX5.1

Soundfield processing

Equalization

Digital Signal Processing Core

–

100 MIPS with a 100 MHz clock at 3.3 V +/- 5%

Object code compatible with the DSP56000 core

Highly parallel instruction set

Data arithmetic logic unit (ALU)

•

Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)

56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and

parsing)

•

Conditional ALU instructions

24-bit or 16-bit arithmetic support under software control

–

Program control unit (PCU)

•

Position independent code (PIC) support

Addressing modes optimized for DSP applications (including immediate offsets)

On-chip instruction cache controller

On-chip memory-expandable hardware stack

Nested hardware DO loops

Fast auto-return interrupts

Direct memory access (DMA)

•

Six DMA channels supporting internal and external accesses

One-, two-, and three- dimensional transfers (including circular buffering)

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Overview

Features

•

End-of-block-transfer interrupts

Triggering from interrupt lines and all peripherals

–

Phase-locked loop (PLL)

•

Software programmable PLL-based frequency synthesizer for the core clock

Allows change of low-power divide factor (DF) without loss of lock

Output clock with skew elimination

Hardware debugging support

•

On-Chip Emulation (OnCE‘) module

Joint Action Test Group (JTAG) test access port (TAP)

Address trace mode reflects internal program RAM accesses at the external port

•

On-Chip Memories

–

Modified Harvard architecture allows simultaneous access to program and data memories

30720 x 24-bit on-chip program ROM¹(disabled in 16-bit compatibility mode)

6144 x 24-bit on-chip X-data ROM¹

6144 x 24-bit on-chip Y-data ROM¹

Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable

.

Instruction

Cache

Switch

Mode

Program RAM

Size

Instruction

Cache Size

X Data RAM

Size

Y Data RAM

Size

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

3072 × 24-bit

2048 × 24-bit

5120 × 24-bit

4096 × 24-bit

0

5632 × 24-bit

3584 × 24-bit

1024 × 24-bit

0

1024 × 24-bit

–

192 x 24-bit bootstrap ROM (disabled in sixteen-bit compatibility mode)

•

Off-Chip Memory Expansion

–

Data memory expansion to 256K x 24-bit word memory for P, X, and Y memory using SRAM.

Data memory expansion to 16M x 24-bit word memory for P, X, and Y memory using DRAM.

External memory expansion port( twenty-four data pins for high speed external memory

access allowing for a large number of external accesses per sample)

–

Chip select logic for glueless interface to SRAMs

On-chip DRAM controller for glueless interface to DRAMs

Peripheral and Support Circuits

Enhanced serial audio interface (ESAI) includes:

–

•

Six serial data lines, 4 selectable as receive or transmit and 2 transmit only.

Master or slave capability

I²S, Sony, AC97, and other audio protocol implementations

1.These ROMs may be factory programmed with data or programs provided by the application developer.

2

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Overview

Documentation

–

Serial host interface (SHI) features:

•

SPI protocol with multi-master capability

I²C protocol with single-master capability

Ten-word receive FIFO

Support for 8-, 16-, and 24-bit words.

–

Byte-wide parallel host interface (HDI08) with DMA support

DAX features one serial transmitter capable of supporting S/PDIF, IEC958, IEC1937, CP-340,

and AES/EBU digital audio formats; alternate configuration supports up to two GPIO lines

–

Triple timer module with single external interface or GPIO line

On-chip peripheral registers are memory mapped in data memory space

•

Reduced Power Dissipation

–

Very low-power (3.3 V) CMOS design

Wait and stop low-power standby modes

Fully-static logic, operation frequency down to 0 Hz (dc)

Optimized power management circuitry (instruction-dependent, peripheral-dependent, and

mode-dependent)

Package

•

144-pin plastic thin quad flat pack (LQFP) surface-mount package

DOCUMENTATION

Table 1 lists the documents that provide a complete description of the DSP56362 and are required to

design properly with the part. Documentation is available from a local Motorola distributor, a Motorola

semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home

page on the Internet (the source for the latest information).

Table 1 DSP56362 Documentation

Document Name

Description

Order Number

DSP56300 Family Manual

Detailed description of the 56000-family

architecture and the 24-bit core processor and

instruction set

DSP56300FM/AD

DSP56362 User’s Manual

Detailed description of memory, peripherals,

and interfaces

DSP56362UM/AD

DSP56362/D

DSP56362 Advance Information Electrical and timing specifications; pin and

package descriptions

There is also a product brief for this chip.

DSP56362 Product Brief

Brief description of the chip

DSP56362P/D

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SECTION 1

SIGNAL/CONNECTION DESCRIPTIONS

SIGNAL GROUPINGS

The input and output signals of the DSP56362 are organized into functional groups, which are listed in

Table 1-1 and illustrated in Figure 1-1.

The DSP56362 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special

notice for this feature is added to the signal descriptions of those inputs.

Table 1-1 DSP56362 Functional Signal Groupings

Number of

Signals

Detailed

Functional Group

Description

20

19

4

Table 1-2

Table 1-3

Table 1-4

Table 1-5

Table 1-6

Table 1-7

Table 1-8

Table 1-9

Table 1-10

Table 1-11

Table 1-12

Table 1-13

Table 1-14

Power (V_CC

)

Ground (GND)

Clock and PLL

Address bus

Data bus

18

24

11

5

Port A¹

Port B²

Bus control

Interrupt and mode control

16

5

HDI08

SHI

Port C³

Port D⁴

12

2

ESAI

Digital audio transmitter (DAX)

Timer

1

6

JTAG/OnCE Port

Port A is the external memory interface port, including the external address bus, data bus, and

control signals.

Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals.

Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.

Port D signals are the GPIO port signals which are multiplexed with the DAX signals.

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Signal/Connection Descriptions

Signal Groupings

DSP56362

Power Inputs:

Non-

Multiplexed

Port B

GPIO

V

CCQH

PLL

Multiplexed Bus Bus

CCP

8

3

4

3

4

2

V

External I/O

Internal Logic

Address Bus

Data Bus

Bus Control

HDI08

H0–H7

HA0

HA1

HA2

HCS/HCS

Single DS

HRW

HDS/HDS

Single HR

HAD0–HAD7 PB0–PB7

V

HAS/HAS

HA8

HA9

HA10

PB8

CCQL

CCA

CCD

CCC

CCH

CCS

Host

Interface

(HDI08)

V

PB9

V

PB10

PB13

V

1

Port

V

Double DS

HRD/HRD

HWR/HWR

Double HR

2

V

SHI/ESAI/DAX/Timer

PB11

PB12

Grounds:

PLL

Internal Logic

Address Bus

Data Bus

Bus Control

HDI08

GNDP

HOREQ/HOREQ HTRQ/HTRQ PB14

HACK/HACK

GNDP1

4

HRRQ/HRRQ PB15

GND

Q

4

2

GND

A

D

C

2

SPI Mode

MOSI

SS

MISO

SCK

HREQ

I C Mode

HA0

GND

Serial

Host

Interface

(SHI)

HA2

GND

H

GND

2

SDA

SHI/ESAI/DAX/Timer

S

SCL

HREQ

EXTAL

CLKOUT

PCAP

Clock and

Port C GPIO

PC0

PLL

SCKR

FSR

PC1

PINIT/NMI

HCKR

SCKT

FST

PC2

PC3

Port A

PC4

Enhanced

Serial

18

External

A0–A17

D0–D23

HCKT

PC5

Address Bus

SDO5/SDI0 PC6

SDO4/SDI1 PC7

SDO3/SDI2 PC8

SDO2/SDI3 PC9

Audio

24

4

External

Data Bus

Interface

2

(ESAI)

AA0–AA3/

RAS0–RAS3

SDO1

SDO0

PC10

PC11

External

Bus

Control

CAS

RD

WR

TA

BR

BG

BB

Port D GPIO

PD0

Digital Audio

ACI

ADO

2

Transmitter (DAX)

PD1

Timer GPIO

2

TIO0

Timer 0

TIO0

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

TCK

TDI

TDO

TMS

TRST

DE

Interrupt/

Mode

Control

JTAG/

OnCE Port

AA0601

Notes:

1. The HDI08 port supports a nonmultiplexed or a multiplexed bus, single or double data strobe (DS), and single or

double host request (HR) configurations. Since each of these modes is configured independently, any

combination of these modes is possible. These HDI08 signals can also be configured alternately as GPIO

signals (PB0–PB15). Signals with dual designations (e.g., HAS/HAS) have configurable polarity.

2. The ESAI signals are multiplexed with the port C GPIO signals (PC0–PC11). The DAX signals are multiplexed

with the Port D GPIO signals (PD0–PD1). The timer 0 signal can be configured alternately as the timer GPIO

signal (TIO0).

Figure 1-1 Signals Identified by Functional Group

1-2

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Signal/Connection Descriptions

Power

POWER

Table 1-2 Power Inputs

Description

Power

Name

PLL Power—V_CCPis V_CCdedicated for PLL use. The voltage should be well-

V_CCP

regulated and the input should be provided with an extremely low impedance path

to the V_CCpower rail. There is one V_CCPinput.

Quiet Core (Low) Power—V_CCQLis an isolated power for the core processing

logic. This input must be tied externally to all other chip power inputs. The user

must provide adequate external decoupling capacitors. There are four V_CCQinputs.

V_CCQL(4)

V_CCQH(3)

Quiet External (High) Power—V_CCQHis a quiet power source for I/O lines. This

input must be tied externally to all other chip power inputs. The user must provide

adequate decoupling capacitors. There are three V_CCQHinputs.

Address Bus Power—V_CCAis an isolated power for sections of the address bus I/

O drivers. This input must be tied externally to all other chip power inputs. The user

must provide adequate external decoupling capacitors. There are three V_CCA

inputs.

V_CCA(3)

Data Bus Power—V_CCDis an isolated power for sections of the data bus I/O

drivers. This input must be tied externally to all other chip power inputs. The user

must provide adequate external decoupling capacitors. There are four V_CCDinputs.

V_CCD(4)

V_CCC(2)

V_CCH

Bus Control Power—V_CCCis an isolated power for the bus control I/O drivers.

This input must be tied externally to all other chip power inputs. The user must

provide adequate external decoupling capacitors. There are two V_CCCinputs.

Host Power—V_CCHis an isolated power for the HDI08 I/O drivers. This input must

be tied externally to all other chip power inputs. The user must provide adequate

external decoupling capacitors. There is one V_CCHinput.

SHI, ESAI, DAX, and Timer Power—V_CCSis an isolated power for the SHI, ESAI,

DAX, and Timer I/O drivers. This input must be tied externally to all other chip

power inputs. The user must provide adequate external decoupling capacitors.

There are two V_CCSinputs.

V_CCS(2)

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Signal/Connection Descriptions

Ground

GROUND

Table 1-3 Grounds

Description

Ground

Name

PLL Ground—GND_Pis a ground dedicated for PLL use. The connection should be

provided with an extremely low-impedance path to ground. V_CCPshould be

bypassed to GND_Pby a 0.47 µF capacitor located as close as possible to the chip

package. There is one GND_Pconnection.

GND_P

PLL Ground 1—GND_P1is a ground dedicated for PLL use. The connection should

be provided with an extremely low-impedance path to ground. There is one GND_P1

connection.

GND_P1

GND_Q(4)

Quiet Ground—GND_Qis an isolated ground for the internal processing logic. This

connection must be tied externally to all other chip ground connections. The user

must provide adequate external decoupling capacitors. There are four GND_Q

connections.

Address Bus Ground—GND_Ais an isolated ground for sections of the address

bus I/O drivers. This connection must be tied externally to all other chip ground

connections. The user must provide adequate external decoupling capacitors.

There are four GND_Aconnections.

GND_{A (4)}

GND_D(4)

GND_C(2)

GND_H

Data Bus Ground—GND_Dis an isolated ground for sections of the data bus I/O

drivers. This connection must be tied externally to all other chip ground

connections. The user must provide adequate external decoupling capacitors.

There are four GND_Dconnections.

Bus Control Ground—GND_Cis an isolated ground for the bus control I/O drivers.

This connection must be tied externally to all other chip ground connections. The

user must provide adequate external decoupling capacitors. There are two GND_C

connections.

Host Ground—GND_His an isolated ground for the HDI08 I/O drivers. This

connection must be tied externally to all other chip ground connections. The user

must provide adequate external decoupling capacitors. There is one GND_H

connection.

SHI, ESAI, DAX, and Timer Ground—GND_Sis an isolated ground for the SHI,

ESAI, DAX, and Timer I/O drivers. This connection must be tied externally to all

other chip ground connections. The user must provide adequate external

decoupling capacitors. There are two GND_Sconnections.

GND_S(2)

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Signal/Connection Descriptions

Clock and PLL

CLOCK AND PLL

Table 1-4 Clock and PLL Signals

State during

Signal

Type

Signal Description

Name

Reset

External Clock Input—An external clock source must be

connected to EXTAL in order to supply the clock to the

internal clock generator and PLL.

EXTAL

Input

This input cannot tolerate 5V.

Clock Output—CLKOUT provides an output clock

synchronized to the internal core clock phase.

If the PLL is enabled and both the multiplication and division

factors equal one, then CLKOUT is also synchronized to

EXTAL.

CLKOUT

Output Chip-driven

If the PLL is disabled, the CLKOUT frequency is half the

frequency of EXTAL. CLKOUT is not functional at

frequencies of 100 MHz and above.

PLL Capacitor—PCAP is an input connecting an off-chip

capacitor to the PLL filter. Connect one capacitor terminal to

PCAP and the other terminal to V_CCP

.

PCAP

Input

If the PLL is not used, PCAP may be tied to V_CC, GND, or left

floating.

PLL Initial/Non maskable Interrupt—During assertion of

RESET, the value of PINIT/NMI is written into the PLL Enable

(PEN) bit of the PLL control register, determining whether the

PLL is enabled or disabled. After RESET deassertion and

during normal instruction processing, the PINIT/NMI Schmitt-

trigger input is a negative-edge-triggered non maskable

interrupt (NMI) request internally synchronized to CLKOUT.

PINIT/

NMI

PINIT/NMI cannot tolerate 5 V.

EXTERNAL MEMORY EXPANSION PORT (PORT A)

When the DSP56362 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-

states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS.

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Signal/Connection Descriptions

External Memory Expansion Port (Port A)

External Address Bus

Table 1-5 External Address Bus Signals

Signal

Name

State during

Type

Signal Description

Reset

Address Bus—When the DSP is the bus master,

A0–A17 are active-high outputs that specify the

address for external program and data memory

accesses. Otherwise, the signals are tri-stated. To

minimize power dissipation, A0–A17 do not change

state when external memory spaces are not being

accessed.

A0–A17

Output

Tri-stated

External Data Bus

Table 1-6 External Data Bus Signals

State during

Signal

Type

Signal Description

Name

Reset

Data Bus—When the DSP is the bus master,

D0–D23 are active-high, bidirectional input/

outputs that provide the bidirectional data bus for

external program and data memory accesses.

Otherwise, D0–D23 are tri-stated.

D0–D23

Input/Output

Tri-stated

External Bus Control

Table 1-7 External Bus Control Signals

State during

Signal

Name

Type

Signal Description

Reset

Address Attribute or Row Address Strobe—When

defined as AA, these signals can be used as chip selects

or additional address lines. When defined as RAS, these

signals can be used as RAS for DRAM interface. These

signals are can be tri-stated outputs with programmable

polarity.

AA0–AA3/

RAS0–

RAS3

Output

Tri-stated

1-6

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Signal/Connection Descriptions

External Memory Expansion Port (Port A)

Table 1-7 External Bus Control Signals (Continued)

Signal

Name

State during

Reset

Type

Signal Description

Column Address Strobe—When the DSP is the bus

master, CAS is an active-low output used by DRAM to

strobe the column address. Otherwise, if the bus

mastership enable (BME) bit in the DRAM control

register is cleared, the signal is tri-stated.

CAS

Output

Tri-stated

Read Enable—When the DSP is the bus master, RD is

an active-low output that is asserted to read external

memory on the data bus (D0–D23). Otherwise, RD is tri-

stated.

RD

Output

Tri-stated

Write Enable—When the DSP is the bus master, WR is

an active-low output that is asserted to write external

memory on the data bus (D0–D23). Otherwise, the

signals are tri-stated.

WR

Transfer Acknowledge—If the DSP56362 is the bus

master and there is no external bus activity, or the

DSP56362 is not the bus master, the TA input is ignored.

The TA input is a data transfer acknowledge (DTACK)

function that can extend an external bus cycle

indefinitely. Any number of wait states (1, 2. . .infinity)

may be added to the wait states inserted by the BCR by

keeping TA deasserted. In typical operation, TA is

deasserted at the start of a bus cycle, is asserted to

enable completion of the bus cycle, and is deasserted

before the next bus cycle. The current bus cycle

completes one clock period after TA is asserted

synchronous to CLKOUT. The number of wait states is

determined by the TA input or by the bus control register

(BCR), whichever is longer. The BCR can be used to set

the minimum number of wait states in external bus

cycles.

TA

Input

Ignored Input

In order to use the TA functionality, the BCR must be

programmed to at least one wait state. A zero wait state

access cannot be extended by TA deassertion,

otherwise improper operation may result. TA can operate

synchronously or asynchronously, depending on the

setting of the TAS bit in the operating mode register

(OMR).

TA functionality may not be used while performing DRAM

type accesses, otherwise improper operation may result.

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Signal/Connection Descriptions

External Memory Expansion Port (Port A)

Table 1-7 External Bus Control Signals (Continued)

Signal

Name

State during

Reset

Type

Signal Description

Bus Request—BR is an active-low output, never tri-

stated. BR is asserted when the DSP requests bus

mastership. BR is deasserted when the DSP no longer

needs the bus. BR may be asserted or deasserted

independent of whether the DSP56362 is a bus master

or a bus slave. Bus “parking” allows BR to be deasserted

even though the DSP56362 is the bus master. (See the

description of bus “parking” in the BB signal description.)

The bus request hold (BRH) bit in the BCR allows BR to

be asserted under software control even though the DSP

does not need the bus. BR is typically sent to an external

bus arbitrator that controls the priority, parking, and

tenure of each master on the same external bus. BR is

only affected by DSP requests for the external bus, never

for the internal bus. During hardware reset, BR is

deasserted and the arbitration is reset to the bus slave

state.

Output

(deasserted)

BR

Output

Bus Grant—BG is an active-low input. BG is asserted by

an external bus arbitration circuit when the DSP56362

becomes the next bus master. When BG is asserted, the

DSP56362 must wait until BB is deasserted before taking

bus mastership. When BG is deasserted, bus mastership

is typically given up at the end of the current bus cycle.

This may occur in the middle of an instruction that

requires more than one external bus cycle for execution.

BG

Input

Ignored Input

The default mode of operation of this signal requires a

setup and hold time referred to CLKOUT. But CLKOUT

operation is not guaranteed from 100MHz and up, so the

asynchronous bus arbitration must be used for clock

frequencies 100MHz and above. The asynchronous bus

arbitration is enabled by setting the ABE bit in the OMR

register.

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External Memory Expansion Port (Port A)

Table 1-7 External Bus Control Signals (Continued)

Signal

Name

State during

Reset

Type

Signal Description

Bus Busy—BB is a bidirectional active-low input/output.

BB indicates that the bus is active. Only after BB is

deasserted can the pending bus master become the bus

master (and then assert the signal again). The bus

master may keep BB asserted after ceasing bus activity

regardless of whether BR is asserted or deasserted. This

is called “bus parking” and allows the current bus master

to reuse the bus without rearbitration until another device

requires the bus. The deassertion of BB is done by an

“active pull-up” method (i.e., BB is driven high and then

released and held high by an external pull-up resistor).

Input/

BB

Input

Output

The default mode of operation of this signal requires a

setup and hold time referred to CLKOUT. But CLKOUT

operation is not guaranteed from 100MHz and up, so the

asynchronous bus arbitration must be used for clock

frequencies 100MHz and above. The asynchronous bus

arbitration is enabled by setting the ABE bit in the OMR

register.

BB requires an external pull-up resistor.

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Signal/Connection Descriptions

Interrupt and Mode Control

INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.

After RESET is deasserted, these inputs are hardware interrupt request lines.

Table 1-8 Interrupt and Mode Control

State during

Signal Name

Type

Signal Description

Reset

Mode Select A/External Interrupt Request A—

MODA/IRQA is an active-low Schmitt-trigger input,

internally synchronized to the DSP clock. MODA/IRQA

selects the initial chip operating mode during hardware

reset and becomes a level-sensitive or negative-edge-

triggered, maskable interrupt request input during

normal instruction processing. MODA, MODB, MODC,

and MODD select one of 16 initial chip operating

modes, latched into the OMR when the RESET signal

is deasserted. If IRQA is asserted synchronous to

CLKOUT, multiple processors can be resynchronized

using the WAIT instruction and asserting IRQA to exit

the wait state. If the processor is in the stop standby

state and the MODA/IRQA pin is pulled to GND, the

processor will exit the stop state.

MODA/IRQA

Input

This input is 5 V tolerant.

Mode Select B/External Interrupt Request B—

MODB/IRQB is an active-low Schmitt-trigger input,

internally synchronized to the DSP clock. MODB/IRQB

selects the initial chip operating mode during hardware

reset and becomes a level-sensitive or negative-edge-

triggered, maskable interrupt request input during

normal instruction processing. MODA, MODB, MODC,

and MODD select one of 16 initial chip operating

modes, latched into OMR when the RESET signal is

deasserted. If IRQB is asserted synchronous to

CLKOUT, multiple processors can be re-synchronized

using the WAIT instruction and asserting IRQB to exit

the wait state.

MODB/IRQB

Input

This input is 5 V tolerant.

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Interrupt and Mode Control

Table 1-8 Interrupt and Mode Control (Continued)

State during

Reset

Signal Name

Type

Signal Description

Mode Select C/External Interrupt Request C—

MODC/IRQC is an active-low Schmitt-trigger input,

internally synchronized to the DSP clock. MODC/IRQC

selects the initial chip operating mode during hardware

reset and becomes a level-sensitive or negative-edge-

triggered, maskable interrupt request input during

normal instruction processing. MODA, MODB, MODC,

and MODD select one of 16 initial chip operating

modes, latched into OMR when the RESET signal is

deasserted. If IRQC is asserted synchronous to

CLKOUT, multiple processors can be resynchronized

using the WAIT instruction and asserting IRQC to exit

the wait state.

MODC/IRQC

Input

This input is 5 V tolerant.

Mode Select D/External Interrupt Request D—

MODD/IRQD is an active-low Schmitt-trigger input,

internally synchronized to the DSP clock. MODD/IRQD

selects the initial chip operating mode during hardware

reset and becomes a level-sensitive or negative-edge-

triggered, maskable interrupt request input during

normal instruction processing. MODA, MODB, MODC,

and MODD select one of 16 initial chip operating

modes, latched into OMR when the RESET signal is

deasserted. If IRQD is asserted synchronous to

CLKOUT, multiple processors can be resynchronized

using the WAIT instruction and asserting IRQD to exit

the wait state.

MODD/IRQD

Input

This input is 5 V tolerant.

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Signal/Connection Descriptions

Host Interface (HDI08)

Table 1-8 Interrupt and Mode Control (Continued)

State during

Reset

Signal Name

Type

Signal Description

Reset—RESET is an active-low, Schmitt-trigger input.

When asserted, the chip is placed in the reset state

and the internal phase generator is reset. The Schmitt-

trigger input allows a slowly rising input (such as a

capacitor charging) to reset the chip reliably. If RESET

is deasserted synchronous to CLKOUT, exact start-up

timing is guaranteed, allowing multiple processors to

start synchronously and operate together in “lock-

step.” When the RESET signal is deasserted, the initial

chip operating mode is latched from the MODA,

MODB, MODC, and MODD inputs. The RESET signal

must be asserted during power up. A stable EXTAL

signal must be supplied while RESET is being

asserted.

RESET

Input

This input is 5 V tolerant.

HOST INTERFACE (HDI08)

The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The

HDI08 supports a variety of standard buses and can be directly connected to a number of industry

standard microcomputers, microprocessors, DSPs, and DMA hardware.

Host Port Configuration

Signal functions associated with the HDI08 vary according to the interface operating mode as determined

by the HDI08 port control register (HPCR). See 6.5.6 Host Port Control Register (HPCR) on

page Section 6-13 for detailed descriptions of this register and (See Host Interface (HDI08) on

page Section 6-1.) for descriptions of the other HDI08 configuration registers.

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Host Interface (HDI08)

Table 1-9 Host Interface

Signal

Name

State during

Reset

Type

Signal Description

Host Data—When the HDI08 is programmed to

interface a nonmultiplexed host bus and the HI

function is selected, these signals are lines 0–7

of the bidirectional, tri-state data bus.

Input/

H0–H7

output

Host Address—When HDI08 is programmed to

interface a multiplexed host bus and the HI

function is selected, these signals are lines 0–7

of the address/data bidirectional, multiplexed, tri-

state bus.

Input/

HAD0–

HAD7

output

GPIO

disconnected

Port B 0–7—When the HDI08 is configured as

GPIO, these signals are individually

programmable as input, output, or internally

disconnected.

Input, output,

or

PB0–PB7

disconnected

The default state after reset for these signals is

GPIO disconnected.

This input is 5 V tolerant.

Host Address Input 0—When the HDI08 is

programmed to interface a nonmultiplexed host

bus and the HI function is selected, this signal is

line 0 of the host address input bus.

Input

HA0

Host Address Strobe—When HDI08 is

programmed to interface a multiplexed host bus

and the HI function is selected, this signal is the

host address strobe (HAS) Schmitt-trigger input.

The polarity of the address strobe is

HAS/

HAS

GPIO

programmable, but is configured active-low

(HAS) following reset.

disconnected

Port B 8—When the HDI08 is configured as

GPIO, this signal is individually programmed as

input, output, or internally disconnected.

Input, output,

or

PB8

The default state after reset for this signal is

GPIO disconnected.

disconnected

This input is 5 V tolerant.

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Host Interface (HDI08)

Table 1-9 Host Interface (Continued)

State during

Signal

Type

Signal Description

Name

Reset

Host Address Input 1—When the HDI08 is

programmed to interface a nonmultiplexed host

bus and the HI function is selected, this signal is

line 1 of the host address (HA1) input bus.

Input

HA1

Host Address 8—When HDI08 is programmed

to interface a multiplexed host bus and the HI

function is selected, this signal is line 8 of the

host address (HA8) input bus.

GPIO

HA8

PB9

disconnected

Port B 9—When the HDI08 is configured as

GPIO, this signal is individually programmed as

input, output, or internally disconnected.

Input, output,

or

The default state after reset for this signal is

GPIO disconnected.

disconnected

This input is 5 V tolerant.

Host Address Input 2—When the HDI08 is

programmed to interface a non-multiplexed host

bus and the HI function is selected, this signal is

line 2 of the host address (HA2) input bus.

Input

HA2

Host Address 9—When HDI08 is programmed

to interface a multiplexed host bus and the HI

function is selected, this signal is line 9 of the

host address (HA9) input bus.

GPIO

HA9

disconnected

Port B 10—When the HDI08 is configured as

GPIO, this signal is individually programmed as

input, output, or internally disconnected.

Input, Output,

or

PB10

The default state after reset for this signal is

GPIO disconnected.

Disconnected

This input is 5 V tolerant.

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Host Interface (HDI08)

Table 1-9 Host Interface (Continued)

State during

Signal

Name

Type

Signal Description

Reset

Host Read/Write—When HDI08 is programmed

to interface a single-data-strobe host bus and the

HI function is selected, this signal is the Host

Read/Write (HRW) input.

Input

HRW

Host Read Data—When HDI08 is programmed

to interface a double-data-strobe host bus and

the HI function is selected, this signal is the host

read data strobe (HRD) Schmitt-trigger input. The

polarity of the data strobe is programmable, but is

configured as active-low (HRD) after reset.

HRD/

HRD

GPIO

disconnected

Port B 11—When the HDI08 is configured as

GPIO, this signal is individually programmed as

input, output, or internally disconnected.

Input, Output,

or

PB11

The default state after reset for this signal is

GPIO disconnected.

Disconnected

This input is 5 V tolerant.

Host Data Strobe—When HDI08 is programmed

to interface a single-data-strobe host bus and the

HI function is selected, this signal is the host data

strobe (HDS) Schmitt-trigger input. The polarity

of the data strobe is programmable, but is

Input

HDS/

HDS

configured as active-low (HDS) following reset.

Host Write Data—When HDI08 is programmed

to interface a double-data-strobe host bus and

the HI function is selected, this signal is the host

write data strobe (HWR) Schmitt-trigger input.

The polarity of the data strobe is programmable,

but is configured as active-low (HWR) following

reset.

GPIO

HWR/

HWR

disconnected

Port B 12—When the HDI08 is configured as

GPIO, this signal is individually programmed as

input, output, or internally disconnected.

Input, output,

or

PB12

The default state after reset for this signal is

GPIO disconnected.

disconnected

This input is 5 V tolerant.

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Host Interface (HDI08)

Table 1-9 Host Interface (Continued)

State during

Signal

Type

Signal Description

Name

Reset

Host Chip Select—When HDI08 is programmed

to interface a nonmultiplexed host bus and the HI

function is selected, this signal is the host chip

select (HCS) input. The polarity of the chip select

is programmable, but is configured active-low

(HCS) after reset.

Input

HCS

Host Address 10—When HDI08 is programmed

to interface a multiplexed host bus and the HI

function is selected, this signal is line 10 of the

host address (HA10) input bus.

GPIO

disconnected

HA10

PB13

Port B 13—When the HDI08 is configured as

GPIO, this signal is individually programmed as

input, output, or internally disconnected.

Input, output,

or

The default state after reset for this signal is

GPIO disconnected.

disconnected

This input is 5 V tolerant.

Host Request—When HDI08 is programmed to

interface a single host request host bus and the

HI function is selected, this signal is the host

request (HOREQ) output. The polarity of the host

request is programmable, but is configured as

active-low (HOREQ) following reset. The host

request may be programmed as a driven or

open-drain output.

Output

HOREQ/

HOREQ

Transmit Host Request—When HDI08 is

programmed to interface a double host request

host bus and the HI function is selected, this

signal is the transmit host request (HTRQ)

output. The polarity of the host request is

programmable, but is configured as active-low

(HTRQ) following reset. The host request may be

programmed as a driven or open-drain output.

HTRQ/

HTRQ

GPIO

disconnected

Port B 14—When the HDI08 is configured as

GPIO, this signal is individually programmed as

input, output, or internally disconnected.

Input, output,

or

PB14

The default state after reset for this signal is

GPIO disconnected.

disconnected

This input is 5 V tolerant.

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Host Interface (HDI08)

Table 1-9 Host Interface (Continued)

State during

Signal

Name

Type

Signal Description

Reset

Host Acknowledge—When HDI08 is

programmed to interface a single host request

host bus and the HI function is selected, this

signal is the host acknowledge (HACK) Schmitt-

trigger input. The polarity of the host

Input

HACK/

HACK

acknowledge is programmable, but is configured

as active-low (HACK) after reset.

Receive Host Request—When HDI08 is

programmed to interface a double host request

host bus and the HI function is selected, this

signal is the receive host request (HRRQ) output.

The polarity of the host request is programmable,

but is configured as active-low (HRRQ) after

reset. The host request may be programmed as a

driven or open-drain output.

Output

HRRQ/

HRRQ

GPIO

disconnected

Port B 15—When the HDI08 is configured as

GPIO, this signal is individually programmed as

input, output, or internally disconnected.

Input, output,

or

PB15

The default state after reset for this signal is

GPIO disconnected.

disconnected

This input is 5 V tolerant.

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Signal/Connection Descriptions

Serial Host Interface

SERIAL HOST INTERFACE

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I²C mode.

Table 1-10 Serial Host Interface Signals

State

Signal Name Signal Type

during

Reset

Signal Description

SPI Serial Clock—The SCK signal is an output

when the SPI is configured as a master and a

Schmitt-trigger input when the SPI is configured as

a slave. When the SPI is configured as a master,

the SCK signal is derived from the internal SHI

clock generator. When the SPI is configured as a

slave, the SCK signal is an input, and the clock

signal from the external master synchronizes the

data transfer. The SCK signal is ignored by the SPI

if it is defined as a slave and the slave select (SS)

signal is not asserted. In both the master and slave

SPI devices, data is shifted on one edge of the SCK

signal and is sampled on the opposite edge where

data is stable. Edge polarity is determined by the

SPI transfer protocol.

Input or

SCK

output

Tri-stated

I²C Serial Clock—SCL carries the clock for I²C bus

transactions in the I²C mode. SCL is a Schmitt-

trigger input when configured as a slave and an

open-drain output when configured as a master.

SCL should be connected to V_CCthrough a pull-up

resistor.

Input or

SCL

output

This signal is tri-stated during hardware, software,

and individual reset. Thus, there is no need for an

external pull-up in this state.

This input is 5 V tolerant.

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Serial Host Interface

Table 1-10 Serial Host Interface Signals (Continued)

State

during

Reset

Signal Name Signal Type

Signal Description

SPI Master-In-Slave-Out—When the SPI is

configured as a master, MISO is the master data

input line. The MISO signal is used in conjunction

with the MOSI signal for transmitting and receiving

serial data. This signal is a Schmitt-trigger input

when configured for the SPI Master mode, an

output when configured for the SPI Slave mode,

and tri-stated if configured for the SPI Slave mode

when SS is deasserted. An external pull-up resistor

is not required for SPI operation.

Input or

MISO

output

I²C Data and Acknowledge—In I²C mode, SDA is

a Schmitt-trigger input when receiving and an open-

drain output when transmitting. SDA should be

connected to V_CCthrough a pull-up resistor. SDA

carries the data for I²C transactions. The data in

SDA must be stable during the high period of SCL.

The data in SDA is only allowed to change when

SCL is low. When the bus is free, SDA is high. The

SDA line is only allowed to change during the time

SCL is high in the case of start and stop events. A

high-to-low transition of the SDA line while SCL is

high is a unique situation, and is defined as the start

event. A low-to-high transition of SDA while SCL is

high is a unique situation defined as the stop event.

Tri-stated

Input or

open-drain

output

SDA

This signal is tri-stated during hardware, software,

and individual reset. Thus, there is no need for an

external pull-up in this state.

This input is 5 V tolerant.

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Serial Host Interface

Table 1-10 Serial Host Interface Signals (Continued)

State

during

Reset

Signal Name Signal Type

Signal Description

SPI Master-Out-Slave-In—When the SPI is

configured as a master, MOSI is the master data

output line. The MOSI signal is used in conjunction

with the MISO signal for transmitting and receiving

serial data. MOSI is the slave data input line when

the SPI is configured as a slave. This signal is a

Schmitt-trigger input when configured for the SPI

Slave mode.

MOSI

HA0

Input or

output

I²C Slave Address 0—This signal uses a Schmitt-

trigger input when configured for the I²C mode.

When configured for I²C slave mode, the HA0

signal is used to form the slave device address.

HA0 is ignored when configured for the I²C master

mode.

Tri-stated

Input

This signal is tri-stated during hardware, software,

and individual reset. Thus, there is no need for an

external pull-up in this state.

This input is 5 V tolerant.

SPI Slave Select—This signal is an active low

Schmitt-trigger input when configured for the SPI

mode. When configured for the SPI Slave mode,

this signal is used to enable the SPI slave for

transfer. When configured for the SPI master mode,

this signal should be kept deasserted (pulled high).

If it is asserted while configured as SPI master, a

bus error condition is flagged. If SS is deasserted,

the SHI ignores SCK clocks and keeps the MISO

output signal in the high-impedance state.

SS

Input

Tri-stated

I²C Slave Address 2—This signal uses a Schmitt-

trigger input when configured for the I²C mode.

When configured for the I²C Slave mode, the HA2

signal is used to form the slave device address.

HA2 is ignored in the I²C master mode.

HA2

Input

This signal is tri-stated during hardware, software,

and individual reset. Thus, there is no need for an

external pull-up in this state.

This input is 5 V tolerant.

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Serial Host Interface

Table 1-10 Serial Host Interface Signals (Continued)

State

during

Reset

Signal Name Signal Type

Signal Description

Host Request—This signal is an active low

Schmitt-trigger input when configured for the

master mode but an active low output when

configured for the slave mode.

When configured for the slave mode, HREQ is

asserted to indicate that the SHI is ready for the

next data word transfer and deasserted at the first

clock pulse of the new data word transfer. When

configured for the master mode, HREQ is an input.

When asserted by the external slave device, it will

trigger the start of the data word transfer by the

master. After finishing the data word transfer, the

master will await the next assertion of HREQ to

proceed to the next transfer.

Input or

HREQ

Output

Tri-stated

This signal is tri-stated during hardware, software,

personal reset, or when the HREQ1–HREQ0 bits in

the HCSR are cleared. There is no need for

external pull-up in this state.

This input is 5 V tolerant.

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Enhanced Serial Audio Interface

ENHANCED SERIAL AUDIO INTERFACE

Table 1-11 Enhanced Serial Audio Interface Signals

Signal

Name

State during

Reset

Signal Type

Signal Description

High Frequency Clock for Receiver—When

programmed as an input, this signal provides a high

frequency clock source for the ESAI receiver as an

alternate to the DSP core clock. When programmed

as an output, this signal can serve as a high-

frequency sample clock (e.g., for external digital to

analog converters [DACs]) or as an additional

system clock.

Input or output

HCKR

GPIO

disconnected

Port C 2—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

Input, output,

or

PC2

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

High Frequency Clock for Transmitter—When

programmed as an input, this signal provides a high

frequency clock source for the ESAI transmitter as

an alternate to the DSP core clock. When

Input or output

HCKT

PC5

programmed as an output, this signal can serve as a

high frequency sample clock (e.g., for external

DACs) or as an additional system clock.

GPIO

disconnected

Port C 5—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

Input, output,

or

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

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Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

State during

Reset

Signal Type

Signal Description

Frame Sync for Receiver—This is the receiver

frame sync input/output signal. In the asynchronous

mode (SYN=0), the FSR pin operates as the frame

sync input or output used by all the enabled

receivers. In the synchronous mode (SYN=1), it

operates as either the serial flag 1 pin (TEBE=0), or

as the transmitter external buffer enable control

(TEBE=1, RFSD=1).

Input or output

FSR

When this pin is configured as serial flag pin, its

direction is determined by the RFSD bit in the RCCR

register. When configured as the output flag OF1,

this pin will reflect the value of the OF1 bit in the

SAICR register, and the data in the OF1 bit will show

up at the pin synchronized to the frame sync in

normal mode or the slot in network mode. When

configured as the input flag IF1, the data value at the

pin will be stored in the IF1 bit in the SAISR register,

synchronized by the frame sync in normal mode or

the slot in network mode.

GPIO

disconnected

Port C 1—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

Input, output,

or

PC1

FST

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Frame Sync for Transmitter—This is the

transmitter frame sync input/output signal. For

synchronous mode, this signal is the frame sync for

both transmitters and receivers. For asynchronous

mode, FST is the frame sync for the transmitters

only. The direction is determined by the transmitter

frame sync direction (TFSD) bit in the ESAI transmit

clock control register (TCCR).

Input or output

GPIO

disconnected

Port C 4—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

Input, output,

or

PC4

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

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Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

State during

Reset

Signal Type

Signal Description

Receiver Serial Clock—SCKR provides the

receiver serial bit clock for the ESAI. The SCKR

operates as a clock input or output used by all the

enabled receivers in the asynchronous mode

(SYN=0), or as serial flag 0 pin in the synchronous

mode (SYN=1).

Input or output

SCKR

When this pin is configured as serial flag pin, its

direction is determined by the RCKD bit in the

RCCR register. When configured as the output flag

OF0, this pin will reflect the value of the OF0 bit in

the SAICR register, and the data in the OF0 bit will

show up at the pin synchronized to the frame sync in

normal mode or the slot in network mode. When

configured as the input flag IF0, the data value at the

pin will be stored in the IF0 bit in the SAISR register,

synchronized by the frame sync in normal mode or

the slot in network mode.

GPIO

disconnected

Port C 0—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

Input, output,

or

PC0

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Transmitter Serial Clock—This signal provides the

serial bit rate clock for the ESAI. SCKT is a clock

input or output used by all enabled transmitters and

receivers in synchronous mode, or by all enabled

transmitters in asynchronous mode.

Input or output

SCKT

PC3

GPIO

Port C 3—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

disconnected

Input, output,

or

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

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Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

State during

Reset

Signal Type

Signal Description

Serial Data Output 5—When programmed as a

transmitter, SDO5 is used to transmit data from the

TX5 serial transmit shift register.

Output

Input

SDO5

SDI0

PC6

Serial Data Input 0—When programmed as a

receiver, SDI0 is used to receive serial data into the

RX0 serial receive shift register.

GPIO

disconnected

Port C 6—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

Input, output,

or

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Serial Data Output 4—When programmed as a

transmitter, SDO4 is used to transmit data from the

TX4 serial transmit shift register.

Output

Input

SDO4

SDI1

PC7

Serial Data Input 1—When programmed as a

receiver, SDI1 is used to receive serial data into the

RX1 serial receive shift register.

GPIO

disconnected

Port C 7—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

Input, output,

or

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

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Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

State during

Reset

Signal Type

Signal Description

Serial Data Output 3—When programmed as a

transmitter, SDO3 is used to transmit data from the

TX3 serial transmit shift register.

Output

Input

SDO3

SDI2

PC8

Serial Data Input 2—When programmed as a

receiver, SDI2 is used to receive serial data into the

RX2 serial receive shift register.

GPIO

disconnected

Port C 8—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

Input, output,

or

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Serial Data Output 2—When programmed as a

transmitter, SDO2 is used to transmit data from the

TX2 serial transmit shift register.

Output

Input

SDO2

SDI3

PC9

Serial Data Input 3—When programmed as a

receiver, SDI3 is used to receive serial data into the

RX3 serial receive shift register.

GPIO

disconnected

Port C 9—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

Input, output,

or

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Serial Data Output 1—SDO1 is used to transmit

data from the TX1 serial transmit shift register.

Output

SDO1

PC10

Port C 10—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

GPIO

Input, output,

or

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

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Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

State during

Reset

Signal Type

Signal Description

Serial Data Output 0—SDO0 is used to transmit

data from the TX0 serial transmit shift register.

Output

SDO0

PC11

Port C 11—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

GPIO

Input, output,

or

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

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Signal/Connection Descriptions

Digital Audio Interface (DAX)

DIGITAL AUDIO INTERFACE (DAX)

Table 1-12 Digital Audio Interface (DAX) Signals

Signal

Name

StateDuring

Type

Signal Description

Reset

Audio Clock Input—This is the DAX clock input. When

programmed to use an external clock, this input supplies

the DAX clock. The external clock frequency must be

256, 384, or 512 times the audio sampling frequency

(256 × Fs, 384 × Fs or 512 × Fs, respectively).

Input

ACI

Disconnecte

d

Port D 0—When the DAX is configured as GPIO, this

signal is individually programmable as input, output, or

internally disconnected.

Input,

PD0

output, or

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Digital Audio Data Output—This signal is an audio and

non-audio output in the form of AES/EBU, CP340 and

IEC958 data in a biphase mark format.

Output

ADO

PD1

Port D 1—When the DAX is configured as GPIO, this

signal is individually programmable as input, output, or

internally disconnected.

Disconnecte

d

Input,

output, or

disconnected

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

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Signal/Connection Descriptions

Timer

TIMER

Table 1-13 Timer Signal

State during

Reset

Signal Name

Type

Signal Description

Timer 0 Schmitt-Trigger Input/Output—When

timer 0 functions as an external event counter or

in measurement mode, TIO0 is used as input.

When timer 0 functions in watchdog, timer, or

pulse modulation mode, TIO0 is used as output.

The default mode after reset is GPIO input. This

can be changed to output or configured as a

timer input/output through the timer 0 control/

status register (TCSR0). If TIO0 is not being

used, it is recommended to either define it as

GPIO output immediately at the beginning of

operation or leave it defined as GPIO input but

connected it to Vcc through a pull-up resistor in

order to ensure a stable logic level at the input.

Input or

Output

TIO0

Input

This input is 5 V tolerant.

JTAG/OnCE INTERFACE

Table 1-14 JTAG/OnCE™ Interface

State

Signal

Name

Type

during

Reset

Signal Description

Test Clock—TCK is a test clock input signal used to synchronize

the JTAG test logic. It has an internal pull-up resistor.

TCK

TDI

Input

This input is 5 V tolerant.

Test Data Input—TDI is a test data serial input signal used for test

instructions and data. TDI is sampled on the rising edge of TCK

and has an internal pull-up resistor.

Input

This input is 5 V tolerant.

Test Data Output—TDO is a test data serial output signal used for

test instructions and data. TDO can be tri-stated and is actively

driven in the shift-IR and shift-DR controller states. TDO changes

on the falling edge of TCK.

Tri-

TDO

Output

stated

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Signal/Connection Descriptions

JTAG/OnCE Interface

Table 1-14 JTAG/OnCE™ Interface (Continued)

State

Signal

Type

during

Reset

Signal Description

Name

Test Mode Select—TMS is an input signal used to sequence the

test controller’s state machine. TMS is sampled on the rising edge

of TCK and has an internal pull-up resistor.

TMS

Input

This input is 5 V tolerant.

Test Reset—TRST is an active-low Schmitt-trigger input signal

used to asynchronously initialize the test controller. TRST has an

internal pull-up resistor.

TRST

The use of TRST is not recommended for new designs. It is

recommended to leave TRST disconnected.

This input is 5 V tolerant.

Debug Event—DE is an open-drain, bidirectional, active-low signal

providing, as an input, a means of entering the debug mode of

operation from an external command controller, and, as an output,

a means of acknowledging that the chip has entered the debug

mode. This signal, when asserted as an input, causes the

DSP56300 core to finish the current instruction being executed,

save the instruction pipeline information, enter the debug mode,

and wait for commands to be entered from the debug serial input

line. This signal is asserted as an output for three clock cycles

when the chip enters the debug mode as a result of a debug

request or as a result of meeting a breakpoint condition. The DE

has an internal pull-up resistor.

Input/

DE

Input

Output

This is not a standard part of the JTAG TAP controller. The signal

connects directly to the OnCE module to initiate debug mode

directly or to provide a direct external indication that the chip has

entered the debug mode. All other interface with the OnCE module

must occur through the JTAG port.

The use of DE is not recommended for new designs. It is

recommended to leave DE disconnected.

This input is not 5 V tolerant.

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SECTION 2

SPECIFICATIONS

INTRODUCTION

The DSP56362 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible

inputs and outputs. The DSP56362 specifications are preliminary and are from design simulations, and

may not be fully tested or guaranteed. Finalized specifications will be published after full characterization

and device qualifications are complete.

MAXIMUM RATINGS

CAUTION

This device contains circuitry protecting

against damage due to high static voltage or

electrical fields. However, normal precautions

should be taken to avoid exceeding maximum

voltage ratings. Reliability of operation is

enhanced if unused inputs are pulled to an

appropriate logic voltage level (e.g., either

GND or V ). The suggested value for a

CC

pullup or pulldown resistor is 10 kΩ.

Note: In the calculation of timing requirements, adding a maximum value of one

specification to a minimum value of another specification does not yield a reasonable

sum. A maximum specification is calculated using a worst case variation of process

parameter values in one direction. The minimum specification is calculated using the

worst case for the same parameters in the opposite direction. Therefore, a “maximum”

value for a specification will never occur in the same device that has a “minimum”

value for another specification; adding a maximum to a minimum represents a

condition that can never exist.

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Specifications

Thermal Characteristics

Table 2-1 Maximum Ratings

1

1, 2

Symbol

Unit

Rating

Value

V_CC

V_IN

V_IN5

I

−0.3 to +4.0

GND −0.3 to V_CC+ 0.3

GND −0.3 to V_CC+ 3.95

10

V

Supply Voltage

3

All input voltages excluding “5 V tolerant” inputs

3

V

All “5 V tolerant” input voltages

mA

°C

Current drain per pin excluding V_CCand GND

Operating temperature range

Storage temperature

T_J

−40 to +105

T_STG

−55 to +125

Notes: 1. GND = 0 V, V_CC= 3.3 V .16V, T_J= 0°C to +100°C, CL = 50 pF

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not

guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent

damage to the device.

3. CAUTION: All “5 V Tolerant” input voltages must not be more than 3.95 V greater than the supply

voltage; this restriction applies to “power on”, as well as during normal operation. In any case, the input

voltages cannot be more than 5.75 V. “5 V Tolerant” inputs are inputs that tolerate 5 V.

THERMAL CHARACTERISTICS

Table 2-2 Thermal Characteristics

Characteristic

Symbol

LQFP Value

45.3

Unit

°C/W

1

R

_θJAor θ_JA

_θJCor θ_JC

Ψ_JT

Junction-to-ambient thermal resistance

2

R

10.1

Junction-to-case thermal resistance

5.5

Thermal characterization parameter

Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-

sided printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor

Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043,

(415) 964-5111.)

Measurements were done with parts mounted on thermal test boards conforming to

specification EIA/JESD51-3.

2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI

G30-88, with the exception that the cold plate temperature is used for the case temperature.

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Specifications

DC Electrical Characteristics

DC ELECTRICAL CHARACTERISTICS

6

Table 2-3 DC Electrical Characteristics

Characteristics

Supply voltage

Symbol

Min

Typ

Max

Unit

V_CC

3.14

3.3

3.46

V

Input high voltage

• D(0:23), BG, BB, TA, DE, and PINIT/

NMI

V_IH

2.0

—

V_CC

1

• MOD /IRQ , RESET, and TCK/TDI/

TMS/TRST/ESAI/Timer/HDI08/

SHI_{(SPI mode)}pins

V

V_IHP

V_CC+ 3.95

• SHI_{(I2C mode)}pins

1.5

V_{CC + 3.95}

V_CC

8

• EXTAL

V_IHX

0.8 ξ V_CC

—

Input low voltage

1

• D(0:23), BG, BB, TA, MOD /IRQ ,

RESET, PINIT/NMI

V_IL

–0.3

0.8

• All JTAG/ESAI/Timer/HDI08/ SHI_(SPI

_mode)pins

V_ILP

—

• SHI_{(I2C mode)}pins

–0.3

0.3 × V_CC

0.2 ξ V_CC

8

• EXTAL

V_ILX

I_IN

–10

—

10

µA

Input leakage current

High impedance (off-state) input current

(@ 2.4 V / 0.4 V)

I_TSI

–10

10

Output high voltage

5,7

2.4

—

• TTL (I_OH= –0.4 mA)

V_OH

V

5

• CMOS (I_OH= –10 µιχροA)

V_CC– 0.01

—

Output low voltage

• TTL (I_OL= 3.0 mA, open-drain pins

0.4

5,7

V_OL

—

I

_OL= 6.7 mA)

5

• CMOS (I_OL= 10 µιχροA)

0.01

2

Internal supply current :

(Operating frequency 100MHz for

current measurements)

• In Normal mode

• In Wait mode

I_CCI

—

127

7. 5

181

11

mA

I_CCW

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Specifications

AC Electrical Characteristics

Table 2-3 DC Electrical Characteristics

6 (Continued)

Characteristics

4

Symbol

Min

—

Typ

100

1

Max

150

2.5

Unit

µA

• In Stop mode

I_CCS

—

mA

PLL supply current

5

C_IN

—

10

pF

Input capacitance

Notes: 1. Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins

2. Power Consumption Considerations on page 4-3 provides a formula to compute the

estimated current requirements in Normal mode. In order to obtain these results, all inputs must be

terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP

benchmarks. The power consumption numbers in this specification are 90% of the measured

results of this benchmark. This reflects typical DSP applications. Typical internal supply current is

measured with V_CC= 3.3V at T_J= 100°C. Maximum internal supply current is measured with V_CC

3.46 V at T_J= 100°C.

=

3. Deleted.

4. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be

terminated (i.e., not allowed to float).

5. Periodically sampled and not 100% tested

6. V_CC= 3.3 V 5% V; T_J= 0°C to +100°C, C_L= 50 pF

7. This characteristic does not apply to PCAP.

8. Driving EXTAL to the low V_IHXor the high V_ILXvalue may cause additional power consumption (DC

current). To minimize power consumption, the minimum V_IHXshould be no lower than

0.9 ξ V_CCand the maximum V_ILXshould be no higher than 0.1 ξ V_CC

.

AC ELECTRICAL CHARACTERISTICS

The timing waveforms shown in the AC electrical characteristics section are tested with a V_ILmaximum of

0.3 V and a V_IHminimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown

in Note 6 of the previous table. AC timing specifications, which are referenced to a device input signal, are

measured in production with respect to the 50% point of the respective input signal's transition. DSP56362

output levels are measured with the production test machine V_OLand V_OHreference levels set at 0.4 V

and 2.4 V, respectively.

Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test

conditions are 15 MHz and rated speed.

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Specifications

Internal Clocks

INTERNAL CLOCKS

Table 2-4 Internal Clocks, CLKOUT

1, 2

Expression

Typ

Characteristics

Symbol

Min

Max

(Ef × MF)/

Internal operation frequency and

CLKOUT with PLL enabled

f

—

(PDF × DF)

Internal operation frequency and

CLKOUT with PLL disabled

—

Ef/2

—

Internal clock and CLKOUT high

period

• With PLL disabled

—

ET_C

—

• With PLL enabled and

0.49 × ET_C×

PDF × DF/MF

0.51 × ET_C×

PDF × DF/MF

T_H

MF ≤ 4

• With PLL enabled and

MF > 4

0.47 × ET_C×

PDF × DF/MF

0.53 × ET_C×

PDF × DF/MF

—

Internal clock and CLKOUT low

period

• With PLL disabled

—

ET_C

—

• With PLL enabled and

0.49 × ET_C×

PDF × DF/MF

0.51 × ET_C×

PDF × DF/MF

T_L

MF ≤ 4

• With PLL enabled and

MF > 4

0.47 × ET_C×

PDF × DF/MF

0.53 × ET_C×

PDF × DF/MF

—

ET_C× PDF ×

Internal clock and CLKOUT cycle

time with PLL enabled

T_C

—

DF/MF

Internal clock and CLKOUT cycle

time with PLL disabled

T_C

—

2 × ET_C

—

I_CYC

T_C

Instruction cycle time

Notes: 1. DF = Division Factor

Ef = External frequency

ET_C= External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

T_C= internal clock cycle

2. See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion

of the PLL.

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Specifications

EXTERNAL CLOCK OPERATION

The DSP56362 system clock is an externally supplied square wave voltage source connected to

EXTAL(Figure 2-1)

.

V_IHC

Midpoint

EXTAL

ETH

ETL

V_ILC

2

3

4

ETC

5

CLKOUT With

PLL Disabled

7

CLKOUT With

PLL Enabled

7

6a

6b

Note: The midpoint is 0.5 (V_IHC+ V_ILC).

Figure 2-1 External Clock Timing

AA0459

Table 2-5 Clock Operation 100 and 120 MHz Values

100 MHz

120 MHz

Min Max

No.

Characteristics

Symbol

Min

Max

Frequency of EXTAL (EXTAL Pin

Frequency)

1

2

Ef

0

100.0

0

120.0

The rise and fall time of this external clock

should be 3 ns maximum.

1, 2

EXTAL input high

• With PLL disabled (46.7%–53.3% duty

ET_H

ET_L

4.67 ns

∞

0.00 ns

∞

6

cycle )

• With PLL enabled (42.5%–57.5% duty

4.25 ns 157.0 µs 0.00 ns 157.0 µs

6

cycle )

1, 2

3

EXTAL input low

• With PLL disabled (46.7%–53.3% duty

4.67 ns

∞

4.67 ns

—

6

cycle )

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Specifications

EXTERNAL CLOCK OPERATION

Table 2-5 Clock Operation (Continued) 100 and 120 MHz Values

100 MHz

Min Max

4.25 ns 157.0 µs 4.25 ns 1570.00

120 MHz

No.

Characteristics

Symbol

Min Max

• With PLL enabled (42.5%–57.5% duty

6

cycle )

2

EXTAL cycle time

4

5

ET_C

• With PLL disabled

• With PLL enabled

10.00 ns

∞

8.33 ns

—

10.00 ns 273.1 µs 8.33 ns 273.1 µs

CLKOUT change from EXTAL fall with PLL

disabled

4.3 ns 11.0 ns

CLKOUT rising edge from EXTAL rising

edge with PLL enabled (MF = 1,

0.0 ns

1.8 ns

3,5

PDF = 1, Ef > 15 MHz)

CLKOUT falling edge from EXTAL rising

edge with PLL enabled (MF = 2 or 4, PDF =

6

3,5

1, Ef > 15 MHz)

CLKOUT falling edge from EXTAL falling

edge with PLL enabled (MF ≤ 4, PDF ≠ 1,

3,5

Ef / PDF > 15 MHz)

4

Instruction cycle time = I_CYC= T_C

See Table 2-5 (46.7%–53.3% duty cycle)

• With PLL disabled

7

I_CYC

0.00 ns

∞

• With PLL enabled

0.00 ns 8.53 µs

8.53 µs

Notes: 1. Measured at 50% of the input transition

2. The maximum value for PLL enabled is given for minimum V_COand

maximum MF.

3. Periodically sampled and not 100% tested

4. The maximum value for PLL enabled is given for minimum V_COand

maximum DF.

5. The skew is not guaranteed for any other MF value.

6. The indicated duty cycle is for the specified maximum frequency for which

a part is rated. The minimum clock high or low time required for correction

operation, however, remains the same at lower operating frequencies;

therefore, when a lower clock frequency is used, the signal symmetry may

vary from the specified duty cycle as long as the minimum high time and

low time requirements are met.

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Specifications

Phase Lock Loop (PLL) Characteristics

PHASE LOCK LOOP (PLL) CHARACTERISTICS

Table 2-6 PLL Characteristics

100 MHz

Characteristics

Min

Unit

Max

V_COfrequency when PLL enabled

30

200

MHz

(MF × E_f× 2/PDF)

PLL external capacitor (PCAP pin

1)

to V_CCP) (C_PCAP

• @ MF ≤ 4

• @ MF > 4

(MF × 580) − 100 (MF × 780) − 140

MF × 830 MF × 1470

pF

Note:

C_PCAPis the value of the PLL capacitor (connected between the PCAP pin and

V_CCP). The recommended value in pF for C_PCAPcan be computed from one of the

following equations:

(680 × MF) – 120, for MF ≤ 4, or

1100 × MF, for MF > 4.

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

6

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

100 MHz

120 MHz

No.

Characteristics

Expression

Unit

ns

Min

Max

Min

Max

Delay from RESET assertion to

8

—

26.0

3

all pins at reset value

4

Required RESET duration

• Power on, external clock

generator, PLL disabled

50 × ET_C

500.0

—

416.7

—

ns

9

• Power on, external clock

1000 × ET_C

75000 × ET_C

10.0

750

—

8.3

625

—

µs

generator, PLL enabled

• Power on, internal oscillator

• During STOP, XTAL

disabled (PCTL Bit 16 = 0)

• During STOP, XTAL enabled

2.5 × T_C

25.0

—

20.8

—

ns

(PCTL Bit 16 = 1)

• During normal operation

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

100 MHz

Min Max

120 MHz

No.

Characteristics

Expression

Unit

Min

Max

Delay from asynchronous

RESET deassertion to first

external address output

(internal reset deassertion)

10

5

• Minimum

• Maximum

3.25 × T_C+ 2.0

20.25 T_C+ 7.50

34.5

—

211.5

29.1

ns

176.2

Synchronous reset setup time

from RESET deassertion to

CLKOUT Transition 1

• Minimum

• Maximum

11

12

5.9

—

10.0

ns

T_C

Synchronous reset deasserted,

delay time from the CLKOUT

Transition 1 to the first external

address output

• Minimum

• Maximum

3.25 × T_C+ 2.0

20.25 T_C+ 7.5

33.5

—

30.0

—

207.5

—

ns

13

14

30.0

0.0

Mode select setup time

Mode select hold time

0.0

—

ns

Minimum edge-triggered

interrupt request assertion

width

15

16

6.6

—

5.5

ns

Minimum edge-triggered

interrupt request deassertion

width

6.6

—

ns

Delay from IRQA, IRQB, IRQC,

IRQD, NMI assertion to

external memory access

address out valid

17

18

• Caused by first interrupt

4.25 × T_C+ 2.0

7.25 × T_C+ 2.0

44.5

74.5

—

37.4

62.4

ns

instruction fetch

• Caused by first interrupt

instruction execution

Delay from IRQA, IRQB, IRQC,

IRQD, NMI assertion to

10 × T_C+ 5.0

105.0

—

88.3

ns

general-purpose transfer output

valid caused by first interrupt

instruction execution

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

100 MHz

120 MHz

No.

Characteristics

Expression

Unit

Min

Max

Min

Max

Delay from address output valid

caused by first interrupt

(3.75 + WS) × T_C–

19

—

(Note 9)

—

(Note 9) ns

(Note 9)

instruction execute to interrupt

request deassertion for level

10.94

1

sensitive fast interrupts

Delay from RD assertion to

interrupt request deassertion

for level sensitive fast

(3.25 + WS) × T_C–

20

21

22

(Note 9)

—

10.94

1

interrupts

Delay from WR assertion to

interrupt request deassertion

for level sensitive fast

1

interrupts

• DRAM for all WS

(WS + 3.5) × T_C–

—

(Note 9)

—

(Note 9) ns

10.94

• SRAM WS =1

(WS + 3.5) × T_C–

10.94

• SRAM WS=2,3

—

(Note 9)

—

(Note 9) ns

1.75 × T_C– 4.0

2.75 × T_C– 4.0

• SRAM WS ≥ 4

Synchronous interrupt setup

time from IRQA, IRQB, IRQC,

IRQD, NMI assertion to the

CLKOUT Transition 2

4.9

—

ns

0.6 × T_C– 0.1

5.9

Synchronous interrupt delay

time from the CLKOUT

Transition 2 to the first external

address output valid caused by

the first instruction fetch after

coming out of Wait Processing

state

• Minimum

• Maximum

23

24

9.25 × T_C+ 1.0

24.75 × T_C+ 5.0

93.5

—

252.5

78.1

—

211.2

ns

Duration for IRQA assertion to

recover from Stop state

0.6 × T_C− 0.1

5.9

—

4.9

—

ns

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

100 MHz

120 MHz

No.

Characteristics

Expression

Unit

Min

Max

Min

Max

Delay from IRQA assertion to

fetch of first instruction (when

2, 3

exiting Stop)

• PLL is not active during Stop

(PCTL Bit 17 = 0) and Stop

delay is enabled

PLC × ET_C× PDF +

(128 K − PLC/2) × T_C

1.3

13.6

—

ms

(OMR Bit 6 = 0)

25

• PLL is not active during Stop

(PCTL Bit 17 = 0) and Stop

delay is not enabled (OMR

Bit 6 = 1)

PLC × ET_C× PDF + 232.5

12.3 ms

87.5

—

(23.75 0.5) × T_C

ns

• PLL is active during Stop

(PCTL Bit 17 = 1) (Implies

No Stop Delay)

(8.25 0.5) × T_C

77.5

64.6

72.9

ns

Duration of level sensitive IRQA

assertion to ensure interrupt

2, 3

service (when exiting Stop)

• PLL is not active during Stop

(PCTL Bit 17 = 0) and Stop

delay is enabled

PLC × ET_C× PDF +

(128K − PLC/2) × T_C

26

13.6

—

ms

(OMR Bit 6 = 0)

• PLL is not active during Stop

(PCTL Bit 17 = 0) and Stop

delay is not enabled

PLC × ET_C× PDF +

(20.5 0.5) × T_C

12.3

55.0

—

ms

ns

(OMR Bit 6 = 1)

• PLL is active during Stop

(PCTL Bit 17 = 1) (implies no

Stop delay)

5.5 × T_C

45.8

—

Interrupt Requests Rate

27

• HI08, ESAI, SHI, Timer

• DMA

• IRQ, NMI (edge trigger)

• IRQ, NMI (level trigger)

12T_C

8T_C

—

120.0

80.0

—

100.0

66.7

ns

12T_C

120.0

100.0

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

100 MHz

120 MHz

No.

Characteristics

Expression

Unit

Min

Max

Min

Max

DMA Requests Rate

• Data read from HI08, ESAI,

SHI

28

6T_C

7T_C

—

60.0

70.0

—

50.0

58.0

ns

• Data write to HI08, ESAI,

SHI

• Timer

• IRQ, NMI (edge trigger)

2T_C

3T_C

—

20.0

30.0

—

16.7

25.0

ns

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

6

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values

100 MHz

Min Max

120 MHz

No.

Characteristics

Expression

Unit

Min

Max

Delay from IRQA, IRQB, IRQC,

IRQD, NMI assertion to

29

4.25 × T_C+ 2.0

44.0

—

37.4

—

ns

external memory (DMA source)

access address out valid

Notes: 1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings

19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the

deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are

recommended when using Level-sensitive mode.

2. This timing depends on several settings:

For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator

disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is

stable before executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide

the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these

specifications do not guarantee timings for that case.

For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL

Bit 17=1), no stabilization delay is required and recovery time will be minimal (OMR Bit 6 setting is

ignored).

For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery

time will be defined by the PCTL Bit 17 and OMR Bit 6 settings.

For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires

the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range

of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery

will end when the last of these two events occurs. The stop delay counter completes count or PLL lock

procedure completion.

PLC value for PLL disable is 0.

The maximum value for ET_Cis 4096 (maximum MF) divided by the desired internal frequency (i.e., for

100 MHz it is 4096/100 MHz = 40.96µs). During the stabilization period, T_C, T_H,and T_Lwill not be

constant, and their width may vary, so timing may vary as well.

3. Periodically sampled and not 100% tested

4. For an external clock generator, RESET duration is measured during the time in which RESET is

asserted, V_CCis valid, and the EXTAL input is active and valid.

For internal oscillator, RESET duration is measured during the time in which RESET is asserted and

V_CCis valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This

number is affected both by the specifications of the crystal and other components connected to the

oscillator and reflects worst case conditions.

When the V_CCis valid, but the other “required RESET duration” conditions (as specified above) have

not been yet met, the device circuitry will be in an uninitialized state that can result in significant power

consumption and heat-up. Designs should minimize this state to the shortest possible duration.

5. If PLL does not lose lock

6.

V_CC= 3.3 V 0.16 V; T_J= 0°C to +100°C, C_L= 50 pF

7. WS = number of wait states (measured in clock cycles, number of T_C)

8. Use expression to compute maximum value.

9. These values depend on the number of wait states (WS) selected

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

V_IH

RESET

9

10

8

All Pins

A0–A17

Reset Value

First Fetch

AA0460

Figure 2-2 Reset Timing

CLKOUT

11

RESET

A0–A17

12

AA0461

Figure 2-3 Synchronous Reset Timing

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

First Interrupt Instruction

Execution/Fetch

A0–A17

RD

20

WR

21

19

17

IRQA, IRQB,

IRQC, IRQD,

NMI

a) First Interrupt Instruction Execution

General

Purpose

I/O

18

IRQA, IRQB,

IRQC, IRQD,

NMI

b) General Purpose I/O

AA0462

Figure 2-4 External Fast Interrupt Timing

IRQA, IRQB,

IRQC, IRQD,

NMI

15

16

IRQA, IRQB,

IRQC, IRQD,

NMI

AA0463

Figure 2-5 External Interrupt Timing (Negative Edge-Triggered)

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

CLKOUT

22

IRQA, IRQB,

IRQC, IRQD,

NMI

23

A0–A17

AA0464

Figure 2-6 Synchronous Interrupt from Wait State Timing

V_IH

RESET

13

14

IRQA, IRQB,

IRQC, IRQD, NMI

V_IH

V_IL

V_IH

V_IL

MODA, MODB,

MODC, MODD,

PINIT

AA0465

Figure 2-7 Operating Mode Select Timing

24

IRQA

25

First Instruction Fetch

A0–A17

AA0466

Figure 2-8 Recovery from Stop State Using IRQA

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Specifications

Reset, Stop, Mode Select, and Interrupt Timing

26

IRQA

25

A0–A17

First IRQA Interrupt

Instruction Fetch

AA0467

Figure 2-9 Recovery from Stop State Using IRQA Interrupt Service

DMA Source Address

A0–A17

RD

WR

29

IRQA, IRQB,

IRQC, IRQD,

NMI

First Interrupt Instruction Execution

AA1104

Figure 2-10 External Memory Access (DMA Source) Timing

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Specifications

External Memory Expansion Port (Port A)

EXTERNAL MEMORY EXPANSION PORT (PORT A)

SRAM Timing

3

Table 2-8 SRAM Read and Write Accesses 100 and 120 MHz

100 MHz

120 MHz

1

No. Characteristics Symbol

Unit

Expression

Min Max Min Max

(WS + 1) × T_C− 4.0

[1 ≤ WS ≤ 3]

16.0

56.0

—

12.0

46.0

87.0

—

ns

Address valid and

(WS + 2) × T_C− 4.0

100

101

t_RC, t_WC

AA assertion pulse

width

[4 ≤ WS ≤ 7]

(WS + 3) × T_C− 4.0

[WS ≥ 8]

106.0

100 MHz:

0.5

—

0.1

—

ns

0.25 × T_C− 2.0

Address and AA

valid to WR

assertion

[WS = 1]

t_AS

1.25 × T_C− 2.0

[WS ≥ 4]

10.5

11.0

—

8.4

8.5

—

ns

100 MHz:

1.5 × T_C− 4.0 [WS = 1]

All frequencies:

WS × T_C− 4.0

[2 ≤ WS ≤ 3]

WR assertion

pulse width

102

t_WP

16.0

31.0

0.5

—

---

—

12.7

25.2

0.1

—

ns

(WS − 0.5) × T_C− 4.0

[WS ≥ 4]

100 MHz:

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

10.5

20.5

8.5

—

8.4

—

WR deassertion to

address not valid

2.25 × T_C− 2.0

[WS ≥ 8]

103

104

t_WR

16.7

ns

All frequencies:

1.25 × T_C− 4.0

[4 ≤ WS ≤ 7]

—

6.4

—

18.5

—

2.25 × T_C− 4.0

[WS ≥ 8]

14.7

Address and AA

valid to input data

valid

100 MHz:

t_AA, t_AC

10.5

7.6

(WS + 0.75) × T_C− 7.0

[WS ≥ 1]

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External Memory Expansion Port (Port A)

3

Table 2-8 SRAM Read and Write Accesses 100 and 120 MHz (Continued)

100 MHz

120 MHz

1

No. Characteristics Symbol

Unit

Expression

Min Max Min Max

100 MHz:

RD assertion to

105

t_OE

—

5.5

—

3.4

ns

(WS + 0.25) × T_C− 7.0

[WS ≥ 1]

input data valid

RD deassertion to

data not valid (data

hold time)

106

107

108

t_OHZ

0.0

13.5

4.5

—

0.0

10.6

3.2

—

ns

Address valid to

WR deassertion²

(WS + 0.75) × T_C− 4.0

[WS ≥ 1]

t_AW

ns

Data valid to WR

deassertion (data

setup time)

100 MHz:

t

_DS(t_DW)

(WS − 0.25) × T_C− 3.0

[WS ≥ 1]

100 MHz:

0.5

—

0.1

—

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

Data hold time

from WR

ns

109

110

111

112

t_DH

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

10.5

20.5

—

8.4

—

deassertion

2.25 × T_C− 2.0

[WS ≥ 8]

16.7

0.75 × T_C− 3.7

—

2.5

—

[WS = 1]

WR assertion to

data active

ns

0.25 × T_C− 3.7

[2 ≤ WS ≤ 3]

—

0.0

—

−0.25 × T_C− 3.7

[WS ≥ 4]

0.25 × T_C+ 0.2

[1 ≤ WS ≤ 3]

—

2.3

WR deassertion to

data high

1.25 × T_C+ 0.2

[4 ≤ WS ≤ 7]

—

10.6

18.9

impedance

2.25 × T_C+ 0.2

[WS ≥ 8]

1.25 × T_C− 4.0

[1 ≤ WS ≤ 3]

—

6.4

—

Previous RD

deassertion to data

active (write)

2.25 × T_C− 4.0

[4 ≤ WS ≤ 7]

—

14.7

23.1

—

3.25 × T_C− 4.0

[WS ≥ 8]

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Specifications

External Memory Expansion Port (Port A)

Table 2-8 SRAM Read and Write Accesses 100 and 120 MHz (Continued)

3

100 MHz

120 MHz

1

No. Characteristics Symbol

Unit

Expression

Min Max Min Max

100 MHz

3.5

—

2.2

—

0.75 × T_C− 4.0

[1 ≤ WS ≤ 3]

RD deassertion

113

ns

1.75 × T_C− 4.0

[4 ≤ WS ≤ 7]

13.5

23.5

—

10.6

18.9

—

time

2.75 × T_C− 4.0

[WS ≥ 8]

100 MHz

1.0

—

0.2

—

0.5 × T_C− 4.0

[WS = 1]

T_C− 2.0

6.0

21.0

31.0

1.0

—

6.3

16.8

25.2

0.2

—

WR deassertion

114

[2 ≤ WS ≤ 3]

ns

time

2.5 × T_C− 4.0

[4 ≤ WS ≤ 7]

3.5 × T_C− 4.0

[WS ≥ 8]

Address valid to

115

100 MHz

ns

RD assertion

0.5 × T_C− 4.0

RD assertion pulse

116

100 MHz

8.5

6.4

width

(WS + 0.25) × T_C−4.0

100 MHz

0.5

—

0.1

—

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

RD deassertion to

117

ns

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

10.5

20.5

—

8.4

—

address not valid

2.25 × T_C− 2.0

[WS ≥ 8]

16.7

TA setup before

118

119

4.5

0

—

4.1

0.0

—

ns

RD or WR

0.25 × T_C+ 2.0

deassertion⁴

TA hold after RD or

WR deassertion

Notes: 1. WS is the number of wait states specified in the BCR.

2. Timings 100, 107 are guaranteed by design, not tested.

3. All timings for 100 MHz are measured from 0.5 · Vcc to .05 · Vcc

4. In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to

remain active

5. Timing 110, 111, and 112, are not specified for 100 MHz.

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Specifications

External Memory Expansion Port (Port A)

100

A0–A17

AA0–AA3

117

106

116

113

RD

115

105

WR

104

119

118

TA

Data

In

D0–D23

AA0468

Figure 2-11 SRAM Read Access

100

A0–A17

AA0–AA3

107

101

102

103

WR

114

RD

TA

118

119

108

111

110

109

112

Data

Out

D0–D23

AA0469

Figure 2-12 SRAM Write Access

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Specifications

External Memory Expansion Port (Port A)

DRAM Timing

The selection guides provided in Figure 2-13 and Figure 2-16 should be used for primary selection only.

Final selection should be based on the timing provided in the following tables. As an example, the

selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode

DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate

whether fewer wait states might be used by determining which timing prevents operation at 100 MHz,

running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available),

and control factors such as capacitive and resistive load to improve overall system performance.

DRAM Type

(tRAC ns)

Note: This figure should be used for primary selection.

For exact and detailed timings see the following

tables.

100

80

70

60

50

Chip Frequency

(MHz)

120

40

66

80

100

1 Wait States

2 Wait States

3 Wait States

4 Wait States

AA0472

Figure 2-13 DRAM Page Mode Wait States Selection Guide

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Specifications

External Memory Expansion Port (Port A)

Table 2-9 DRAM Page Mode Timings, One Wait State

1, 2, 3

(Low-Power Applications)

6

20 MHz

30 MHz

No.

Characteristics

Symbol

Expression

2 × T_C

Unit

Min

Max

Min

Max

Page mode cycle time for

two consecutive accesses of

the same direction

100.0

62.5

—

66.7

—

131

t_PC

ns

Page mode cycle time for

mixed (read and write)

accesses.

1.25 x Tc

—

41.7

—

CAS assertion to data valid

(read)

132

133

134

135

t_CAC

t_AA

t_OFF

t_RSH

T_C− 7.5

—

42.5

67.5

—

25.8

42.5

—

ns

Column address valid to

data valid (read)

1.5 × T_C− 7.5

CAS deassertion to data not

valid (read hold time)

0.0

21.0

Last CAS assertion to RAS

deassertion

0.75 × T_C− 4.0 33.5

2 × T_C− 4.0 96.0

—

Previous CAS deassertion to

RAS deassertion

136

137

t_RHCP

t_CAS

—

62.7

21.0

—

ns

0.75 × T_C− 4.0 33.5

CAS assertion pulse width

Last CAS deassertion to

4

RAS deassertion

• BRW[1:0] = 00

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

1.75 × T_C− 6.0 81.5

3.25 × T_C− 6.0 156.5

4.25 × T_C− 6.0 206.5

6.25 × T_C– 6.0 306.5

—

52.3

102.2

135.5

202.1

12.7

—

138

t_CRP

ns

139

140

t_CP

0.5 × T_C− 4.0

21.0

ns

CAS deassertion pulse width

Column address valid to

CAS assertion

t_ASC

0.5 × T_C− 4.0

21.0

—

12.7

21.0

62.7

21.2

4.6

—

CAS assertion to column

address not valid

141

142

143

144

145

t_CAH

t_RAL

0.75 × T_C− 4.0 33.5

2 × T_C− 4.0 96.0

0.75 × T_C− 3.8 33.7

ns

Last column address valid to

RAS deassertion

WR deassertion to CAS

assertion

t_RCS

t_RCH

t_WCH

CAS deassertion to WR

assertion

0.25 × T_C− 3.7

0.5 × T_C− 4.2

8.8

CAS assertion to WR

deassertion

20.8

12.5

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Specifications

External Memory Expansion Port (Port A)

Table 2-9 DRAM Page Mode Timings, One Wait State

1, 2, 3

(Low-Power Applications)

(Continued)

6

20 MHz

30 MHz

No.

Characteristics

Symbol

Expression

Unit

Min

Max

Min

Max

146

147

t_WP

1.5 × T_C− 4.5

70.5

—

45.5

—

ns

WR assertion pulse width

Last WR assertion to RAS

deassertion

t_RWL

1.75 × T_C− 4.3 83.2

—

54.0

4.3

—

WR assertion to CAS

deassertion

148

149

150

151

t_CWL

t_DS

—

ns

Data valid to CAS assertion

(Write)

0.25 × T_C− 4.0

8.5

CAS assertion to data not

valid (write)

t_DH

0.75 × T_C− 4.0 33.5

21.0

29.0

WR assertion to CAS

assertion

t_WCS

T_C− 4.3

45.7

Last RD assertion to RAS

deassertion

152

153

154

155

156

t_ROH

t_GA

1.5 × T_C− 4.0

T_C− 7.5

71.0

—

42.5

—

46.0

—

25.8

—

ns

RD assertion to data valid

RD deassertion to data not

t_GZ

0.0

24.7

—

5

valid

0.75 × T_C− 0.3 37.2

0.25 × T_C

—

WR assertion to data active

WR deassertion to data high

impedance

—

12.5

8.3

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. All the timings are calculated for the worst case. Some of the timings are better for specific cases

(e.g., t_PCequals 2 × T_Cfor read-after-read or write-after-write sequences).

4. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in

each DRAM out-of-page access.

5. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand

not t_GZ

.

6. Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state. See Figure 2-13.

1, 2, 3, 7

Table 2-10 DRAM Page Mode Timings, Two Wait States

80 MHz

No.

Characteristics

Symbol

Expression

Unit

Min Max

Page mode cycle time for two

consecutive accesses of the same

direction

3 × T_C

37.5

34.4

—

131

t_PC

ns

Page mode cycle time for mixed (read

and write) accesses.

2.75 x Tc

2-24

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1, 2, 3, 7

Table 2-10 DRAM Page Mode Timings, Two Wait States

(Continued)

80 MHz

No.

Characteristics

Symbol

Expression

Unit

Min Max

132

133

t_CAC

t_AA

1.5 × T_C− 6.5

2.5 × T_C− 6.5

—

12.3

ns

CAS assertion to data valid (read)

Column address valid to data valid

(read)

—

24.8

CAS deassertion to data not valid (read

hold time)

134

135

136

137

t_OFF

t_RSH

t_RHCP

t_CAS

0.0

—

ns

1.75 × T_C− 4.0

3.25 × T_C− 4.0

1.5 × T_C− 4.0

17.9

36.6

14.8

Last CAS assertion to RAS deassertion

Previous CAS deassertion to RAS

deassertion

CAS assertion pulse width

Last CAS deassertion to RAS

5

deassertion

• BRW[1:0] = 00

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

2.0 × T_C− 6.0

3.5 × T_C− 6.0

4.5 × T_C− 6.0

6.5 × T_C− 6.0

1.25 × T_C− 4.0

19.0

37.8

50.3

75.3

11.6

—

138

t_CRP

ns

139

140

t_CP

ns

CAS deassertion pulse width

t_ASC

T_C− 4.0

8.5

—

Column address valid to CAS assertion

CAS assertion to column address not

valid

141

142

t_CAH

t_RAL

1.75 × T_C− 4.0

17.9

—

ns

Last column address valid to RAS

deassertion

3 × T_C− 4.0

33.5

—

143

144

145

146

147

148

149

150

151

152

153

154

155

t_RCS

t_RCH

t_WCH

t_WP

1.25 × T_C− 3.8

0.5 × T_C− 3.7

1.5 × T_C− 4.2

2.5 × T_C− 4.5

2.75 × T_C− 4.3

2.5 × T_C− 4.3

0.25 × T_C− 3.0

1.75 × T_C− 4.0

T_C− 4.3

11.8

2.6

—

ns

WR deassertion to CAS assertion

CAS deassertion to WR assertion

CAS assertion to WR deassertion

WR assertion pulse width

14.6

26.8

30.1

27.0

0.1

—

t_RWL

t_CWL

t_DS

—

Last WR assertion to RAS deassertion

WR assertion to CAS deassertion

Data valid to CAS assertion (write)

CAS assertion to data not valid (write)

WR assertion to CAS assertion

Last RD assertion to RAS deassertion

RD assertion to data valid

—

t_DH

17.9

8.2

—

t_WCS

t_ROH

t_GA

—

2.5 × T_C− 4.0

1.75 × T_C− 6.5

27.3

—

15.4

—

6

t_GZ

0.0

RD deassertion to data not valid

0.75 × T_C− 0.3

9.1

—

WR assertion to data active

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Specifications

External Memory Expansion Port (Port A)

1, 2, 3, 7

Table 2-10 DRAM Page Mode Timings, Two Wait States

(Continued)

80 MHz

No.

Characteristics

Symbol

Expression

Unit

Min Max

WR deassertion to data high

impedance

156

0.25 × T_C

—

3.1

ns

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56362.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases

(e.g., t_PCequals 3 × T_Cfor read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted

in each DRAM out-of-page access.

6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFF

and not t_GZ.

7. There are not any fast enough DRAMs to fit to two wait states Page mode @ 100MHz. See

Figure 2-13.

1, 2, 3

Table 2-11 DRAM Page Mode Timings, Three Wait States

100 MHz

No.

Characteristics

Symbol Expression

Unit

Min

Max

Page mode cycle time for two

consecutive accesses of the same

direction

4 × T_C

40.0

—

131

t_PC

ns

Page mode cycle time for mixed (read

and write) accesses.

3.5 x Tc

35.0

—

100 MHz:

132

133

t_CAC

13.0

23.0

ns

CAS assertion to data valid (read)

2 × T_C− 7.0

Column address valid to data valid

(read)

100 MHz:

t_AA

—

3 × T_C− 7.0

CAS deassertion to data not valid (read

hold time)

134

135

136

137

t_OFF

0.0

—

ns

t_RSH

t_RHCP

t_CAS

2.5 × T_C− 4.0 21.0

4.5 × T_C− 4.0 41.0

Last CAS assertion to RAS deassertion

Previous CAS deassertion to RAS

deassertion

2 × T_C− 4.0

16.0

CAS assertion pulse width

Last CAS deassertion to RAS

5

assertion

• BRW[1:0] = 00

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

2.25 × T_C− 6.0

3.75 × T_C− 6.0

4.75 × T_C− 6.0 41.5

6.75 × T_C− 6.0 61.5

—

138

t_CRP

ns

2-26

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Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-11 DRAM Page Mode Timings, Three Wait States

(Continued)

100 MHz

No.

Characteristics

Symbol Expression

Unit

Min

1.5 × T_C− 4.0 11.0

T_C− 4.0 6.0

2.5 × T_C− 4.0 21.0

Max

—

139

140

t_CP

ns

CAS deassertion pulse width

t_ASC

—

Column address valid to CAS assertion

CAS assertion to column address not

valid

141

142

143

144

t_CAH

t_RAL

t_RCS

t_RCH

—

ns

Last column address valid to RAS

deassertion

4 × T_C− 4.0

36.0

8.5

100 MHz:

WR deassertion to CAS assertion

CAS deassertion to WR assertion

1.25 × T_C− 4.0

100 MHz:

3.5

0.75 × T_C− 4.0

145

146

147

148

149

150

151

152

t_WCH

t_WP

2.25 × T_C− 4.2 18.3

3.5 × T_C− 4.5 30.5

3.75 × T_C− 4.3 33.2

3.25 × T_C− 4.3 28.2

—

ns

CAS assertion to WR deassertion

WR assertion pulse width

t_RWL

t_CWL

t_DS

Last WR assertion to RAS deassertion

WR assertion to CAS deassertion

Data valid to CAS assertion (write)

CAS assertion to data not valid (write)

WR assertion to CAS assertion

Last RD assertion to RAS deassertion

0.5 × T_C− 4.0

1.0

t_DH

2.5 × T_C− 4.0 21.0

1.25 × T_C− 4.3 8.2

3.5 × T_C− 4.0 31.0

t_WCS

t_ROH

t_GA

t_GZ

100 MHz:

153

—

18.0

ns

RD assertion to data valid

2.5 × T_C− 7.0

6

154

155

0.0

—

ns

RD deassertion to data not valid

0.75 × T_C− 0.3 7.2

WR assertion to data active

WR deassertion to data high

impedance

156

0.25 × T_C

—

2.5

ns

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56362.

4. All the timings are calculated for the worst case. Some of the timings are better for specific

cases (e.g., t_PCequals 4 × T_Cfor read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be

inserted in each DRAM out-of page-access.

6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is

t_OFFand not t_GZ

.

MOTOROLA

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Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz

100 MHz

120 MHz

No.

Characteristics

Symbol Expression

Unit

Min Max Min Max

Page mode cycle time for two

consecutive accesses of the same

direction

5 × T_C

50.0

—

41.7

131

t_PC

ns

Page mode cycle time for mixed (read

and write) accesses.

4.5 × T_C

45.0

—

20.5

30.5

—

37.5

—

100 MHz:

132

133

134

135

t_CAC

15.9 ns

24.2 ns

CAS assertion to data valid (read)

2.75 × T_C− 7.0

Column address valid to data valid

(read)

100 MHz:

t_AA

—

3.75 × T_C− 7.0

CAS deassertion to data not valid

(read hold time)

t_OFF

0.0

25.2

—

ns

Last CAS assertion to RAS

deassertion

t_RSH

3.5 × T_C− 4.0 31.0

—

Previous CAS deassertion to RAS

deassertion

136

137

t_RHCP

t_CAS

6 × T_C− 4.0

56.0

—

46.0

16.8

—

ns

2.5 × T_C− 4.0 21.0

CAS assertion pulse width

Last CAS deassertion to RAS

5

assertion

138

t_CRP

ns

• BRW[1:0] = 00

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

2.75 × T_C− 6.0

4.25 × T_C− 6.0

5.25 × T_C− 6.0 46.5

7.25 × T_C− 6.0 66.5

—

37.7

54.4

12.7

—

139

140

t_CP

2 × T_C− 4.0

16.0

ns

CAS deassertion pulse width

Column address valid to CAS

assertion

t_ASC

T_C− 4.0

6.0

—

4.3

25.2

37.7

6.4

—

CAS assertion to column address not

valid

141

142

143

144

t_CAH

t_RAL

t_RCS

t_RCH

3.5 × T_C− 4.0 31.0

ns

Last column address valid to RAS

deassertion

5 × T_C− 4.0

46.0

8.5

100 MHz:

WR deassertion to CAS assertion

CAS deassertion to WR assertion

1.25 × T_C− 4.0

100 MHz:

8.5

6.4

1.25 × T_C− 4.0

145

146

t_WCH

t_WP

3.25 × T_C− 4.2 28.3

4.5 × T_C− 4.5 40.5

—

22.9

33.0

—

ns

CAS assertion to WR deassertion

WR assertion pulse width

2-28

DSP56362 Advance Information

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Specifications

External Memory Expansion Port (Port A)

1, 2, 3

Table 2-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz

(Continued)

100 MHz

120 MHz

No.

Characteristics

Symbol Expression

Unit

Min Max Min Max

Last WR assertion to RAS

deassertion

147

t_RWL

4.75 × T_C− 4.3 43.2

—

35.3

—

ns

148

149

150

151

152

t_CWL

t_DS

3.75 × T_C− 4.3 33.2

0.5 × T_C− 4.0 1.0

3.5 × T_C− 4.0 31.0

1.25 × T_C− 4.3 8.2

4.5 × T_C− 4.0 41.0

—

26.9

0.2

—

ns

WR assertion to CAS deassertion

Data valid to CAS assertion (write)

CAS assertion to data not valid (write)

WR assertion to CAS assertion

t_DH

25.2

6.1

t_WCS

t_ROH

t_GA

t_GZ

33.5

Last RD assertion to RAS deassertion

100 MHz:

153

—

25.5

—

20.1 ns

RD assertion to data valid

3.25 × T_C− 7.0

6

154

155

0.0

—

0.0

5.9

—

ns

RD deassertion to data not valid

0.75 × T_C− 0.3 7.2

WR assertion to data active

WR deassertion to data high

impedance

156

0.25 × T_C

—

2.5

—

2.1

ns

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56362.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases

(e.g., t_PCequals 3 × T_Cfor read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in

each DRAM out-of-page access.

6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand

not t_GZ

.

MOTOROLA

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Specifications

External Memory Expansion Port (Port A)

RAS

136

131

135

CAS

137

140

139

141

138

142

Column

Address

Last Column

Address

Column

Address

Row

Add

A0–A17

151

144

143

145

147

WR

RD

146

148

155

149

156

150

D0–D23

Data Out

AA0473

Figure 2-14 DRAM Page Mode Write Accesses

2-30

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Specifications

External Memory Expansion Port (Port A)

RAS

CAS

136

131

135

137

140

139

141

138

142

Row

Add

Last Column

Address

Column

Address

Column

Address

A0–A17

WR

143

132

133

153

152

RD

134

154

D0–D23

Data In

AA0474

Figure 2-15 DRAM Page Mode Read Accesses

MOTOROLA

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Specifications

External Memory Expansion Port (Port A)

DRAM Type

(tRAC ns)

Note: This figure should be use for primary selection. For

exact and detailed timings see the following tables.

100

80

70

60

Chip Frequency

(MHz)

50

120

40

66

80

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

AA0475

Figure 2-16 DRAM Out-of-Page Wait States Selection Guide

1, 2

Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

4

20 MHz

30 MHz

3

No.

Symbol

Expression

Unit

Characteristics

Min

Max

Min

Max

Random read or write

cycle time

157

158

159

160

161

162

t_RC

t_RAC

t_CAC

t_AA

5 × T_C

250.0

—

166.7

—

ns

RAS assertion to data

valid (read)

2.75 × T_C− 7.5

1.25 × T_C− 7.5

1.5 × T_C− 7.5

130.0

55.0

67.5

—

84.2

34.2

42.5

—

CAS assertion to data

valid (read)

—

Column address valid to

data valid (read)

—

CAS deassertion to data

not valid (read hold time)

t_OFF

t_RP

0.0

83.5

0.0

54.3

RAS deassertion to RAS

assertion

1.75 × T_C− 4.0

—

2-32

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1, 2

Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

(Continued)

4

20 MHz

30 MHz

3

No.

Symbol

Expression

Unit

Characteristics

Min

Max

Min

Max

RAS assertion pulse

width

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

3.25 × T_C− 4.0 158.5

—

104.3

—

ns

CAS assertion to RAS

deassertion

1.75 × T_C− 4.0

83.5

—

54.3

87.7

37.7

48.0

39.7

71.0

54.3

37.7

4.3

—

RAS assertion to CAS

deassertion

2.75 × T_C− 4.0 133.5

CAS assertion pulse

width

1.25 × T_C− 4.0

58.5

73.0

60.5

—

RAS assertion to CAS

assertion

1.5 × T_C

2

77.0

64.5

—

52.0

43.7

—

RAS assertion to column

address valid

1.25 × T_C

2

CAS deassertion to RAS

assertion

2.25 × T_C− 4.0 108.5

CAS deassertion pulse

width

1.75 × T_C− 4.0

1.25 × T_C− 4.0

0.25 × T_C− 4.0

1.75 × T_C− 4.0

83.5

58.5

8.5

—

Row address valid to

RAS assertion

t_ASR

t_RAH

t_ASC

t_CAH

t_AR

—

RAS assertion to row

address not valid

—

Column address valid to

CAS assertion

—

CAS assertion to column

address not valid

83.5

—

54.3

104.3

62.7

46.2

21.3

4.6

—

RAS assertion to column

address not valid

3.25 × T_C− 4.0 158.5

—

Column address valid to

RAS deassertion

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

2 × T_C− 4.0

1.5 × T_C− 3.8

0.75 × T_C− 3.7

0.25 × T_C− 3.7

1.5 × T_C− 4.2

3 × T_C− 4.2

96.0

71.2

33.8

8.8

—

WR deassertion to CAS

assertion

—

CAS deassertion to WR

assertion

—

RAS deassertion to WR

assertion

—

CAS assertion to WR

deassertion

70.8

145.8

—

45.8

95.8

—

RAS assertion to WR

deassertion

—

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1, 2

Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

(Continued)

4

20 MHz

30 MHz

3

No.

Symbol

Expression

Unit

Characteristics

Min

Max

Min

Max

182

183

t_WP

4.5 × T_C− 4.5

220.5

—

145.5

—

ns

WR assertion pulse width

WR assertion to RAS

deassertion

t_RWL

4.75 × T_C− 4.3 233.2

4.25 × T_C− 4.3 208.2

2.25 × T_C− 4.0 108.5

—

154.0

—

WR assertion to CAS

deassertion

184

185

186

187

188

189

190

t_CWL

t_DS

137.4

71.0

54.3

104.3

95.7

12.7

37.7

ns

Data valid to CAS

assertion (write)

CAS assertion to data not

valid (write)

t_DH

1.75 × T_C− 4.0

83.5

RAS assertion to data not

valid (write)

t_DHR

t_WCS

t_CSR

t_RPC

3.25 × T_C− 4.0 158.5

WR assertion to CAS

assertion

3 × T_C− 4.3

0.5 × T_C− 4.0

1.25 × T_C− 4.0

145.7

21.0

58.5

CAS assertion to RAS

assertion (refresh)

RAS deassertion to CAS

assertion (refresh)

RD assertion to RAS

deassertion

191

192

193

t_ROH

t_GA

4.5 × T_C− 4.0

4 × T_C− 7.5

221.0

—

192.5

—

146.0

—

125.8 ns

RD assertion to data valid

RD deassertion to data

t_GZ

0.0

—

ns

3

not valid

WR assertion to data

active

194

195

0.75 × T_C− 0.3

0.25 × T_C

37.2

—

24.7

—

WR deassertion to data

high impedance

—

12.5

8.3

Notes: 1. The number of wait states for out of page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand

not t_GZ

.

4. Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states. See

Figure 2-16.

2-34

DSP56362 Advance Information

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Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

80 MHz

4

3

No.

Symbol

Unit

Characteristics

Expression

Min Max

112.

157

t_RC

9 × T_C

—

ns

Random read or write cycle time

5

158

159

160

t_RAC

t_CAC

t_AA

4.75 × T_C− 6.5

2.25 × T_C− 6.5

3 × T_C− 6.5

52.9 ns

21.6 ns

31.0 ns

RAS assertion to data valid (read)

CAS assertion to data valid (read)

Column address valid to data valid (read)

—

CAS deassertion to data not valid (read

hold time)

161

t_OFF

0.0

—

ns

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

t_RP

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

3.25 × T_C− 4.0 36.6

5.75 × T_C− 4.0 67.9

3.25 × T_C− 4.0 36.6

4.75 × T_C− 4.0 55.4

2.25 × T_C− 4.0 24.1

—

ns

RAS deassertion to RAS assertion

RAS assertion pulse width

CAS assertion to RAS deassertion

RAS assertion to CAS deassertion

CAS assertion pulse width

2.5 × T_C

2

29.3 33.3 ns

19.9 23.9 ns

RAS assertion to CAS assertion

RAS assertion to column address valid

CAS deassertion to RAS assertion

CAS deassertion pulse width

1.75 × T_C

2

4.25 × T_C− 4.0 49.1

2.75 × T_C− 4.0 30.4

3.25 × T_C− 4.0 36.6

1.75 × T_C− 4.0 17.9

0.75 × T_C− 4.0 5.4

3.25 × T_C− 4.0 36.6

5.75 × T_C− 4.0 67.9

—

ns

t_ASR

t_RAH

t_ASC

t_CAH

t_AR

Row address valid to RAS assertion

RAS assertion to row address not valid

Column address valid to CAS assertion

CAS assertion to column address not valid

RAS assertion to column address not valid

Column address valid to RAS deassertion

WR deassertion to CAS assertion

CAS deassertion to WR⁵assertion

RAS deassertion to WR⁵assertion

CAS assertion to WR deassertion

RAS assertion to WR deassertion

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

4 × T_C− 4.0

2 × T_C− 3.8

46.0

21.2

1.25 × T_C− 3.7 11.9

0.25 × T_C− 3.0 0.1

3 × T_C− 4.2

33.3

5.5 × T_C− 4.2 64.6

101.

182

183

t_WP

8.5 × T_C− 4.5

—

ns

WR assertion pulse width

8

105.

t_RWL

8.75 × T_C− 4.3

WR assertion to RAS deassertion

1

184

185

t_CWL

t_DS

7.75 × T_C− 4.3 92.6

4.75 × T_C− 4.0 55.4

—

ns

WR assertion to CAS deassertion

Data valid to CAS assertion (write)

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Specifications

External Memory Expansion Port (Port A)

1, 2

Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States

(Continued)

80 MHz

4

3

No.

Symbol

Unit

Characteristics

Expression

Min Max

186

187

188

189

190

t_DH

3.25 × T_C− 4.0 36.6

5.75 × T_C− 4.0 67.9

5.5 × T_C− 4.3 64.5

1.5 × T_C− 4.0 14.8

1.75 × T_C− 4.0 17.9

—

ns

CAS assertion to data not valid (write)

RAS assertion to data not valid (write)

WR assertion to CAS assertion

t_DHR

t_WCS

t_CSR

t_RPC

CAS assertion to RAS assertion (refresh)

RAS deassertion to CAS assertion (refresh)

102.

191

t_ROH

8.5 × T_C− 4.0

—

ns

RD assertion to RAS deassertion

3

192

193

194

195

t_GA

t_GZ

7.5 × T_C− 6.5

—

87.3 ns

RD assertion to data valid

4

0.0

—

ns

RD deassertion to data not valid

0.75 × T_C− 0.3 9.1

0.25 × T_C

WR assertion to data active

—

3.1

WR deassertion to data high impedance

Notes: 1. The number of wait states for out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56362.

4. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFF

and not t_GZ

.

5. Either t_RCHor t_RRHmust be satisfied for read cycles.

Table 2-15 DRAM Out-of-Page and Refresh Timings,

1, 2

Eleven Wait States

100 MHz

4

3

No.

Symbol

Unit

Characteristics

Expression

Min

Max

—

157

158

159

t_RC

12 × T_C

120.0

—

ns

Random read or write cycle time

RAS assertion to data valid (read)

CAS assertion to data valid (read)

t_RAC

t_CAC

6.25 × T_C− 7.0

3.75 × T_C− 7.0

55.5

30.5

—

Column address valid to data valid

(read)

160

161

t_AA

4.5 × T_C− 7.0

—

38.0

—

ns

CAS deassertion to data not valid (read

hold time)

t_OFF

0.0

162

163

164

165

t_RP

4.25 × T_C− 4.0 38.5

7.75 × T_C− 4.0 73.5

5.25 × T_C− 4.0 48.5

6.25 × T_C− 4.0 58.5

—

ns

RAS deassertion to RAS assertion

RAS assertion pulse width

t_RAS

t_RSH

t_CSH

CAS assertion to RAS deassertion

RAS assertion to CAS deassertion

2-36

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Specifications

External Memory Expansion Port (Port A)

Table 2-15 DRAM Out-of-Page and Refresh Timings,

1, 2

Eleven Wait States

(Continued)

100 MHz

4

3

No.

Symbol

Unit

Characteristics

Expression

Min

3.75 × T_C− 4.0 33.5

2.5 × T_C4.0 21.0

Max

—

166

167

168

169

170

171

172

173

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

ns

CAS assertion pulse width

29.0

21.5

—

RAS assertion to CAS assertion

RAS assertion to column address valid

CAS deassertion to RAS assertion

CAS deassertion pulse width

1.75 × T_C4.0 13.5

5.75 × T_C− 4.0 53.5

4.25 × T_C− 4.0 38.5

1.75 × T_C− 4.0 13.5

—

t_ASR

t_RAH

t_ASC

—

Row address valid to RAS assertion

RAS assertion to row address not valid

Column address valid to CAS assertion

—

0.75 × T_C− 4.0

3.5

—

CAS assertion to column address not

valid

174

175

176

t_CAH

t_AR

5.25 × T_C− 4.0 48.5

7.75 × T_C− 4.0 73.5

—

ns

RAS assertion to column address not

valid

Column address valid to RAS

deassertion

t_RAL

6 × T_C− 4.0

56.0

26.0

—

177

178

t_RCS

t_RCH

3.0 × T_C− 4.0

ns

WR deassertion to CAS assertion

CAS deassertion to WR⁵assertion

1.75 × T_C− 4.0 13.5

—

0.25 × T_C− 3.0

0.25 × T_C− 2.0

—

0.5

RAS deassertion to WR⁵assertion

179

t_RRH

ns

180

181

182

183

184

185

186

187

188

t_WCH

t_WCR

t_WP

5 × T_C− 4.2

45.8

70.8

—

ns

CAS assertion to WR deassertion

RAS assertion to WR deassertion

WR assertion pulse width

7.5 × T_C− 4.2

11.5 × T_C− 4.5 110.5

11.75 × T_C− 4.3 113.2

10.25 × T_C− 4.3 103.2

5.75 × T_C− 4.0 53.5

5.25 × T_C− 4.0 48.5

7.75 × T_C− 4.0 73.5

t_RWL

t_CWL

t_DS

WR assertion to RAS deassertion

WR assertion to CAS deassertion

Data valid to CAS assertion (write)

CAS assertion to data not valid (write)

RAS assertion to data not valid (write)

WR assertion to CAS assertion

t_DH

t_DHR

t_WCS

t_CSR

6.5 × T_C− 4.3

60.7

CAS assertion to RAS assertion

(refresh)

189

190

1.5 × T_C− 4.0

11.0

—

ns

RAS deassertion to CAS assertion

(refresh)

t_RPC

t_ROH

t_GA

2.75 × T_C− 4.0 23.5

191

192

11.5 × T_C− 4.0 111.0

10 × T_C− 7.0

—

ns

RD assertion to RAS deassertion

RD assertion to data valid

93.0

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External Memory Expansion Port (Port A)

Table 2-15 DRAM Out-of-Page and Refresh Timings,

1, 2

Eleven Wait States

(Continued)

100 MHz

4

3

No.

Symbol

Unit

Characteristics

Expression

Min

Max

—

4

193

194

t_GZ

0.0

7.2

ns

RD deassertion to data not valid

WR assertion to data active

0.75 × T_C− 0.3

0.25 × T_C

—

WR deassertion to data high

impedance

195

—

2.5

ns

Notes: 1. The number of wait states for out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56362.

4. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is

t

_OFFand not t_GZ.

5. Either t_RCHor t_RRHmust be satisfied for read cycles.

Table 2-16 DRAM Out-of-Page and Refresh Timings,

1, 2

Fifteen Wait States 100 and 120MHz

100 MHz

120 MHz

3

No.

Symbol

Expression

Unit

Characteristics

Min

160.0

—

Max

—

Min

Max

—

157

158

159

t_RC

16 × T_C

133.3

—

ns

Random read or write cycle time

RAS assertion to data valid (read)

CAS assertion to data valid (read)

t_RAC

t_CAC

8.25 × T_C− 5.7

4.75 × T_C− 5.7

76.8

41.8

63.0

33.9

—

Column address valid to data valid

(read)

160

161

t_AA

5.5 × T_C− 5.7

—

49.3

—

40.1

—

ns

CAS deassertion to data not valid

(read hold time)

t_OFF

0.0

162

163

164

165

166

167

t_RP

6.25 × T_C− 4.0 58.5

9.75 × T_C− 4.0 93.5

6.25 × T_C− 4.0 58.5

8.25 × T_C− 4.0 78.5

4.75 × T_C− 4.0 43.5

—

48.1

77.2

48.1

64.7

35.6

27.2

—

ns

RAS deassertion to RAS assertion

RAS assertion pulse width

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

—

CAS assertion to RAS deassertion

RAS assertion to CAS deassertion

CAS assertion pulse width

—

3.5 × T_C

2

33.0

37.0

31.2

RAS assertion to CAS assertion

RAS assertion to column address

valid

168

t_RAD

2.75 × T_C

2

25.5

29.5

20.9

24.9

ns

169

170

t_CRP

t_CP

7.75 × T_C− 4.0 73.5

6.25 × T_C− 4.0 58.5

—

60.6

48.1

—

ns

CAS deassertion to RAS assertion

CAS deassertion pulse width

Row address valid to RAS

assertion

171

t_ASR

6.25 × T_C− 4.0 58.5

—

48.1

—

ns

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Specifications

External Memory Expansion Port (Port A)

Table 2-16 DRAM Out-of-Page and Refresh Timings,

1, 2

Fifteen Wait States 100 and 120MHz

(Continued)

100 MHz

120 MHz

3

No.

Symbol

Expression

Unit

Characteristics

Min

2.75 × T_C− 4.0 23.5

Max

Min

Max

RAS assertion to row address not

valid

172

173

174

175

176

t_RAH

t_ASC

t_CAH

t_AR

—

18.9

2.2

—

ns

Column address valid to CAS

assertion

0.75 × T_C− 4.0

3.5

—

CAS assertion to column address

not valid

6.25 × T_C− 4.0 58.5

9.75 × T_C− 4.0 93.5

48.1

77.2

54.3

RAS assertion to column address

not valid

Column address valid to RAS

deassertion

t_RAL

7 × T_C− 4.0

5 × T_C− 3.8

66.0

46.2

177

178

179

180

181

182

183

184

185

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

—

37.9

10.9

0.1

—

ns

WR deassertion to CAS assertion

CAS deassertion to WR⁵assertion

RAS deassertion to WR⁵assertion

CAS assertion to WR deassertion

RAS assertion to WR deassertion

WR assertion pulse width

1.75 × T_C− 3.7 13.8

0.25 × T_C− 2.0

6 × T_C− 4.2

0.5

55.8

90.8

45.8

75.0

124.7

126.9

114.4

68.9

9.5 × T_C− 4.2

15.5 × T_C− 4.5 150.5

15.75 × T_C− 4.3 153.2

14.25 × T_C− 4.3 138.2

8.75 × T_C− 4.0 83.5

t_RWL

t_CWL

t_DS

WR assertion to RAS deassertion

WR assertion to CAS deassertion

Data valid to CAS assertion (write)

CAS assertion to data not valid

(write)

186

t_DH

6.25 × T_C− 4.0 58.5

9.75 × T_C− 4.0 93.5

—

48.1

—

ns

RAS assertion to data not valid

(write)

187

188

189

t_DHR

t_WCS

t_CSR

—

77.2

74.9

8.5

—

ns

9.5 × T_C− 4.3

1.5 × T_C− 4.0

90.7

11.0

WR assertion to CAS assertion

CAS assertion to RAS assertion

(refresh)

RAS deassertion to CAS assertion

(refresh)

190

t_RPC

4.75 × T_C− 4.0 43.5

15.5 × T_C− 4.0 151.0

—

35.6

—

ns

191

192

193

194

t_ROH

t_GA

—

134.3

—

125.2

—

RD assertion to RAS deassertion

RD assertion to data valid

14 × T_C− 5.7

—

111.0 ns

3

t_GZ

0.0

7.2

0.0

—

ns

RD deassertion to data not valid

0.75 × T_C− 0.3

0.25 × T_C

—

5.9

WR assertion to data active

WR deassertion to data high

impedance

195

—

2.5

—

2.1

ns

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Specifications

External Memory Expansion Port (Port A)

Table 2-16 DRAM Out-of-Page and Refresh Timings,

1, 2

Fifteen Wait States 100 and 120MHz

(Continued)

100 MHz

120 MHz

Min Max

3

No.

Symbol

Expression

Unit

Characteristics

Min

Max

Notes: 1. The number of wait states for out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

4. Either t_RCHor t_RRHmust be satisfied for read cycles.

157

162

169

163

165

162

RAS

167

168

164

170

166

CAS

171

173

174

175

Row Address

Column Address

A0–A17

172

176

177

179

191

WR

RD

168

160

159

193

158

192

161

Data

In

D0–D23

AA0476

Figure 2-17 DRAM Out-of-Page Read Access

2-40

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Specifications

External Memory Expansion Port (Port A)

157

162

163

165

162

RAS

167

168

164

166

169

170

CAS

171

173

172

174

176

Row Address

Column Address

A0–A17

181

175

180

188

182

WR

RD

184

183

187

186

185

195

194

Data Out

AA0477

D0–D23

Figure 2-18 DRAM Out-of-Page Write Access

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Specifications

External Memory Expansion Port (Port A)

157

162

163

165

162

RAS

CAS

190

170

189

177

WR

AA0478

Figure 2-19 DRAM Refresh Access

2-42

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Specifications

External Memory Expansion Port (Port A)

Synchronous Timings (SRAM)

4

Table 2-17 External Bus Synchronous Timings (SRAM Access)

100 MHz

1, 2

No.

Characteristics

Unit

Expression

Min Max

CLKOUT high to address, and

198

199

200

201

0.25 × T_C+ 4.0

0.25 × T_C

—

6.5

—

ns

5

AA valid

CLKOUT high to address, and

2.5

4.0

5

AA invalid

TA valid to CLKOUT high

(setup time)

—

CLKOUT high to TA invalid

(hold time)

0.0

2.5

—

202

203

0.25 × T_C

ns

CLKOUT high to data out active

CLKOUT high to data out valid

0.25 × T_C+ 4.0 3.3 6.5

CLKOUT high to data out

invalid

204

205

206

0.25 × T_C

2.5

—

2.5

—

ns

CLKOUT high to data out high

impedance

Data in valid to CLKOUT high

(setup)

4.0

0.0

CLKOUT high to data in invalid

(hold)

207

208

209

—

0.75 × T_C+ 4.0 8.2 11.5 ns

CLKOUT high to RD assertion

CLKOUT high to RD

deassertion

0.0 4.0

ns

0.5 × T_C+ 4.3

[WS = 1 or

WS ≥ 4]

6.3 9.3

3

210

211

CLKOUT high to WR assertion

All frequencies:

1.3 4.3

0.0 3.8

[2 ≤ WS ≤ 3]

CLKOUT high to WR

deassertion

Notes: 1. WS is the number of wait states specified in the BCR.

2. The asynchronous delays specified in the expressions are valid for

DSP56362.

3. If WS > 1, WR assertion refers to the next rising edge of CLKOUT.

4. External bus synchronous timings should be used only for reference

to the clock and not for relative timings.

5. T198 and T199 are valid for Address Trace mode if the ATE bit in

the OMR is set. Use the status of BR (See T212) to determine

whether the access referenced by A0–A23 is internal or external,

when this mode is enabled

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Specifications

External Memory Expansion Port (Port A)

CLKOUT

199

198

A0–A17

AA0–AA3

201

200

TA

211

WR

210

205

203

204

D0–D23

Data Out

202

208

209

RD

207

206

D0–D23

Data In

AA0479

Figure 2-20 Synchronous Bus Timings SRAM 1 WS (BCR Controlled)

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Specifications

External Memory Expansion Port (Port A)

CLKOUT

198

199

A0–A17

AA0–AA3

201

211

200

TA

WR

210

205

203

202

204

Data Out

D0–D23

208

209

RD

207

206

Data In

D0–D23

AA0480

Figure 2-21 Synchronous Bus Timings SRAM 2 WS (TA Controlled)

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Specifications

External Memory Expansion Port (Port A)

Arbitration Timings

1

Table 2-18 Arbitration Bus Timings

100 MHz

No.

Characteristics

Expression

Unit

Min Max

CLKOUT high to BR assertion/

212

213

214

215

216

217

218

219

220

221

1.0 4.0

ns

2

deassertion

BG asserted/deasserted to

CLKOUT high (setup)

4.0

0.0

4.0

0.0

—

CLKOUT high to BG deasserted/

asserted (hold)

BB deassertion to CLKOUT high

(input setup)

CLKOUT high to BB assertion

(input hold)

CLKOUT high to BB assertion

(output)

1.0 4.0

CLKOUT high to BB deassertion

(output)

BB high to BB high impedance

(output)

—

4.5

—

CLKOUT high to address and

controls active

0.25 × T_C

2.5

CLKOUT high to address and

controls high impedance

0.25 × T_C

—

2.5

—

222

223

2.5

ns

CLKOUT high to AA active

0.25 × T_C+ 4.0 3.2 6.5

CLKOUT high to AA deassertion

CLKOUT high to AA high

impedance

224

0.75 × T_C7.5

—

ns

Notes: 1. The asynchronous delays specified in the expressions are valid for

DSP56362.

2. T212 is valid for Address Trace mode when the ATE bit in the OMR is

set. BR is deasserted for internal accesses and asserted for external

accesses.

2-46

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Specifications

External Memory Expansion Port (Port A)

CLKOUT

BR

212

214

213

215

BG

BB

216

217

220

A0–A17

RD, WR

222

AA0–AA3

AA0481

Figure 2-22 Bus Acquisition Timings

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Specifications

External Memory Expansion Port (Port A)

CLKOUT

212

BR

214

213

BG

BB

219

218

221

A0–A17

RD, WR

224

223

AA0–AA3

AA0482

Figure 2-23 Bus Release Timings Case 1 (BRT Bit in OMR Cleared)

2-48

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Specifications

External Memory Expansion Port (Port A)

CLKOUT

BR

212

214

213

BG

BB

219

218

221

A0–A17

RD, WR

224

223

AA0–AA3

AA0483

Figure 2-24 Bus Release Timings Case 2 (BRT Bit in OMR Set)

Table 2-19 Asynchronous Bus Arbitration timing

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

BB assertion window from BG

input negation.

2 .5* Tc + 5

2 * Tc + 5

—

20

ns

250

251

Delay from BB assertion to BG

assertion

20

—

Comments:

1.

Bit 13 in the OMR register must be set to enter Asynchro-

nous Arbitration mode

2.

3.

4.

At 100 MHz it is recommended to use Asynchronous Arbi-

tration mode.

If Asynchronous Arbitration mode is active, none of the tim-

ings in Table 2-19 is required.

In order to guarantee timings 250, and 251, it is recommend-

ed to assert BG inputs to different 56300 devices (on the

same bus) in a non overlap manner as shown in Figure

2-25.

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Specifications

External Memory Expansion Port (Port A)

BG1

BB

250

BG2

251

Figure 2-25 Asynchronous Bus Arbitration Timing

BG1

BG2

250+251

Figure 2-26 Asynchronous Bus Arbitration Timing

Background explanation for Asynchronous Bus Arbitration:

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG, and BB inputs.

These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a

result of this delay, a 56300 part may assume mastership and assert BB, for some time after BG is

negated. This is the reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is

exposed to other 56300 components which are potential masters on the same bus. If BG input is asserted

before that time, a situation of BG asserted, and BB negated, may cause another 56300 component to

assume mastership at the same time. Therefore some non-overlap period between one BG input active to

another BG input active, is required. Timing 251 ensures that such a situation is avoided.

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Specifications

Parallel Host Interface (HDI08) Timing

PARALLEL HOST INTERFACE (HDI08) TIMING

1, 2

Table 2-20 Host Interface (HDI08) Timing

100 MHz

3

No.

Expression

Unit

Characteristics

Min Max

4

Read data strobe assertion width

HACK read assertion width

317

318

T_C+ 9.9

—

19.9

9.9

—

ns

4

Read data strobe deassertion width

HACK read deassertion width

4

Read data strobe deassertion width after “Last

5,6

Data Register” reads , or between two

7

319

320

2.5 × T_C+ 6.6 31.6

—

ns

consecutive CVR, ICR, or ISR reads

HACK deassertion width after “Last Data

5,6

Register” reads

8

Write data strobe assertion width

—

13.2

31.6

—

ns

HACK write assertion width

Write data strobe deassertion width⁸

HACK write deassertion width

• after ICR, CVR and “Last Data Register”

5

writes

321

2.5 × T_C+ 6.6

• after IVR writes, or

• after TXH:TXM writes (with HBE=0), or

after TXL:TXM writes (with HBE=1)

•

16.5

—

322

323

—

9.9

0.0

—

ns

HAS assertion width

9

HAS deassertion to data strobe assertion

Host data input setup time before write data

8

strobe deassertion

324

325

—

9.9

3.3

—

ns

Host data input setup time before HACK write

deassertion

Host data input hold time after write data strobe

8

deassertion

Host data input hold time after HACK write

deassertion

Read data strobe assertion to output data active

4

from high impedance

326

327

—

3.3

—

HACK read assertion to output data active from

high impedance

4

Read data strobe assertion to output data valid

24.2 ns

HACK read assertion to output data valid

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Specifications

Parallel Host Interface (HDI08) Timing

Table 2-20 Host Interface (HDI08) Timing

1, 2

(Continued)

100 MHz

3

No.

Expression

Unit

Characteristics

Min Max

Read data strobe deassertion to output data

4

high impedance

328

—

9.9 ns

HACK read deassertion to output data high

impedance

Output data hold time after read data strobe

4

deassertion

329

—

3.3

—

ns

Output data hold time after HACK read

deassertion

4

8

330

331

332

333

T_C+9.9

19.9

9.9

—

ns

HCS assertion to read data strobe deassertion

—

HCS assertion to write data strobe deassertion

19.1 ns

HCS assertion to output data valid

9

0.0

—

ns

HCS hold time after data strobe deassertion

Address (AD7–AD0) setup time before HAS

deassertion (HMUX=1)

334

335

—

4.7

3.3

—

ns

Address (AD7–AD0) hold time after HAS

deassertion (HMUX=1)

—

ns

A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W

9

—

0

setup time before data strobe assertion

336

• Read

• Write

4.7

3.3

—

A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W

337

338

ns

9

hold time after data strobe deassertion

Delay from read data strobe deassertion to host

4,

10

20

—

request assertion for “Last Data Register” read T_C

5, 10

Delay from write data strobe deassertion to host

339

340

ns

request assertion for “Last Data Register”

2 × T_C

5, 8, 10

write

Delay from data strobe assertion to host request

deassertion for “Last Data Register” read or

—

19.1 ns

5, 9, 10

write (HROD = 0)

Delay from data strobe assertion to host request

deassertion for “Last Data Register” read or

300.

ns

341

—

5, 9,

0

write (HROD = 1, open drain Host Request)

10, 11

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Specifications

Parallel Host Interface (HDI08) Timing

1, 2

Table 2-20 Host Interface (HDI08) Timing

(Continued)

100 MHz

Min Max

3

No.

Expression

Unit

Characteristics

Delay from DMA HACK deassertion to HOREQ

assertion

5

• For “Last Data Register” read

342

ns

2 × T_C+ 19.1 39.1

1.5 × T_C+ 19.1 34.1

—

5

• For “Last Data Register” write

• For other cases

0.0

Delay from DMA HACK assertion to HOREQ

deassertion

343

344

—

20.2 ns

5

• HROD = 0

Delay from DMA HACK assertion to HOREQ

deassertion for “Last Data Register” read or

write

300.

ns

0

5, 11

• HROD = 1, open drain Host Request

Notes: 1. See Host Port Usage Considerations in the DSP56362 User Design Manual.

2. In the timing diagrams below, the controls pins are drawn as active low. The pin

polarity is programmable.

3. V_CC= 3.3 V 0.16 V; T_J= 0°C to +100°C, C_L= 50 pF

4. The read data strobe is HRD in the dual data strobe mode and HDS in the single

data strobe mode.

5. The “last data register” is the register at address $7, which is the last location to be

read or written in data transfers. This is RXL/TXL in the little endian mode (HBE = 0),

or RXH/TXH in the big endian mode (HBE = 1).

6. This timing is applicable only if a read from the “last data register” is followed by a

read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits,

or waiting for the assertion of the HOREQ signal.

7. This timing is applicable only if two consecutive reads from one of these registers

are executed.

8. The write data strobe is HWR in the dual data strobe mode and HDS in the single

data strobe mode.

9. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe

mode and host data strobe (HDS) in the single data strobe mode.

10. The host request is HOREQ in the single host request mode and HRRQ and HTRQ

in the double host request mode.

11. In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the

open-drain mode.

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Specifications

Parallel Host Interface (HDI08) Timing

317

318

HACK

328

327

329

326

HD7–HD0

HOREQ

AA1105

Figure 2-27 Host Interrupt Vector Register (IVR) Read Timing Diagram

HA0–HA2

336

337

333

330

HCS

317

HRD, HDS

318

319

328

332

327

329

326

341

HD0–HD7

338

340

HOREQ,

HRRQ,

HTRQ

AA0484

Figure 2-28 Read Timing Diagram, Non-Multiplexed Bus

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Specifications

Parallel Host Interface (HDI08) Timing

HA0–HA2

337

333

336

331

HCS

320

HWR, HDS

321

325

324

HD0–HD7

340

339

341

HOREQ, HRRQ, HTRQ

AA0485

Figure 2-29 Write Timing Diagram, Non-Multiplexed Bus

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Specifications

Parallel Host Interface (HDI08) Timing

HA8–HA10

336

337

322

HAS

323

317

HRD, HDS

334

318

319

335

327

328

329

HAD0–HAD7

Address

Data

326

338

340

341

HOREQ, HRRQ, HTRQ

AA0486

Figure 2-30 Read Timing Diagram, Multiplexed Bus

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Specifications

Parallel Host Interface (HDI08) Timing

HA8–HA10

336

322

HAS

323

320

HWR, HDS

334

324

321

325

335

HAD0–HAD7

Data

340

Address

339

341

HOREQ, HRRQ, HTRQ

AA0487

Figure 2-31 Write Timing Diagram, Multiplexed Bus

HOREQ

(Output)

342

343

344

320

321

HACK

(Input)

TXH/M/L

Write

324

325

H0–H7

(Input)

Data

Valid

Figure 2-32 Host DMA Write Timing Diagram

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Specifications

Serial Host Interface SPI Protocol Timing

HOREQ

(Output)

343

342

318

317

HACK

(Input)

RXH

Read

327

328

329

326

H0-H7

(Output)

Data

Valid

Figure 2-33 Host DMA Read Timing Diagram

SERIAL HOST INTERFACE SPI PROTOCOL TIMING

Table 2-21 Serial Host Interface SPI Protocol Timing

100MHz

Min Max

Filter

Mode

No.

Characteristics

Mode

Expression

Unit

Bypassed

Narrow

Wide

Bypassed

—

106

212

283

0

50

100

—

Tolerable spike width

on clock or data in

140

—

ns

6×T_C+46

6×T_C+152

6×T_C+223

Minimum serial clock

141

Master Narrow

Wide

ns

cycle = t_SPICC(min)

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Specifications

Serial Host Interface SPI Protocol Timing

Table 2-21 Serial Host Interface SPI Protocol Timing (Continued)

100MHz

Filter

Mode

No.

Characteristics

Mode

Expression

Unit

Min Max

Bypassed 0.5×t_SPICC–10

43

96

—

10

2000

—

Master Narrow

Wide

0.5×t_SPICC–10

0.5×t_SPICC–10 131

142

ns

Serial clock high period

Bypassed

Narrow

2.5×T_C+12

2.5×T_C+102

2.5×T_C+189

37

127

214

43

Slave

Wide

Bypassed 0.5×t_SPICC–10

Master Narrow 0.5×t_SPICC–10

96

Wide

Bypassed

Narrow

Wide

0.5×t_SPICC–10 131

2.5×T_C+12

2.5×T_C+102

2.5×T_C+189

143

144

146

ns

Serial clock low period

37

127

214

—

50

0

10

0

Slave

Master

Slave

—

Serial clock rise/fall

time

—

Bypassed

Narrow

Wide

3.5×T_C+15

SS assertion to first

SCK edge CPHA = 0

Slave

slave

0

Bypassed

Narrow

Wide

10

0

CPHA = 1

0

Bypassed

Narrow

Wide

12

102

189

0

12

102

189

0

Last SCK edge to SS

not asserted

147

148

149

ns

Bypassed

Master

/Slave

Data input valid to SCK

edge (data input set-up

time)

Narrow MAX{(20-T_C), 0} 10

Wide

Bypassed

Narrow

Wide

MAX{(40-T_C), 0} 30

2.5×T_C+10

2.5×T_C+30

2.5×T_C+50

35

55

75

SCK last sampling

edge to data input not

valid

Master

/Slave

SS assertion to data

out active

150

151

Slave

—

2

9

2

—

9

ns

SS deassertion to data

high impedance

—

Bypassed

Narrow

Wide

2×T_C+33

2×T_C+123

2×T_C+210

—

53

143

230

SCK edge to data out

valid (data out delay

time)

Master

/Slave

152

ns

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Specifications

Serial Host Interface SPI Protocol Timing

Table 2-21 Serial Host Interface SPI Protocol Timing (Continued)

100MHz

Filter

Mode

No.

Characteristics

Mode

Expression

Unit

Min Max

Bypassed

Narrow

Wide

T_C+5

T_C+55

T_C+106

15

65

116

—

SCK edge to data out

not valid

Master

/Slave

153

154

157

ns

(data out hold time)

SS assertion to data

out valid (CPHA = 0)

Slave

—

T_C+33

—

43

Bypassed

Narrow

Wide

Bypassed

Narrow

2.5×T_C+30

2.5×T_C+120

2.5×T_C+217

2.5×T_C+30

2.5×T_C+80

—

55

105

55

145

242

—

First SCK sampling

edge to HREQ output

deassertion

Last SCK sampling

edge to HREQ output

not deasserted

—

158

Slave

ns

Wide

2.5×T_C+136

161

—

(CPHA = 1)

SS deassertion to

HREQ output not

159

160

Slave

—

2.5×T_C+30

55

—

ns

deasserted (CPHA = 0)

SS deassertion pulse

width (CPHA = 0)

—

T_C+6

16

—

0.5 × t_SPICC

2.5×T_C+43

+

Bypassed

121

174

209

—

0.5 ×t_SPICC

+

HREQ in assertion to

first SCK edge

161

162

Master Narrow

Wide

ns

2.5×T_C+43

0.5 ×t_SPICC

+

2.5×T_C+43

HREQ in deassertion

to last SCK sampling

edge (HREQ in set-up

time) (CPHA = 1)

Master

—

0

—

ns

First SCK edge to

163

Master

—

HREQ in not asserted

(HREQ in hold time)

Note:

Periodically sampled, not 100% tested

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Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

141

144

142

143

144

SCK (CPOL=0

(Output)

141

144

142

SCK (CPOL =

1 (Output)

148

149

148

149

163

MISO

MSB

Valid

LSB

Valid

(Input)

153

152

MSB

MOSI

LSB

(Output)

161

HREQ

(Input)

AA0271

Figure 2-34 SPI Master Timing (CPHA = 0)

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Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

142

141

144

SCK (CPOL = 0

(Output)

142

143

144

SCK (CPOL = 1

(Output)

148

149

MISO

MSB

Valid

LSB

Valid

(Input)

152

153

MOSI

MSB

LSB

(Output)

161

162

163

HREQ

(Input)

AA0272

Figure 2-35 SPI Slave Timing (CPHA = 0)

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Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

142

141

144

142

143

144

SCK (CPOL = 0

(Output)

141

144

SCK (CPOL = 1

(Output)

148

149

MISO

MSB

Valid

LSB

Valid

(Input)

152

153

MOSI

MSB

LSB

(Output)

161

162

163

HREQ

(Input)

AA0272

Figure 2-36 SPI Master Timing (CPHA = 1)

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Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

142

141

147

144

160

SCK (CPOL =

0) (Input)

146

154

142

144

143

SCK (CPOL = 1)

(Input)

152

153

151

LSB

150

MISO

MSB

(Output)

148

149

MSB

Valid

MOSI

LSB

Valid

(Input)

157

159

HREQ

(Output)

AA0273

Figure 2-37 SPI Slave Timing (CPHA = 0)

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Specifications

Serial Host Interface SPI Protocol Timing

SS

(Input)

143

141

147

142

144

SCK (CPOL =

0) (Input)

146

142

144

143

SCK (CPOL = 1)

(Input)

152

153

151

150

MISO

MSB

LSB

(Output)

148

149

MSB

Valid

LSB

Valid

MOSI

(Input)

157

158

HREQ

(Output)

AA0274

Figure 2-38 SPI Slave Timing (CPHA = 1)

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Specifications

2

Serial Host Interface (SHI) I C Protocol Timing

SERIAL HOST INTERFACE (SHI) I²C PROTOCOL TIMING

2

Table 2-22 SHI I C Protocol Timing

Standard I²C*

Standard

Min Max

Fast-Mode

Unit

Symbol/

No.

Characteristics

Expression

Min

Max

Tolerable spike width on SCL or SDA

Filters bypassed

—

0

50

100

—

0

50

ns

—

Narrow filters enabled

Wide filters enabled

—

100

400 kHz

171

172

173

174

175

176

177

178

179

180

181

182

F_SCL

T_BUF

SCL clock frequency

Bus free time

4.7

4.0

4.7

4.0

—

1.3

0.6

1.3

—

µs

ns

µs

pF

T_SU;STA

T_HD;STA

T_LOW

Start condition set-up time

Start condition hold time

SCL low period

T_HIGH

SCL high period

T

R

1000 20 + 0.1 × C_b300

300 20 + 0.1 × C_b300

SCL and SDA rise time

SCL and SDA fall time

Data set-up time

T

F

—

T_SU;DAT

T_HD;DAT

T_SU;STO

C_b

250

0.0

4.0

—

100

0.0

0.6

—

0.9

—

Data hold time

—

Stop condition set-up time

Capacitive load for each line

400

F_DSP

DSP clock frequency

Filters bypassed

10.6

11.8

13.1

—

28.5

39.7

61.0

—

MHz

183

184

Narrow filters enabled

Wide filters enabled

HREQ in deassertion to last SCL edge

(HREQ in set-up time)

t_SU;RQI

0.0

—

0.0

—

ns

First SCL sampling edge to HREQ

T_NG;RQO

2

output deassertion

186

Filters bypassed 2 × T_C+ 30

Narrow filters enabled 2 × T_C+ 120

Wide filters enabled 2 × T_C+ 208

—

50

140

228

—

50

140

228

ns

Last SCL edge to HREQ output not

T_AS;RQO

2

deasserted

187

Filters bypassed 2 × T_C+ 30

Narrow filters enabled 2 × T_C+ 80 100

Wide filters enabled 2 × T_C+ 135 155

50

—

50

100

155

—

ns

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Specifications

Serial Host Interface (SHI) I C Protocol Timing

2

Table 2-22 SHI I C Protocol Timing (Continued)

Standard I²C*

Standard

Min Max

Fast-Mode

Unit

Symbol/

No.

Characteristics

Expression

Min

Max

HREQ in assertion to first SCL edge

T_AS;RQI

Filters bypassed 0.5 × T_I2_CCP4327

Narrow filters enabled

Wide filters enabled

—

927

882

838

—

ns

188

-

4282

4238

0.5 × T_C- 21

Note:

R_P(min) = 1.5 k¾

Programming the Serial Clock

The programmed serial clock cycle, T_I²_CCP, is specified by the value of the HDM[5:0] and HRS bits of the

HCKR (SHI clock control register).

The expression for T_I²_CCPis

T

= [T × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]

C

I²CCP

where

–

HRS is the prescaler rate select bit. When HRS is cleared, the fixed

divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.

–

HDM[7:0] are the divider modulus select bits.

A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.

In I²C mode, the user may select a value for the programmed serial clock cycle from

6 × T

(if HDM[5:0] = $02 and HRS = 1)

(if HDM[7:0] = $FF and HRS = 0)

C

to

4096 × T

C

The programmed serial clock cycle (T_I²_CCP), SCL rise time (T_R), and the filters selected should be chosen

in order to achieve the desired SCL frequency, as shown in Table 2-23

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Specifications

2

Serial Host Interface (SHI) I C Protocol Timing

.

Table 2-23 SCL Serial Clock Cycle generated as Master

2

Filters bypassed

T

+ 2.5 × T_C+ 45ns + T

+ 2.5 × T_C+ 135ns + T

+ 2.5 × T_C+ 223ns + T

I CCP

R

2

Narrow filters enabled T

Wide filters enabled

I CCP

R

2

T

I CCP

EXAMPLE:

For DSP clock frequency of 100 MHz (i.e. T_C= 10ns), operating in a standard-mode I²C environment

(F_SCL= 100 KHz (i.e. T_SCL= 10µs), T_R= 1000ns), with filters bypassed

2

T

= 10µs - 2.5×10ns - 45ns - 1000ns = 8930ns

I CCP

Choosing HRS = 0 gives

HDM[7:0] = 8930ns / (2× 10ns× 8) - 1 = 55.8

Thus the HDM[7:0] value should be programmed to $38 (=56).

171

173

176

175

SCL

SDA

177

180

178

172

179

MSB

LSB

ACK

Stop

Start

174

188

186

182

183

187

189

184

HREQ

AA0275

2

Figure 2-39 I C Timing

2-68

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Specifications

Enhanced Serial Audio Interface Timing

ENHANCED SERIAL AUDIO INTERFACE TIMING

Table 2-24 Enhanced Serial Audio Interface Timing

100 MHz

Min Max

1, 2, 3

4

No.

Symbol Expression

4 x T

Unit

Characteristics

Cond-ition

40.0

30

—

i ck

x ck

C

RXC:3 xT

TXC:MAX

C

5

430

t_SSICC

ns

Clock cycle

40

x ck

[3xT_C;t₄₅₄

]

Clock high period

2 × T − 10.0 10.0

—

C

431 • For internal clock

• For external clock

—

ns

1.5 × T

15.0

2 × T − 10.0 10.0

C

Clock low period

C

432 • For internal clock

• For external clock

1.5 × T

15.0

—

C

37.0

22.0

37.0

22.0

39.0

24.0

39.0

24.0

36.0

21.0

37.0

22.0

—

x ck

i ck a

x ck

i ck a

x ck

i ck a

x ck

i ck a

x ck

i ck a

x ck

i ck a

x ck

RXC rising edge to FSR out (bl)

433

—

ns

high

434

435

436

437

438

—

RXC rising edge to FSR out (bl) low

RXC rising edge to FSR out (wr)

—

6

high

RXC rising edge to FSR out (wr)

6

low

—

RXC rising edge to FSR out (wl)

high

RXC rising edge to FSR out (wl)

low

0.0

Data in setup time before RXC

(TXC in synchronous mode) falling

edge

439

—

ns

19.0

—

i ck

5.0

3.0

23.0

1.0

23.0

3.0

0.0

19.0

—

x ck

i ck

x ck

i ck a

x ck

i ck a

x ck

i ck a

x ck

i ck s

Data in hold time after RXC falling

edge

440

441

442

443

444

—

ns

FSR input (bl, wr) high before

6

RXC falling edge

FSR input (wl) high before RXC

falling edge

FSR input hold time after RXC

falling edge

—

Flags input setup before RXC

falling edge

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Specifications

Enhanced Serial Audio Interface Timing

Table 2-24 Enhanced Serial Audio Interface Timing (Continued)

100 MHz

Min Max

1, 2, 3

4

No.

Symbol Expression

Unit

Characteristics

Cond-ition

6.0

0.0

—

2.0

21.0

—

x ck

i ck s

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

x ck

i ck

Flags input hold time after RXC

falling edge

445

446

447

448

449

450

451

452

453

454

455

456

457

458

459

460

461

—

ns

29.0

15.0

31.0

17.0

31.0

17.0

33.0

19.0

30.0

16.0

31.0

17.0

31.0

17.0

34.0

20.0

28.0

21.0

31.0

16.0

34.0

20.0

—

TXC rising edge to FST out (bl)

high

TXC rising edge to FST out (bl) low

TXC rising edge to FST out (wr)

6

high

TXC rising edge to FST out (wr)

6

low

TXC rising edge to FST out (wl)

high

TXC rising edge to FST out (wl) low

TXC rising edge to data out enable

from high impedance

TXC rising edge to transmitter drive

enable assertion

23 + 0.5 × T

C

TXC rising edge to data out valid

TXC rising edge to data out high

21.0

—

7

impedance

TXC rising edge to transmitter drive

7

enable deassertion

FST input (bl, wr) setup time before

—

6

TXC falling edge

—

FST input (wl) to data out enable

from high impedance

—

27.0

31.0

—

FST input (wl) to transmitter drive

enable assertion

—

2.0

21.0

4.0 ——

0.0

—

40.0

—

x ck

i ck

x ck

i ck

x ck

i ck

FST input (wl) setup time before

TXC falling edge

FST input hold time after TXC

falling edge

—

32.0

18.0

Flag output valid after TXC rising

edge

462

463

—

ns

—

HCKR/HCKT clock cycle

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Specifications

Enhanced Serial Audio Interface Timing

Table 2-24 Enhanced Serial Audio Interface Timing (Continued)

100 MHz

Min Max

1, 2, 3

4

No.

Symbol Expression

Unit

Characteristics

Cond-ition

HCKT input rising edge to TXC

output

464

465

—

27.5

ns

HCKR input rising edge to RXC

output

Notes: 1. V_CC= 3.3 V 0.16 V; T_J= 0°C to +100°C, C_L= 50 pF

2. i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that TXC and RXC are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that TXC and RXC are the same clock)

3. bl = bit length

wl = word length

wr = word length relative

4. TXC(SCKT pin) = transmit clock

RXC(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

5. For the internal clock, the clock cycle at the pin is defined by Icyc and the ESAI control registers.

6. The word-relative frame sync signal waveform relative to the clock operates in the same manner

as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit

clock (same as bit length frame sync signal), until the one before last bit clock of the first word in

frame.

7. Periodically sampled and not 100% tested

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Enhanced Serial Audio Interface Timing

430

431

432

TXC

(Input/Output)

446

447

FST (Bit)

Out

450

451

FST (Word)

Out

454

452

454

455

Data Out

First Bit

Last Bit

459

Transmitter

Drive Enable

457

453

456

FST (Bit) In

461

460

FST (Word) In

Flags Out

458

461

462

See Note

Note: In network mode, output flag transitions can occur at the start of each time slot

within the frame. In normal mode, the output flag state is asserted for the entire

frame period.

AA0490

Figure 2-40 ESAI Transmitter Timing

2-72

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Enhanced Serial Audio Interface Timing

430

431

432

RXC

(Input/Output)

433

434

FSR (Bit)

Out

437

438

FSR (Word)

Out

440

439

443

Data In

Last Bit

First Bit

FSR (Bit)

In

441

FSR (Word)

In

442

443

445

Flags In

444

AA0491

Figure 2-41 ESAI Receiver Timing

HCKT

463

SCKT(output)

464

Figure 2-42 ESAI HCKT Timing

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Specifications

Digital Audio Transmitter Timing

HCKR

463

SCKR (output)

465

Figure 2-43 ESAI HCKR Timing

DIGITAL AUDIO TRANSMITTER TIMING

Table 2-25 Digital Audio Transmitter Timing

100 MHz

No.

Characteristic

Expression

Unit

Min

—

20

5

Max

50

—

MHz

ns

ACI frequency (see note)

ACI period

220

221

222

2 × T_C

0.5 × T_C

1.5 × T_C

—

ns

ACI high duration

5

—

ns

ACI low duration

223

—

15

ns

ACI rising edge to ADO valid

Note:

In order to assure proper operation of the DAX, the ACI frequency should be

less than 1/2 of the DSP56362 internal clock frequency. For example, if the

DSP56362 is running at 100 MHz internally, the ACI frequency should be less

than 50 MHz.

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Timer Timing

ACI

220

221

222

223

ADO

AA1280

Figure 2-44 Digital Audio Transmitter Timing

TIMER TIMING

Table 2-26 Timer Timing

100 MHz

No.

Characteristics

Expression

Unit

Min Max

480

2 × T_C+ 2.0

22.0

—

ns

TIO Low

TIO High

481

Timer setup time from TIO (Input)

assertion to CLKOUT rising edge

482

9.0 10.0 ns

Synchronous timer delay time from

CLKOUT rising edge to the external

memory access address out valid

caused by first interrupt instruction

execution

103.

483

484

10.25 × T_C+ 1.0

—

ns

5

CLKOUT rising edge to TIO (Output)

assertion

0.5 × T_C+ 3.5

0.5 × T_C+ 19.8

8.5

—

• Minimum

• Maximum

ns

24.8

CLKOUT rising edge to TIO (Output)

deassertion

• Minimum

485

60.5 × T_C+ 3.5 8.5

0.5 × T_C+ 19.0

—

24.8

• Maximum

—

Note:

V_CC= 3.3 V 0.16 V; T_J= 0°C to +100°C, C_L= 50 pF

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Specifications

GPIO Timing

TIO

480

481

AA0492

Figure 2-45 TIO Timer Event Input Restrictions

CLKOUT

TIO (Input)

482

Address

483

First Interrupt Instruction Execution

AA0493

Figure 2-46 Timer Interrupt Generation

CLKOUT

TIO (Output)

484

485

AA0494

Figure 2-47 External Pulse Generation

GPIO TIMING

Table 2-27 GPIO Timing

100 MHz

No.

Characteristics

Expression

Unit

Min Max

CLKOUT edge to GPIO out valid (GPIO

out delay time)

CLKOUT edge to GPIO out not valid

(GPIO out hold time)

490

491

—

31.0 ns

ns

3.0

—

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GPIO Timing

Table 2-27 GPIO Timing (Continued)

100 MHz

No.

Characteristics

Expression

Unit

Min Max

GPIO In valid to CLKOUT edge (GPIO

in set-up time)

492

493

12.0

0.0

—

ns

CLKOUT edge to GPIO in not valid

(GPIO in hold time)

Fetch to CLKOUT edge before GPIO

change

494

495

6.75 × T_C

67.5

—

13

ns

GPIO out rise time

GPIO out fall time

496

Note:

V_CC= 3.3 V 0.16 V; T_J= 0°C to +100°C, C_L= 50 pF

CLKOUT

(Output)

490

491

GPIO

(Output)

492

493

GPIO

Valid

(Input)

A0–A17

494

Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO

and R0 contains the address of GPIO data register.

AA0495

GPIO

(Output)

495

496

Figure 2-48 GPIO Timing

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Specifications

JTAG Timing

JTAG TIMING

Table 2-28 JTAG Timing

All frequencies

No.

Characteristics

Unit

Min

0.0

Max

22.0

—

500

501

502

503

504

505

506

507

508

509

510

511

512

513

MHz

ns

TCK frequency of operation (1/(T_C× 3); maximum 22 MHz)

TCK cycle time in Crystal mode

TCK clock pulse width measured at 1.5 V

TCK rise and fall times

45.0

20.0

0.0

—

3.0

—

5.0

Boundary scan input data setup time

Boundary scan input data hold time

TCK low to output data valid

24.0

0.0

—

40.0

—

0.0

TCK low to output high impedance

TMS, TDI data setup time

5.0

25.0

0.0

—

TMS, TDI data hold time

44.0

—

TCK low to TDO data valid

0.0

TCK low to TDO high impedance

TRST assert time

100.0

40.0

—

TRST setup time to TCK low

Notes: 1. V_CC= 3.3 V 0.16V; T_J= 0°C to +100°C, C_L= 50 pF

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

501

502

V_M

V_IH

TCK

V_IL

(Input)

503

AA0496

Figure 2-49 Test Clock Input Timing Diagram

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Specifications

JTAG Timing

VIH

TCK

VIL

(Input)

504

Input Data Valid

505

Data

Inputs

506

507

506

Data

Output Data Valid

Outputs

Data

Outputs

Data

Output Data Valid

Outputs

AA0497

Figure 2-50 Boundary Scan (JTAG) Timing Diagram

VIH

509

TCK

VIL

(Input)

508

Input Data Valid

TDI

TMS

(Input)

510

TDO

Output Data Valid

(Output)

511

TDO

(Output)

510

TDO

Output Data Valid

(Output)

AA0498

Figure 2-51 Test Access Port Timing Diagram

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Specifications

OnCE Module TimIng

TCK

(Input)

513

TRST

(Input)

512

AA0499

Figure 2-52 TRST Timing Diagram

OnCE MODULE TIMING

OnCE Module Timing

100 MHz

No.

Characteristics

Expression

Unit

Min Max

1/(T_C× 3),

500

514

0.0 22.0 MHz

ns

TCK frequency of operation

max 22.0 MHz

DE assertion time in order to enter

Debug mode

1.5 × T_C+ 10.0 25.0

—

Response time when DSP56362 is

executing NOP instructions from

internal memory

515

5.5 × T_C+ 30.0

3 × T_C+ 10.0

—

85.0 ns

ns

516

40.0

—

Debug acknowledge assertion time

Note:

V_CC= 3.3 V 0.16 V; T_J= 0°C to +100°C, C_L= 50 pF

DE

514

515

516

AA0500

Figure 2-53 OnCE—Debug Request

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SECTION 3

PACKAGING

PIN-OUT AND PACKAGE INFORMATION

This section provides information about the available package for this product, including diagrams of the

package pinouts and tables describing how the signals described in Section 1 are allocated for the

package. The DSP56362 is available in a 144-pin LQFP package.

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Pin-out and Package Information

LQFP Package Description

Top view of the LQFP package is shown in Figure 3-1 with its pin-outs. The LQFP package mechanical

drawing is shown in Figure 3-2.

109

A0

BG

D7

D8

(Top View)

AA0

AA1

RD

WR

GND_C

V_CCC

BB

BR

TA

PINIT

nc

V

GND

CCD

D

D9

D10

D11

D12

D13

D14

V

CCD

GND

D

D15

D16

CLKOUT

GND

D17

D18

D19

C

V_CCC

V_CCQL

EXTAL

GND_Q

DE

V_CCQL

GND

Q

DSP56362

D20

CAS

AA2

AA3

V

CCD

GND

D

D21

D22

D23

MODD

MODC

MODB

MODA

TRST

TDO

TDI

TCK

TMS

MOSI

MISO

V

CCQH

GND_P1

GND_P

PCAP

V_CCP

RESET

HAD0

HAD1

HAD2

HAD3

GND_H

V_CCH

Orientation Mark

HAD4

37

1

Note: Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to

Table 3-1 and Table 3-2 for detailed information about pin functions and signal names.

AA0301

Figure 3-1 DSP56362 Thin Quad Flat Pack (LQFP), Top View

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Pin-out and Package Information

Table 3-1 DSP56362 LQFP Signal Identification by Pin Number

No.

Signal Name

1

2

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

SCK/SCL

GND_S

AA2/RAS2

SS/HA2

ADO or PD1

CAS

3

HREQ

ACI or PD0

DE

4

SDO0 or PC11

SDO1 or PC10

SDO2/SDI3 or PC9

SDO3/SDI2 or PC8

V_CCS

TIO0

GND_Q

EXTAL

V_CCQL

V_CCC

5

HCS/HCS, HA10, or PB13

HA2, HA9, or PB10

HA1, HA8, or PB9

HA0, HAS/HAS, or PB8

H7, HAD7, or PB7

H6, HAD6, or PB6

H5, HAD5, or PB5

H4, HAD4, or PB4

V_CCH

6

7

8

GND_C

CLKOUT

NC (not connected)

PINIT/NMI

TA

9

GND_S

10

11

12

13

14

15

16

17

18

19

20

SDO4/SDI1 or PC7

SDO5/SDI0 or PC6

FST or PC4

FSR or PC1

SCKT or PC3

SCKR or PC0

HCKT or PC5

HCKR or PC2

V_CCQL

BR

GND_H

BB

H3, HAD3, or PB3

H2, HAD2, or PB2

H1, HAD1, or PB1

H0, HAD0, or PB0

RESET

V_CCC

GND_C

WR

RD

GND_Q

AA1/RAS1

AA0/RAS0

V_CCQH

V_CCP

HDS/HDS, HWR/HWR, or

PB12

21

22

23

46

47

48

71

72

73

PCAP

GND_P

GND_P1

BG

A0

A1

HRW, HRD/HRD, or PB11

HACK/HACK,

HRRQ/HRRQ, or PB15

HOREQ/HOREQ,

24

25

49

50

74

75

V_CCQH

V_CCA

HTRQ/HTRQ, or PB14

V_CCS

AA3/RAS3

GND_A

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Pin-out and Package Information

Table 3-1 DSP56362 LQFP Signal Identification by Pin Number (Continued)

No.

Signal Name

76

A2

99

A17

122 D16

123 D17

124 D18

125 D19

126 V_CCQL

127 GND_Q

128 D20

129 V_CCD

130 GND_D

131 D21

132 D22

133 D23

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

A3

100 D0

A4

101 D1

A5

102 D2

V_CCA

GND_A

A6

103 V_CCD

104 GND_D

105 D3

A7

106 D4

A8

107 D5

A9

108 D6

V_CCA

GND_A

A10

A11

GND_Q

V_CCQL

A12

A13

A14

V_CCQH

GND_A

A15

A16

109 D7

110 D8

111 V_CCD

112 GND_D

113 D9

134 MODD/IRQD

135 MODC/IRQC

136 MODB/IRQB

137 MODA/IRQA

138 TRST

114 D10

115 D11

116 D12

117 D13

118 D14

119 V_CCD

120 GND_D

121 D15

139 TDO

140 TDI

141 TCK

142 TMS

143 MOSI/HA0

144 MISO/SDA

98

Note:

Signal names are based on configured functionality. Most pins supply a single signal. Some pins

provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode

after RESET is deasserted, but act as interrupt lines during operation. Some signals have configurable

polarity; these names are shown with and without overbars, such as HAS/HAS. Some pins have two or

more configurable functions; names assigned to these pins indicate the function for a specific

configuration. For example, pin 34 is data line H7 in nonmultiplexed bus mode, data/address line HAD7

in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin.

Table 3-2 DSP56362 LQFP Signal Identification by Name

No.

Signal Name

not connected

60

72

73

D13

D14

D15

117

118

121

GND_P1

GND_Q

48

19

54

A0

A1

3-4

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Pin-out and Package Information

Table 3-2 DSP56362 LQFP Signal Identification by Name (Continued)

No.

Signal Name

A10

A11

A12

A13

A14

A15

A16

A17

A2

A3

A4

A5

A6

A7

A8

A9

AA0

AA1

AA2

AA3

ACI

ADO

BB

88

89

92

93

94

97

98

99

76

77

78

79

82

83

84

85

70

69

51

50

28

27

64

71

63

52

59

100

101

114

115

116

D16

D17

D18

D19

D2

D20

D21

D22

D23

D3

D4

D5

D6

D7

D8

D9

DE

122

123

124

125

102

128

131

132

133

105

106

107

108

109

110

113

53

55

13

12

75

81

87

96

58

GND_Q

GND_S

H0

H1

H2

H3

H4

H5

H6

H7

HA0

HA1

HA10

HA2

90

127

9

26

43

42

41

40

37

36

35

34

33

143

32

30

2

31

32

31

23

43

42

41

40

37

36

35

34

33

30

21

EXTAL

FSR

FST

HA8

HA9

GND_A

GND_C

GND_D

GND_H

GND_P

HACK/HACK

HAD0

HAD1

HAD2

HAD3

HAD4

HAD5

HAD6

HAD7

HAS/HAS

HCS/HCS

HDS/HDS

BG

BR

CAS

CLKOUT

D0

66

104

112

120

130

39

D1

D10

D11

D12

47

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Packaging

Pin-out and Package Information

Table 3-2 DSP56362 LQFP Signal Identification by Name (Continued)

No.

Signal Name

HOREQ/HOREQ

HRD/HRD

HREQ

HRRQ/HRRQ

HRW

HCKR

HCKT

HTRQ/HTRQ

HWR/HWR

IRQA

24

22

3

23

22

17

16

24

21

137

136

135

134

144

137

136

135

134

143

61

43

42

31

22

21

30

24

23

41

40

37

36

35

34

33

PB9

PC0

PC1

PC10

PC11

PC2

PC3

PC4

PC5

PC6

PC7

PC8

PC9

PCAP

PD0

32

15

13

5

SDO3

SDO4

SDO5

SS

TA

TCK

TDI

TDO

TIO0

TMS

TRST

V_CCA

V_CCC

V_CCD

V_CCH

V_CCP

V_CCQH

V_CCQL

V_CCS

WR

7

10

11

2

4

62

17

14

12

16

11

10

7

141

140

139

29

142

138

74

80

86

57

65

103

111

119

129

38

45

20

49

95

IRQB

IRQC

IRQD

MISO

MODA

MODB

MODC

MODD

MOSI

NMI

PB0

PB1

PB10

PB11

PB12

PB13

PB14

PB15

PB2

PB3

PB4

PB5

PB6

PB7

PB8

6

46

28

27

61

70

69

52

51

68

44

1

15

14

1

144

11

10

7

PD1

PINIT

RAS0

RAS1

RAS2

RAS3

RD

RESET

SCK

SCKR

SCKT

SCL

18

56

91

126

8

SDA

SDI0

SDI1

SDI2

SDI3

SDO0

SDO1

SDO2

25

67

6

4

5

6

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Packaging

Pin-out and Package Information

LQFP PACKAGE MECHANICAL DRAWING

Figure 3-2 DSP56362 144-pin LQFP Package

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Packaging

Ordering Drawings

ORDERING DRAWINGS

The detailed package drawing is available on the Motorola web page at:

http://mot.sps.com/cgi-bin/cases

Use package 918-03 for the search.

3-8

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SECTION 4

DESIGN CONSIDERATIONS

THERMAL DESIGN CONSIDERATIONS

An estimation of the chip junction temperature, T_J, in °C can be obtained from the following equation:

T

= T + (P × R

)

J

A

D

θJA

Where:

T_A= ambient temperature °C

R_qJA= package junction-to-ambient thermal resistance °C/W

P_D= power dissipation in package W

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance

and a case-to-ambient thermal resistance.

R

= R

+ R

θJA

Where:

θJC

θCA

R_θJA= package junction-to-ambient thermal resistance °C/W

R_θJC= package junction-to-case thermal resistance °C/W

R_θCA= package case-to-ambient thermal resistance °C/W

R

_θJCis device-related and cannot be influenced by the user. The user controls the thermal environment to

change the case-to-ambient thermal resistance, R_θCA. For example, the user can change the air flow

around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB),

or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This

model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated

through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations

where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of

the device thermal performance may need the additional modeling capability of a system level thermal

simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which

the package is mounted. Again, if the estimations obtained from R_θJAdo not satisfactorily answer whether

the thermal performance is adequate, a system level model may be appropriate.

A complicating factor is the existence of three common ways for determining the junction-to-case thermal

resistance in plastic packages.

•

To minimize temperature variation across the surface, the thermal resistance is measured from

the junction to the outside surface of the package (case) closest to the chip mounting area when

that surface has a proper heat sink.

•

To define a value approximately equal to a junction-to-board thermal resistance, the thermal

resistance is measured from the junction to where the leads are attached to the case.

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Design Considerations

Electrical Design Considerations

•

If the temperature of the package case (T_T) is determined by a thermocouple, the thermal

resistance is computed using the value obtained by the equation

(T_J– T_T)/P_D.

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using

the first definition. From a practical standpoint, that value is also suitable for determining the junction

temperature from a case thermocouple reading in forced convection environments. In natural convection,

using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple

reading on the case of the package will estimate a junction temperature slightly hotter than actual

temperature. Hence, the new thermal metric, thermal characterization parameter or Ψ_JT, has been defined

to be (T_J– T_T)/P_D. This value gives a better estimate of the junction temperature in natural convection

when using the surface temperature of the package. Remember that surface temperature readings of

packages are subject to significant errors caused by inadequate attachment of the sensor to the surface

and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge

thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

ELECTRICAL DESIGN CONSIDERATIONS

CAUTION

This device contains circuitry protecting

against damage due to high static voltage or

electrical fields. However, normal precautions

should be taken to avoid exceeding maximum

voltage ratings. Reliability of operation is

enhanced if unused inputs are tied to an

appropriate logic voltage level (e.g., either

GND or V ). The suggested value for a

CC

pullup or pulldown resistor is 10 k ohm.

Use the following list of recommendations to assure correct DSP operation:

•

Provide a low-impedance path from the board power supply to each V_CCpin on the DSP and from

the board ground to each GND pin.

Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of

the package to connect the V_CCpower source to GND.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V_CCand

GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.

•

Use at least a four-layer PCB with two inner layers for V_CCand GND.

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be

minimal. This recommendation particularly applies to the address and data buses as well as the

IRQA, IRQB, IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 15 cm

(6 inches) are recommended.

4-2

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Design Considerations

Power Consumption Considerations

•

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating

capacitance. This is especially critical in systems with higher capacitive loads that could create

higher transient currents in the V_CCand GND circuits.

All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the pins with

internal pull-up resistors (TRST, TMS, DE, TCK, and TDI).

•

Take special care to minimize noise levels on the V_CCP, GND_P, and GND_P1pins.

If multiple DSP56362 devices are on the same board, check for cross-talk or excessive spikes on

the supplies due to synchronous operation of the devices.

•

RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied

before deassertion of RESET.

At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V_CC

never exceeds 3.95 V.

POWER CONSUMPTION CONSIDERATIONS

Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current

consumption are described in this section. Most of the current consumed by CMOS devices is alternating

current (ac), which is charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by the following formula:

I = C × V × f

where

C = node/pin capacitance

V = voltage swing

f = frequency of node/pin toggle

Example 1 Current Consumption

For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz clock, toggling

at its maximum possible rate (50 MHz), the current consumption is

–12

6

I = 50 × 10

× 3.3 × 50 × 10 = 8.25mA

The maximum internal current (I_CCImax) value reflects the typical possible switching of the internal buses

on best-case operation conditions, which is not necessarily a real application case. The typical internal

current (I_CCItyp) value reflects the average switching of the internal buses on typical operating conditions.

For applications that require very low current consumption, do the following:

•

Set the EBD bit when not accessing external memory.

Minimize external memory accesses and use internal memory accesses.

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Design Considerations

PLL Performance Issues

•

Minimize the number of pins that are switching.

Minimize the capacitive load on the pins.

Connect the unused inputs to pull-up or pull-down resistors.

Disable unused peripherals.

Disable unused pin activity (e.g., CLKOUT, XTAL).

One way to evaluate power consumption is to use a current per MIPS measurement methodology to

minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A

benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test

current measurements, and the following equation to derive the current per MIPS value.

I § MIPS = I § MHz = (I

– I

typF2 typF1

) § (F2 – F1)

where :

I_typF2= current at F2

I_typF1= current at F1

F2 = high frequency (any specified operating frequency)

F1 = low frequency (any specified operating frequency lower than F2)

Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1

could be 33 MHz. The degree of difference between F1 and F2 determines the

amount of precision with which the current rating can be determined for an application.

PLL PERFORMANCE ISSUES

The following explanations should be considered as general observations on expected PLL behavior.

There is no testing that verifies these exact numbers. These observations were measured on a limited

number of parts and were not verified over the entire temperature and voltage ranges.

Phase Skew Performance

The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and

CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature, and voltage

ranges. As defined in Figure 2-1, for input frequencies greater than 15 MHz and the MF ≤ 4, this skew is

greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for

MF < 10 and input frequencies greater than 10 MHz, this skew is between −1.4 ns and +3.2 ns.

Phase Jitter Performance

The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and

CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on

CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than

15 MHz and MF ≤ 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. However, for MF

< 10 and input frequencies greater than 10 MHz, this jitter is less than 2 ns.

4-4

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Design Considerations

Host Port Considerations

Frequency Jitter Performance

The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF <

10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is between 0.5% and

approximately 2%. For large MF (MF > 500), the frequency jitter is 2–3%.

Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is

slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of

the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%.

The phase and frequency jitter performance results are only valid if the input jitter is less than the

prescribed values.

HOST PORT CONSIDERATIONS

Careful synchronization is required when reading multi-bit registers that are written by another

asynchronous system. This synchronization is a common problem when two asynchronous systems are

connected, as they are in the host interface. The following paragraphs present considerations for proper

operation.

Host Programming Considerations

•

Unsynchronized Reading of Receive Byte Registers—When reading the receive byte

registers, receive register high (RXH), receive register middle (RXM), or receive register low

(RXL), the host interface programmer should use interrupts or poll the receive register data full

(RXDF) flag that indicates whether data is available. This ensures that the data in the receive byte

registers will be valid.

Overwriting Transmit Byte Registers—The host interface programmer should not write to the

transmit byte registers, transmit register high (TXH), transmit register middle (TXM), or transmit

register low (TXL), unless the transmit register data empty (TXDE) bit is set, indicating that the

transmit byte registers are empty. This ensures that the transmit byte registers will transfer valid

data to the host receive (HRX) register.

Synchronization of Status Bits from DSP to Host—HC, HOREQ, DMA, HF3, HF2, TRDY,

TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host

processor (refer to the user’s manual for descriptions of these status bits). The host can read these

status bits very quickly without regard to the clock rate used by the DSP, but the state of the bit

could be changing during the read operation. This is not generally a system problem, because the bit

will be read correctly in the next pass of any host polling routine.

However, if the host asserts HEN for more than timing number 31, with

a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be

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Design Considerations

Host Port Considerations

stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP

changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits

during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has

significance, the host could read the wrong combination. Therefore, read the bits twice and

check for consensus.

•

Overwriting the Host Vector—The host interface programmer should change the host vector

(HV) register only when the host command (HC) bit is clear. This ensures that the DSP interrupt

control logic will receive a stable vector.

Cancelling a Pending Host Command Exception—The host processor may elect to clear the

HC bit to cancel the host command exception request at any time before it is recognized by the

DSP. Because the host does not know exactly when the exception will be recognized (due to

exception processing synchronization and pipeline delays), the DSP may execute the host

command exception after the HC bit is cleared. For these reasons, the HV bits must not be

changed at the same time that the HC bit is cleared.

•

Variance in the Host Interface Timing—The host interface (HDI) may vary (e.g. due to the PLL

lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make

sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then

polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together

with the INIT and then polling INIT, ISR, and the HOREQ pin).

DSP Programming Considerations

•

Synchronization of Status Bits from Host to DSP—DMA, HF1, HF0, HCP, HTDE, and HRDF

status bits are set or cleared by the host processor side of the interface. These bits are individually

synchronized to the DSP clock. (Refer to the user’s manual for descriptions of these status bits.)

•

Reading HF0 and HF1 as an Encoded Pair—Care must be exercised when reading status bits

HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have

significance). A very small probability exists that the DSP will read the status bits synchronized

during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.

4-6

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SECTION 5

ORDERING INFORMATION

Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability

and to place an order.

For information on ordering this and all DSP Audio products, review the SG1004 selector guide at http://e-

www.motorola.com/files/shared/doc/selector_guide/SG1004.pdf.

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NOTES

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APPENDIX A

POWER CONSUMPTION BENCHMARK

The following benchmark program permits evaluation of DSP power usage in a test situation. It enables

the PLL, disables the external clock, and uses repeated

multiply-accumulate instructions with a set of synthetic DSP application data to emulate intensive

sustained DSP operation.

;********************************************************************;**

******************************************************************

;* ;* CHECKS

Typical Power Consumption

;********************************************************************

page

200,55,0,0,0

nolist

I_VEC EQU $000000 ; Interrupt vectors for program debug only

START EQU $8000 ; MAIN (external) program starting address

INT_PROG EQU $100 ; INTERNAL program memory starting address

INT_XDAT EQU $0

INT_YDAT EQU $0

; INTERNAL X-data memory starting address

; INTERNAL Y-data memory starting address

INCLUDE "ioequ.asm"

INCLUDE "intequ.asm"

list

org

P:START

;

movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM)

; Default: 1 w.s (SRAM)

;

movep

#$0d0000,x:M_PCTL

; XTAL disable

; PLL enable

; CLKOUT disable

;

; Load the program

;

move

#INT_PROG,r0

#PROG_START,r1

do

move

#(PROG_END-PROG_START),PLOAD_LOOP

p:(r1)+,x0

move

x0,p:(r0)+

nop

PLOAD_LOOP

;

; Load the X-data

;

move

#INT_XDAT,r0

#XDAT_START,r1

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Power Consumption Benchmark

do

move

#(XDAT_END-XDAT_START),XLOAD_LOOP

p:(r1)+,x0

x0,x:(r0)+

XLOAD_LOOP

;

; Load the Y-data

;

move

#INT_YDAT,r0

move

#YDAT_START,r1

do

move

#(YDAT_END-YDAT_START),YLOAD_LOOP

p:(r1)+,x0

move

YLOAD_LOOP

;

x0,y:(r0)+

jmp

INT_PROG

PROG_START

move

;

#$0,r0

#$0,r4

#$3f,m0

#$3f,m4

clr

a

clr

b

move

bset

;

#$0,x0

#$0,x1

#$0,y0

#$0,y1

#4,omr

; ebd

sbr

dor

mac

add

mac

move

#60,_end

x0,y0,a x:(r0)+,x1

x1,y1,a x:(r0)+,x0

a,b

x0,y0,a x:(r0)+,x1

x1,y1,a

y:(r4)+,y1

y:(r4)+,y0

b1,x:$ff

_end

bra

nop

sbr

PROG_END

nop

XDAT_START

;

org

x:0

dc

$262EB9

$86F2FE

$E56A5F

Appendix A-2

DSP56362 Advance Information

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Power Consumption Benchmark

dc

$616CAC

$8FFD75

$9210A

$A06D7B

$CEA798

$8DFBF1

$A063D6

$6C6657

$C2A544

$A3662D

$A4E762

$84F0F3

$E6F1B0

$B3829

$8BF7AE

$63A94F

$EF78DC

$242DE5

$A3E0BA

$EBAB6B

$8726C8

$CA361

$2F6E86

$A57347

$4BE774

$8F349D

$A1ED12

$4BFCE3

$EA26E0

$CD7D99

$4BA85E

$27A43F

$A8B10C

$D3A55

$25EC6A

$2A255B

$A5F1F8

$2426D1

$AE6536

$CBBC37

$6235A4

$37F0D

$63BEC2

$A5E4D3

$8CE810

$3FF09

$60E50E

$CFFB2F

$40753C

$8262C5

$CA641A

$EB3B4B

$2DA928

$AB6641

MOTOROLA

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Appendix A-3

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Power Consumption Benchmark

dc

$28A7E6

$4E2127

$482FD4

$7257D

$E53C72

$1A8C3

$E27540

XDAT_END

YDAT_START

;

org

y:0

dc

$5B6DA

$C3F70B

$6A39E8

$81E801

$C666A6

$46F8E7

$AAEC94

$24233D

$802732

$2E3C83

$A43E00

$C2B639

$85A47E

$ABFDDF

$F3A2C

$2D7CF5

$E16A8A

$ECB8FB

$4BED18

$43F371

$83A556

$E1E9D7

$ACA2C4

$8135AD

$2CE0E2

$8F2C73

$432730

$A87FA9

$4A292E

$A63CCF

$6BA65C

$E06D65

$1AA3A

$A1B6EB

$48AC48

$EF7AE1

$6E3006

$62F6C7

$6064F4

$87E41D

$CB2692

$2C3863

$C6BC60

Appendix A-4

DSP56362 Advance Information

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Power Consumption Benchmark

dc

$43A519

$6139DE

$ADF7BF

$4B3E8C

$6079D5

$E0F5EA

$8230DB

$A3B778

$2BFE51

$E0A6B6

$68FFB7

$28F324

$8F2E8D

$667842

$83E053

$A1FD90

$6B2689

$85B68E

$622EAF

$6162BC

$E4A245

YDAT_END

MOTOROLA

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Appendix A-5

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NOTES

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Freescale Semiconductor, Inc.

APPENDIX B

IBIS MODEL

[IBIS ver]

[File name]

[File Rev]

[Date]

2.1

56362.ibs

0.0

29/6/2000

56362

[Component]

[Manufacturer] Motorola

[Package]

|variable

R_pkg

typ

45m

min

22m

max

75m

L_pkg

C_pkg

2.5nH

1.3pF

1.1nH

1.2pF

4.3nH

1.4pF

[Pin]signal_name model_name

1 sck

2 ss_

ip5b_io

3 hreq_

4 sdo0

5 sdo1

ip5b_io

6 sdoi23

7 sdoi32

8 svcc

ip5b_io

power

gnd

9 sgnd

10 sdoi41

11 sdoi50

12 fst

ip5b_io

power

13 fsr

14 sckt

15 sckr

16 hsckt

17 hsckr

18 qvccl

19 gnd

gnd

20 qvcch

21 hp12

22 hp11

23 hp15

24 hp14

25 svcc

26 sgnd

27 ado

28 aci

29 tio

30 hp13

31 hp10

32 hp9

power

ip5b_io

power

gnd

ip5b_io

33 hp8

MOTOROLA

DSP56362 Advance Information

Appendix B-1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

34 hp7

35 hp6

36 hp5

37 hp4

38 svcc

39 sgnd

40 hp3

41 hp2

42 hp1

ip5b_io

power

gnd

ip5b_io

ip5b_i

power

gnd

43 hp0

44 ires_

45 pvcc

46 pcap

47 pgnd

48 pgnd1

49 qvcch

50 aa3

51 aa2

52 cas_

53 de_

54 qgnd

55 cxtldis_

56 qvccl

57 cvcc

58 cgnd

59 clkout

61 nmi_

62 ta_

63 br_

64 bb_

65 cvcc

66 cgnd

67 wr_

68 rd_

69 aa1

70 aa0

71 bg_

72 eab0

73 eab1

74 avcc

75 agnd

76 eab2

77 eab3

78 eab4

79 eab5

80 avcc

81 agnd

82 eab6

83 eab7

84 eab8

85 eab9

86 avcc

87 agnd

88 eab10

gnd

power

icbc_o

ipbw_io

gnd

iexlh_i

power

gnd

icba_o

ipbw_i

icbc_o

power

gnd

icbc_o

icba_o

power

gnd

icba_o

power

gnd

icba_o

power

gnd

icba_o

Appendix B-2

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

89 eab11

90 qgnd

icba_o

gnd

91 qvcc

power

92 eab12

93 eab13

94 eab14

95 qvcch

96 agnd

icba_o

power

gnd

97 eab15

98 eab16

99 eab17

100 edb0

101 edb1

102 edb2

103 dvcc

104 dgnd

105 edb3

106 edb4

107 edb5

108 edb6

109 edb7

110 edb8

111 dvcc

112 dgnd

113 edb9

114 edb10

115 edb11

116 edb12

117 edb13

118 edb14

119 dvcc

120 dgnd

121 edb15

122 edb16

123 edb17

124 edb18

125 edb19

126 qvccl

127 qgnd

128 edb20

129 dvcc

130 dgnd

131 edb21

132 edb22

133 edb23

134 irqd_

135 irqc_

136 irqb_

137 irqa_

138 trst_

139 tdo

icba_o

icba_io

power

gnd

icba_io

power

gnd

icba_io

power

gnd

icba_io

power

gnd

icba_io

power

gnd

icba_io

ip5b_i

ip5b_o

ip5b_i

140 tdi

141 tck

142 tms

MOTOROLA

DSP56362 Advance Information

Appendix B-3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

143 mosi

144 sda

|

ip5b_io

[Model]

Model_type

Polarity

ip5b_i

Input

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

|

[Voltage Range]

[GND_clamp]

|voltage

|

5.00pF

3v

5.00pF

3.3v

I(typ)

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-5.21e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-9.69e-03

-2.83e-04

-1.35e-06

-1.31e-09

-2.92e-11

-2.44e-11

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-5.70e-03

-4.53e-05

-3.74e-07

-3.00e-09

-5.14e-10

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.61e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.67e+00

-7.81e-03

-8.42e-04

-1.00e-05

-8.58e-09

-3.64e-11

-2.79e-11

|

[Model]

Model_type

Polarity

ip5b_io

I/O

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

|

[Voltage Range]

[Pulldown]

|voltage

|

5.00pF

3v

5.00pF

3.3v

I(typ)

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-5.21e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

Appendix B-4

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-5.10e-02

-3.65e-02

-2.65e-02

-1.62e-02

-5.49e-03

5.377e-03

1.516e-02

2.370e-02

3.098e-02

3.700e-02

4.175e-02

4.531e-02

4.779e-02

4.935e-02

5.013e-02

5.046e-02

5.063e-02

5.075e-02

5.085e-02

5.090e-02

4.771e-02

4.525e-02

4.657e-02

4.904e-02

5.221e-02

5.524e-02

5.634e-02

5.751e-02

5.634e-02

5.648e-02

5.664e-02

5.679e-02

5.693e-02

5.707e-02

5.722e-02

5.741e-02

5.766e-02

5.801e-02

5.824e-02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-2.25e-02

-1.38e-02

-8.35e-03

-2.80e-03

2.744e-03

7.871e-03

1.252e-02

1.667e-02

2.026e-02

2.324e-02

2.553e-02

2.709e-02

2.803e-02

2.851e-02

2.876e-02

2.892e-02

2.904e-02

2.912e-02

2.876e-02

2.994e-02

3.321e-02

3.570e-02

3.801e-02

4.029e-02

4.253e-02

4.463e-02

4.645e-02

4.786e-02

4.881e-02

4.912e-02

4.795e-02

4.679e-02

4.688e-02

4.700e-02

4.712e-02

4.723e-02

4.733e-02

4.737e-02

-1.61e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.69e+00

-5.63e-02

-4.28e-02

-3.12e-02

-1.91e-02

-6.52e-03

6.427e-03

1.823e-02

2.869e-02

3.776e-02

4.544e-02

5.171e-02

5.660e-02

6.023e-02

6.271e-02

6.419e-02

6.494e-02

6.525e-02

6.540e-02

6.549e-02

6.555e-02

6.561e-02

6.182e-02

6.049e-02

6.178e-02

6.450e-02

6.659e-02

6.867e-02

6.970e-02

6.938e-02

6.960e-02

6.983e-02

7.005e-02

7.026e-02

7.049e-02

7.074e-02

7.105e-02

7.147e-02

7.205e-02

7.242e-02

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

2.922e-04

2.881e-04

2.853e-04

2.836e-04

2.825e-04

2.819e-04

2.177e-04

2.175e-04

2.173e-04

2.172e-04

2.171e-04

2.170e-04

4.123e-04

4.021e-04

3.946e-04

3.893e-04

3.857e-04

3.834e-04

MOTOROLA

DSP56362 Advance Information

Appendix B-5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

2.815e-04

2.813e-04

2.812e-04

2.811e-04

2.810e-04

2.809e-04

2.808e-04

2.997e-04

1.750e-02

1.048e-02

3.487e-03

-3.40e-03

-9.69e-03

-1.52e-02

-2.02e-02

-2.46e-02

-2.84e-02

-3.14e-02

-3.37e-02

-3.55e-02

-3.68e-02

-3.78e-02

-3.85e-02

-3.91e-02

-3.96e-02

-4.01e-02

-4.04e-02

-4.08e-02

-4.11e-02

-4.14e-02

-4.17e-02

-4.32e-02

-4.08e-01

-2.73e+01

-6.13e+01

-9.54e+01

-1.38e+02

-1.89e+02

-2.40e+02

-2.91e+02

-3.42e+02

-3.93e+02

-4.44e+02

-4.95e+02

-5.21e+02

2.169e-04

2.167e-04

2.520e-04

3.078e-02

2.684e-02

2.277e-02

1.864e-02

1.447e-02

1.031e-02

6.181e-03

2.084e-03

-2.03e-03

-5.71e-03

-8.99e-03

-1.19e-02

-1.43e-02

-1.62e-02

-1.77e-02

-1.88e-02

-1.95e-02

-2.00e-02

-2.04e-02

-2.07e-02

-2.10e-02

-2.12e-02

-2.15e-02

-2.17e-02

-2.18e-02

-2.20e-02

-2.78e-02

-1.20e+00

-2.15e+01

-4.52e+01

-6.89e+01

-9.25e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

-2.59e+02

-2.94e+02

-3.30e+02

-3.65e+02

-4.01e+02

-4.18e+02

3.820e-04

3.812e-04

3.808e-04

3.806e-04

3.804e-04

3.802e-04

3.801e-04

3.799e-04

3.797e-04

3.776e-04

4.568e-03

-4.22e-03

-1.24e-02

-1.95e-02

-2.61e-02

-3.21e-02

-3.73e-02

-4.18e-02

-4.55e-02

-4.85e-02

-5.09e-02

-5.27e-02

-5.41e-02

-5.51e-02

-5.60e-02

-5.67e-02

-5.74e-02

-5.79e-02

-5.84e-02

-5.89e-02

-5.94e-02

-5.98e-02

-6.10e-02

-6.84e-02

-7.73e+00

-4.18e+01

-7.59e+01

-1.11e+02

-1.61e+02

-2.12e+02

-2.63e+02

-3.14e+02

-3.65e+02

-4.16e+02

-4.41e+02

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-5.21e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

Appendix B-6

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-9.69e-03

-2.83e-04

-1.35e-06

-1.31e-09

-2.92e-11

-2.44e-11

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-5.70e-03

-4.53e-05

-3.74e-07

-3.00e-09

-5.14e-10

-2.63e+02

-2.12e+02

-1.61e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.67e+00

-7.81e-03

-8.42e-04

-1.00e-05

-8.58e-09

-3.64e-11

-2.79e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.030/0.465

1.290/0.671

0.605/0.676

0.829/0.122

1.320/0.366

1.520/0.431

dV/dt_f

|

[Model]

Model_type

Polarity

C_comp

|

ip5b_o

3-state

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

-5.21e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-5.10e-02

-3.65e-02

-2.65e-02

-1.62e-02

-5.49e-03

5.377e-03

1.516e-02

-3.65e+02

-5.18e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-2.25e-02

-1.38e-02

-8.35e-03

-2.80e-03

2.744e-03

7.871e-03

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.61e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.69e+00

-5.63e-02

-4.28e-02

-3.12e-02

-1.91e-02

-6.52e-03

6.427e-03

1.823e-02

MOTOROLA

DSP56362 Advance Information

Appendix B-7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

2.370e-02

3.098e-02

3.700e-02

4.175e-02

4.531e-02

4.779e-02

4.935e-02

5.013e-02

5.046e-02

5.063e-02

5.075e-02

5.085e-02

5.090e-02

4.771e-02

4.525e-02

4.657e-02

4.904e-02

5.221e-02

5.524e-02

5.634e-02

5.751e-02

5.634e-02

5.648e-02

5.664e-02

5.679e-02

5.693e-02

5.707e-02

5.722e-02

5.741e-02

5.766e-02

5.801e-02

5.824e-02

1.252e-02

1.667e-02

2.026e-02

2.324e-02

2.553e-02

2.709e-02

2.803e-02

2.851e-02

2.876e-02

2.892e-02

2.904e-02

2.912e-02

2.876e-02

2.994e-02

3.321e-02

3.570e-02

3.801e-02

4.029e-02

4.253e-02

4.463e-02

4.645e-02

4.786e-02

4.881e-02

4.912e-02

4.795e-02

4.679e-02

4.688e-02

4.700e-02

4.712e-02

4.723e-02

4.733e-02

4.737e-02

2.869e-02

3.776e-02

4.544e-02

5.171e-02

5.660e-02

6.023e-02

6.271e-02

6.419e-02

6.494e-02

6.525e-02

6.540e-02

6.549e-02

6.555e-02

6.561e-02

6.182e-02

6.049e-02

6.178e-02

6.450e-02

6.659e-02

6.867e-02

6.970e-02

6.938e-02

6.960e-02

6.983e-02

7.005e-02

7.026e-02

7.049e-02

7.074e-02

7.105e-02

7.147e-02

7.205e-02

7.242e-02

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

2.922e-04

2.881e-04

2.853e-04

2.836e-04

2.825e-04

2.819e-04

2.815e-04

2.813e-04

2.812e-04

2.811e-04

2.810e-04

2.809e-04

2.808e-04

2.997e-04

1.750e-02

1.048e-02

3.487e-03

-3.40e-03

2.177e-04

2.175e-04

2.173e-04

2.172e-04

2.171e-04

2.170e-04

2.169e-04

2.167e-04

2.520e-04

3.078e-02

2.684e-02

2.277e-02

1.864e-02

1.447e-02

1.031e-02

6.181e-03

2.084e-03

-2.03e-03

4.123e-04

4.021e-04

3.946e-04

3.893e-04

3.857e-04

3.834e-04

3.820e-04

3.812e-04

3.808e-04

3.806e-04

3.804e-04

3.802e-04

3.801e-04

3.799e-04

3.797e-04

3.776e-04

4.568e-03

-4.22e-03

Appendix B-8

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-9.69e-03

-1.52e-02

-2.02e-02

-2.46e-02

-2.84e-02

-3.14e-02

-3.37e-02

-3.55e-02

-3.68e-02

-3.78e-02

-3.85e-02

-3.91e-02

-3.96e-02

-4.01e-02

-4.04e-02

-4.08e-02

-4.11e-02

-4.14e-02

-4.17e-02

-4.32e-02

-4.08e-01

-2.73e+01

-6.13e+01

-9.54e+01

-1.38e+02

-1.89e+02

-2.40e+02

-2.91e+02

-3.42e+02

-3.93e+02

-4.44e+02

-4.95e+02

-5.21e+02

-5.71e-03

-8.99e-03

-1.19e-02

-1.43e-02

-1.62e-02

-1.77e-02

-1.88e-02

-1.95e-02

-2.00e-02

-2.04e-02

-2.07e-02

-2.10e-02

-2.12e-02

-2.15e-02

-2.17e-02

-2.18e-02

-2.20e-02

-2.78e-02

-1.20e+00

-2.15e+01

-4.52e+01

-6.89e+01

-9.25e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

-2.59e+02

-2.94e+02

-3.30e+02

-3.65e+02

-4.01e+02

-4.18e+02

-1.24e-02

-1.95e-02

-2.61e-02

-3.21e-02

-3.73e-02

-4.18e-02

-4.55e-02

-4.85e-02

-5.09e-02

-5.27e-02

-5.41e-02

-5.51e-02

-5.60e-02

-5.67e-02

-5.74e-02

-5.79e-02

-5.84e-02

-5.89e-02

-5.94e-02

-5.98e-02

-6.10e-02

-6.84e-02

-7.73e+00

-4.18e+01

-7.59e+01

-1.11e+02

-1.61e+02

-2.12e+02

-2.63e+02

-3.14e+02

-3.65e+02

-4.16e+02

-4.41e+02

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

-5.21e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-9.69e-03

-2.83e-04

-1.35e-06

-1.31e-09

-2.92e-11

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-5.70e-03

-4.53e-05

-3.74e-07

-3.00e-09

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.61e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.67e+00

-7.81e-03

-8.42e-04

-1.00e-05

-8.58e-09

-3.64e-11

MOTOROLA

DSP56362 Advance Information

Appendix B-9

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

0.000e+00

|

-2.44e-11

-5.14e-10

-2.79e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.030/0.465

1.290/0.671

0.605/0.676

0.829/0.122

1.320/0.366

1.520/0.431

dV/dt_f

|

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

icba_io

I/O

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-2.70e-02

-1.32e-02

-9.33e-03

-5.75e-03

-1.97e-03

1.945e-03

5.507e-03

8.649e-03

1.136e-02

1.364e-02

1.547e-02

1.688e-02

1.299e-01

1.366e-01

1.404e-01

1.423e-01

1.433e-01

-3.65e+02

-5.18e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.19e+00

-1.25e-02

-4.69e-03

-2.81e-03

-9.48e-04

9.285e-04

2.640e-03

4.168e-03

5.504e-03

6.636e-03

7.551e-03

8.240e-03

6.458e-02

6.746e-02

6.916e-02

7.006e-02

7.059e-02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.60e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.68e+00

-2.90e-02

-1.63e-02

-1.10e-02

-6.76e-03

-2.32e-03

2.307e-03

6.599e-03

1.048e-02

1.393e-02

1.693e-02

1.950e-02

2.162e-02

2.331e-02

1.755e-01

1.847e-01

1.907e-01

1.940e-01

Appendix B-10

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

1.440e-01

1.445e-01

1.450e-01

1.454e-01

1.458e-01

1.461e-01

1.464e-01

1.469e-01

1.490e-01

1.501e+00

1.813e+01

3.540e+01

5.269e+01

7.541e+01

1.012e+02

1.270e+02

1.527e+02

1.785e+02

2.043e+02

2.301e+02

2.559e+02

2.688e+02

7.098e-02

7.128e-02

7.154e-02

7.176e-02

7.196e-02

7.223e-02

8.810e-02

2.589e+00

1.451e+01

2.658e+01

3.866e+01

5.076e+01

6.461e+01

8.261e+01

1.006e+02

1.186e+02

1.366e+02

1.546e+02

1.726e+02

1.906e+02

2.086e+02

2.176e+02

1.958e-01

1.970e-01

1.979e-01

1.986e-01

1.993e-01

1.999e-01

2.004e-01

2.009e-01

2.015e-01

2.030e-01

2.385e-01

9.563e+00

2.682e+01

4.409e+01

6.258e+01

8.836e+01

1.141e+02

1.399e+02

1.657e+02

1.915e+02

2.173e+02

2.302e+02

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.360e+00

4.275e-02

8.208e-03

5.635e-03

3.370e-03

1.118e-03

-1.09e-03

-3.12e-03

-4.96e-03

-6.60e-03

-8.04e-03

-9.26e-03

-1.03e-02

-1.25e-01

-1.31e-01

-1.36e-01

-1.40e-01

1.905e+02

1.725e+02

1.545e+02

1.365e+02

1.185e+02

1.005e+02

8.253e+01

6.454e+01

5.068e+01

3.859e+01

2.651e+01

1.444e+01

2.518e+00

2.012e-02

3.518e-03

2.053e-03

6.789e-04

-6.56e-04

-1.86e-03

-2.93e-03

-3.87e-03

-4.66e-03

-5.30e-03

-6.55e-02

-6.93e-02

-7.19e-02

-7.38e-02

-7.53e-02

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.362e+00

4.663e-02

1.070e-02

7.068e-03

4.233e-03

1.410e-03

-1.38e-03

-3.99e-03

-6.39e-03

-8.59e-03

-1.06e-02

-1.23e-02

-1.38e-02

-1.70e-01

-1.82e-01

-1.91e-01

-1.97e-01

MOTOROLA

DSP56362 Advance Information

Appendix B-11

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-1.42e-01

-1.44e-01

-1.46e-01

-1.48e-01

-1.49e-01

-1.50e-01

-1.52e-01

-1.53e-01

-1.54e-01

-1.57e-01

-5.25e-01

-2.74e+01

-6.14e+01

-9.55e+01

-1.38e+02

-1.89e+02

-2.40e+02

-2.91e+02

-3.42e+02

-3.93e+02

-4.44e+02

-4.95e+02

-5.21e+02

-7.65e-02

-7.76e-02

-7.85e-02

-7.93e-02

-8.00e-02

-8.06e-02

-8.13e-02

-8.84e-02

-1.26e+00

-2.16e+01

-4.53e+01

-6.89e+01

-9.26e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

-2.59e+02

-2.94e+02

-3.30e+02

-3.65e+02

-4.01e+02

-4.19e+02

-2.03e-01

-2.07e-01

-2.10e-01

-2.13e-01

-2.15e-01

-2.17e-01

-2.19e-01

-2.21e-01

-2.22e-01

-2.24e-01

-2.27e-01

-2.38e-01

-7.90e+00

-4.20e+01

-7.60e+01

-1.11e+02

-1.61e+02

-2.12e+02

-2.63e+02

-3.14e+02

-3.65e+02

-4.16e+02

-4.42e+02

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-1.22e-02

-5.18e-04

-2.43e-06

-2.33e-09

-2.10e-11

-1.70e-11

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-6.62e-03

-6.64e-05

-6.35e-07

-6.31e-09

-1.95e-09

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.60e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.67e+00

-1.17e-02

-1.56e-03

-1.80e-05

-1.54e-08

-2.99e-11

-1.91e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.905e+02

1.725e+02

1.545e+02

1.365e+02

1.185e+02

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

Appendix B-12

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

1.397e+02

1.139e+02

8.814e+01

6.236e+01

4.389e+01

2.662e+01

9.358e+00

3.399e-02

3.426e-04

2.840e-06

3.401e-09

6.162e-11

5.758e-11

1.005e+02

8.253e+01

6.454e+01

5.068e+01

3.859e+01

2.651e+01

1.444e+01

2.517e+00

1.577e-02

7.857e-05

6.836e-07

7.379e-09

2.438e-09

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.359e+00

3.554e-02

9.211e-04

1.655e-05

1.946e-08

7.622e-11

6.240e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.680/0.164

1.690/0.219

1.360/0.329

1.310/0.442

1.900/0.124

1.880/0.155

dV/dt_f

|

[Model]

Model_type

Polarity

C_comp

|

icba_o

3-state

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-2.70e-02

-1.32e-02

-9.33e-03

-5.75e-03

-1.97e-03

1.945e-03

5.507e-03

-3.65e+02

-5.18e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.19e+00

-1.25e-02

-4.69e-03

-2.81e-03

-9.48e-04

9.285e-04

2.640e-03

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.60e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.68e+00

-2.90e-02

-1.63e-02

-1.10e-02

-6.76e-03

-2.32e-03

2.307e-03

6.599e-03

MOTOROLA

DSP56362 Advance Information

Appendix B-13

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

8.649e-03

1.136e-02

1.364e-02

1.547e-02

1.688e-02

1.299e-01

1.366e-01

1.404e-01

1.423e-01

1.433e-01

1.440e-01

1.445e-01

1.450e-01

1.454e-01

1.458e-01

1.461e-01

1.464e-01

1.469e-01

1.490e-01

1.501e+00

1.813e+01

3.540e+01

5.269e+01

7.541e+01

1.012e+02

1.270e+02

1.527e+02

1.785e+02

2.043e+02

2.301e+02

2.559e+02

2.688e+02

4.168e-03

5.504e-03

6.636e-03

7.551e-03

8.240e-03

6.458e-02

6.746e-02

6.916e-02

7.006e-02

7.059e-02

7.098e-02

7.128e-02

7.154e-02

7.176e-02

7.196e-02

7.223e-02

8.810e-02

2.589e+00

1.451e+01

2.658e+01

3.866e+01

5.076e+01

6.461e+01

8.261e+01

1.006e+02

1.186e+02

1.366e+02

1.546e+02

1.726e+02

1.906e+02

2.086e+02

2.176e+02

1.048e-02

1.393e-02

1.693e-02

1.950e-02

2.162e-02

2.331e-02

1.755e-01

1.847e-01

1.907e-01

1.940e-01

1.958e-01

1.970e-01

1.979e-01

1.986e-01

1.993e-01

1.999e-01

2.004e-01

2.009e-01

2.015e-01

2.030e-01

2.385e-01

9.563e+00

2.682e+01

4.409e+01

6.258e+01

8.836e+01

1.141e+02

1.399e+02

1.657e+02

1.915e+02

2.173e+02

2.302e+02

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.360e+00

4.275e-02

8.208e-03

5.635e-03

3.370e-03

1.118e-03

-1.09e-03

1.905e+02

1.725e+02

1.545e+02

1.365e+02

1.185e+02

1.005e+02

8.253e+01

6.454e+01

5.068e+01

3.859e+01

2.651e+01

1.444e+01

2.518e+00

2.012e-02

3.518e-03

2.053e-03

6.789e-04

-6.56e-04

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.362e+00

4.663e-02

1.070e-02

7.068e-03

4.233e-03

1.410e-03

-1.38e-03

Appendix B-14

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-3.12e-03

-4.96e-03

-6.60e-03

-8.04e-03

-9.26e-03

-1.03e-02

-1.25e-01

-1.31e-01

-1.36e-01

-1.40e-01

-1.42e-01

-1.44e-01

-1.46e-01

-1.48e-01

-1.49e-01

-1.50e-01

-1.52e-01

-1.53e-01

-1.54e-01

-1.57e-01

-5.25e-01

-2.74e+01

-6.14e+01

-9.55e+01

-1.38e+02

-1.89e+02

-2.40e+02

-2.91e+02

-3.42e+02

-3.93e+02

-4.44e+02

-4.95e+02

-5.21e+02

-1.86e-03

-2.93e-03

-3.87e-03

-4.66e-03

-5.30e-03

-6.55e-02

-6.93e-02

-7.19e-02

-7.38e-02

-7.53e-02

-7.65e-02

-7.76e-02

-7.85e-02

-7.93e-02

-8.00e-02

-8.06e-02

-8.13e-02

-8.84e-02

-1.26e+00

-2.16e+01

-4.53e+01

-6.89e+01

-9.26e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

-2.59e+02

-2.94e+02

-3.30e+02

-3.65e+02

-4.01e+02

-4.19e+02

-3.99e-03

-6.39e-03

-8.59e-03

-1.06e-02

-1.23e-02

-1.38e-02

-1.70e-01

-1.82e-01

-1.91e-01

-1.97e-01

-2.03e-01

-2.07e-01

-2.10e-01

-2.13e-01

-2.15e-01

-2.17e-01

-2.19e-01

-2.21e-01

-2.22e-01

-2.24e-01

-2.27e-01

-2.38e-01

-7.90e+00

-4.20e+01

-7.60e+01

-1.11e+02

-1.61e+02

-2.12e+02

-2.63e+02

-3.14e+02

-3.65e+02

-4.16e+02

-4.42e+02

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.83e+01

-4.43e+01

-1.02e+01

-1.22e-02

-5.18e-04

-2.43e-06

-2.33e-09

-2.10e-11

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-6.88e+01

-4.52e+01

-2.15e+01

-1.18e+00

-6.62e-03

-6.64e-05

-6.35e-07

-6.31e-09

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.60e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.67e+00

-1.17e-02

-1.56e-03

-1.80e-05

-1.54e-08

-2.99e-11

MOTOROLA

DSP56362 Advance Information

Appendix B-15

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

0.000e+00

|

-1.70e-11

-1.95e-09

-1.91e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.236e+01

4.389e+01

2.662e+01

9.358e+00

3.399e-02

3.426e-04

2.840e-06

3.401e-09

6.162e-11

5.758e-11

1.905e+02

1.725e+02

1.545e+02

1.365e+02

1.185e+02

1.005e+02

8.253e+01

6.454e+01

5.068e+01

3.859e+01

2.651e+01

1.444e+01

2.517e+00

1.577e-02

7.857e-05

6.836e-07

7.379e-09

2.438e-09

2.686e+02

2.428e+02

2.170e+02

1.912e+02

1.655e+02

1.397e+02

1.139e+02

8.814e+01

6.237e+01

4.389e+01

2.662e+01

9.359e+00

3.554e-02

9.211e-04

1.655e-05

1.946e-08

7.622e-11

6.240e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.680/0.164

1.690/0.219

1.360/0.329

1.310/0.442

1.900/0.124

1.880/0.155

dV/dt_f

|

[Model]

Model_type

Polarity

C_comp

|

icbc_o

3-state

Non-Inverting

5.00pF

|

[Voltage Range]

[Pulldown]

|voltage

|

3.3v

I(typ)

3v

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-3.65e+02

-5.18e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.25e+01

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.11e+02

-1.60e+02

-1.10e+02

Appendix B-16

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-7.83e+01

-4.42e+01

-1.02e+01

-2.51e-02

-1.30e-02

-9.33e-03

-5.75e-03

-1.97e-03

1.945e-03

5.507e-03

8.649e-03

1.136e-02

1.364e-02

1.547e-02

1.688e-02

9.632e-02

1.012e-01

1.039e-01

1.053e-01

1.060e-01

1.065e-01

1.069e-01

1.073e-01

1.076e-01

1.078e-01

1.081e-01

1.083e-01

1.086e-01

1.103e-01

1.437e+00

1.800e+01

3.519e+01

5.241e+01

7.505e+01

1.007e+02

1.264e+02

1.522e+02

1.779e+02

2.036e+02

2.293e+02

2.550e+02

2.678e+02

-6.88e+01

-4.51e+01

-2.15e+01

-1.18e+00

-1.16e-02

-4.67e-03

-2.81e-03

-9.48e-04

9.285e-04

2.640e-03

4.168e-03

5.504e-03

6.636e-03

7.551e-03

8.240e-03

4.783e-02

4.994e-02

5.118e-02

5.184e-02

5.223e-02

5.251e-02

5.274e-02

5.293e-02

5.309e-02

5.324e-02

5.344e-02

6.705e-02

2.529e+00

1.438e+01

2.638e+01

3.839e+01

5.041e+01

6.419e+01

8.210e+01

1.000e+02

1.179e+02

1.359e+02

1.538e+02

1.717e+02

1.896e+02

2.075e+02

2.165e+02

-7.58e+01

-4.17e+01

-7.67e+00

-2.65e-02

-1.58e-02

-1.10e-02

-6.76e-03

-2.32e-03

2.307e-03

6.599e-03

1.048e-02

1.393e-02

1.693e-02

1.950e-02

2.162e-02

2.331e-02

1.302e-01

1.369e-01

1.412e-01

1.436e-01

1.449e-01

1.458e-01

1.464e-01

1.470e-01

1.475e-01

1.479e-01

1.483e-01

1.487e-01

1.491e-01

1.503e-01

1.810e-01

9.452e+00

2.664e+01

4.384e+01

6.224e+01

8.794e+01

1.136e+02

1.394e+02

1.651e+02

1.908e+02

2.165e+02

2.293e+02

[Pullup]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

2.677e+02

2.420e+02

2.163e+02

1.906e+02

1.649e+02

1.392e+02

1.135e+02

8.778e+01

1.896e+02

1.716e+02

1.537e+02

1.358e+02

1.179e+02

9.996e+01

8.205e+01

6.413e+01

2.677e+02

2.420e+02

2.163e+02

1.906e+02

1.649e+02

1.392e+02

1.135e+02

8.778e+01

MOTOROLA

DSP56362 Advance Information

Appendix B-17

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

6.208e+01

4.368e+01

2.649e+01

9.302e+00

3.838e-02

8.115e-03

5.634e-03

3.370e-03

1.118e-03

-1.09e-03

-3.12e-03

-4.96e-03

-6.60e-03

-8.04e-03

-9.26e-03

-1.03e-02

-9.03e-02

-9.49e-02

-9.84e-02

-1.01e-01

-1.03e-01

-1.05e-01

-1.06e-01

-1.07e-01

-1.08e-01

-1.09e-01

-1.10e-01

-1.11e-01

-1.14e-01

-4.76e-01

-2.73e+01

-6.14e+01

-9.54e+01

-1.38e+02

-1.89e+02

-2.40e+02

-2.91e+02

-3.42e+02

-3.93e+02

-4.44e+02

-4.95e+02

-5.20e+02

5.035e+01

3.834e+01

2.633e+01

1.433e+01

2.477e+00

1.789e-02

3.503e-03

2.053e-03

6.789e-04

-6.56e-04

-1.86e-03

-2.93e-03

-3.87e-03

-4.66e-03

-5.30e-03

-4.75e-02

-5.02e-02

-5.21e-02

-5.34e-02

-5.45e-02

-5.54e-02

-5.62e-02

-5.68e-02

-5.74e-02

-5.79e-02

-5.84e-02

-5.89e-02

-6.49e-02

-1.23e+00

-2.16e+01

-4.52e+01

-6.89e+01

-9.25e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

-2.59e+02

-2.94e+02

-3.30e+02

-3.65e+02

-4.01e+02

-4.18e+02

6.208e+01

4.368e+01

2.649e+01

9.303e+00

4.183e-02

1.045e-02

7.064e-03

4.233e-03

1.410e-03

-1.38e-03

-3.99e-03

-6.39e-03

-8.59e-03

-1.06e-02

-1.23e-02

-1.41e-02

-1.23e-01

-1.31e-01

-1.38e-01

-1.43e-01

-1.47e-01

-1.50e-01

-1.52e-01

-1.54e-01

-1.56e-01

-1.57e-01

-1.59e-01

-1.60e-01

-1.61e-01

-1.62e-01

-1.64e-01

-1.73e-01

-7.82e+00

-4.19e+01

-7.59e+01

-1.11e+02

-1.61e+02

-2.12e+02

-2.63e+02

-3.14e+02

-3.65e+02

-4.16e+02

-4.41e+02

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-3.65e+02

-3.30e+02

-2.94e+02

-2.59e+02

-2.23e+02

-1.88e+02

-1.52e+02

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.11e+02

Appendix B-18

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-1.63e+02

-1.13e+02

-7.83e+01

-4.42e+01

-1.02e+01

-1.03e-02

-3.74e-04

-1.72e-06

-1.67e-09

-2.03e-11

-1.69e-11

-1.17e+02

-9.25e+01

-6.88e+01

-4.51e+01

-2.15e+01

-1.17e+00

-5.73e-03

-5.06e-05

-4.65e-07

-4.80e-09

-1.61e-09

-1.60e+02

-1.10e+02

-7.58e+01

-4.17e+01

-7.66e+00

-9.27e-03

-1.14e-03

-1.28e-05

-1.10e-08

-2.71e-11

-1.89e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

2.677e+02

2.420e+02

2.163e+02

1.906e+02

1.649e+02

1.392e+02

1.135e+02

8.778e+01

6.208e+01

4.368e+01

2.649e+01

9.300e+00

2.962e-02

2.501e-04

2.066e-06

2.487e-09

5.672e-11

5.334e-11

1.896e+02

1.716e+02

1.537e+02

1.358e+02

1.179e+02

9.996e+01

8.205e+01

6.413e+01

5.035e+01

3.834e+01

2.633e+01

1.433e+01

2.475e+00

1.354e-02

6.280e-05

5.128e-07

5.639e-09

1.992e-09

2.677e+02

2.420e+02

2.163e+02

1.906e+02

1.649e+02

1.392e+02

1.135e+02

8.778e+01

6.208e+01

4.368e+01

2.649e+01

9.301e+00

3.075e-02

6.708e-04

1.204e-05

1.417e-08

6.832e-11

5.783e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.570/0.200

1.590/0.304

1.210/0.411

1.170/0.673

1.810/0.149

1.800/0.205

dV/dt_f

|

[Model]

Model_type

Polarity

Vinl= 0.8000v

Vinh= 2.000v

C_comp

ipbw_i

Input

Non-Inverting

5.00pF

|

[Voltage Range]

3.3v

3v

3.6v

MOTOROLA

DSP56362 Advance Information

Appendix B-19

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

[GND_clamp]

|voltage

|

I(typ)

I(min)

-3.65e+02

I(max)

-5.17e+02

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.82e+01

-4.42e+01

-1.02e+01

-7.17e-03

-1.14e-04

-4.86e-07

-5.19e-10

-1.91e-11

-1.68e-11

-3.29e+02

-2.94e+02

-2.58e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.24e+01

-6.87e+01

-4.51e+01

-2.15e+01

-1.16e+00

-4.39e-03

-2.55e-05

-1.91e-07

-2.47e-09

-1.17e-09

-4.66e+02

-4.15e+02

-3.64e+02

-3.13e+02

-2.62e+02

-2.11e+02

-1.60e+02

-1.10e+02

-7.57e+01

-4.16e+01

-7.64e+00

-4.87e-03

-3.03e-04

-2.73e-06

-2.57e-09

-2.19e-11

-1.84e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

2.667e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

2.634e+01

9.237e+00

2.454e-02

8.741e-05

6.316e-07

8.479e-10

4.420e-11

4.215e-11

1.885e+02

1.707e+02

1.528e+02

1.350e+02

1.172e+02

9.935e+01

8.152e+01

6.369e+01

4.999e+01

3.806e+01

2.613e+01

1.421e+01

2.430e+00

1.104e-02

4.079e-05

2.484e-07

3.001e-09

1.346e-09

2.667e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

2.634e+01

9.237e+00

2.488e-02

2.050e-04

2.961e-06

3.721e-09

4.943e-11

4.543e-11

|

[Model]

Model_type

Polarity

ipbw_io

I/O

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

|

5.00pF

3v

5.00pF

[Voltage Range]

3.3v

3.6v

Appendix B-20

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

[Pulldown]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

|

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.82e+01

-4.42e+01

-1.02e+01

-3.69e-02

-2.52e-02

-1.83e-02

-1.11e-02

-3.77e-03

3.729e-03

1.076e-02

1.723e-02

2.311e-02

2.836e-02

3.292e-02

3.675e-02

3.979e-02

4.205e-02

4.347e-02

4.413e-02

4.445e-02

4.465e-02

4.479e-02

4.492e-02

4.502e-02

4.511e-02

4.519e-02

4.526e-02

4.536e-02

4.614e-02

1.344e+00

1.783e+01

3.495e+01

5.208e+01

7.463e+01

1.002e+02

1.259e+02

1.515e+02

1.771e+02

2.027e+02

2.283e+02

2.539e+02

2.667e+02

-3.65e+02 -5.17e+02

-3.29e+02

-2.94e+02

-2.58e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.24e+01

-6.87e+01

-4.51e+01

-2.15e+01

-1.17e+00

-1.67e-02

-9.77e-03

-5.89e-03

-1.98e-03

1.940e-03

5.578e-03

8.907e-03

1.191e-02

1.455e-02

1.680e-02

1.862e-02

1.997e-02

2.085e-02

2.136e-02

2.162e-02

2.176e-02

2.186e-02

2.194e-02

2.200e-02

2.206e-02

2.211e-02

2.219e-02

3.324e-02

2.452e+00

1.423e+01

2.615e+01

3.808e+01

5.001e+01

6.371e+01

8.154e+01

9.937e+01

1.172e+02

1.350e+02

1.529e+02

1.707e+02

1.885e+02

2.064e+02

2.153e+02

-4.66e+02

-4.15e+02

-3.64e+02

-3.13e+02

-2.62e+02

-2.11e+02

-1.60e+02

-1.10e+02

-7.57e+01

-4.17e+01

-7.66e+00

-3.79e-02

-2.81e-02

-2.04e-02

-1.24e-02

-4.20e-03

4.177e-03

1.216e-02

1.965e-02

2.663e-02

3.305e-02

3.887e-02

4.404e-02

4.850e-02

5.223e-02

5.518e-02

5.728e-02

5.843e-02

5.899e-02

5.931e-02

5.953e-02

5.971e-02

5.986e-02

5.999e-02

6.010e-02

6.021e-02

6.032e-02

6.065e-02

8.548e-02

9.298e+00

2.640e+01

4.352e+01

6.184e+01

8.745e+01

1.131e+02

1.387e+02

1.643e+02

1.899e+02

2.155e+02

2.283e+02

MOTOROLA

DSP56362 Advance Information

Appendix B-21

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

[Pullup]

|voltage

|

I(typ)

I(min)

1.885e+02

I(max)

2.667e+02

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

1.000e-01

3.000e-01

5.000e-01

7.000e-01

9.000e-01

1.100e+00

1.300e+00

1.500e+00

1.700e+00

1.900e+00

2.100e+00

2.300e+00

2.500e+00

2.700e+00

2.900e+00

3.100e+00

3.300e+00

3.500e+00

3.700e+00

3.900e+00

4.100e+00

4.300e+00

4.500e+00

4.700e+00

4.900e+00

5.100e+00

5.300e+00

5.500e+00

5.700e+00

5.900e+00

6.100e+00

6.300e+00

6.500e+00

6.600e+00

2.667e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

2.635e+01

9.243e+00

5.536e-02

2.847e-02

2.025e-02

1.208e-02

3.994e-03

-3.88e-03

-1.11e-02

-1.76e-02

-2.35e-02

-2.86e-02

-3.30e-02

-3.65e-02

-3.92e-02

-4.12e-02

-4.26e-02

-4.36e-02

-4.43e-02

-4.49e-02

-4.54e-02

-4.58e-02

-4.61e-02

-4.65e-02

-4.68e-02

-4.70e-02

-4.73e-02

-4.81e-02

-4.00e-01

-2.72e+01

-6.12e+01

-9.52e+01

-1.37e+02

-1.88e+02

-2.39e+02

-2.90e+02

-3.41e+02

-3.92e+02

-4.43e+02

-4.94e+02

-5.20e+02

1.707e+02

1.528e+02

1.350e+02

1.172e+02

9.935e+01

8.152e+01

6.369e+01

4.999e+01

3.806e+01

2.613e+01

1.421e+01

2.435e+00

2.689e-02

1.265e-02

7.503e-03

2.474e-03

-2.38e-03

-6.76e-03

-1.06e-02

-1.40e-02

-1.69e-02

-1.93e-02

-2.10e-02

-2.22e-02

-2.29e-02

-2.35e-02

-2.38e-02

-2.42e-02

-2.44e-02

-2.47e-02

-2.49e-02

-2.50e-02

-2.52e-02

-2.54e-02

-2.99e-02

-1.19e+00

-2.15e+01

-4.51e+01

-6.87e+01

-9.24e+01

-1.17e+02

-1.52e+02

-1.88e+02

-2.23e+02

-2.58e+02

-2.94e+02

-3.29e+02

-3.65e+02

-4.00e+02

-4.18e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

2.635e+01

9.245e+00

6.260e-02

3.437e-02

2.451e-02

1.467e-02

4.868e-03

-4.76e-03

-1.37e-02

-2.20e-02

-2.95e-02

-3.63e-02

-4.23e-02

-4.75e-02

-5.17e-02

-5.51e-02

-5.77e-02

-5.97e-02

-6.11e-02

-6.22e-02

-6.31e-02

-6.38e-02

-6.44e-02

-6.49e-02

-6.54e-02

-6.58e-02

-6.62e-02

-6.66e-02

-6.72e-02

-7.21e-02

-7.70e+00

-4.17e+01

-7.57e+01

-1.10e+02

-1.60e+02

-2.11e+02

-2.62e+02

-3.13e+02

-3.64e+02

-4.15e+02

-4.41e+02

Appendix B-22

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

|

[GND_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-5.20e+02

-4.69e+02

-4.18e+02

-3.67e+02

-3.16e+02

-2.65e+02

-2.14e+02

-1.63e+02

-1.13e+02

-7.82e+01

-4.42e+01

-1.02e+01

-7.17e-03

-1.14e-04

-4.86e-07

-5.19e-10

-1.91e-11

-1.68e-11

-3.65e+02 -5.17e+02

-3.29e+02

-2.94e+02

-2.58e+02

-2.23e+02

-1.88e+02

-1.52e+02

-1.17e+02

-9.24e+01

-6.87e+01

-4.51e+01

-2.15e+01

-1.16e+00

-4.39e-03

-2.55e-05

-1.91e-07

-2.47e-09

-1.17e-09

-4.66e+02

-4.15e+02

-3.64e+02

-3.13e+02

-2.62e+02

-2.11e+02

-1.60e+02

-1.10e+02

-7.57e+01

-4.16e+01

-7.64e+00

-4.87e-03

-3.03e-04

-2.73e-06

-2.57e-09

-2.19e-11

-1.84e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

2.667e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

2.634e+01

9.237e+00

2.454e-02

8.741e-05

6.316e-07

8.479e-10

4.420e-11

4.215e-11

1.885e+02

1.707e+02

1.528e+02

1.350e+02

1.172e+02

9.935e+01

8.152e+01

6.369e+01

4.999e+01

3.806e+01

2.613e+01

1.421e+01

2.430e+00

1.104e-02

4.079e-05

2.484e-07

3.001e-09

1.346e-09

2.667e+02

2.411e+02

2.155e+02

1.898e+02

1.642e+02

1.386e+02

1.130e+02

8.739e+01

6.178e+01

4.346e+01

2.634e+01

9.237e+00

2.488e-02

2.050e-04

2.961e-06

3.721e-09

4.943e-11

4.543e-11

[Ramp]

R_load = 50.00

|voltage

I(typ)

I(min)

I(max)

|

dV/dt_r

|

1.140/0.494

1.150/0.505

0.699/0.978

0.642/0.956

1.400/0.354

1.350/0.350

dV/dt_f

|

MOTOROLA

DSP56362 Advance Information

Appendix B-23

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IBIS Model

[Model]

iexlh_i

Model_type

Polarity

Input

Non-Inverting

Vinl= 0.8000v

Vinh= 2.000v

C_comp

|

[Voltage Range]

[GND_clamp]

|voltage

|

5.00pF

3v

5.00pF

3.3v

I(typ)

3.6v

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

-5.21e+02

-4.70e+02

-4.19e+02

-3.68e+02

-3.17e+02

-2.66e+02

-2.15e+02

-1.64e+02

-1.14e+02

-7.93e+01

-4.53e+01

-1.13e+01

-7.94e-03

-1.62e-06

-3.45e-10

-1.29e-11

-1.10e-11

-1.01e-11

-3.66e+02

-3.30e+02

-2.95e+02

-2.59e+02

-2.24e+02

-1.89e+02

-1.53e+02

-1.18e+02

-9.34e+01

-6.98e+01

-4.62e+01

-2.26e+01

-1.87e+00

-5.11e-03

-1.40e-05

-3.90e-08

-8.67e-10

-7.13e-10

-5.18e+02

-4.67e+02

-4.16e+02

-3.65e+02

-3.14e+02

-2.63e+02

-2.12e+02

-1.61e+02

-1.11e+02

-7.68e+01

-4.28e+01

-8.78e+00

-3.77e-03

-7.69e-07

-1.72e-10

-1.38e-11

-1.19e-11

-1.10e-11

[POWER_clamp]

|voltage

|

I(typ)

I(min)

I(max)

-3.30e+00

-3.10e+00

-2.90e+00

-2.70e+00

-2.50e+00

-2.30e+00

-2.10e+00

-1.90e+00

-1.70e+00

-1.50e+00

-1.30e+00

-1.10e+00

-9.00e-01

-7.00e-01

-5.00e-01

-3.00e-01

-1.00e-01

0.000e+00

|

2.653e+02

2.398e+02

2.143e+02

1.888e+02

1.633e+02

1.378e+02

1.123e+02

8.682e+01

6.133e+01

4.313e+01

2.614e+01

9.145e+00

1.797e-02

3.667e-06

7.730e-10

2.293e-11

2.096e-11

2.004e-11

1.870e+02

1.693e+02

1.516e+02

1.339e+02

1.162e+02

9.847e+01

8.076e+01

6.305e+01

4.947e+01

3.766e+01

2.585e+01

1.404e+01

2.364e+00

7.589e-03

2.072e-05

5.767e-08

1.163e-09

9.618e-10

2.653e+02

2.398e+02

2.143e+02

1.888e+02

1.633e+02

1.378e+02

1.123e+02

8.682e+01

6.133e+01

4.313e+01

2.614e+01

9.145e+00

1.797e-02

3.667e-06

7.748e-10

2.476e-11

2.278e-11

2.186e-11

[End]

Appendix B-24

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INDEX

DMA iii

A

DRAM

ac electrical characteristics 2-4

Address Trace mode iv, 2-44, 2-47

ALU iii

out of page

read access 2-41

wait states selection guide 2-33

write access 2-42

out of page and refresh timings

11 wait states 2-37

15 wait states 2-39

4 wait states 2-33

8 wait states 2-36

Page mode

applications v

arbitration bus timings 2-47

Arithmetic Logic Unit iii

B

benchmark test algorithm A-1, B-1

bootstrap ROM iv

read accesses 2-32

wait states selection guide 2-22

write accesses 2-31

Page mode timings

1 wait state 2-23

Boundary Scan (JTAG Port) timing diagram 2-

83

bus

address 1-2

data 1-2

2 wait states 2-24

3 wait states 2-27

4 wait states 2-29

refresh access 2-43

DRAM controller iv

DSP programming 4-8

DSP56300

multiplexed 1-2

non-multiplexed 1-2

bus acquisition timings 2-48

bus release timings 2-49, 2-50

C

case outline drawing 3-8

core features iii

clock

DSP56362

external 2-5

operation 2-6

clocks

features iii

specifications 2-1

internal 2-5

E

D

electrical design considerations 4-3

Enhanced Serial Audio Interface iv

ESAI iv, 1-2

Data Arithmetic Logic Unit iii

data memory expansion iv

DAX iv, 1-2, 1-19

ESSI

receiver timing 2-75, 2-76

dc electrical characteristics 2-3

Debug support iv

timings 2-71

transmitter timing 2-74

EXTAL jitter 4-6

description, general i

design considerations

electrical 4-3

external bus control 1-7, 1-8

external bus synchronous timings (SRAM

access) 2-44

PLL 4-5, 4-6

power consumption 4-4

thermal 4-1

external clock operation 2-5

external interrupt timing (negative edge-

triggered) 2-15

Digital Audio Transmitter iv, 1-19

Direct Memory Access iii

MOTOROLA

DSP56362 Advance Information

For More Information On This Product,

1

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Index

external level-sensitive fast interrupt timing 2-15

external memory access (DMA Source) timing 2-

17

M

maximum ratings 2-1, 2-2

mechanical drawings 3-8

Memory Expansion Port iv

Mfax system 3-8

External Memory Expansion Port 2-18

F

mode control 1-9

functional groups 1-2

Mode select timing 2-9

multiplexed bus 1-2

multiplexed bus timings

read 2-57

functional signal groups 1-1

G

general description i

General Purpose Input/Output iv

GPIO iv, 1-2, 1-25

GPIO timing 2-80

Ground 1-4

write 2-58

N

non-multiplexed bus 1-2

non-multiplexed bus timings

read 2-55

PLL 1-4

write 2-56

H

O

HDI08 iv, 1-2, 1-11, 1-12, 1-14, 1-15

DSP programming 4-8

DSP synchronization 4-8

Host synchronization 4-6

HDI08 timing 2-52

off-chip memory iv

OnCE

module timing 2-85

OnCE module iv, 1-25

Debug request 2-85

on-chip DRAM controller iv

On-Chip Emulation module iv

on-chip memory iv

Host Interface iv, 1-2, 1-11, 1-12, 1-14, 1-15

Host Interface timing 2-52

host port

configuration 1-11

Host Port considerations 4-6

Host programming 4-6

Host Request

operating mode select timing 2-16

ordering drawings 3-8

ordering information 5-1

Double 1-2

Single 1-2

P

I

package

144-pin TQFP 3-1

instruction cache iv

TQFP description 3-2, 3-3

PCU iii

internal clocks 2-5

interrupt and mode control 1-9

interrupt control 1-9

Phase Lock Loop iii, 2-8

PLL iii, 2-8

interrupt timing 2-9

Characteristics 2-8

external level-sensitive fast 2-15

external negative edge-triggered 2-15

synchronous from Wait state 2-16

performance issues 4-5

PLL design considerations 4-5, 4-6

PLL performance issues 4-6

Port A 1-2

J

Port B 1-2, 1-12, 1-13, 1-14, 1-15

Port C 1-2, 1-19

Jitter 4-6

JTAG 1-25

Port D 1-2, 1-19

JTAG Port iv

power consumption benchmark test A-1, B-1

power consumption design considerations 4-4

power management v

Program Control Unit iii

reset timing diagram 2-84

timing 2-82, 2-83

2

DSP56362 Advance Information

For More Information On This Product,

MOTOROLA

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Index

program memory expansion iv

program RAM iv

Digital Audio Transmitter (DAX) 2-77

Enhanced Serial Audio Interface (ESAI) 2-

73

R

General Purpose I/O (GPIO) Timing 2-71

OnCE™ (On Chip Emulator) Timing 2-71

Serial Host Interface (SHI) SPI Protocol

Timing 2-60

recovery from Stop state using IRQA 2-16, 2-17

RESET 1-10

Reset timing 2-9, 2-14

synchronous 2-14

Serial Host Interface (SHI) Timing 2-60

timing

ROM, bootstrap iv

interrupt 2-9

mode select 2-9

Reset 2-9

S

Serial Host Interface iv, 1-16

SHI iv, 1-2, 1-16

signal groupings 1-1

signals 1-1

Stop 2-9

TQFP 3-1

pin list by number 3-3

pin-out drawing (top) 3-2

TQFP package drawing 3-8

functional grouping 1-2

SRAM 2-45

Access 2-44

W

read access 2-21

Wait mode v

read and write accesses 2-18

support iv

X

write access 2-21

Stop mode v

X data RAM iv

Stop state

Y

recovery from 2-16, 2-17

Stop timing 2-9

Y data RAM iv

supply voltage 2-2

Switch mode iv

Synchronization 4-6

synchronous bus timings

SRAM

2 wait states 2-46

SRAM 1 wait state (BCR controlled) 2-45

synchronous interrupt from Wait state timing 2-

16

synchronous Reset timing 2-14

T

TAP iv

target applications v

Test Access Port iv

Test Access Port timing diagram 2-84

Test Clock (TCLK) input timing diagram 2-83

thermal characteristics 2-2

thermal design considerations 4-1

Timer iv, 1-2, 1-25

event input restrictions 2-78

interrupt generation 2-79

timing 2-78

Timing

MOTOROLA

DSP56362 Advance Information

For More Information On This Product,

3

Go to: www.freescale.com


型号：	DSP56300AD
厂家：	MOTOROLA
描述：	24-Bit Audio Digital Signal Processor 24位音频数字信号处理器数字信号处理器
文件：	总168页 (文件大小：2933K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DSP56300AD [MOTOROLA]

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