74LS174 [MOTOROLA]
HEX D FLIP-FLOP; 六路D触发器
| 型号： | 74LS174 |
| 厂家： | 
MOTOROLA |
| 描述： | HEX D FLIP-FLOP |
| 文件： | 总3页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS174
HEX D FLIP-FLOP
The LSTTL/MSI SN54/74LS174 is a high speed Hex D Flip-Flop. The
device is used primarily as a 6-bit edge-triggered storage register. The
information on the D inputs is transferred to storage during the LOW to HIGH
clock transition. The device has a Master Reset to simultaneously clear all
flip-flops. The LS174 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all Motorola TTL families.
HEX D FLIP-FLOP
LOW POWER SCHOTTKY
• Edge-Triggered D-Type Inputs
• Buffered-Positive Edge-Triggered Clock
• Asynchronous Common Reset
• Input Clamp Diodes Limit High Speed Termination Effects
J SUFFIX
CERAMIC
CONNECTION DIAGRAM DIP (TOP VIEW)
CASE 620-09
V
Q
D
D
Q
D
Q
3
CP
9
CC
5
5
4
4
3
16
16
15
14
13
12
11
10
1
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
N SUFFIX
PLASTIC
CASE 648-08
16
1
2
3
4
5
6
8
7
1
MR
Q
D
D
Q
D
Q
2
GND
0
0
1
1
2
D SUFFIX
SOIC
CASE 751B-03
PIN NAMES
LOADING (Note a)
16
HIGH
LOW
1
D –D
0
Data Inputs
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5
CP
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
ORDERING INFORMATION
MR
Q –Q
0
5 (2.5) U.L.
5
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC SYMBOL
LOGIC DIAGRAM
3
4
6
11 13 14
MR CP
D
D
D
D
D
D
0
5
4
3
2
1
1
9
14
13
11
6
4
3
D
D
D
D
D
D
0
1
1
2
2
3
3
4
4
5
5
9
1
CP
MR
Q
Q
Q
Q
Q
Q
0
D
Q
D
D
Q
D
D
Q
D
D
Q
D
D
Q
D
D
Q
D
CP
CP
CP
CP
CP
CP
C
C
C
C
C
C
2
5
7 10 12 15
15
5
12
10
7
5
Q
1
2
V
= PIN 16
Q
Q
Q
Q
Q
CC
GND = PIN 8
4
0
3
2
V
= PIN 16
CC
GND = PIN 8
= PIN NUMBERS
FAST AND LS TTL DATA
5-1
SN54/74LS174
FUNCTIONAL DESCRIPTION
The LS174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and Master
Reset (MR) are common to all flip-flops.
Each D input’s state is transferred to the corresponding flip-
flop’s output following the LOW to HIGH Clock (CP) transition.
A LOW input to the Master Reset (MR) will force all outputs
LOW independent of Clock or Data inputs. The LS174 is
useful for applications where the true output only is required
and the Clock and Master Reset are common to all storage
elements.
TRUTH TABLE
Inputs (t = n, MR = H)
Outputs (t = n+1) Note 1
D
Q
H
L
H
L
Note 1: t = n + 1 indicates conditions after next clock.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
OH
= MAX, V = V
IN
CC
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
CC
MIN,
= V or V
IL IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
V
Output LOW Voltage
Input HIGH Current
OL
per Truth Table
OL
20
0.1
µA
mA
mA
mA
mA
V
V
V
V
V
= MAX, V = 2.7 V
IN
CC
CC
CC
CC
CC
I
IH
= MAX, V = 7.0 V
IN
I
I
I
Input LOW Current
–0.4
–100
26
= MAX, V = 0.4 V
IN
IL
Short Circuit Current (Note 1)
Power Supply Current
–20
= MAX
= MAX
OS
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-2
SN54/74LS174
AC CHARACTERISTICS (T = 25°C)
A
Limits
Symbol
Parameter
Unit
MHz
ns
Test Conditions
Min
Typ
40
Max
f
t
Maximum Input Clock Frequency
Propagation Delay, MR to Output
30
MAX
23
35
V = 5.0 V
CC
= 15 pF
PHL
C
L
t
t
20
21
30
30
PLH
PHL
Propagation Delay, Clock to Output
ns
AC SETUP REQUIREMENTS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Clock or MR Pulse Width
Data Setup Time
Unit
ns
Test Conditions
Min
20
Max
t
t
t
t
W
20
ns
s
V
CC
= 5.0 V
Data Hold Time
5.0
25
ns
h
Recovery Time
ns
rec
AC WAVEFORMS
1/f
max
t
w
1.3 V
s(H)
1.3 V
CP
t
W
t
t
s(L)
h(H)
1.3 V
1.3 V
MR
t
t
h(L)
1.3 V
t
rec
1.3 V
1.3 V
1.3 V
D
Q
*
t
t
PLH
PHL
1.3 V
CP
Q
t
1.3 V
PHL
1.3 V
1.3 V
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
DEFINITIONS OF TERMS
SETUP TIME (t ) — is defined as the minimum time required
s
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
RECOVERY TIME (t ) — is defined as the minimum time
rec
HOLD TIME (t ) — is defined as the minimum time following
h
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
required between the end of the reset pulse and the clock
transitionfromLOWtoHIGHinordertorecognizeandtransfer
HIGH Data to the Q outputs.
FAST AND LS TTL DATA
5-3
相关型号：
74LS174B
D Flip-Flop, LS Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, TTL, PDIP16, DIP-16
NXP
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