2N5064RLRA [MOTOROLA]

0.8A, 200V, SCR, TO-92, PLASTIC, TO-226AA, 3 PIN;
2N5064RLRA
型号: 2N5064RLRA
厂家: MOTOROLA    MOTOROLA
描述:

0.8A, 200V, SCR, TO-92, PLASTIC, TO-226AA, 3 PIN

栅 栅极
文件: 总7页 (文件大小:81K)
中文:  中文翻译
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Preferred Device  
Reverse Blocking Thyristors  
Annular PNPN devices designed for high volume consumer  
applications such as relay and lamp drivers, small motor controls, gate  
drivers for larger thyristors, and sensing and detection circuits.  
Supplied in an inexpensive plastic TO-226AA (TO-92) package  
which is readily adaptable for use in automatic insertion equipment.  
http://onsemi.com  
SCRs  
Sensitive Gate Trigger Current — 200 µA Maximum  
0.8 AMPERES RMS  
30 thru 200 VOLTS  
Low Reverse and Forward Blocking Current — 50 µA Maximum,  
T
= 110°C  
C
Low Holding Current — 5 mA Maximum  
Passivated Surface for Reliability and Uniformity  
Device Marking: Device Type, e.g., 2N5060, Date Code  
G
A
K
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Rating  
Symbol  
Value  
Unit  
(1)  
Peak Repetitive Off–State Voltage  
V
Volts  
DRM,  
(T  
J
=
40 to 110°C, Sine Wave,  
V
RRM  
50 to 60 Hz, Gate Open)  
2N5060  
2N5061  
2N5062  
2N5064  
30  
60  
100  
200  
On-State Current RMS  
(180° Conduction Angles; T = 80°C)  
I
0.8  
Amp  
Amp  
T(RMS)  
1
2
C
3
*Average On-State Current  
(180° Conduction Angles)  
I
T(AV)  
TO–92 (TO–226AA)  
CASE 029  
(T = 67°C)  
(T = 102°C)  
C
0.51  
0.255  
C
STYLE 10  
*Peak Non-repetitive Surge Current,  
I
10  
Amps  
TSM  
T
= 25°C  
A
PIN ASSIGNMENT  
Cathode  
(1/2 cycle, Sine Wave, 60 Hz)  
Circuit Fusing Considerations (t = 8.3 ms)  
*Forward Peak Gate Power  
1
2
3
2
2
I t  
0.4  
0.1  
A s  
Gate  
P
Watt  
Watt  
Amp  
Volts  
°C  
GM  
Anode  
(Pulse Width  
1.0 µsec; T = 25°C)  
A
*Forward Average Gate Power  
(T = 25°C, t = 8.3 ms)  
A
P
0.01  
1.0  
G(AV)  
ORDERING INFORMATION  
*Forward Peak Gate Current  
I
GM  
Seedetailedorderingandshippinginformationinthepackage  
dimensions section on page 264 of this data sheet.  
(Pulse Width  
1.0 µsec; T = 25°C)  
A
*Reverse Peak Gate Voltage  
V
5.0  
RGM  
Preferred devices are recommended choices for future use  
and best overall value.  
(Pulse Width  
1.0 µsec; T = 25°C)  
A
*Operating Junction Temperature Range  
T
J
–40 to  
+110  
*Storage Temperature Range  
T
stg  
–40 to  
+150  
°C  
*Indicates JEDEC Registered Data.  
(1) V  
DRM  
and V for all types can be applied on a continuous basis. Ratings  
RRM  
apply for zero or negative gate voltage; however, positive gate voltage shall  
not be applied concurrent with negative potential on the anode. Blocking  
voltages shall not be tested with a constant current source such that the  
voltage ratings of the devices are exceeded.  
Semiconductor Components Industries, LLC, 2000  
258  
Publication Order Number:  
May, 2000 – Rev. 4  
2N5060/D  
2N5060 Series  
THERMAL CHARACTERISTICS  
Characteristic  
(1)  
Symbol  
Max  
75  
Unit  
°C/W  
°C/W  
°C  
*Thermal Resistance, Junction to Case  
R
R
θJC  
Thermal Resistance, Junction to Ambient  
*Lead Solder Temperature  
200  
θJA  
+230*  
(Lead Length  
1/16from case, 10 s Max)  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
C
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
(2)  
*Peak Repetitive Forward or Reverse Blocking Current  
(V = Rated V or V  
I
, I  
DRM RRM  
)
T
C
T
C
= 25°C  
= 110°C  
10  
50  
µA  
µA  
AK DRM  
RRM  
ON CHARACTERISTICS  
(3)  
*Peak Forward On–State Voltage  
V
TM  
1.7  
Volts  
(I = 1.2 A peak @ T = 25°C)  
TM  
A
(4)  
(4)  
Gate Trigger Current (Continuous dc)  
I
µA  
GT  
*(V  
AK  
= 7 Vdc, R = 100 Ohms)  
T
T
= 25°C  
= –40°C  
200  
350  
L
C
C
Gate Trigger Voltage (Continuous dc)  
*(V = 7 Vdc, R = 100 Ohms)  
T
C
T
C
= 25°C  
= –40°C  
V
0.8  
1.2  
Volts  
Volts  
mA  
GT  
AK  
*Gate Non–Trigger Voltage  
(V = Rated V , R = 100 Ohms)  
L
V
GD  
T
= 110°C  
0.1  
AK  
DRM  
L
C
(4)  
Holding Current  
T
C
T
C
= 25°C  
= –40°C  
I
H
5.0  
10  
*(V = 7 Vdc, initiating current = 20 mA)  
AK  
Turn-On Time  
Delay Time  
Rise Time  
µs  
t
t
3.0  
0.2  
d
r
(I  
GT  
= 1 mA, V = Rated V  
,
D
DRM  
Forward Current = 1 A, di/dt = 6 A/µs  
Turn-Off Time  
(Forward Current = 1 A pulse,  
Pulse Width = 50 µs,  
t
µs  
q
0.1% Duty Cycle, di/dt = 6 A/µs,  
dv/dt = 20 V/µs, I  
= 1 mA)  
2N5060, 2N5061  
2N5062, 2N5064  
10  
30  
GT  
DYNAMIC CHARACTERISTICS  
Critical Rate of Rise of Off–State Voltage  
dv/dt  
30  
V/µs  
(Rated V  
, Exponential)  
DRM  
*Indicates JEDEC Registered Data.  
(1) This measurement is made with the case mounted “flat side down” on a heat sink and held in position by means of a metal clamp over the  
curved surface.  
(2) R  
= 1000 is included in measurement.  
GK  
(3) Forward current applied for 1 ms maximum duration, duty cycle  
(4) R current is not included in measurement.  
1%.  
GK  
http://onsemi.com  
259  
2N5060 Series  
Voltage Current Characteristic of SCR  
+ Current  
Anode +  
V
TM  
Symbol  
Parameter  
V
Peak Repetitive Off State Forward Voltage  
Peak Forward Blocking Current  
Peak Repetitive Off State Reverse Voltage  
Peak Reverse Blocking Current  
Peak on State Voltage  
DRM  
DRM  
on state  
I
I
H
I
at V  
RRM  
RRM  
V
RRM  
I
RRM  
V
TM  
+ Voltage  
at V  
DRM DRM  
I
H
Holding Current  
I
Reverse Blocking Region  
(off state)  
Forward Blocking Region  
(off state)  
Reverse Avalanche Region  
Anode –  
CURRENT DERATING  
130  
130  
110  
90  
a
α = CONDUCTION ANGLE  
α
α = CONDUCTION ANGLE  
120  
110  
100  
90  
CASE MEASUREMENT  
POINT – CENTER OF  
FLAT PORTION  
TYPICAL PRINTED  
CIRCUIT BOARD  
MOUNTING  
dc  
70  
80  
dc  
α = 30°  
180°  
120°  
60°  
90°  
70  
50  
30  
60  
50  
α = 30°  
60° 90° 120°  
180°  
0
0.1  
0.2  
0.3  
0.4  
0.5  
0
0.1  
0.2  
0.3  
0.4  
I
, AVERAGE ON-STATE CURRENT (AMP)  
I
, AVERAGE ON-STATE CURRENT (AMP)  
T(AV)  
T(AV)  
Figure 1. Maximum Case Temperature  
Figure 2. Maximum Ambient Temperature  
http://onsemi.com  
260  
2N5060 Series  
CURRENT DERATING  
10  
7.0  
5.0  
5.0  
3.0  
2.0  
T = 110°C  
J
25°C  
3.0  
2.0  
1.0  
0.7  
0.5  
1.0  
1.0  
2.0 3.0  
5.0 7.0 10  
20 30  
50 70 100  
0.3  
0.2  
NUMBER OF CYCLES  
Figure 4. Maximum Non–Repetitive Surge Current  
0.8  
0.6  
0.4  
180°  
120°  
0.1  
0.07  
0.05  
a
90°  
60°  
α = CONDUCTION ANGLE  
α = 30°  
0.03  
0.02  
dc  
0.2  
0
0.01  
0
0.5  
1.0  
1.5  
2.0  
2.5  
0
0.1  
0.2  
0.3  
0.4  
0.5  
v , INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)  
T
I , AVERAGE ON-STATE CURRENT (AMP)  
T(AV)  
Figure 3. Typical Forward Voltage  
Figure 5. Power Dissipation  
1.0  
0.5  
0.2  
0.1  
0.05  
0.02  
0.01  
0.002  
0.005  
0.01  
0.02  
0.05  
0.1  
0.2  
0.5  
1.0  
2.0  
5.0  
10  
20  
t, TIME (SECONDS)  
Figure 6. Thermal Response  
http://onsemi.com  
261  
2N5060 Series  
TYPICAL CHARACTERISTICS  
0.8  
0.7  
0.6  
0.5  
200  
V
= 7.0 V  
AK  
R = 100  
V
= 7.0 V  
AK  
100  
50  
L
R = 100  
L
R
GK  
= 1.0 k  
2N5062-64  
20  
10  
5.0  
2N5060-61  
2.0  
1.0  
0.5  
0.4  
0.3  
0.2  
75  
–50  
–25  
0
25  
50  
75  
100 110  
–75  
–50  
–25  
0
25  
50  
75  
100 110  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 7. Typical Gate Trigger Voltage  
Figure 8. Typical Gate Trigger Current  
4.0  
3.0  
V
= 7.0 V  
AK  
R = 100  
L
R
GK  
= 1.0 k  
2.0  
2N5060,61  
1.0  
0.8  
2N5062-64  
0.6  
0.4  
–75  
–50  
–25  
0
25  
50  
75  
100 110  
T , JUNCTION TEMPERATURE (°C)  
J
Figure 9. Typical Holding Current  
http://onsemi.com  
262  
2N5060 Series  
TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL  
H2A  
H2A  
H2B  
H2B  
H
W2  
H4  
H5  
T1  
L1  
H1  
W1  
W
L
T
T2  
F1  
F2  
D
P2  
P1  
P2  
P
Figure 10. Device Positioning on Tape  
Specification  
Millimeter  
Inches  
Symbol  
D
Item  
Min  
Max  
Min  
Max  
0.1496  
0.015  
0.0945  
.059  
0.1653  
3.8  
4.2  
Tape Feedhole Diameter  
D2  
F1, F2  
H
0.020  
0.110  
.156  
0.38  
2.4  
1.5  
8.5  
0
0.51  
2.8  
Component Lead Thickness Dimension  
Component Lead Pitch  
4.0  
Bottom of Component to Seating Plane  
Feedhole Location  
H1  
H2A  
H2B  
H4  
H5  
L
0.3346  
0
0.3741  
0.039  
0.051  
0.768  
0.649  
0.433  
9.5  
1.0  
Deflection Left or Right  
0
0
1.0  
Deflection Front or Rear  
0.7086  
0.610  
0.3346  
0.09842  
0.4921  
0.2342  
0.1397  
0.06  
18  
19.5  
16.5  
11  
Feedhole to Bottom of Component  
Feedhole to Seating Plane  
Defective Unit Clipped Dimension  
Lead Wire Enclosure  
15.5  
8.5  
2.5  
12.5  
5.95  
3.55  
0.15  
L1  
P
0.5079  
0.2658  
0.1556  
0.08  
12.9  
6.75  
3.95  
0.20  
1.44  
0.65  
19  
Feedhole Pitch  
P1  
Feedhole Center to Center Lead  
First Lead Spacing Dimension  
Adhesive Tape Thickness  
Overall Taped Package Thickness  
Carrier Strip Thickness  
P2  
T
T1  
0.0567  
0.027  
0.7481  
0.2841  
0.01968  
T2  
0.014  
0.6889  
0.2165  
.0059  
0.35  
17.5  
5.5  
.15  
W
Carrier Strip Width  
W1  
W2  
6.3  
Adhesive Tape Width  
0.5  
Adhesive Tape Position  
NOTES:  
1. Maximum alignment deviation between leads not to be greater than 0.2 mm.  
2. Defective components shall be clipped from the carrier tape such that the remaining protrusion (L) does not exceed a maximum of 11 mm.  
3. Component lead to tape adhesion must meet the pull test requirements.  
4. Maximum non–cumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches.  
5. Holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive.  
6. No more than 1 consecutive missing component is permitted.  
7. A tape trailer and leader, having at least three feed holes is required before the first and after the last component.  
8. Splices will not interfere with the sprocket feed holes.  
http://onsemi.com  
263  
2N5060 Series  
ORDERING & SHIPPING INFORMATION: 2N5060 Series packaging options, Device Suffix  
Europe  
Equivalent  
U.S.  
Shipping  
Description of TO92 Tape Orientation  
2N5060,61,62,64  
Bulk in Box (5K/Box)  
N/A, Bulk  
2N5060,61,62,64RLRA  
2N5060,64RLRM  
Radial Tape and Reel (2K/Reel)  
Radial Tape and Fan Fold Box (2K/Box)  
Round side of TO92 and adhesive tape visible  
Flat side of TO92 and adhesive tape visible  
2N5060RL1  
http://onsemi.com  
264  

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