V62C1802048L-150V [MOSEL]
Ultra Low Power 256K x 8 CMOS SRAM; 超低功耗256K ×8 CMOS SRAM
| 型号： | V62C1802048L-150V |
| 厂家： | 
MOSEL VITELIC, CORP |
| 描述： | Ultra Low Power 256K x 8 CMOS SRAM |
| 文件： | 总9页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
V62C1802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Low-power consumption
Functional Description
The V62C1802048L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1 , an active HIGH CE2, an act-
- Active: 25mA at 70ns
- Stand-by: 10 mA (CMOS input/output)
2 mA CMOS input/output, L version
, and Tri-state I/O’s. This device has an auto-
ive LOW OE
matic power-down mode feature when deselected.
• Single + 1.8 to 2.2V Power Supply
• Equal access and cycle time
• 70/85/100/150 ns access time
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1
) LOW, and Chip En-
) with Write Enable (WE
able 2 (CE2) HIGH. Reading from the device is performed
by taking Chip Enable 1 (CE1
) with Output Enable
(OE ) LOW while Write Enable (WE ) and Chip Enable 2
(CE2) is HIGH. The I/O pins are placed in a high-imped-
ance state when the device is deselected: the outputs are
disabled during a write cycle.
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
The V62C1802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1802048L is available in
a 32-pin 8 x 13.4 & 8 x 20 mm TSOP1 / STSOP packages.
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32-TSOP1 / STSOP
Logic Block Diagram
32-Pin TSOP1 / STSOP
A
11
OE
10
CE1
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
9
A
A
8
3
A
13
8
4
INPUT BUFFER
WE
CE
15
7
5
A0
2
6
6
A
A
1
2
A
5
7
Vcc
A17
4
8
I/O8
I/O1
A
A
3
4
9
A
16
14
12
3
10
11
12
13
14
15
16
A
2
A
A
5
6
Cell Array
A
1
A
7
6
5
4
A0
A
A
1
A
2
A3
A
A
7
8
A
A
A9
OE
COLUMN DECODER
WE
CE1
CE2
CONTROL
CIRCUIT
A
10
A
11
A12
A13
A14
A15
A16
A17
1
REV. 1.2 May 2001 V62C1802048L(L)
V62C1802048L(L)
Absolute Maximum Ratings *
Parameter
Symbol Minimum Maximum
Unit
Voltage on Any Pin Relative to Gnd
Power Dissipation
Vt
-0.5
4.6
1.0
V
P
-
W
T
0
Storage Temperature (Plastic)
Temperature Under Bias
Tstg
-55
-40
+150
+85
C
0
Tbias
C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table
CE1
CE2
WE
OE
X
Data
High-Z
High-Z
Data Out
High-Z
Data In
Mode
H
X
L
L
L
X
L
X
X
H
H
L
Standby
X
Standby
H
H
H
L
Active, Read
H
Active, Output Disable
Active, Write
X
* Key: X = Don’t Care, L = Low, H = High
Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**)
Parameter
Symbol
Min
1.8
Typ
Max
2.2
Unit
V
2.0
0.0
-
V
V
V
V
CC
Supply Voltage
Gnd
0.0
0.0
V
1.6
V
+ 0.2
CC
IH
Input Voltage
V
-0.5*
-
0.4
IL
* VIL min = -1.0V for pulse width less than tRC/2.
** For Industrial Temperature.
2
REV. 1.2 May 2001 V62C1802048L(L)
V62C1802048L(L)
DC Operating Characteristics (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
-70
-85
-100
-150
Parameter
Sym Test Conditions
Unit
Min Max Min Max Min Max Min Max
Vcc = Max,
Vin = Gnd to Vcc
-
-
-
1
1
3
-
-
-
1
1
3
-
-
-
1
1
3
-
-
-
1
1
3
mA
Input Leakage Current
II I
LI
CE1 = VIH or CE2 = VIL
Vcc= Max, VOUT = Gnd to Vcc
mA
Output Leakage
Current
IILOI
CE1 = VIL , CE2 = VIH
VIN=VIHorVIL,IOUT=0mA
mA
Operating Power
Supply Current
ICC
CE1 = VIL , CE2 = VIH
IOUT = 0mA,
Min Cycle, 100% Duty
-
-
20
3
-
-
20
3
-
-
15
3
-
-
15
3
mA
mA
ICC1
Average Operating
Current
CE1 = 0.2V ,
CE2 =Vcc - 0.2V
ICC2
I
OUT = 0mA,
Cycle Time=1ms, 100% Duty
CE1 = VIH or CE2 = VIL
-
-
0.3
10
-
-
0.3
10
-
-
0.3
10
-
-
0.3
10
mA
Standby Power Supply ISB
Current (TTL Level)
CE1 > Vcc - 0.2V or
CE2 < 0.2V, f = 0
VIN < 0.2V or
mA
Standby Power Supply ISB1
Current (CMOS Level)
-
-
2
0.4
-
-
-
2
0.4
-
-
-
2
0.4
-
-
-
2
0.4
-
mA
V
V
IN > Vcc- 0.2V
L
IOL = 2 mA
IOH = -1 mA
Output Low Voltage
Output High Voltage
VOL
VOH
1.6
1.6
1.6
1.6
V
Capacitance (f = 1MHz, TA = 250C)
Parameter*
Symbol
Cin
Test Condition
Max
7
Unit
pF
Input Capacitance
V
= 0V
in
I/O Capacitance
CI/O
V
= V = 0V
8
pF
in
out
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing
Reference Level
0.4V to 1.6V
5ns
TTL
CL
*
50% of input level
(VIL+VIH)/2
Output Load Condition
70ns/85 ns CL = 30pf + 1TTL Load
Load 100ns/150 ns CL = 100pf + 1TTL Load
Figure A.
* Including Scope and Jig Capacitance
3
REV. 1.2 May 2001 V62C1802048L(L)
V62C1802048L(L)
Read Cycle (3,9) (Vcc = 1.8 to2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Note
Unit
Parameter
Symbol
-70
-85
-100
-150
Min Max Min Max Min Max Min Max
tRC
tAA
tACE
tOE
70
-
-
85
-
-
100
-
100
100
50
-
150
-
150
150
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
70
70
40
-
85
85
40
-
-
-
-
-
Address Access Time
-
-
Chip Enable Access Time
Output Enable Access Time
OutputHold fromAddress Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
OutputDisable toOutput in High-Z
Power-Up Time
-
-
-
-
tOH
10
10
-
10
10
-
10
10
-
10
10
-
tCLZ
tCHZ
tOLZ
tOHZ
tPU
-
-
-
-
4,5
4,5
4,5
4,5
5
30
-
35
-
40
-
50
-
5
-
5
-
5
-
5
-
25
-
30
-
35
-
40
-
0
-
0
-
0
-
0
-
tPD
70
85
100
150
5
Power-Down Time
Write Cycle (3,11) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Note
-70
-85
-100
-150
Unit
Parameter
Symbol
Min Max Min Max Min Max Min Max
tWC
tCW
tAW
tAS
70
60
60
0
-
-
85
70
70
0
-
-
100
80
80
0
-
-
150
120
120
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
-
-
-
-
-
-
-
-
tWP
tWR
tDW
tDH
tWZ
tOW
50
0
-
60
0
-
70
0
-
100
0
-
Write Pulse Width
-
-
-
-
Write Recovering Time
Data Valid to Write End
Data Hold Time
30
0
-
35
0
-
40
0
-
60
0
-
-
-
-
-
-
30
-
-
35
-
-
40
-
-
50
-
4,5
4,5
Write Enable to Output in High-Z
Output Active from Write End
5
5
5
5
4
REV. 1.2 May 2001 V62C1802048L(L)
V62C1802048L(L)
Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled)
tRC
Address
tAA
tOH
DOUT
Data Valid
Timing Waveform of Read Cycle 2 (5,6,8,9) (CE1 Controlled)
tRC
CE1
tOE
OE
tOHZ
tCHZ
tOLZ
tACE
DOUT
Data Valid
tPD
tCLZ
tPU
ICC
ISB
Supply Current
50%
50%
Timing Waveform of Read Cycle 3 (3,6,8,9) (CE2 Controlled)
tRC
CE2
tOE
OE
tOHZ
tCHZ
tOLZ
tACE
DOUT
Data Valid
tPD
tCLZ
tPU
ICC
ISB
Supply Current
50%
50%
5
REV. 1.2 May 2001 V62C1802048L(L)
V62C1802048L(L)
Timing Waveform of Write Cycle 1 (10,11) (WE Controlled)
tWC
tAW
tWR
Address
tWP
WE
tAS
tDW
tDH
DIN
Data Valid
tWZ
tOW
DOUT
Timing Waveform of Write Cycle 2 (10,11) (CE1 Controlled)
tWC
tAW
tWR
Address
CE1
tAS
tCW
tWP
WE
tWZ
tDW
tDH
DIN
Data Valid
DOUT
Timing Waveform of Write Cycle 3 (10,11) (CE2 Controlled)
tWC
tAW
tWR
Address
tAS
tCW
CE2
WE
tWP
tWZ
tDW
tDH
DIN
Data Valid
DOUT
6
REV. 1.2 May 2001 V62C1802048L(L)
V62C1802048L(L)
Data Retention Characteristics (L Version Only)(1)
Parameter
Symbol
VDR
Test Condition
Min Max Unit
-
V
for Data Retention
CE > VCC - 0.2V or
1.0
V
CC
1
Data Retention Current
ICCDR
CE < + 0.2V
1
mA
2
Chip Deselect to Data Retention Time
Operation Recovery Time(2)
tCDR
tR
VIN > VCC - 0.2V or
VIN < 0.2V
0
-
-
ns
ns
t
RC
Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C)
Data Retention Mode
VCC
Vcc_typ
V
>
1.0V
Vcc_typ
DR
tCDR
tR
CE
V
V
V
IH
DR
IH
Notes
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition, Figure A.
4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE1 and OE are LOW and CE2 is HIGH for read cycle.
8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
7
REV. 1.2 May 2001 V62C1802048L(L)
V62C1802048L(L)
Ordering Information
Device Type*
Speed
Package
8x13.4 mm 32-pin Plastic STSOP
V62C1802048L-70V
V62C1802048L-85V
V62C1802048L-100V
V62C1802048L-150V
70 ns
85 ns
100 ns
150 ns
V62C1802048LL-70V
V62C1802048LL-85V
V62C1802048LL-100V
V62C1802048LL-150V
70 ns
85 ns
100 ns
150 ns
V62C1802048L-70T
V62C1802048L-85T
V62C1802048L-100T
V62C1802048L-150T
70 ns
85 ns
100 ns
150 ns
8 x 20 mm 32-pin Plastic TSOP1
V62C1802048LL-70T
V62C1802048LL-85T
V62C1802048LL-100T
V62C1802048LL-150T
70 ns
85 ns
100 ns
150 ns
* For Industrial Temperature tested devices, an “I” designator will be added to the end of the Device number.
8
REV. 1.2 May 2001 V62C1802048L(L)
MOSEL VITELIC WORLDWIDE OFFICES
V62C1802048L(L)
U.S.A.
TAIWAN
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UK & IRELAND
SUITE 50, GROVEWOOD
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STRATHCLYDE BUSINESS
PARK
BELLSHILL, LANARKSHIRE,
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PHONE: 44-1698-748515
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5/01
Printed in U.S.A.
© Copyright 2001, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
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