M62301FP [MITSUBISHI]
10~12-BIT 4CH INTEGRATING A-D CONVERTER; 10 〜 12位4路INTEGRATING A- D转换器
| 型号： | M62301FP |
| 厂家： | 
Mitsubishi Group |
| 描述： | 10~12-BIT 4CH INTEGRATING A-D CONVERTER |
| 文件： | 总9页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI<Dig.Ana.INTERFACE>
M62301SP,FP
10~12-BIT 4CH INTEGRATING A-D CONVERTER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
M62301 semiconductor integrated circuit forms an integrating
A-D converter,being connected to a microcomputer unit.By
using selection signals and counter clock signals from the
unit,a 10~12-bit A-D converter can be created at a low cost.
The integration time and resolution can be set at the user‘s
option by changing external parameters.In addition,the built-in
circuit offset,delay time and temperature fluctuation are
adjustable,enabling a wide range of applications.
M62301 has a 3 input decoder circuit,high-precision
reference voltage(1.22V)generator,current supply and
comparator for integration,and voltage-monitoring reset circuit
for a 5V power supply.It is also equipped with girdling to
prevent current leak from integration capacitor.
Vcc FOR RESET
1
2
20
DIGITAL GND
19 A1
C0
C1
3
18
17
16
15
A2
C2
INT
4
A3
A4
5
REFERENCE INPUT
6
RESET
14 DIGITAL VDD
7
GIRDLING 1
REFERENCE
VOLTAGE
INTEGRATING
CAPACITOR
8
13
FEATURES
CONSTANT CURRENT
CONTROL
9
12
GIRDLING 2
•Separate power supplies for analog section and digital section.
•Low power dissipation.....................................2mA(typ)
(1mA for A-D conversion and the other 1mA for reset)
•Linear error......................................................±0.02%(typ)
•Conversion time...............................................526µs/ch(typ)
•Built-in system reset.........................................4.45V(typ)
10
11
ANALOG GND
ANALOG Vcc
Outline 20P4B(SP)
20P2N-A(FP)
APPLICATION
High-precision control systems such as temperature control
and speed control
ANALOG
Vcc
DIGITAL
GND
CONSTANT
CURRENT
CONTROL
BLOCK DIAGRAM
ANALOG
GND
DIGITAL
VDD
10
12
20
11
14
A1
A1 19
A2
+
-
A2 18
INT
5
0.49V
A3
A3
17
+
-
A4
A4
16
0.36V
VREF
REFERENCE 15
1 Vcc FOR RESET
INPUT
150µs
GND
RESET
6
+
-
DELAY
CIRCUIT
DISCHARGE
REFERENCE 13
DECODER
VOLTAGE
VREF
1.22V
4
3
2
C0
8
7
9
C1 C2
INTEGRATING
CAPACITOR
GIRDLING 2
GIRDLING 1
MITSUBISHI
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MITSUBISHI<Dig.Ana.INTERFACE>
M62301SP,FP
10~12-BIT 4CH INTEGRATING A-D CONVERTER
ABSOLUTE MAXIMUM RATINGS(Ta=25°C, unless otherwise noted)
Symbol
Ratings
15
Conditions
Parameter
Analog section supply voltage
Digital section supply voltage
Unit
V
Vcc
VDD
VID
8
V
Digital input voltage
Analog input voltage
INT output current
Reset output current
-0.3~VDD+0.3
-0.3~VDD+0.3
6
V
V
VIA
IoINT
mA
mA
V
IoRE
VINT
6
INT output withstand voltage
15
15
V
VRESET
VRE
Reset output withstand voltage
Reset supply voltage
6
V
Pd
K
990(DIP)/660(FP)
9.9(DIP)/6.6(FP)
mW
mW/°C
°C
Power dissipation
Thermal derating
Operating temperature
Storage temperature
-20 ~ +75
Topr
Tstg
-55 ~ +125
°C
RECOMMENDED OPERATING CONDITIONS(Ta=25°C, unless otherwise noted)
Limits
Symbol
Unit
Parameter
Min
4.5
4.5
Typ
Max
12.0
Analog section supply voltage
Digital section supply voltage
8.0
V
V
Vcc
5.0
5.5
VDD
Analog input voltage range
(II=50µA)
No more than(Vcc-2.5V)
and VDD(Note 1)
0
V
VIA
No more than(Vcc-2.5V)
and VDD(Note 1)
Reference input voltage(II=50µA)
VIR
CI
V
1
pF
kW
mA
Integration capacity
22000
60
300
6
Resistance to determine charge current
Output current
RI
Io
4
Note 1.Maximum analog input voltage is less than the difference between Vcc-2.5V as well as VDD.
VREF
*Charging current II=
R1
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MITSUBISHI<Dig.Ana.INTERFACE>
M62301SP,FP
10~12-BIT 4CH INTEGRATING A-D CONVERTER
ELECTRICAL CHARACTERISTICS(Vcc=5.0V,VDD=5.0V,Ta=25°C, unless otherwise noted)
Limits
Typ.
Symbol
Icc
Unit
Test conditions
Parameter
Supply current
Min.
Max.
1.0
2.0
2.5
2.2
mA
V
II=100µA
II=200µA
Analog input voltage range
Reference input voltage
VIA
0
IREF=±5µA
VREF
V
1.17
1.22
1.27
50
CREF=4700pF
IREF +
IREF -
Permissible current inflow at
reference voltage
µA
-10
Conversion error
Linear error
(Note 1)RI=24kW
(Note 2)RI=24kW
0.1
0.09
Ec
EL
0.05
0.02
%/FSR
%/FSR
VIA=2.5V,CI=0.01µF
RI=24kW
Conversion time
526
µs
TT
V 8=3V 0.3V
CI=4700pF
µs
Discharge time
3
17
Tdi
-0.35
µA
V
IB
VIH
VIL
-3.5
Analog input current
Digital input “H“ level
Digital input “L“ level
INT output “L“ level
INT output leak current
Detection voltage
Hysteresis voltage
Delay time
3.5
0.8
0.4
1
4.60
80
V
V
µA
0.1
IOL=1mA
V 5=15V
VLINT
IOHINT
VDET
4.45
50
150
4.30
30
V
mV
µs
DVDET
TDE
300
0.4
75
IOL=1mA
0.1
V
µA
VLRE
IOHRE
Reset output “L“ level
Reset output leak current
Supply current
V 5=15V
VRE=5V
1
2.0
1.0
mA
IRE
0.75
0.6
1.0
0.8
RL=2.2kW,VLRE£0.4V
RL=100kW,VLRE£0.4V
VOPL
Limit operating voltage
V
Note 1.Conversion error;Deviation from the line that links the “0“ scale point (mode 0) and reference scale point (mode 3. VFSR=2.5V).Associated
with all channels.
Note 2.Linear error;Deviation from the line that links the 0-V input point and 2.5V input point on a given channel.
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ELECTRIC
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MITSUBISHI<Dig.Ana.INTERFACE>
M62301SP,FP
10~12-BIT 4CH INTEGRATING A-D CONVERTER
OPERATING DESCRIPTION
(1)Decoder
from integration capacitor (CI) is performed.None of these operations
is performed when the "mode 8" input is given:
Based on digital inputs to C0,C1,C2,the analog switch
is set to on,and the input of "0" scale (GND input),input
of reference scale (reference voltage input),input to
A1~A4,or discharge
Mode
C0
1
2
1
7
5
0
6
1
3
0
4
8
1
0
0
1
1
C1
0
0
0
1
1
1
1
0
0
1
0
C2
0
0
1
1
Discharge
VREF
A4
GND
A1
A2
A3
(2)A-D conversion
DECODER SELECTION MODE
1
1
2
1
1
3
4 ~ 7
VIN+0.49V
V 8
VREF+0.49V
0.49V
0.36V
TGND
TREF
TIN
Multiplexer first selects VGND,obtaining minimum pulse
TGND.It then selects VREF,obtaining reference pulse
TREF.Input is selected next,obtaining input pulse TIN.VIN is
obtained by deducting TGND,as the offset,from TREF and
TIN.
Note. To ensure discharge from capacitor CI,the decoder input as in
the above diagram should stay in mode 1 at least for the
VIAmax+0.49
period calculated above:
Tdi=(CI X
)
1mA
TIN-TG
VIN=VREF •
TREF-TG
It is not necessary to measure TGND,and TREF for each
channel.
By measuring voltage at the maximum input for
approximately 500µs under the counter clock of
8MHz,resolution of approximately 12bits can be obtained;
.
500µs
125ns
12
2
=
.
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MITSUBISHI<Dig.Ana.INTERFACE>
M62301SP,FP
10~12-BIT 4CH INTEGRATING A-D CONVERTER
(3)Constant current control
Integrating current II can be obtained based on the reference
voltage(1.22V)by the built-in high-precision generator and
resistance RI.
II
1.22
RI
II=
(A)........................(1)
VREF
13
8
12
Integration time TI can be calculated as follows;
CI
RI
1.22V
CI
TI=(VIN+0.49)
.............(2)
II
(However,parameters such as built-in comparator offset
voltage,analog switch offset,voltage leak current and delay
time are not counted.)
50mA
4.45V
RESET SUPPLY VOLTAGE
VRE
0.8V
t
RESET OUTPUT
OUTPUT
UNSETTLED
TDE
TDE
t
When voltage applied to pin VRE becomes less than
4.45V,the RESET output status becomes "L".If voltage
increases over 4.50V,the RESET status becomes "H"
within 150µsec.
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MITSUBISHI<Dig.Ana.INTERFACE>
M62301SP,FP
10~12-BIT 4CH INTEGRATING A-D CONVERTER
APPLICATION SUGGESTION
1.4-channel 11-bit A-D converter system
5V
CREF:To stabilize reference voltage,
be sure to connect
TO MICROCOMPUTER
5V POWER SUPPLY
capacitance of approximately
4700pF.
10k 10k
1
2
20
19
18
17
16
15
14
13
12
11
CINT:We suggest that this capacitance
be connected to prevent
TO MICROCOMPUTER
3
malfunction due to noise.
CONTROL PIN
INPUT ANALOG
VOLTAGE
4
5
6
TO COUNTER
TO RESET
CINT
680PF
7
CREF
4700pF
Use CI that leaks as slight current
as possible.To prevent leak to the
circuit board,we recommend providing
girdling 7 , 9
8
9
50µA
II=50µA
24k
10
CI
4700pF
RI
.
1.22V
24kW
Charge current II =
=
.
50µA
Resolution depends on the number of microcomputer
counter clock pulses that are generated while the INT
output status is "high" at the maximum input voltage 2.5V
(vcc-2.5V).
When the microcomputer counter clock frequency is
8MHz,the resolution can be calculated by using the
constant calculated above,as follows;
(2.5+0.13)
4700pFX
.
50µA
11
=
2
.
1
8M
Therefore,the resolution of this system is approximately
11 bits.
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MITSUBISHI<Dig.Ana.INTERFACE>
M62301SP,FP
10~12-BIT 4CH INTEGRATING A-D CONVERTER
2.4-channel 12-bit A-D converter system
Separate power supplies to analog section and digital section,
analog input voltage range mode wider up to VDD,external
reference voltage for integration.
8V
CREF:To stabilize reference voltage,
be sure to connect
TO MICROCOMPUTER
5V POWER SUPPLY
capacitance of approximately
4700pF.
10k 10k
1
2
20
19
18
17
A1
A2
A3
CINT:We suggest that this capacitance
be connected to prevent
TO MICROCOMPUTER
CONTROL PIN
3
malfunction due to noise.
INPUT ANALOG
VOLTAGE
4
5
A4 16
15
TO COUNTER
TO RESET
2.5V
6
CINT
680pF
TO MICROCOMPUTER 5V POWER SUPPLY
4700pF
7
14
13
12
11
VDD
CREF
8
Use CI that leaks as slight current
as possible.To prevent leak to the
circuit board,we recommend providing
girdling 7 , 9
9
50µA
II=50µA
24k
10
CI
6800pF
RI
When the counter clock frequency is 8MHz,resolution is:
Because separate power supplies are provided for the
analog are digital sections,the M62301 has two supply
(5 + 0.13)
6800pF X
50µA
.
12
=
2
.
voltage Vcc and VDD,enabling a wide analog input voltage
range VIA.The upper limit of the range is required to be no
more than the difference between Vcc-2.5V as well as
VDD,therefore,the analog input voltage range in this
application is 0V to 5V.
1
8M
An A-D converter system with resolution of approximately
12 bits can be formed.
Recommended operational settings according to clock frequency,resolution,and time required for
discharge(decoder mode 1)
Discharge time
Tdi(µs)
Change current Resistance to determine
Integration
capacitance CI
1400pF
Counter clock
Resolution
10-bit
II(µA)
50
constant current RI(kW)
7.7
24
12
24
12
24
12
24
12
24
12
24
12
100
15.4
15.4
30.7
30.7
65.9
3.9
2800pF
50
2800pF
11-bit
12-bit
10-bit
8MHz
100
5600pF
5600pF
50
12000pF
700pF
100
50
100
50
100
50
7.7
1400pF
1400pF
7.7
16MHz
11-bit
12-bit
2800pF
15.4
15.4
30.7
2800pF
100
5600pF
VIAmax+0.49
1mA
Note 1.Discharge time Tdi=(CI X
)
The values in this table apply when VIAmax is 5V.
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MITSUBISHI<Dig.Ana.INTERFACE>
M62301SP,FP
10~12-BIT 4CH INTEGRATING A-D CONVERTER
TYPICAL CHARACTERISTICS
THERMAL DERATING
ANALOG PART SUPPLY CURRENT
VS.SUPPLY VOLTAGE
1000
2.0
1.0
800
600
400
200
0
0
0
25
0
50
125
100
5
75
10
ANALOG Vcc (V)
AMBIENT TEMPERATURE Ta(°C)
STANDARD VOLTAGE VS.
AMBIENT TEMPERATURE
LINEAR ERROR
1.24
0.05
1.23
1.22
0.04
0.03
0.02
1.21
1.20
RI=24kW
RI=12kW
0.01
1.19
0
2.0
20
40
60
80
2.5
(FSR)
-20
0
1.0
0
(OSR)
AMBIENT TEMPERATURE Ta (V)
ANALOG INPUT RANGE VIA(V)
INT OUTPUT “L“ LEVEL
VS.OUTPUT CURRENT
INT OUTPUT VS.AMBIENT TEMPERATURE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
200
100
0
-20
80
60
0
0.1
1
10
0
20
40
INT OUTPUT CURRENT IO INT (mA)
AMBIENT TEMPERATURE Ta (°C)
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MITSUBISHI<Dig.Ana.INTERFACE>
M62301SP,FP
10~12-BIT 4CH INTEGRATING A-D CONVERTER
DETECTION VOLTAGE vs.
AMBIENT TEMPERATURE
RESET SUPPLY CURRENT VS.
SUPPLY VOLTAGE
4.7
4.6
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
4.5
4.4
4.3
4.2
9
10
8
0
80
3
0
2
5
6
7
20
40
60
4
-20
1
RESET VOLTAGE Vcc VRE (V)
AMBIENT TEMPERATURE Ta(°C)
RESET OUTPUT “L“ LEVEL
VS.OUTPUT CURRENT
DELAY TIME VS.AMBIENT TEMPERATURE
250
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
200
150
100
50
0
-20
0
0.1
1
10
0
80
20
40
60
AMBIENT TEMPERATURE Ta(°C)
RESET OUTPUT CURRENT IORE (mA)
LIMIT RESET VOLTAGE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
RL=2.2kW
RL=100kW
0
1.0
0.6
2.0
RESET VOLTAGE Vcc VRE (V)
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