M61506FP [MITSUBISHI]

Peak hold IC for 5 band spectrum analyzer displays; 峰值保持IC的5频段频谱分析仪显示器


型号：	M61506FP
厂家：	Mitsubishi Group
描述：	Peak hold IC for 5 band spectrum analyzer displays 峰值保持IC的5频段频谱分析仪显示器显示器
文件：	总13页 (文件大小：209K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MITSUBISHI SOUND PROCESSORS

M61506FP

Peak hold IC for 5 band spectrum analyzer displays

DESCRIPTION

The M61506FP is a 5 band peak hold ICs that use microprocessor time division to produce

serial output for spectrum analyzer displays.

FEATURES

5 band peak hold elements for spectrum analyzer displays.

Discharge time constant circuit for each band is on the chip.

Single 5V power supply.

RECOMMENDED OPERATING CONDITIONS

Supply voltage range

4.5 to 6.5V

Rated supply voltage

5.0V

SYSTEM BLOCK DIAGRAM

Peak

BPF5

Peak

Hold

Peak

Audio

signal

BPF5

HoPlde5ak

Hold5

SELECTOR

output

m-com

interface

SELC

SELB

SELA

ENB

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BLOCK DIAGRAM

Vcc/2

VREF

Vcc/2 Gen.

16 GND2

SELECTOR

V REF Gen.

(VccX0.3)

PHOUT

TEST

IREF

DIFOUT

COUT

CNF

I REF Gen.

GND1

ENB

HOLD

OUTPUT

BPF IN

f1 BPF 1

P.HOLD

Amp-

P.HOLD

BPF 2

BPF 3

BPF 4

BPF 5

SELC

Amp-

SELB

SELA

AOUT

ANF

Amp-A

HOLD C RESET

Vcc

(Notes)f1=105Hz,f2=340Hz,f3=1KHz,f4=3.4KHz,f5=10.5KHz

(The value is the design value)

Units Resistance :W

Capacitance: F

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FUNCTIONAL DESCRIPTION

(1)The audio signal amplified by Amp-A and Amp-D into BPF/peak

hold circuit for spectrum analyzer display.

Because the last output signal inputs into A/D of microprocessor.

The Vcc,GND had better be common with Vcc,GND of A/D of

maicroprocessor.

It untilizes effect of common-mode rejection of Amp-D.Amp-C is the input

amplifier to reject common-mode signal(noise).To get to good ground isolation.

(2)BPF/peak hold circuit is fit for 5 band spectrum analyzer display.

f1=105Hz

f2=340Hz

f3=1KHz

f4=3.4KHz

f5=10.5KHz

(The value is the design value)

Center frequency and Q of BPF is

w0=gm/C

gm:matual condactance of inside amplifier circuit

(It depends on outside resistor value of Pin.No.3)

C:inside capacitor

Q=(R1+R2)/R1:it is fixed by inside resistor ratio.

(The design value of Q is 3.5)

(3)The hold capacitor of peak hold circuit is included.

The reset(discharge) signal is made automatically after ending the output

of hold value(Discharge pulse effect:-3dB(typ).fall refer to output value)

(4)The internal output voltage of peak hold circuit is refered to Vcc/2.

(Pin.No.1)

When it is selected by the output select circuit,it appear at PHout

(Pin.No.15) refered to GND.

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PIN DESCRIPTION

PIN No.

Name

I/O

Function

1/2Vcc bias

0.3Vcc bias

Vcc/2

VREF

IREF

BPF center frequency setting current terminal

Output of amplifier-D(BPF input signal)

DIFOUT

Output of amplifier-C

COUT

CNF

Inverted input of amplifier-C

Output of amplifier-A

AOUT

Inverted input of amplifier-A

ANF

System supply

Vcc

SELA

Output setting control terminal A(logic input)

Output setting control terminal B(logic input)

Output setting control terminal C(logic input)

Output setting control enable terminal(logic input)

Ground 1

SELB

SELC

ENB

GND1

Peak hold output terminal

Ground 2

PHOUT

GND2

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PIN No.

Peripheral circuit of pins

Name

Vcc/2

I/O

Vcc

350K

180K

VREF

IREF

150K

GND2

DIFOUT

Vcc/2

COUT

CNF

AOUT

Vcc/2

ANF

Vcc

Supply

SELA

10,11,12,13

20K

SELB

SELC

ENB

VccX0.3

10K

VccX0.3

Ground1

GND1

PHOUT

GND2

10K

GND2

Ground2

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ABSOLUTE MAXIMUM RATINGS

Unit

Parameter

Conditions

Ratings

Symbol

Vcc(max) Supply Voltage

Ta<25 C

Power dissipation

540

5.4

mW/

Thermal derating

Ta>25

Topr

Tstg

-20 to +75

-40 to +125

Operating temperature

Storage temperature

GND-0.3 to Vcc+0.3

GND to Vcc

Input voltage range

Output voltage range

Vi(max)

Vo(max)

Thermal derating(maximum rating)

0.6

0.54

0.5

0.4

0.3

0.27

0.2

0.1

100

150

125

AMBIENT TEMPERATURE Ta (

)

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Recommended operating conditions

(Ta=25

unless otherwise noted)

Symbol

Parameter

Conditions

MAX

6.5

Unit

MIN

4.5

TYP

5.0

Supply voltage

Vcc

Logic input H

level voltage

Vcc=5V

VIH

VIL

VCC

0.5

2.5

Logic input L

level voltage

GND

(Note 1)

The center frequency characteristics of BPF are determined by the

resistor connected between 3pin terminal and GND.If it is necess-

ary,adjust the resistor value(note:all bands will be shifted

together).

The Q of BPF is fixed in 3.5 by inside circuit.

(Note 2)

The internal output resistor of peak hold output(PIN 15)is 10kW

typ.

The input resistance of the microprocessor must be much larger

than 10kW .

(Note 3)

The control voltage from the microprocessor must be from GND

-0.3V to Vcc+0.3V.

If the control voltage is out of the above range.

It`s necessary to modify the control voltage in the above range by

using resistors or diodes.

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OUTPUT CONTROL SPECIFICATION

PHout

(PinNo.15)

ENB

SELA

SELB SELC

Note

GND(output stop)

GND

X:Don`t Care

f1:105Hz

f2:340Hz

GND

f3:1kHz

GND

f4:3.4kHz

f5:10.5kHz

'H'=low level,'1'=high level,'X'='0'or'1'

The output setting time is more than 10msec.

(When the output setting time is short,the output value and reset

signal become unstable)

90%

PHout

Ts(10mSec.MAX)

fn SELECT

(internal signal)

<Automatic Generation by

inside time constant>

fn RESET

(internal signal)

Tr(25mSec.TYP)

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TIMING CHART

ENB

SELA

SELB

SELC

PHout

GND

f1 RESET

(105Hz)

f2 RESET

(340Hz)

f3 RESET

(1KHz)

f4 RESET

(3.4KHz)

f5 RESET

(10.5KHZ)

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ELECTRICAL CHARACTERISTICS

(Ta=25

,Vcc=5.0V,PHout(Pin.No.15)RL=1MW unless otherwise

noted.VAIN=-30dBV, f=1KHz,ENB(Pin.No.13)=1)

Limits

typ

Condition

Unit

Parameter

Symbol

Min

Max

No signal,No select

Circuit current

Icc

(ENB,SELA,SELB,SELC=0)

f1 to f5 Measured at each output

(VAIN=-14dBV)

4.0

4.7

Maximum output level

Output offset voltage

f1 to f5 Measured at each output

(No signal,ENB=0/1)

Vos

VIH

Vcc

+0.3

Logic input H level

Logic input L level

2.5

5.0

GND

-0.3

VIL

0.5

Common-mode rejection ratio

CMRR

f1 output level

Vo1

Vo2

Vo3

0.5

f1(fin=80 to 130Hz)

f2(fin=270 to 410Hz)

f3(fin=0.8 to 1.2KHz)

f4(fin=2.7 to 4.1KHz)

f5(fin=8.0 to 13.0KHz)

1.70

1.0

f2 output level

f3 output level

f4 output level

f5 output level

Vo4

Vo5

The time from the rise of output

selection until the rise of PHout

(90% of peak)

msec

Output response time

Discharge level

Inside reset signal

Tr=25msecTYP.

-3

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TEST CIRCUIT

Vcc/2

Vcc/2 Gen.

GND2

0.1m

PHOUT

VREF

V REF Gen.

(Vccx0.3)

SELECTOR

0.1m

IREF

I REF Gen.

GND1

100K

HOLD

OUTPUT

CONTROL

CIRCUIT

BPF IN

DIFOUT

Px4

BPF 1

P.HOLD

ENB

Amp-

BPF 2

BPF 3

BPF 4

BPF 5

COU

^T5

Px3

Amp-

SELC

100K

0.47m

SELB

Px2

39K

AOU

Px1

SELA

Amp-A

100K

HOLD C RESET

0.47m

Vcc

AIN

39K

0.01m

10m

Units resistance:W

capacitance:F

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APPLICATION EXAMPLE

Vcc/2

Vcc/2 Gen.

GND2

0.1m

VREF

PHOUT

V REF Gen.

(VccX0.3)

SELECTOR

0.1m

IREF

I REF Gen.

100K

GND1

HOLD

OUTPUT

A/D

BPF IN

DIFOUT

Px4

BPF 1

P.HOLD

ENB

Amp-

BPF 2

BPF 3

BPF 4

BPF 5

COU

^T5

Px3

Amp-

P.HOLD

SELC

100K

0.47m

MCU

COM

SELB

Px2

270K/2

<Common-mode Noise Rejection>

ground isolation

AOU

Px1

SELA

Amp-A

100K

HOLD C RESET

Vcc

0.047m

CH1

270K

0.047m

CH2

0.01m

270K

10m

Units resistance:W

capacitance:F

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OUTLINE

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M61506FP [MITSUBISHI]

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