M5M4V4265CTP-6ST [MITSUBISHI]
EDO DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40;
| 型号： | M5M4V4265CTP-6ST |
| 厂家： | 
Mitsubishi Group |
| 描述： | EDO DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40 存储 内存集成电路 光电二极管 动态存储器 |
| 文件： | 总31页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
This is a family of 262144-word by 16-bit dynamic RAMs with EDO
mode fuction, fabricated with the high performance CMOS
process, and is ideal for the buffer memory systems of personal
computer graphics and HDD where high speed, low power
dissipation, and low costs are essential. The use of double-layer
metalization process technology and a single-transistor dynamic
storage stacked capacitor cell provide high circuit density at
reduced costs. The lower supply (3.3V) operation, due to the
optimization of transistor structure, provides low power dissipation
while maintaining high speed operation. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application. This device has 2CAS and 1W
terminals with a refresh cycle of 512 cycles every 8.2ms.
1
2
(3.3V)VCC
DQ1
40 VSS(0V)
39
DQ16
38
DQ2
3
4
DQ15
37
36
35
DQ14
DQ3
DQ4
5
6
DQ13
(3.3V)VCC
DQ5
VSS(0V)
7
8
9
34 DQ12
33 DQ11
DQ6
DQ7
32
31
30
29
28
DQ10
DQ9
NC
DQ8 10
FEATURES
NC
NC
W
11
12
13
14
15
16
17
18
19
20
Power
dissipa-
tion
OE
access
time
RAS
access
time
CAS
access access
time time
Address
Cycle
time
(min.ns)
LCAS
Type name
UCAS
OE
(typ.mW)
(max.ns) (max.ns) (max.ns) (max.ns)
27
26
RAS
NC
A0
M5M4V4265CXX-5,-5S
M5M4V4265CXX-6,-6S
M5M4V4265CXX-7,-7S
XX=TP,J
13
15
20
25
30
35
50
60
70
13
15
20
408
363
333
90
110
130
A8
25 A7
24
23
22
21
A6
A1
A2
Standard 40 pin SOJ, 44 pin TSOP (II)
Single 3.3±0.3V supply
Low stand-by power dissipation
CMOS Input level
A5
A4
A3
VSS(0V)
(3.3V)VCC
1.8mW (Max)
CMOS Input level
360µW (Max) *
Operating power dissipation
M5M4V4265CXX-5,-5S
M5M4V4265CXX-6,-6S
M5M4V4265CXX-7,-7S
Self refresh capability *
Self refresh current
Extended refresh capability
Extended refresh current
EDO mode (512-column random access), Read-modify-write, RAS-
only refresh, CAS before RAS refresh, Hidden refresh capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A0~A8)
Outline 40P0K (400mil SOJ)
486mW (Max)
432mW (Max)
396mW (Max)
1
2
(3.3V)VCC
DQ1
44 VSS(0V)
43
DQ16
100µA (Max)
100µA (Max)
42
DQ2
3
4
DQ15
41
40
39
DQ14
DQ13
DQ3
DQ4
5
6
(3.3V)VCC
DQ5
VSS(0V)
DQ12
7
8
38
512 refresh cycles every 128ms (A0~A8) *
DQ11
DQ10
DQ9
DQ6
37
36
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S,
-7S : option) only
DQ7
9
10
DQ8
35
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame buffer
NC
NC
W
32
31
30
13
14
15
16
17
18
19
20
21
22
NC
memory for CRT
LCAS
PIN DESCRIPTION
UCAS
OE
Pin name
A0~A8
Function
Address inputs
29
28
RAS
NC
A0
A8
DQ1~DQ16
RAS
Data inputs / outputs
27 A7
Row address strobe input
26
25
24
23
A6
A1
A2
Lower byte control
column address strobe input
LCAS
A5
A4
A3
Upper byte control
UCAS
W
column address strobe input
(3.3V)VCC
VSS(0V)
Write control input
Output enable input
Power supply (+3.3V)
Ground (0V)
OE
VCC
Outline 44P3W-R (400mil TSOP Nomal Bend)
VSS
NC : NO CONNECTION
1
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
In addition to EDO Mode, normal read, write and read-modify-
write operations the M5M4V4265CXX provides a number of other
functions, e.g., RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Input/Output
Operation
DQ1~DQ8
DOUT
OPN
DOUT
DIN
DQ9~DQ16
OPN
DOUT
DOUT
DNC
DIN
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
LCAS
ACT
NAC
ACT
ACT
NAC
ACT
NAC
ACT
ACT
ACT
DNC
UCAS
NAC
ACT
ACT
NAC
ACT
ACT
NAC
ACT
ACT
ACT
DNC
W
OE
Lower byte read
Upper byte read
Word read
NAC
NAC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
DNC
DNC
ACT
ACT
ACT
NAC
NAC
NAC
DNC
ACT
DNC
DNC
DNC
Lower byte write
Upper byte write
Word write
DNC
DIN
DIN
RAS only refresh
Hidden refresh
OPN
DOUT
OPN
OPN
OPN
OPN
DOUT
OPN
OPN
OPN
CAS before RAS (Extended *) refresh ACT
Self refresh *
Stand-by
ACT
NAC
Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open
BLOCK DIAGRAM
VCC (3.3V)
VSS (0V)
ROW ADDRESS
STROBE INPUT
RAS
CLOCK GENERATOR
CIRCUIT
LOWER BYTE CONTROL
LCAS
UCAS
COLUMN ADDRESS
STROBE INPUT
(8)LOWER
DATA IN
BUFFER
LOWER
UPPER
UPPER BYTE CONTROL
COLUMN ADDRESS
STROBE INPUT
DQ1
LOWER DATA
INPUTS /
DQ2
WRITE CONTROL
INPUT
W
OUTPUTS
DQ8
(8)LOWER
DATA OUT
BUFFER
VCC (3.3V)
VSS (0V)
A0~A8
COLUMN DECODER
(8)UPPER
DATA IN
BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
DQ9
UPPER DATA
INPUTS /
OUTPUTS
SENSE REFRESH
AMPLIFIER & I /O CONTROL
DQ10
ROW &
COLUMN
ADDRESS
BUFFER
DQ16
(8)UPPER
DATA OUT
BUFFER
ADDRESS INPUTS
MEMORY CELL
(4,194,304 BITS)
ROW
DECODER
A0~
A8
VCC (3.3V)
VSS (0V)
OUTPUT ENABLE
INPUT
OE
2
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
V I
Parameter
Conditions
With respect to VSS
Ratings
-0.5~4.6
-0.5~4.6
-0.5~4.6
50
Unit
V
Supply voltage
Input voltage
Output voltage
Output current
V
VO
V
mA
I O
Power dissipation
1000
Pd
Ta=25˚C
mW
˚C
˚C
Operating temperature
Storage temperature
Topr
0~70
-65~150
Tstg
RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted) (Note 1)
Limits
Symbol
Parameter
Unit
Nom
3.3
0
Min
3.0
0
Max
3.6
0
Supply voltage
Supply voltage
V
V
V
V
VCC
VSS
VIH
VIL
VCC+0.3
High-level input voltage, all inputs
Low-level input voltage, all inputs
2.0
-0.3
0.8
Note 1 : All voltage values are with respect to VSS.
ELECTRICAL CHARACTERISTICS (Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted) (Note 2)
Limits
Typ
Parameter
Test conditions
Unit
V
Symbol
Min
2.4
0
Max
VCC
0.4
5
VOH
VOL
IOZ
I I
High-level output voltage
Low-level output voltage
Off-state output current
Input current
IOH=-2mA
IOL=2mA
V
µA
µA
Q floating 0V£VOUT£VCC
-5
0V£VIN£VCC+0.3V, Other inputs pins=0V
-5
5
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
135
120
110
Average supply current
from Vcc, operating
(Note 3,4,5)
RAS, CAS cycling
tRC=tWC=min.
output open
mA
ICC1(AV)
ICC2
2
RAS= CAS =VIH, output open
mA
0.5
Supply current from VCC, stand-by
(Note 6)
RAS= CAS³ VCC -0.2V
output open
0.1 *
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
125
110
95
Average supply current
from Vcc, RAS only
refresh mode
RAS cycling, CAS=VIH
tRC=min.
mA
mA
ICC3(AV)
ICC4(AV)
output open
(Note 3,5)
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
125
110
95
Average supply current
RAS=VIL, CAS cycling
tPC=min.
output open
from Vcc EDO mode
(Note 3,4,5)
Average supply current
from Vcc
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
(Note 3,5)
115
100
85
CAS before RAS refresh cycling
tRC=min.
output open
mA
ICC6(AV)
CAS before RAS refresh
mode
RAS cycling CAS£0.2V or CAS
before RAS refresh cycling
RAS£0.2V or ³ VCC-0.2V
CAS£0.2V or ³ VCC-0.2V
W£0.2V or³ VCC-0.2V
OE£0.2V or ³ VCC-0.2V
A0~A8 £ 0.2V or ³ VCC-0.2V,
DQ=open
Average supply current
from VCC
Extended-refresh mode
ICC8(AV) *
µA
µA
100
100
(Note 6)
tRC=250µs, tRAS=tRAS min~1µs
RAS=CAS£0.2V
output open
Average supply current from VCC
Self-refresh mode
ICC9(AV) *
(Note 6)
Note 2 : Current flowing into an IC is positive, out is negative.
3 : ICC1(AV), ICC3(AV), ICC4(AV), and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4 : ICC1(AV) and ICC4(AV) are dependent on output loading. Specified values are obtained with the output open.
5 : Column Address can be changed once or less while RAS=VIL and CAS=VIH.
3
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAPACITANCE (Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted)
Limits
Typ
Unit
Parameter
Test conditions
Symbol
Min
Max
5
pF
pF
pF
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
CI (A)
VI=VSS
f=1MHz
CI (CLK)
CI / O
7
VI=25mVrms
7
SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=3.3±0.3V, Vss=0V, unless otherwise noted, see notes 6,14,15)
Limits
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Symbol
Parameter
Min
Max
13
Min
Max
15
Min
Max
20
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
ns
ns
ns
ns
ns
ns
ns
tCAC
tRAC
Access time from CAS
Access time from RAS
50
25
28
13
60
30
33
15
70
35
38
20
tAA
Columu address access time
Access time from CAS precharge
Access time from OE
tCPA
tOEA
tOHC
tOHR
(Note 13)
(Note 13)
5
5
5
5
5
5
5
5
5
Output hold time from CAS
Output hold time from RAS
(Note 7)
tCLZ
Output low impedance time from CAS low
ns
ns
(Note 12)
tOEZ
tWEZ
13
13
13
13
15
15
15
15
20
20
20
20
Output disable time after OE high
Output disable time after WE high
Output disable time after CAS high
Output disable time after RAS high
ns
(Note 12)
(Note 12,13)
(Note 12,13)
tOFF
tREZ
ns
ns
Note 6 : An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS
inactivity before proper device operation is achieved.
7 : Measured with a load circuit equivalent to 50pF, VOH (IOH=-2mA) and VOL(IOL=2mA). The reference levels for measuring of output signals are
2.0V(VOH) and 0.8V(VOL).
8 : Assumes that tRCD³ tRCD(max) and tASC³ tASC(max) and tCP³ tCP(max).
9 : Assumes that tRCD£tRCD(max) and tRAD£tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC
will increase by amount that tRCD exceeds the value shown.
10 : Assumes that tRAD³ tRAD(max) and tASC£tASC(max).
11 : Assumes that tCP£tCP(max) and tASC³ tASC(max).
12 : tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT£ ±5µA ) and is not
reference to VOH(min) or VOL(max).
13 : Output is disabled after both RAS and CAS go to high.
4
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and EDO Mode Cycles)
(Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted, see notes 14,15)
Limits
M5M4V4265C-5,-5S M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
Unit
Symbol
Parameter
Min
Max
8.2
Min
Max
8.2
Min
Max
8.2
tREF
tREF
tRP
Refresh cycle time
Refresh cycle time *
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
128
128
128
30
18
5
40
20
5
50
20
5
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tT
(Note 16)
32
45
50
0
0
0
8
10
15
0
10
15
0
13
0
25
10
30
13
35
13
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
(Note 17)
(Note 18)
0
0
0
8
10
10
10
10
0
8
(Note 19)
(Note 19)
(Note 20)
(Note 20)
(Note 20)
(Note 21)
0
0
0
0
Delay time, data to OE low
0
Delay time, RAS high to data
13
13
13
1
15
15
15
1
20
20
20
1
Delay time, CAS high to data
Delay time, OE high to data
50
50
50
Transition time
Note 14 : The timing requirements are assumed tT=2ns.
Note 15 : VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Note 16 : tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
Note 17 : tRAD(max) is specified as a reference point only. If tRAD³ tRAD(max) and tASC£tASC(max), access time is controlled exclusively by tAA.
Note 18 : tASC(max) is specified as a reference point only. If tRCD³ tRCD(max) and tASC³ tASC(max), access time is controlled exclusively by tCAC.
Note 19 : Either tDZC or tDZO must be satisfied.
Note 20 : Either tRDD or tCDD or tODD must be satisfied.
Note 21 : tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Limits
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Symbol
Parameter
Min
90
50
8
Max
Min
110
60
10
48
15
0
Max
Min
130
70
13
55
20
0
Max
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tRAS
tCAS
tCSH
tRSH
10000
10000
10000
10000
10000
10000
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
Column address to CAS hold time
RAS hold time after OE low
40
13
0
tRCS
tRCH
tRRH
tRAL
(Note 22)
(Note 22)
0
0
0
0
0
0
25
13
13
13
30
18
15
15
35
23
20
20
tCAL
tORH
tOCH
CAS hold time after OE low
Note 22 : Either tRCH or tRRH must be satisfied for a read cycle.
5
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Min
90
50
8
Max
Min
110
60
10
48
15
0
Max
Min
130
70
10
55
20
0
Max
tWC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
RAS low pulse width
CAS low pulse width
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
10000
10000
10000
10000
10000
10000
40
13
0
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
(Note 24)
8
10
10
10
10
0
13
13
13
13
0
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
8
8
8
tDS
0
Data setup time before CAS low or W low
Data hold time after CAS low or W low
tDH
8
10
13
Read-Write and Read-Modify-Write Cycles
Limits
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Symbol
Parameter
Min
109
75
38
70
38
0
Max
Min
133
89
44
82
44
0
Max
Min
161
107
57
99
57
0
Max
Read write/read modify write cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC
tRAS
(Note 23)
10000
10000
10000
10000
10000
10000
RAS low pulse width
tCAS
tCSH
tRSH
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
OE hold time after W low
tRCS
tCWD
tRWD
tAWD
tOEH
(Note 24)
(Note 24)
(Note 24)
28
65
40
13
32
77
47
15
42
92
57
20
Note 23 : tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
Note 24 : tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCS³ tWCS(min) the cycle is an early write cycle and the DQ pins
will remain high impedance throughout the entire cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min), tAWD³ tAWD(min) and tCPWD³ tCPWD(min)
(for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.
6
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Cycle
(Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25)
Limits
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Symbol
Parameter
Min
20
57
5
Max
Min
25
66
5
Max
Min
30
79
5
Max
(Note 26)
Hyper page mode read/write cycle time
tHPC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hyper page mode read write/read modify write cycle time
Output hold time from CAS low
tHPRWC
tDOH
(Note 27)
92
10
38
60
7
tRAS
65
8
77
10
33
50
7
100000
13
100000
16
100000
16
RAS low pulse width for read or write cycle
CAS high pulse width
(Note 28)
tCP
tCPRH
tCPWD
tCHOL
tOEPE
tWPE
28
43
7
RAS hold time after CAS precharge
Delay time, CAS precharge to W low
(Note 24)
Hold time to maintain the data Hi-Z until CAS access
OE pulse width (Hi-Z control)
7
7
7
7
7
7
W pulse width (Hi-Z control)
tHCWD
tHAWD
tHPWD
tHCOD
tHAOD
tHPOD
28
40
43
13
25
28
32
47
50
15
30
33
42
57
60
20
35
38
Delay time, CAS low to W low after read
Delay time, Address to W low after read
Delay time, CAS precharge to W low after read
Delay time, CAS low to OE high after read
Delay time, Address to OE high after read
Delay time, CAS precharge to OE high after read
Note 25 : All previously specified timing requirements and switching characteristics are applicable to their respective EDO mode cycle.
Note 26 : tHPC(min) is specified in the case of read-only and early write-only in EDO mode.
Note 27 : tRAS(min) is specified as two cycles of CAS input are performed.
Note 28 : tCP(max) is specified as a reference point only.
CAS before RAS Refresh Cycle (Note 29)
Limits
M5M4V4265C-7,-7S
M5M4V4265C-5,-5S M5M4V4265C-6,-6S
Unit
Symbol
Parameter
CAS setup time before RAS low
Min
5
Max
Min
5
Max
Min
5
Max
tCSR
tCHR
tCAS
ns
ns
ns
10
17
10
17
15
22
CAS hold time after RAS low
CAS low pulse width
Note 29 : Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Self Refresh Cycle * (Note 30)
Limits
M5M4V4265C-5,-5S M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
Unit
Symbol
Parameter
Min
100
90
Max
Min
100
110
-50
Max
Min
100
130
-50
Max
µs
ns
ns
tRASS
CBR self refresh RAS low pulse width
CBR self refresh RAS high precharge time
CBR self refresh CAS hold time
tRPS
tCHS
-50
7
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Timing Diagrams (Note 31)
Read Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tRPC
tCSH
tCRP
tRCD
tRSH
tCAS
tCRP
VIH
LCAS/UCAS
VIL
tRAD
tRAL
tCAL
tASR
tASR
tRAH
tASC
tCAH
VIH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
A0~A8
VIL
tRRH
tRCH
tRCS
VIH
W
VIL
tDZC
tCDD
VIH
Hi-Z
DQ1~DQ16
(INPUTS)
VIL
tCAC
tWEZ
tOFF
tREZ
tAA
tCLZ
tOHC
tOHR
DATA VALID
VOH
Hi-Z
Hi-Z
DQ1~DQ16
(OUTPUTS)
VOL
tRAC
tOEZ
tODD
tOEA
tDZO
tOCH
VIH
OE
VIL
tORH
Indicates the don't care input.
Note 31
VIH(min)£VIN£VIH(max) or VIL(min)£VIN£VIL(max)
Indicates the invalid output.
8
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Read Cycle
tRC
tRP
tRAS
tCSH
VIH
RAS
VIL
tRPC
tCRP
tRCD
tRSH
tCRP
VIH
LCAS
(or UCAS)
VIL
tCPN
tCAS
VIH
VIL
UCAS
(or LCAS)
tRAD
tRAL
tCAL
tASR
tRAH
tASR
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
A0~A8
tRRH
tRCS
tRCH
VIH
VIL
W
DQ1~DQ8
(or DQ9~DQ16)
VIH
VIL
(INPUTS)
DQ1~DQ8
(or DQ9~DQ16)
(OUTPUTS)
VOH
Hi-Z
VOL
tCDD
tDZC
DQ9~DQ16
(or DQ1~DQ8)
(INPUTS)
Hi-Z
VIH
VIL
tREZ
tCAC
tWEZ
Hi-Z
tOHR
tAA
tOFF
tOHC
tCLZ
DQ9~DQ16
(or DQ1~DQ8)
(OUTPUTS)
VOH
Hi-Z
DATA VALID
VOL
tRAC
tOEZ
tODD
tOEA
tDZO
tOCH
VIH
VIL
OE
tORH
9
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Early Write Cycle
tWC
tRP
tRAS
tCSH
VIH
RAS
VIL
tRPC
tCRP
tASR
tRCD
tRSH
tCAS
tCRP
VIH
LCAS/UCAS
VIL
tASR
tRAH
tCAH
tASC
VIH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
A0~A8
VIL
tWCS
tWCH
VIH
W
VIL
tDH
tDS
VIH
VIL
DQ1~DQ16
(INPUTS)
DATA VALID
VOH
VOL
Hi-Z
DQ1~DQ16
(OUTPUTS)
VIH
VIL
OE
10
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Early Write Cycle
tWC
tRP
tRAS
VIH
RAS
VIL
tCSH
tRPC
tCRP
tRCD
tRSH
tCAS
tCRP
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
UCAS
(or LCAS)
tASR
tASR
tRAH
tCAH
tASC
VIH
VIL
COLUMN
ADDRESS
ROW
ADDRESS
ROW
ADDRESS
A0~A8
tWCS
tWCH
VIH
VIL
W
DQ1~DQ8
(or DQ9~DQ16)
VIH
VIL
(INPUTS)
DQ1~DQ8
(or DQ9~DQ16)
(OUTPUTS)
VOH
Hi-Z
VOL
tDS
tDH
DQ9~DQ16
(or DQ1~DQ8)
(INPUTS)
VIH
VIL
DATA VALID
DQ9~DQ16
(or DQ1~DQ8)
(OUTPUTS)
VOH
Hi-Z
VOL
VIH
VIL
OE
11
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Delayed Write Cycle
tWC
tRAS
tRP
VIH
RAS
VIL
tRPC
tCSH
tRCD
tRSH
tCAS
tCRP
tCRP
tASR
VIH
LCAS/UCAS
VIL
tCAH
tASR
tRAH
tASC
VIH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
A0~A8
VIL
tCWL
tRWL
tWP
tRCS
VIH
W
VIL
tWCH
tDZC
tDS
tDH
VIH
VIL
Hi-Z
tCLZ
DQ1~DQ16
(INPUTS)
DATA
VALID
VOH
VOL
Hi-Z
Hi-Z
DQ1~DQ16
(OUTPUTS)
tOEH
tDZO
tOEZ
tODD
VIH
VIL
OE
12
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Delayed Write Cycle
tWC
tRP
tRAS
VIH
RAS
VIL
tCSH
tRPC
tCRP
tRCD
tRSH
tCRP
VIH
LCAS
(or UCAS)
VIL
tCAS
VIH
VIL
UCAS
(or LCAS)
tASR
tCAH
tRAH
tASC
tASR
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
A0~A8
tCWL
tRWL
tWP
tRCS
VIH
VIL
W
DQ1~DQ8
(or DQ9~DQ16)
VIH
VIL
(INPUTS)
DQ1~DQ8
(or DQ9~DQ16)
(OUTPUTS)
VOH
Hi-Z
Hi-Z
VOL
tWCH
tDZC
tDS
tDH
DQ9~DQ16
(or DQ1~DQ8)
(INPUTS)
VIH
VIL
DATA
VALID
tCLZ
DQ9~DQ16
(or DQ1~DQ8)
VOH
Hi-Z
Hi-Z
VOL
(OUTPUTS)
tOEH
tOEZ
tDZO
tODD
VIH
VIL
OE
13
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRP
tRAS
VIH
VIL
RAS
tCSH
tRPC
tCRP
tASR
tRCD
tRAD
tRSH
tCAS
tCRP
VIH
VIL
LCAS/UCAS
A0~A8
tASR
tCAH
tRAH
tASC
VIH
VIL
COLUMN
ADDRESS
ROW
ADDRESS
ROW
ADDRESS
tAWD
tCWD
tRWD
tCWL
tRWL
tWP
tRCS
VIH
VIL
W
tDH
tDZC
tDS
VIH
VIL
Hi-Z
DQ1~DQ16
(INPUTS)
DATA VALID
tCAC
tAA
tCLZ
VOH
VOL
Hi-Z
Hi-Z
DQ1~DQ16
(OUTPUTS)
DATA
VALID
tRAC
tDZO
tODD
tOEZ
tOEH
tOEA
VIH
VIL
OE
14
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Read-Write, Read-Modify-Write Cycle
tRWC
tRP
tRAS
VIH
VIL
RAS
tCSH
tRPC
tRCD
tRSH
tCRP
tCRP
VIH
VIL
LCAS
(or UCAS)
tCAS
VIH
VIL
UCAS
(or LCAS)
tRAD
tASR
tRAH
tCAH
tASR
tASC
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
A0~A8
tAWD
tCWD
tRWD
tCWL
tRWL
tWP
tRCS
VIH
VIL
W
DQ1~DQ8
(or DQ9~DQ16)
VIH
VIL
(INPUTS)
DQ1~DQ8
(or DQ9~DQ16)
(OUTPUTS)
VOH
Hi-Z
VOL
tDH
tDS
tDZC
DQ9~DQ16
(or DQ1~DQ8)
(INPUTS)
VIH
VIL
Hi-Z
DATA VALID
tCAC
tAA
tCLZ
DQ9~DQ16
(or DQ1~DQ8)
(OUTPUTS)
VOH
Hi-Z
Hi-Z
DATA
VALID
VOL
tRAC
tODD
tOEZ
tOEH
tOEA
tDZO
VIH
VIL
OE
15
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle
tRAS
tRP
VIH
RAS
VIL
tCSH
tHPC
tCAS
tRSH
tCAS
tCP
tRCD
tCP
tCAS
tCRP
VIH
VIL
LCAS/UCAS
tRAD
tCPRH
tCAH
tASR
tASR
tASC
tASC
tRAH
tCAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-3
A0~A8
COLUMN-2
tCAL
COLUMN-1
tCAL
tRCS
tRRH
tRAL
tCAL
tRCH
VIH
VIL
W
tWEZ
tDZC
tRDD
tCDD
Hi-Z
VIH
VIL
DQ1~DQ16
(INPUTS)
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
tDOH
tDOH
Hi-Z
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DQ1~DQ16
(OUTPUTS)
DATA
VALID-3
tRAC
tDZO
tCPA
tCPA
tOEA
tOEZ
tOCH
VIH
VIL
OE
tODD
16
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Read Cycle
tRP
tRAS
VIH
VIL
RAS
tHPC
tCAS
tCSH
tRSH
tCRP
tCP
tRCD
tCP
VIH
VIL
LCAS
(or UCAS)
tCRP
tCAS
tCAS
VIH
VIL
UCAS
(or LCAS)
tRAD
tCPRH
tCAH
tASC
tASR
tASC
tASR
tRAH
tCAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
A0~A8
COLUMN-3
COLUMN-2
tCAL
COLUMN-1
tCAL
tRAL
tCAL
tRRH
tRCS
tRCH
VIH
VIL
W
tDZC
DQ1~DQ8
(or DQ9~DQ16)
VIH
Hi-Z
VIL
(INPUTS)
tCAC
tAA
tREZ
tOHR
DQ1~DQ8
(or DQ9~DQ16)
(OUTPUTS)
VOH
Hi-Z
DATA
VALID-2
VOL
tCLZ
tCPA
tRDD
tCDD
tDZC
DQ9~DQ16
(or DQ1~DQ8)
(INPUTS)
VIH
VIL
Hi-Z
tCAC
tAA
tCAC
tAA
tWEZ
tOFF
tOHC
tDOH
tCLZ
DQ9~DQ16
(or DQ1~DQ8)
(OUTPUTS)
VOH
Hi-Z
DATA
VALID-3
DATA
VALID-1
VOL
tRAC
tDZO
tCPA
tOEA
tOCH
tOEZ
VIH
VIL
OE
tODD
17
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Early Write Cycle
tRAS
tRP
VIH
VIL
RAS
tCSH
tHPC
tCAS
tRSH
tCAS
tCP
tCRP
tRCD
tCAS
tCP
tCRP
VIH
VIL
LCAS/UCAS
tCAL
tCAH
tCAL
tCAH
tASC
tASC
tASR
tRAH
tASC
tASR
tCAH
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
A0~A8
COLUMN-3
COLUMN-1
COLUMN-2
tWCH
tWCH
tWCS
tWCS
tWCS
tWCH
VIH
VIL
W
tDS
tDH
tDH
tDS
tDH
tDS
VIH
VIL
DQ1~DQ16
(INPUTS)
DATA
VALID-2
DATA
VALID-1
DATA
VALID-3
VOH
VOL
Hi-Z
DQ1~DQ16
(OUTPUTS)
VIH
VIL
OE
18
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Early Write Cycle
tRAS
tRP
VIH
VIL
RAS
tHPC
tCSH
tRSH
tCRP
VIH
VIL
LCAS
(or UCAS)
tRCD
tCAS
tCRP
tCAS
tCAS
tCP
tCP
VIH
VIL
UCAS
(or LCAS)
tCAL
tCAH
tCAL
tCAH
tASC
tASR
tRAH
tASR
tCAH
tASC
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
A0~A8
COLUMN-2
COLUMN-3
COLUMN-1
tWCS
tWCH
tWCS
tWCS
tWCH
tWCH
VIH
VIL
W
tDS
tDH
tDS
tDH
DQ1~DQ8
(or DQ9~DQ16)
(INPUTS)
VIH
DATA
VALID-1
DATA
VALID-3
VIL
DQ1~DQ8
(or DQ9~DQ16)
(OUTPUTS)
VOH
Hi-Z
VOL
tDS
tDH
DQ9~DQ16
(or DQ1~DQ8)
(INPUTS)
VIH
VIL
DATA
VALID-2
DQ9~DQ16
(or DQ1~DQ8)
VOH
Hi-Z
VOL
(OUTPUTS)
VIH
VIL
OE
19
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read-Write, Read-Modify-Write Cycle
tRAS
tRP
VIH
RAS
VIL
tRWL
tCSH
tHPRWC
tCAS
tCRP
tCRP
tRCD
tCAS
tCP
VIH
LCAS/UCAS
VIL
tRAD
tCAH
tCWL
tASC
tASR
tRAH
tCAH
tASR
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
A0~A8
COLUMN-2
tAWD
COLUMN-1
tAWD
tCWD
tCWL
tWP
tCWD
tRCS
tRCS
tWP
VIH
VIL
W
tRWD
tCPWD
tDS
tDS
tDH
tDH
tDZC
tDZC
Hi-Z
Hi-Z
VIH
VIL
DQ1~DQ16
(INPUTS)
DATA
VALID-1
DATA
VALID-2
tCAC
tCAC
tAA
tAA
tCLZ
tCLZ
VOH
VOL
Hi-Z
Hi-Z
Hi-Z
DQ1~DQ16
(OUTPUTS)
DATA
VALID-2
DATA
VALID-1
tRAC
tDZO
tCPA
tODD
tOEZ
tODD
tOEZ
tOEH
tOEA
tDZO
tOEA
VIH
VIL
OE
20
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Read-Write, Read-Modify-Write Cycle
tRAS
tRP
VIH
RAS
VIL
tCSH
tRWL
tCRP
VIH
LCAS
VIL
(or UCAS)
tCRP
tCAS
tHPRWC
tCAS
tRCD
tCP
VIH
VIL
UCAS
(or LCAS)
tRAD
tCAH
tCWL
tASC
tASR
tRAH
tCAH
tASR
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
A0~A8
COLUMN-2
tAWD
COLUMN-1
tAWD
tCWD
tCWL
tWP
tCWD
tRCS
tRCS
tWP
VIH
VIL
W
tRWD
tCPWD
DQ1~DQ8
(or DQ9~DQ16)
VIH
VIL
(INPUTS)
DQ1~DQ8
(or DQ9~DQ16)
(OUTPUTS)
VOH
Hi-Z
VOL
tDS
tDS
tDZC
tDH
tDH
tDZC
DQ9~DQ16
(or DQ1~DQ8)
(INPUTS)
Hi-Z
Hi-Z
VIH
VIL
DATA
VALID-2
DATA
VALID-1
tCAC
tCAC
tAA
tAA
tCLZ
tCLZ
DQ9~DQ16
(or DQ1~DQ8)
(OUTPUTS)
VOH
Hi-Z
Hi-Z
Hi-Z
DATA
VALID-1
DATA
VALID-2
VOL
tRAC
tDZO
tCPA
tODD
tODD
tOEZ
tOEH
tOEA
tDZO
tOEZ
tOEA
VIH
VIL
OE
21
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (1)
tRAS
tHPC
tRP
tRWL
VIH
RAS
VIL
tCRP
tCSH
tHPRWC
tCAS
tCRP
tRCD
tRAD
tCAS
tCP
tCP
tCAS
tCWL
VIH
VIL
LCAS/UCAS
tASR
tASC
tASC
tRAH
tCAH
tCAH
tCAH
tASR
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
A0~A8
COLUMN-1
tCAL
COLUMN-2
tWCH
COLUMN-3
tCPWD
tRCS
tWCS
tAWD
tCWD
tCAL
tWP
VIH
VIL
W
tDZC
tDZC
tDH
tDH
tDS
tDS
VIH
VIL
DQ1~DQ16
(INPUTS)
DATA
VALID-2
DATA
VALID-3
tCAC
tAA
tAA
tCAC
tWEZ
tCLZ
tCLZ
VOH
VOL
Hi-Z
DQ1~DQ16
(OUTPUTS)
DATA
VALID-3
DATA
VALID-1
tRAC
tDZO
tCPA
tOEA
tOEA
tOEZ
tOEH
tDZO
tOEZ
tOCH
VIH
VIL
OE
tODD
tODD
22
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (2)
VIH
RAS
VIL
VIH
LCAS/UCAS
VIL
tCP
tASC
tCAS
tCAH
tCAS
tCAH
tASC
tASC
tCAH
VIH
A0~A8
COLUMN-1
COLUMN-2
COLUMN-3
VIL
tCAL
tRCH
tCAL
tWCH
tWCS
VIH
W
VIL
tHCWD
tHAWD
tDH
tDZC
tHPWD
tDS
VIH
Hi-Z
Hi-Z
DQ1~DQ16
(INPUTS)
DATA
VALID-2
VIL
tCAC
tAA
tCPA
tCAC
tAA
tCPA
tCLZ
tWEZ
VOH
Hi-Z
DQ1~DQ16
DATA
DATA
VALID-1
VALID-3
(OUTPUTS)
VOL
tHCOD
tOEA
tOEZ
tDZC
tHAOD
tHPOD
tODD
VIH
OE
VIL
23
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by OE)
tRP
tRAS
VIH
VIL
RAS
tHPC
tCAS
tCSH
tRSH
tCAS
tCRP
tCP
tCRP
tRCD
tCAS
tCP
VIH
VIL
LCAS/UCAS
tRAD
tRAH
tCPRH
tASC
tASR
tASC
tASR
tCAH
tCAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
A0~A8
COLUMN-1
COLUMN-3
tRAL
COLUMN-2
tRRH
tRCS
tRCH
VIH
VIL
W
tWEZ
tDZC
tRDD
tCDD
VIH
VIL
Hi-Z
DQ1~DQ16
(INPUTS)
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
tDOH
tCLZ
Hi-Z
VOH
VOL
Hi-Z
DQ1~DQ16
(OUTPUTS)
DATA
VALID-1
DATA
VALID-2
DATA
VALID-1
DATA
VALID-3
tRAC
tDZO
tCPA
tOEZ
tCPA
tOEZ
tOEA
tOEZ
tCHOL
tOCH
tOEA
VIH
VIL
OE
tOEPE
tODD
tOEPE
24
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by W)
tRAS
tRP
VIH
RAS
VIL
tCSH
tRSH
tCAS
tHPC
tCP
tCRP
tRCD
tCRP
tCAS
tCAS
tCP
VIH
LCAS/UCAS
VIL
tRAD
tCPRH
tASC
tASR
tASC
tASR
tRAH
tCAH
tCAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
A0~A8
COLUMN-1
COLUMN-2
COLUMN-3
tRAL
tRRH
tRCS
tDZC
tRCH
tRCH
tRCS
VIH
VIL
W
tWEZ
tWPE
tRDD
tCDD
VIH
VIL
Hi-Z
DQ1~DQ16
(INPUTS)
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
tDOH
tWEZ
tCLZ
Hi-Z
VOH
VOL
Hi-Z
DQ1~DQ16
(OUTPUTS)
DATA
VALID-1
DATA
VALID-2
DATA
VALID-3
tRAC
tCPA
tCPA
tOEA
tOCH
tDZO
tOEZ
VIH
VIL
OE
tODD
25
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tRPC
tCRP
tCRP
VIH
VIL
LCAS/UCAS
tASR
tASR
tRAH
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
A0~A8
VIH
VIL
W
VIH
VIL
DQ1~DQ16
(INPUTS)
VOH
VOL
Hi-Z
DQ1~DQ16
(OUTPUTS)
VIH
VIL
OE
26
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle, Extended Refresh Cycle *
tRC
tRC
tRAS
tRP
tRP
tRAS
VIH
VIL
RAS
tCSR
tRPC
tRPC
tCHR
tRPC
tCRP
tCSR
tCHR
VIH
VIL
LCAS/UCAS
tCPN
tASR
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
A0~A8
tRRH
tRCS
tRCH
VIH
VIL
W
VIH
VIL
DQ1~DQ16
(INPUTS)
tREZ
tOHR
tOFF
tOHC
VOH
VOL
DQ1~DQ16
(OUTPUTS)
Hi-Z
tOEZ
VIH
VIL
OE
27
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 32)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
RAS
VIL
tCRP
tRCD
tRSH
tCHR
VIH
LCAS/UCAS
VIL
tRAD
tRAH
tASR
tASR
tCAH
tASC
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
A0~A8
tRCS
tRAL
tRRH
VIH
VIL
W
tCDD
tDZC
tRDD
Hi-Z
VIH
VIL
DQ1~DQ16
(INPUTS)
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
Hi-Z
VOH
VOL
Hi-Z
DQ1~DQ16
(OUTPUTS)
DATA VALID
tRAC
tDZO
tOEZ
tODD
tOEA
tORH
VIH
VIL
OE
Note 32 : Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
28
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Self Refresh Cycle * (Note 30)
tRASS
tRP
tRPS
VIH
VIL
RAS
tRPC
tRPC
tCRP
tCSR
tCHS
VIH
VIL
LCAS/UCAS
tCPN
tASR
VIH
VIL
ROW
ADDRESS
A0~A8
tRRH
tRCH
tRCS
VIH
VIL
W
tRDD
tCDD
VIH
VIL
DQ1~DQ16
(INPUTS)
Hi-Z
tREZ
tOHR
tOFF
tOHC
Hi-Z
VOH
VOL
DQ1~DQ16
(OUTPUTS)
tOEZ
tODD
VIH
VIL
OE
29
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Note 30 : Self refresh sequence
Two refreshing methods should be used properly depending on
the low pulse width (tRASS) of RAS signal during self refresh
period.
1. Distributed refresh during Read/Write operation
(A) Timing Diagram
Read / Write Cycle
Self Refresh Cycle
tRASS³ 100µs
Read / Write Cycle
tNSD
tSND
RAS
last
first
refresh cycle
refresh cycle
Table 2
Read / Write
Self Refresh
Self Refresh
Read / Write
Read / Write Cycle
CBR distributed
refresh
tNSD£250µs
tNSD£16µs
tSND£250µs
RAS only
distributed refresh
tSND£16µs
(B) Definition of distributed refresh
tREF
tREF / 512
tREF / 512
RAS
refresh
cycle
read/write
cycles
refresh
cycle
read/write
cycles
refresh
cycle
Definition of CBR distributed refresh
(Including extended refresh)
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end
of self refresh operation to the falling edge of RAS signal in the
first CBR refresh cycle during read/write operation period should
be set within tSND (shown in table 2).
The CBR distributed refresh performs more than 512
constant period (250µs max.) CBR cycles within 128 ms.
Definition of RAS only distributed refresh
All combinations of nine row address signals (A0 ~ A8) are
selected during 512 constant period (16µs max.) RAS only
refresh cycles within 8.2 ms.
1.2 RAS only distributed refresh
Switching from read/write operation to self refresh operation.
The time interval tNSD from the falling edge of RAS signal in the
last RAS only refresh cycle during read/write operation period to
the falling edge of RAS signal at the start of self refresh
operation should be set within 16µs.
Note:
Hidden refresh may be used instead of CBR refresh.
RAS/CAS refresh may be used instead of RAS only refresh.
Switching from self refresh operation to read/write operation.
The time interval tSND from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the first CBR refresh cycle during read/write operation period
should be set within 16µs.
1.1 CBR distributed refresh
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the last
CBR refresh cycle during read/write operation period to the falling
edge of RAS signal at the start of self refresh operation should be
set within tNSD (shown in table 2).
30
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
2. Burst refresh during Read/Write operation
(A) Timing diagram
Read / Write
Self Refresh
Read / Write
tRASS³ 100µs
tNSB
tSNB
RAS
first
refresh cycles
refresh cycles
511 cycles
refresh cycles
511 cycles
last
refresh cycles
Table 3
Read / Write
Self Refresh
Self Refresh
Read / Write
Read / Write Cycle
CBR burst
refresh
tNSB£8.2ms
tSNB£8.2ms
RAS only
burst refresh
tNSB+tSNB£8.2ms
(B) Definition of burst refresh
8.2ms
RAS
refresh cycles
512 cycles
read/write cycles
Definition of CBR burst refresh
The CBR burst refresh performs more than 512 continuous
CBR cycles within 8.2 ms.
Definition of RAS only burst refresh
All combination of nine row address signals (A0~A8) are
selected during 512 continuous RAS only refresh cycles
within 8.2 ms.
2.2 RAS only burst refresh
2.1 CBR burst refresh
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the first
RAS only refresh cycle during read/write operation period
to the falling edge of RAS signal at the start of self refresh
operation should be set within tNSB (shown in table 3).
Switching from read/write operation to self refresh operation.
The time interval tNSB from the falling edge of RAS signal in the
first CBR refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within 8.2 ms.
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end
of self refresh operation to the falling edge of RAS signal in the
last RAS only refresh cycle during read/write operation period
should be set within tSNB (shown in table 3).
Switching from self refresh operation to read/write operation.
The time interval tSNB from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the last CBR refresh cycle during read/write operation period
should be set within 8.2 ms.
31
M5M4V4265CJ,TP-5,-5S:under development
相关型号：
M5M4V4265CTP-6T
EDO DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40
MITSUBISHI
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