M5M4V16169DTP-8 [MITSUBISHI]
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM; 16MCDRAM ： 16M （ 1M - WORD 16位）缓存的DRAM与16K （ 1024字×16位） SRAM
| 型号： | M5M4V16169DTP-8 |
| 厂家： | 
Mitsubishi Group |
| 描述： | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| 文件： | 总64页 (文件大小：731K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Preliminary
This document is a preliminary Target Spec. and some of the contents are subject to change without notice.
PINCONFIGURATION
DESCRIPTION
(TOP VIEW)
Vss
Ad9
Ad8
Ad7
Ad11
Ad10
As9
As8
As7
As6
DQ15
Vss
DQ14
DQ13
VccQ
DQ12
Vcc
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
1
2
3
4
5
6
7
8
9
Vcc
DQCl
DQCu
CC1#
CC0#
The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input
1.
registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word
by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single
monolithic circuit. The block data transfer between the DRAM and the data
transfer buffers (RB1/RB2/WB1/WB2) is performed in one instruction cycle, a
fundamental advantage over a conventional DRAM/SRAM cache.
The RAM is fabricated with a high performance CMOS process, and is ideal for
large-capacity memory systems where high speed, low power dissipation, and
low cost are essential. The use of quadruple-layer polysilicon process combined
with silicide and double layer aluminum wiring technology, a single-transistor
dynamic storage stacked capacitor cell, and a six-transistor static storage cache
cell provide high circuit density at reduced costs.
WE#
CS#
CMd#
CMs#
K
DQ0
Vss
DQ1
DQ2
VddQ
DQ3
10
11
12
13
14
15
16
17
2.
400 mil
70Pin
TSOP
Type II
Vss
DQ4
VccQ
DQ5
DQ6
Vss
DQ11
VccQ
DQ10
DQ9
Vss
DQ8
MCH
G#
As5
As4
As3
Ad6
Ad5
Ad4
Ad3
ADF#
Vss
19
20
21
22
23
24
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
0.65mm
Lead
Pitch
FEATURES
DQ7
MCL 25
SRAM
Access/cycle
DRAM
Access/cycle
Power
Dissipation (Typ)
Type name
As0
As1
As2
RAS#
CAS#
DTD#
Ad0
Ad1
Ad2
Vcc
26
27
28
DRAM: 530
SRAM: 860
29
5.6ns/7ns
6.4ns/8ns
8.0ns/10ns
8.0ns/15ns
M5M4V16169TP/RT-7
M5M4V16169TP/RT-8
49ns/70ns
56ns/80ns
30
31
DRAM: 500
SRAM: 800
32
33
34
DRAM: 430
SRAM: 660
DRAM: 330
SRAM: 420
M5M4V16169TP/RT-10
M5M4V16169TP/RT-15
60ns/90ns
35
Package code:70P3S-L
75ns/120ns
Vss
Ad9
Ad8
Ad7
Ad11
Ad10
As9
As8
As7
As6
DQ15
Vss
DQ14
DQ13
VccQ
DQ12
Vcc
70
1
2
3
4
5
6
7
DQCl
DQCu
CC1#
CC0#
WE#
CS#
CMd#
CMs#
K
DQ0
Vss
DQ1
DQ2
69
# 70-pin,400-mil TSOP (type II ) with 0.65mm
lead pitch and 23.49mm package length.
68
67
66
# Multiplexed DRAM address inputs for reduced pin
count and higher system densities.
# Selectable output operation (transparent / latched /
registered) using set command register cycle.
# Single 3.3V +/- 0.3V Power Supply.
(3.3V +/- 0.15V for -7 part)
# 2048 refresh cycles every 64ms (Ad0->Ad10).
# Programmable burst length (1,2,4,8) and burst
sequence (sequential,interleave) with no latency.
# Synchronous design for precise control with
an external clock (K).
# Output retention by advanced mask clock (CMs#).
# All inputs/outputs low capacitance and LVTTL
compatible.
# Separate DRAM and SRAM address inputs
for fast SRAM access.
65
: Master Clock
: Chip Select
K
CS#
64
63
8
: DRAM Clock Mask
: Row Addr. Strobe
: Column Addr. Strobe
: Data Transfer Direction
: DRAM Address
: SRAM Clock Mask
: Control Clocks
CMd#
RAS#
CAS#
DTD#
Ad
CMs#
CC0#,CC1#
WE#
DQC(u/l)
As
G#
DQ
Vcc
VccQ
Vss
62
9
61
10
11
12
60
59
58
13
14
15
16
17
57
400 mil
70Pin
TSOP
Type II
VccQ
DQ3
Vss
56
: Write Enable
55
Vcc
: I/O Byte Control
: SRAM Address
: Output Enable
: Data I/O
: Power Supply
: DQ Power Supply
: Ground
:Address Fetch clock
This pin can be None-Connect.
:Must Connect Low
:Must Connect High
54
DQ4
VccQ
DQ5
DQ6
Vss
DQ7
MCL
As0
As1
As2
RAS#
CAS#
DTD#
Ad0
52
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DQ11
VccQ
51
0.65mm
Lead
Pitch
DQ10 50
49
DQ9
Vss 48
47
DQ8
MCH
ADF#
46
G# 45
MCL
MCH
44
As5
As4 43
42
As3
Ad6
Ad5
Ad4
Ad3
ADF#
Vss
41
# Page Mode capability.
# Auto Refresh capability.
# Self Refresh capability.
40
39
Ad1
Ad2
Vcc
38
37
36
Package code:70P3S-M
1
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Vcc
VccQ
Vss
BLOCK DIAGRAM 1
54 35
12
48 59 70
23
36
15 20 51 56
17
1
29
RAS#
66
65
69
68
Ad11
Ad10
(Row Address strobe)
30
31
CAS#
(Column Address strobe)
Col.3-7
Column Block Decoder
Ad9
Ad8
Row 0-11
DTD#
(Data Transfer Direction)
DRAM
Address
Input
Ad7 67
1M bit
DRAM
Array
8 CMd#
Mask
(Clock Mask for DRAM)
1M x 16=
16M DRAM
Ad6
41
40
39
0 1
7
Ad5
Ad4
KBuffer
7
CS#
(Chip Select)
Timing
control
10 K
Ad3 38
Ad2
(Master ClocK)
Sense Amplifier and I/O control
34
Ad1 33
9
CMs#
Mask
(Clock Mask for SRAM)
Command (0-6)
0
1
2
6
5
4
WE#
7
Ad0
32
(Write Enable)
CC0#
(Control Clock 0)
RB1
RB2
Read Buffer1
Read Buffer2
CC1#
(Control Clock 1)
WB2M
WB2 Mask
WB2
WB1
Write Buffer 2
WB1
Mask
37 ADF#
Write Buffer 1
WB1M
(Address Fetch)
DQCu(Enable upper)
3
64
63
62
As9
2 DQCl(Enable lower)
0 1
As8
As7
2
7
11 DQ0
As3-9
S/A and I/O
13
DQ1
16
SRAM
Address
input
14 DQ2
As6 61
As5 44
Din
Buffer
Col.Decoder
16
DQ3
19 DQ4
43
As4
As3
As2
21
DQ5
22 DQ6
24
42
28
Main
Amp.
DQ7
47 DQ8
49
1Kx16=16K
SRAM
As0-2
1KBit
SRAM
Array
DQ9
50 DQ10
52
As1 27
26
As0
DQ11
55 DQ12
57
DQ13
58 DQ14
60 DQ15
45
G#
(Output Enable)
2
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
BLOCK DIAGRAM 2
8X16 Block
DRAM
1MX16
Ad3-7
1 of 32
Decode
DRAM Row Decoder
8X16
Ad0-11
8X16
1 of 4096 Decode
RB1
Lower Byte Upper Byte
WB2
Lower Byte Upper Byte
As0-2
1of8Decode
DQ0-7
DQ8-15
RB2
As0-2
1of8
Lower Byte Upper Byte
8X16
16 bits
Decode
DQs
WB1
Lower Byte Upper Byte
16 bits
16 bits
8X16
8X16
8X16 Block
16 bits
SRAM
1KX16
As0-2
1of8Decode
SRAM Row Decoder
As3 - 9
1 of 128 Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
3
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
FUNCTION TRUTH TABLE
(SRAM
address)
DRAM
SRAM
As
Ad (DRAM address)
Mnemonic
Previous
Previous
CODE
DQC
(u/l)
Ad2 Ad1 Ad0
CS#
H
X
L
RAS# CAS# DTD#
CMs#
As0-9
Ad0-11
CC0# CC1#
WE#
X
CMd#
H
L
X
X
H
H
H
H
L
X
X
H
H
L
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP
SPD
LBM
DES
X
H
X
H
H
L
X
L
X
H
H
H
H
H
H
H
H
H
H
X
L
X
H
L
X
L
As0-9
As0-9
As3-9 (2)
As3-9 (2)
As0-9
As0-9
As0-2(2)
As0-2(2)
SR
L
L
SW
BRT
L
H
H
H
H
L
H
L
L
L
L
BWT
BRTR
BWTW
BR
L
L
H
H
H
H
H
L
L
L
L
L
H
L
BW
L
L
L
DPD
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X (1) X(1) X(1)
X
X
H
H
H
H
H
L
X
H
DNOP
DRT
Ad3-7
(Col.Block)
(2)
0
0
0
Ad3-7 (2)
(Col.Block)
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
0
0
0
0
0
0
1
1
0
1
0
1
DWT1
Ad3-7
(Col.Block)
(2)
DWT1R
DWT2
Ad3-7
(Col.Block)
(2)
Ad3-7
(Col.Block)
(2)
DWT2R
Ad3-7
(Col.Block)
(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
0
0
1
1
0
1
0
1
L
L
L
L
1
1
1
1
DWT3
DWT3R
DWT4
DWT4R
ACT
Ad3-7
(Col.Block)
(2)
Ad3-7
(Col.Block)
(2)
Ad3-7
(Col.Block)
(2)
Ad0-11
(Row Add.)
L
L
X
X
X
X
X
X
X
X
X
X
X
X
H
H
L
L
H
H
H
L
PCG
X
ARF
L
X
X
X
X
X
X
H(7)
L
L
H
X
SRF
SCR
L
L
X
X
X
X
X
X
X
X
X
X
X
X
H (8)
H
L
L
L
L
H
L
X
Command
NOTES
1) For the DPD function, the RAS#, CAS# and DTD# inputs are
DON'T CARE except for the L,L,H combination. (Respectively).
2) The unused addresses must be set to Low.
5) Actual number of bits transfer depends on the state of the DTBW Mask and
the DQCU/DQCL inputs. Note: If DQC(U/L) is Low, the corresponding DQ(s)
is(are) disabled (Input and Output Buffer). SR,SW,BR and BW cycles
with DQCU and DQCL Low result in a Deselect SRAM operation.
3) Use New: If BW or BWT or BWTW is initiated the same cycle
as DWT1 or DWT1R, new data is loaded into the buffer
and transferred to DRAM.
6) Following a DWT1 or DWT1R cycle, the entire WB1 Transfer Mask is Set .
(i.e. , data can no longer be transferred from WB1 to DRAM.)
Succeeding Buffer-Writes or Buffer Write Transfers will Clear Mask bits.
7) CMd# during current cycle must be High (see timing diagram for Auto-Refresh).
8) CMd# during current cycle must be Low (see timing diagram for Self-Refresh).
4) Clear 1 or 2 Transfer Mask Bits (as addressed by As0-2 and DQCU/L).
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
FUNCTION TRUTH TABLE
Data Transfer Buffers
DQ pin
Write Buffers
WB1 WB2
Xfer Masks
Read
Buffer
RB1,2
WB1
WB2
Function
Din
Dout
Hi-Z
Mask
Mask
-
-
-
-
-
-
No Operation
SRAM Power Down&
Data retention
DRAM Power Down
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Suspend
Hi-Z
No operation
No operation
No operation
SRAM->DO
Byte
mask
Deselect SRAM
-
-
Hi-Z
Valid SRAM Read
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Valid Hi-Z SRAM Write
DIN->SRAM
RB2->SRAM
SRAM->WB1
-
Load
-
Use
-
-
-
Hi-Z Buffer Read Xfer
Hi-Z Buffer Write Xfer
Clear
Mask
-
-
Use
Valid Buffer Read Xfer & Read RB2->SRAM->DO
Clear
Mask
Load
-
-
Use
-
Valid Hi-Z Buffer Read Xfer & Read DIN->SRAM->WB1
-
-
Valid Buffer Read
RB2->DO
(4)
Clear 1
or 2 bits
Load
Valid Hi-Z
Buffer Write
DIN->WB1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DRAM Power Down
DRAM No OPeration
DRAM Read Xfer
No operation
No operation
Load
DRAM->RB1->RB2
(3)
WB1->WB2->DRAM
WB1->WB2
(6)
Use
Load/
Use
Load/
Use
Use
-
-
-
DRAM Write Xfer1
(6)
Use
Load/
Use
Load/
Use
(3)
Use
-
Load
-
-
-
-
DRAM Write Xfer1& Read
->DRAM->RB1->RB2
Use
-
Use
-
DRAM Write Xfer2
WB2->DRAM
WB2->DRAM
->RB1->RB2
DRAM Write Xfer2& Read
Load
-
Use
-
-
Use
-
-
-
-
Load/
Use
DRAM Write Xfer3
Load
Use
-
WB1->WB2->DRAM
WB1->WB2
->DRAM->RB1->RB2
Load/
Use
(3)
DRAM Write Xfer3& Read
DRAM Write Xfer4
Load Load
Use
-
-
-
-
-
-
-
Use
Use
-
-
-
WB2->DRAM
-
-
Load
-
-
DRAM Write Xfer4& Read
WB2->DRAM->RB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DRAM Activate
Page Call
DRAM Precharge
Auto Refresh
Self Refresh Entry
Set Command Register
Function
Data Transferred (max)
Function
Data Transferred (max)
DO: Data Out
DIN: Data In
WB1: Write Buffer 1
WB2: Write Buffer 2
RB: Read Buffer
(5)
(5)
WB2 --> RB
DRAM --> RB
RB --> Dout
RB --> SRAM
128 bits (8X16bit-block)
128 bits (8X16bit-block)
Din --> SRAM
Din --> WB1
8/16 bits
8/16bits
(5)
8/16 bits
SRAM --> WB1
WB1 --> WB2
WB2 --> DRAM
128 bits (8X16bit-block)
128 bits (8X16bit-block)
128 bits (8X16bit-block)
128 bits (8X16bit-block)
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
PIN DESCRIPTIONS(1)
Master Clock Provides the fundamental timing and the internal clock frequency for
K
Input
the CDRAM. All external timing parameters (with the exception of G# in read cycle
and CMd# in Self refresh cycle) are specified with respect to the rising edge of K.
DRAM Clock Mask controls the operation of the internal DRAM master clock (K).
When CMd# is Low at the rising edge of K, the internal DRAM master clock (K) for
the following cycle is ceased and input stages are powered-off, resulting in a DRAM
Power Down.
CMd#
Input
Row Address Strobe is used in conjunction with Master clock K (depending on the
states of CMd#, CAS#, and DTD#) to activate the DRAM (latching the Row Address
lines and accessing 1 of 4096 rows), initiate a DRAM precharge cycle, perform a
DRAM Read or Write Transfer, DRAM Write Transfer & Read, set the command
registers, start an Auto-Refresh cycle, enter a Self-Refresh cycle,create a DRAM
NOP cycle, or power down the DRAM.
RAS#
CAS#
Input
Input
Column Address Strobe is used in conjunction with the Master Clock K to latch the
Column addresses. When preceded by RAS# in a DRAM access cycle, CAS#
initiates a DRAM Write Transfer (WB1/2 -> DRAM, if DTD#=L), DRAM Write
Transfer & Read (WB1/2 -> DRAM -> RB, if DTD#=L) or DRAM Read Transfer
(DRAM -> RB, if DTD#=H), depending on the state of DTD# (see DTD# pin
description).
Data Transfer Direction controls DRAM-to-RB(read) / WB-to-DRAM (write)
direction. If preceded by a RAS# low cycle, both CAS# and DTD# low (on the
rising edge of K) initiate a DRAM Write Transfer cycle. If DTD# stays High with the
above conditions, a DRAM Read Transfer cycle results. DTD# can also initiate
DRAM Activate, DRAM Precharge, Auto-Refresh, Set-Command Register, and
Self Refresh cycles.
DTD#
Input
Input
DRAM Address Lines are Multiplexed to reduce pin count. Ad0-Ad11 (@
RAS=low,CAS=high,DTD=high, K=Rising edge) specify the Row Address of the
DRAM to activate and refresh the selected page and Ad3-Ad7 (@
RAS=high,CAS=low,K=Rising edge) specify the Block Address of the DRAM. In
addition, Ad0-Ad2 (@ RAS=high,CAS=low, K=Rising edge) specify the transfer
operation of the DRAM . Also Ad0-Ad9 (@RAS=low,CAS=low, DTD=low,
K=Rising Edge) are used as the command in set command register cycle.
Ad0-Ad11
The Chip Select controls the operation of the CDRAM. When CS#=H at the rising
edge of K and the previous CMd# or CMs# is high, the chip is in No Operation
mode.
CS#
Input
Input
SRAM Clock Mask controls the operation of the internal SRAM master clock (Ks).
When CMs# is asserted at a rising edge of K, the internal SRAM master clock for
the following cycle is suspended, resulting in the power down of the SRAM portion
of the circuit, including the Sense Amps. CMs# can also be used to retain output
data during SRAM power-down.
CMs#
6
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MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
PIN DESCRIPTIONS(2)
DQCu/l are I/OByte control signals. If G#=Low, DQCu/l have a control of output
impedence: DQCu controls upper DQs (DQ8-15) & DQCl controls lower DQs (DQ0-7).
DQCu/l also control both input data during SRAM Writes or Buffer Writes and transfer
mask during Buffer Writes. (WB1 transfer Masks for each byte are written (bits are
cleared) during Buffer Writes depending on DQCu/l inputs.)
Input
DQCl,DQCu
Write Enable controls SRAM and Buffer read and write operations. A high on the WE#
pin causes either a Buffer Read, SRAM Read, Buffer Read Transfer and/or a Buffer
Read Transfer & Read to occur (depending on the state of the CC0# and CC1# bits).
A low on the WE# pin causes either a Buffer Write, SRAM Write, Buffer Write Transfer
and/or a Buffer Write Transfer & Write to occur (depending on the state of the CC0#
and CC1# inputs)
WE#
Input
The Control Clock Inputs control SRAM and Buffer operations. CC0# is Low for all
Buffer Writes, Reads, and Transfers, and High for all other SRAM operations. CC1# is
high for all Buffer Read Transfers and Buffer Write Transfers , and Deselect SRAM.
CC0#,CC1#
As0-As9
Inputs
SRAM Addresses are non-multiplexed, and access 1024 - 16-bit words ( configured as
128 Rows X 8 Columns X 16 Bits, where the Block Size is 8 X 16) in the SRAM array.
As0-As3 select word address within a block, and As3-As9 select the SRAM row(block).
Inputs
Input
The Output Enable is an asynchronous input. G#=high forces the outputs to high
impedence.
G#
Output operation is either transparent, latched, or registered depending on the state of
the command register. The Data Lines for the CDRAM are asynchronously controlled
by G#.
Inputs /
Outputs
DQ0-DQ15
VccQ is the DQ power supply and allows the device to operate in a mixed voltage
system (e.g., 5V data bus). As specified in the Table: Recommended Operating
Conditions, VccQ must be greater-than or equal-to the highest voltage experienced
by the data bus. For 3.3V system operation, VccQ may be tied to Vcc.
VccQ
Supply
7
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (1)
No Operation. Outputs are high-impedance. All input buffers remain active.
NOP
If CMs#=Low at the rising edge of K, the SRAM enters SRAM Power Down at the next rising
edge of K. During this mode, the internal SRAM K clock becomes inactive. The Output
Buffers remain enabled and are controlled by G#. All input buffers of SRAM clocks and
SRAM addresses are inactive.
SRAM
Power-Down
All transfer functions and input/output operations to and from the SRAM and Buffer are
disabled. This cycle is useful for output impedance control (Hi-Z,Low-Z) without G#. Output
buffers are active during this cycle for registered output mode control.
Deselect SRAM
Data is read from the SRAM to the I/O pins. Addresses As0-As9 are used to select the data
to be read. As3-As9 decode the SRAM Row (=Block), and As0-As2 decode (1 of 8) the 16-
bit word. DQCu and DQCl control the impedence (High-Z/Low-Z) of the upper and lower
bytes, respectively.
SRAM Read
Data is written from the I/O pins to the SRAM. Addresses As0-As9 are used to select the
location to be written. As3-As9 decode the SRAM Row (=Block), and As0-As2 decode
(1of8) the 16-bit word to be written. DQCUu and DQCl control Upper and Lower byte writes,
respectively.
8X16Block
DRAM
1MX16
Ad3-7
1of32
Decode
DRAM RowDecoder
8X16
Ad0-9
1of4096Decode
8X16
RB1
WB2
DQ0-7
DQ8-15
Upper Byte
Lower Byte
SRAM Write
Lower Byte
As0-2
1of8Decode
Upper Byte
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Lower Byte Upper Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
8
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (2)
Data is transferred from the Read Buffer (RB2) to the SRAM. Addresses As3-9 select the
SRAM row to which the 8X16 bit block is to be written. Addresses As0-As2 must be set low.
8X16Block
DRAM
1M X 16
Ad3-7
1of32
Decode
DRAM RowDecoder
8X16
Ad0-11
1of4096Decode
8X16
RB1
Upper Byte
Lower Byte
WB2
Buffer Read
Transfer
DQ0-7
DQ8-15
Lower Byte Upper Byte
As0-2
1of8Decode
8X16
RB2
Lower Byte Upper Byte
16bits
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
Data is transferred from the SRAM to the Write-Buffer1 (WB1). Addresses As3-As9 decode
the SRAM Row (=8X16 bit block) to be transferred. Addresses As0-As2 must be set low.
The Buffer Write Transfer cycle "clears" all transfer mask bits in the WB1 Mask (allowing all
data to be transferred in a successive DRAM Write Transfer cycle).
8X16Block
DRAM
1M X 16
Ad3-7
1of32
Decode
DRAM RowDecoder
8X16
Ad0-11
1of4096Decode
8X16
Buffer Write
Transfer
RB1
WB2
Upper Byte
DQ0-7
DQ8-15
Lower Byte
As0-2
Lower Byte Upper Byte
1of8Decode
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
9
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (3)
Data is transferred from the Read Buffer (RB2) to the SRAM, and simultaneously, data (16
bit word) is read from the RB2 to the I/O pins. Addresses As3-9 select the SRAM Row to
which the 8X16 bit block is to be written. Addresses As0-As2 decode the 16-bit word to be
read.
8X16Block
DRAM
1M X 16
Ad3-7
1of32
Decode
DRAM RowDecoder
Ad0-11
1of4096Decode
8X16
8X16
Buffer Read
Transfer &
SRAM Read
RB1
Lower Byte
Upper Byte
WB2
DQ0-7
DQ8-15
As0-2
Lower Byte Upper Byte
1of8Decode
RB2
8X16
16bits
Lower Byte Upper Byte
As0-2
1of8Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
Data is first written from the I/O pins to SRAM as decoded by As0-As9. Then, the SRAM
Row (=Block) decoded by As3-As9 is transferred to the Write-Buffer1 (WB1). The Buffer
Write Transfer cycle "clears" all transfer mask bits in the WB1 Mask (allowing all data to be
transferred in a successive DRAM Write Transfer cycle). DQCu and DQCl control Upper
and Lower byte writes respectively, however all transfer mask bits in the WB1 are cleared.
8X16Block
DRAM
1M X 16
Ad3-7
1of32
Decode
DRAM RowDecoder
Buffer Write
Transfer &
SRAM Write
8X16
Ad0-11
1of4096Decode
8X16
RB1
WB2
Upper Byte
Lower Byte
DQ0-7
DQ8-15
As0-2
1of8Decode
Lower Byte
Upper Byte
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
8X16
DQs
16bits
8X16
WB1
X
Lower Byte Upper Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
10
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (4)
Data is read from the Read Buffer (RB2) to the I/O pins. Addresses As0-As2 are used to
select (1 of 8) the 16-bit word to be read. Addresses As3-As9 must be set low for this
operation.
8X16Block
DRAM
1M X 16
Ad3-7
1of32
Decode
DRAM RowDecoder
Ad0-11
1of4096Decode
8X16
8X16
RB1
Upper Byte
Lower Byte
WB2
As0-2
1of8Decode
DQ0-7
DQ8-15
Lower Byte Upper Byte
Buffer Read
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
Data is written from the I/O pins to the Write-Buffer1. Addresses As0-A2 are used to select
(1of8) the 16-bit word to be written. Addresses As3-As9 must be set low for this operation.
The transfer mask bits associated with the Upper and Lower bytes are cleared in the WB1
Mask. DQCu and DQCl control Upper and Lower byte writes (and associated tranfer mask
bits), respectively.
8X16Block
DRAM
1M X 16
Ad3-7
1of32
Decode
DRAM RowDecoder
Ad0-11
1of4096Decode
8X16
8X16
RB1
Buffer Write
Upper Byte
Lower Byte
WB2
DQ0-7
DQ8-15
As0-2
1of8Decode
Lower Byte Upper Byte
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
11
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (5)
If CMd#=Low at the rising edge of K, the DRAM enters DRAM Power Down at the next rising
DRAM
Power-Down
edge of K. During this mode, the internal DRAM K clock becomes inactive. Also all input
buffers of DRAM clocks and DRAM addresses are inactive. Note that the latency of DRAM
Read Transfer cycle is not counted up in this cycle.
The DNOP cycle is used when no other DRAM operations are desired, holding the DRAM in
its present (precharge/activate) state.
DRAM NOP
A Block (8x16) is transferred from the DRAM to the Read Buffer1 and 2 (RB1,RB2) as specified
by Addresses Ad3-Ad7. Addresses Ad8-Ad11 and Ad0-Ad2 must be set to Low. After the
Latency Period (specified in the Access Latency Table) new data will be present in the Read
Buffer2. Prior to the Latency timeout, old data will be present in the RB2. (Notes 1,2,4)
8X16Block
DRAM
1M X 16
Ad3-7
1of32
Decode
DRAM RowDecoder
Ad0-11
1of4096Decode
8X16
DRAM Read
Transfer
8X16
RB1
Upper Byte
Lower Byte
WB2
DQ0-7
DQ8-15
As0-2
1of8Decode
Lower Byte Upper Byte
RB2
8X16
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
12
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (6)
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by
Addresses Ad3-Ad7. Addresses Ad8-Ad11 must be set to Low. The Mask present in WB1 is
also transferred to WB2 and controls the data written to the DRAM. After data has been
transferred from WB1 to WB2 in the present cycle, the entire WB1 Mask is Set. (Notes 3,4)
8X16Block
DRAM
1M X 16
Ad3-7
1of32
Decode
DRAM RowDecoder
8X16
Ad0-11
1of4096Decode
DRAM Write
8X16
Transfer1
RB1
WB2
Upper Byte
Lower Byte
DQ0-7
DQ8-15
As0-2
Lower Byte Upper Byte
1of8Decode
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by
Addresses Ad3-Ad7. Addresses Ad8-A11 must be set to Low. The transfer mask present in
WB1 is also transferred to WB2 and controls the data written to the DRAM. The block to which
the data is written in DRAM is simultaneously transferred to the Read Buffer.(Notes 2,3,4)
8X16Block
DRAM
1M X 16
Ad3-7
1of32
Decode
DRAM RowDecoder
Ad0-11
1of4096Decode
8X16
DRAM Write
Transfer1
& Read
8X16
RB1
Upper Byte
Lower Byte
WB2
DQ0-7
DQ8-15
As0-2
1of8Decode
Lower Byte Upper Byte
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
MITSUBISHI ELECTRIC
13
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (7)
Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3-
Ad7. Addresses Ad8-Ad11 must be set to Low. The WB2 Mask controls the data written to
the DRAM. With the DWT2 function, the WB2 data and WB2 transfer mask remain unchanged.
(Note 4)
8X16Block
DRAM
1M X 16
Ad3-7
1of32
Decode
DRAM RowDecoder
8X16
Ad0-11
1of4096Decode
8X16
DRAM Write
Transfer2
RB1
WB2
Upper Byte
Lower Byte
DQ0-7
DQ8-15
As0-2
1of8Decode
Lower Byte Upper Byte
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3-
Ad7. Addresses Ad8-Ad11 must be set to Low. The WB2 transfer mask controls the data
written to the DRAM. With the DWT2 function, the WB2 data and WB2 transfer mask remain
unchanged. The block to which the data is written in DRAM is simultaneously transferred to the
Read Buffer1 and 2. (Notes 1,2,4)
8X16Block
DRAM
1MX16
Ad3-7
1of32
Decode
DRAM RowDecoder
8X16
Ad0-11
1of4096Decode
8X16
DRAM Write
Transfer2
& Read
RB1
WB2
Upper Byte
Lower Byte
DQ0-7
DQ8-15
As0-2
1of8Decode
Lower Byte Upper Byte
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
MITSUBISHI ELECTRIC
14
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (8)
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by
Addresses Ad3-Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte
MaskRegister controls the data written to the DRAM. The Byte Mask Register is set at Load Byte
Mask cycle,where corresponding byte masks are set depending on DQ data in the cycle. (Note
4,5) The data of WB1 and the mask data of WBM1 are tranferred to WB2 and WBM2, however
WBM1/2 is not used in this cycle.
8X16Block
DRAM
256KX16
Ad3-7
1of32
Decode
DRAM RowDecoder
8X16
Ad0-11
1of4096Decode
DRAM Write
Transfer3
8X16
RB1
Upper Byte
WB2
Lower Byte
DQ0-7
DQ8-15
As0-2
1of8Decode
Lower Byte Upper Byte
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by
Addresses Ad3-Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte
MaskRegister controls the data written to the DRAM. The block to which the data is written in
DRAM is simultaneously transferred to the Read Buffer.(Notes 1,2,4,5)
8X16Block
DRAM
256KX16
Ad3-7
1of32
Decode
DRAM RowDecoder
8X16
Ad0-11
1of4096Decode
DRAM Write
Transfer3
& Read
8X16
RB1
Upper Byte
Lower Byte
WB2
DQ0-7
DQ8-15
As0-2
1of8Decode
Lower Byte Upper Byte
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
MITSUBISHI ELECTRIC
15
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (9)
Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3-
Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte MaskRegister
controls the data written to the DRAM. With the DWT4 function, the WB2 data and WB2 Mask
remain unchanged. (Note 4,5)
8X16Block
DRAM
256KX16
Ad3-7
1of32
Decode
DRAM RowDecoder
Ad0-11
1of4096Decode
8X16
DRAM Write
8X16
Transfer4
RB1
Upper Byte
Lower Byte
DQ0-7
WB2
DQ8-15
As0-2
1of8Decode
Lower Byte Upper Byte
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3-
Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte MaskRegister
controls the data written to the DRAM. With the DWT4R function, the WB2 data and WB2
transfer mask remain unchanged. The block to which the data is written in DRAM is
simultaneously transferred to the Read Buffer. (Notes 1,2,4,5)
8X16Block
DRAM
256KX16
Ad3-7
1of32
Decode
DRAM RowDecoder
Ad0-11
DRAM Write
Transfer4
& Read
1of4096Decode
8X16
8X16
RB1
Upper Byte
Lower Byte
WB2
DQ0-7
DQ8-15
As0-2
1of8Decode
Lower Byte Upper Byte
8X16
RB2
16bits
Upper Byte
Lower Byte
As0-2
1of8
Decode
DQs
16bits
8X16
WB1
X
Upper Byte
Lower Byte
16bits
8X16
8X16Block
16bits
SRAM
1KX16
As0-2
1of8Decode
SRAM RowDecoder
As3-9
1of128Decode
16
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (10)
Addresses are latched from the Ad0-Ad11 inputs by the rising edge of K. Internally, a DRAM row is
selected (Page Call) in preparation for a DRAM Read or Write Transfer cycle. A DRAM Precharge
cycle must separate all DRAM Activate cycles.
DRAM
Activate
Internally, the active DRAM Row is deselected (completing the refresh process) and page-mode is
disabled. The DRAM is precharged prior to another DRAM Activate cycle.
DRAM
Precharge
Internally, a DRAM row is selected and refreshed (as addressed by an internal, self-incrementing
counter), followed by an internally generated Precharge cycle. The Auto refresh cycle can be
implemented only if the DRAM is in Precharge state (i.e., a Precharge or Auto-Refresh cycle
occurred more recently than an Acitvate cycle). DRAM Auto-Refresh is similar to a CAS-Before-
RAS (CBR) mode in standard DRAMs.
DRAM
Auto-Refresh
All clock buffers are suspended, and CMd# asynchronously controls Self Refresh (CMd# rising
edge initiates exit from Self Refresh). During Self Refresh, device enters a low power mode, with
2048 automatic refresh cycles.
DRAM
Self Refresh
When SCR is initiated,the addresses present on the Ad0-Ad11 DRAM Address pins determine the
DRAM Read Transfer Latency, the Output Mode (transparent / latched / registered), and WB1
transfer mask mode (set-all/ no change). No DRAM operation is executed in this cycle. Refer to
the SCR Truth Table for legal Address values.
Set
During SCR cycle and the following 3 clock cycles(totally 4 clock cycles), only NOP,DNOP orDPD
are allowed in DRAM portion and only NOP,DES or SPD are done in SRAM portion. The set
commands are valid at least after the above 4 clocks later and the previous function is not
guaranteed to work if it has not been completed.(i.e. DRT ,DWT1&R,DWT2&R and SR,BR and
BRTR with registered output mode.)
Command
Register
Notes:
1) This function is performed in a Latency period specified in the Access Latency Table.
2) After the Latency Period (specified in the Access Latency Table) new data will be present
in the Read Buffer2. Prior to the Latency timeout, old data will be present in the RB2.
3) After data has been transferred from WB1, the entire WB1 Mask is Set.
4) Valid Ad0-Ad2 addresses are shown in the FUNCTION TRUTH TABLE.
Power-On sequence
Before starting normal operation, the following power on sequence is necessary.
1) Apply power and maintain stable power (pause) for 500us.
2) Perform a precharge (PCG) operation.
3) After tRP, perform 8 auto refresh commands (ARF) with adequate interval (tRC).
4) Issue set command register (SCR) to initilize the mode register.
After this sequence, the RAM is in idle state and ready for normal operation.
Note that DNOP / DPD and DES / SPD or NOP command will be the stand-by command
for the above power sequence.
Vcc must be powered-on at the same time or before VccQ is on.
And Vcc must be powered-off at the same time or after VccQ is off.
17
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Output Operations
Output appears from the rising edge of K clock.
Transparent
SR
SR
DES
SR
SR
DES
K
K
DQC
G#
DQC
tKHA
tKHA
G#
tGLA
tKHQZ
tKHQX
Q
Q
DQ0-15
DQ0-15
tGLQ
tGHQ
Latched
Output appears from the falling edge of K clock.
DES
SR
SR
SR
DES
SR
K
K
This outputmode
DQC
tKHA
t
G#
was deleted.
tKLQZ
tKLQX
tGLA
tGHQ
Q
Q
DQ0-15
DQ0-15
tGLQ
Registered
Output appears from the rising edge of K clock.
DES
SR
DES
SR
SR
SR
SR
SR
K
K
tK
DQC
DQC
tKHAR
tK
tKHAR
G#
G#
tKHQZ
tGHQ
tGLA
tGLQ
tKHQZ
tKHQX
Q
Q
DQ0-15
DQ0-15
18
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
tK
tKH
tKL
K,K#
tS tH
CMd#
tCMDS
tCSS
tRS
tCMDH
tCSH
tRH
CS#
RAS#
tCS
tCH
CAS#
tDTS
tDTH
DTD#
CMs#
tCMSS
tC0S
tCMSH
tC0H
CC0#
tC1S
tWS
tC1H
tWH
CC1#
WE#
DQC(u / l)
tDQCS
tSADF
tDQCH
ADF#
tHADF
Ad0-11
As0-9
tAS
tDS
tAH
tDH
DQ0-15
(Input)
19
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Load Byte Mask
Byte mask allocation during DWT3 and DWT4
Byte Mask Register
Lower DQs
Upper DQs
DQ0
DQ2
DQ4
DQ6
DQ8
DQ10
DQ12
DQ14
DQ13 DQ15
DQ1
DQ3
DQ5
DQ7
DQ9
DQ11
Lower
Upper
Block
address
0
1 2
3
4
5 6
7
Column Block
(16 byte)
0 : mask, no write
1 : unmask, write enable
20
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DWT3 / DWT4
1023
0 ---
DRAM row
Write data / Mask data
0
DRAM
column
128 set
0
1
2
byte
mask
0
1
0
written
3
4
1
1
5
6
1
0
0
7
Lower
8bit
Upper8
bit
Byte
mask
SRAM
WB1/WB2
lower byte
255
upper byte
1 1 1 1
0
0
1 1 1 0 0 1
1
0 0 0
->DQ15
Byte
mask bit
DQ0->
Write / Mask logic
DWT2
DWT1
addition
As0-2
DWT3/DWT4
DQ0-15
DQCl
DQCu
WM1
WM2
Load Byte Mask
(LBM)
WB2
WB1
DRAM
SRAM
DWT1/DWT3
DWT2/DWT4
21
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DWT3-DWT4 for Window clear(Block Write)
shadow clear / window clear
Window Boundary
Page boundary
PCG
DWT4
DWT4 DNOP
DNOP
DNOP DWT3
DWT4 DNOP DWT4 DNOP
ACT
DES
LBM DES
DES
DES
DES
DES LBM DES LBM DES
BWT
Color data is transferred from WB2 to
DRAM column block with new byte mask.
Color data is transferred from WB2 to DRAM column block with byte mask.
Color data is transferred from WB1 through WB2 to DRAM column block with byte mask,
which is loaded by Load Byte Mask cycle(LBM). The byte mask data is valid from the LBM cycle
immediately and lasts until the next LBM cycle is initiated.
Color data is loaded from SRAM cache to WB1.(BWT)
Page call.(ACT)
22
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Burst Mode (1)
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMs#
ADF#
CC0#
CC1#
Accept interrupt
for inputting new
address w/o gap.
WE#
DQC(u / l)
C1
C1
C2
C2
C3
C3
As0-2
As3-11
G#
L
Q1
Q2
Q3
DQ0-15
Q3
Q1+1
Q1+3
Q3+3
Q1+2
Q2+1
Q3+1 Q3+2
DES
SR
SR
SR
SR
SR
SR
SR
SR
DES
SR
SR
SR
SRAM address and
DRAM address can
be multiplexed
using this duration
for DRAM control
23
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Burst Mode (2)
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMs#
ADF#
CC0#
CC1#
WE#
DQC(u / l)
C1
C1
C2
C2
C3
C4
C4
C5
C6
C6
As0-2
C3
C5
As3-11
G#
L
Q1
Q4
D2
Q5
DQ0-15
Q3
Q6
Q1+1
D1+2
DES
DES
SPD
DES
SW
SR
SR
SR
SR
SPD
SW
SR
SR
Burst address is
not incremented
by DES, SPD.
ADF#=Low
is equal to
non-burst
mode.
"Insert wait" is possible.
M5M4V16169D keeps compatibility setting ADF# low or setting Burst length=1 by SCR cycle.
(Ad7, Ad8 and Ad9=0)
24
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
**-15 spec is the same as M5M4V16169TP/RT-15
ABSOLUTE MAXIMUM RATINGS
(Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7
Vss=0V, unless otherwise noted)
Conditions
Ratings
Unit
Symbol
Vcc
Parameter
With respect to Vss
-0.5 ~
Supply Voltage
Input Voltage
Output Voltage
Output Current
4.6
4.6
4.6
V
V
V
I
-0.5 ~
-0.5 ~
V
VO
O
50
1000
0 ~
mA
I
Pd
Power Dissipation
Operating Temperature
Storage Temperature
mW
°C
Topr
70
-65 ~ 150
°C
Tstg
RECOMMENDED OPERATING CONDITIONS
(Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7
Vss=0V, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
3.0
Max
3.6
Typ.
3.3
Vcc
Supply Voltage
V
Vss
Supply Voltage
Supply Voltage for Output
0
3.3
V
V
V
0
3.0
2.0
0
3.6
VccQ
(LVTTL)
High-level Input Voltage clock and add.
Vdd+0.3
VIH
High-level Input Voltage master clock (K)
High-level Input Voltage data pin
Low-level Input Voltage all inputs
(LVTTL)
(LVTTL)
2.2
2.0
V
V
V
Vdd+0.3
VddQ+0.3
0.8
VIH
VIH
(LVTTL)
VIL
-0.3
CAPACITANCE
(Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7
Vss=0V, unless otherwise noted)
Symbol
Parameter
Limits (MAX)
Test Condition
I=Vss
Unit
pF
I(A)
I(C)
Input Capacitance, Address pin
Input Capacitance, Clock pin
Input Capacitance, I/O pin
5
5
7
C
V
f=1MHz
pF
pF
C
=25mVrms
V
CI/O
I
25
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
**-15 spec is the same as M5M4V16169TP/RT-15
AVERAGE SUPPLY CURRENT from Vcc
(Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7
Vss=0V, unless otherwise noted)
Limits (MAX)
Symbol
IccS
Unit
mA
mA
mA
mA
mA
mA
mA
Condition
-7
-10
-15
-8
Average supply current of SRAM operating, tK=min.
260
200
140
240
DRAM=DPD
output open
data input=H or L
Average supply current of DRAM operating, tRC=min.
SRAM=SPD
150
130
60
50
5
IccD
160
140
60
50
5
130
110
50
40
5
100
80
30
25
5
Average supply current of DRAM page-mode tPC=min.
SRAM=SPD
IccD(PG)
Icc(STN1)
LVTTL standby, tK=min, DRAM=DNOP&SRAM=DES,
or NOP all input=stable.
output open
data input=H or L
CMOS standby, tK=min, DRAM=DNOP&SRAM+DES,
Icc(STN2)
or NOP all input=stable.
output open
data input=H or L
CMOS Power Down current, CMd#=CMs#=L,tK=min.
CMOS Self Refresh current, CMd#=CMs#=L,tK=
Icc(PD)
1
1
1
1
Icc(SRF)
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7
Vss=0V, unless otherwise noted)
Limits
Symbol
Parameter
Test Condition
Unit
V
Min.
Max
VOH(DC)*(LVTTL)
2.4
-
High-level Output Voltage (DC)
IOH= -2mA
IOL= 2mA
-
VOL(DC)*(LVTTL)
0.4
V
Low-level Output Voltage (DC)
Off-state Output Current
Input Current
O
Q floating V
IOZ
II
=0 ~VddQ
-10
-10
uA
uA
10
10
V =0 ~VddQ+0.3V
IH
* VOH(AC) and VOL(AC) are the reference levels for AC measurements.
VOH(DC) and VOL(DC) are the final levels the outputs reach.
VTT
50ohm
VOUT
30pF
AC Condition
(Access Time)
MITSUBISHI ELECTRIC
26
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
**-15 spec is the same as M5M4V16169TP/RT-15
TIMING REQUIREMENTS
(CLK pulse, input signals setup / hold time to CLK edge)
(Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7
Vss=0V, unless otherwise noted)
Input Pulse Levels:
Input Timing Measurement Reference Level:
VIH=3.0V,VIL=0.0V (LVTTL)
1.5V (LVTTL)
Limits
Unit
-7
-8
-10
-15
Symbol
Parameter
Max Min.
Max
Max
Min.
Max Min.
Min.
Clock Cycle Time
tK
tKH
tKL
tS
7
3
3
3
1
8
3
3
10
3.5
4
3
1
15
5
5
4
1
ns
ns
ns
Clock High Pulse Width
Clock Low Pulse Width
Setup Time for Inputs
Hold Time for Inputs
ns
ns
3
1
tH
MITSUBISHI ELECTRIC
27
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MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
**-15 spec is the same as M5M4V16169TP/RT-15
TIMING REQUIREMENTS
(Read, Write, Refresh)
(Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7
Vss=0V, unless otherwise noted)
Input Pulse Levels:
Input Timing Measurement Reference Level:
VIH=3.0V,VIL=0.0V (LVTTL)
1.5V (LVTTL)
Limits
-8
Symbol
-7
-10
-15
Min.
Parameter
Unit
Max
Max
Min.
Min.
Min.
Max
Max
tREF
Refresh Cycle Time
64
64
64
64
ms
ns
ns
ns
ns
tRP
21
21
24
24
80
80
16
56
30
30
Precharge Time
40
30
120
120
30
tRCD
tRC*
Delay Time, Add Strb. Row to Col.
DRAM Activate-Read Cycle Time
DRAM Activate-Write Cycle Time
Page Cycle Time
70
70
14
49
49
14
14
90
90
20
60
60
20
20
tWC*
tPC
ns
ns
10,000
10,000
10,000
tRAS
tRASP
tRWL
tRSH
12,000
70
Activate Time
100,000
Page mode Activate Time
Write to Precharge Lead Time
100,000
100,000
100,000
56
16
16
ns
ns
ns
70
20
20
Read to Precharge Hold Time
*Note: When tRP and tRAS = Min. values, tRC and tWC = tRP + tRAS.
MITSUBISHI ELECTRIC
28
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
**-15 spec is the same as M5M4V16169TP/RT-15
SWITCHING CHARACTERISTICS
(Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7
Vss=0V, unless otherwise noted)
Limits
Symbol
Parameter
-7
Min.
-8
Unit
ns
-10
Min.
-15
Min.
Min.
Max
20
Max
20
Max
20
10
Max
20
15
tCBF
Buffer-Fill from DRAM Read Transfer
Access Time from K-High Edge
tKHA
ns
ns
tKHQX
tKHQZ
tKHAR
Output Active Time from K-High Edge
2
2
3
3
12
3
3
10
7
Output Disable Time from K-High Edge
Access Time from K-High Edge
5
ns
ns
ns
ns
5.6
6.4
tKHQXR Output Active Time from K-High Edge
2
2
2
2
2
2
Output Disable Time from K-High Edge
tKHQZR
7
5.6
8
6.4
10
7
tGLA
ns
ns
Access Time from G#-Low Edge
Output Active Time from G#-Low Edge
Output Disable Time from G#-High Edge
tGLQ
tGHQ
0
2
0
2
0
2
5.6
6.4
ns
8
MITSUBISHI ELECTRIC
29
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
non-G# controlled Write & Read (DES control)
( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down )
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMs#
CS#
CC0#
CC1#
WE#
DQC(u / l)
C1
C1
C2
C2
C3
C4
C5
C5
C6
C6
As0-2
As3-9
C3
C4
G#
L
Q4
Q2
D3
Q6
D1
D5
DQ0-15
DES
SR
SW
DES
SR
SPD
DES
SPD
SW
DES
SR
SW
SPD
Note : Output is transparent.
DRAM operation can be freely performed.
30
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
G# controlled Write & Read
( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down )
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
H
CMs#
CS#
CC0#
L
CC1#
WE#
DQC(u / l)
C2
C2
C3
C3
C4
C5
C5
C6
C6
C7
C7
C1
C1
As0-2
As3-9
C4
G#
Q2
Q5
Q7
D4
Q6
D1
DQ0-15
Q3
SR
DES
SR
SPD
DES
SW
SR
DES
SW
SPD
SPD
SR
SR
Note : Output is transparent.
DRAM operation can be freely performed.
31
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DQC controlled Write & Read
( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down )
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMs#
CS#
CC0#
CC1#
WE#
DQCu
DQCl
As0-2
C1
C2
C3
C4
C5
C6
As3-9
G#
C1
C2
C3
C4
C5
C6
L
DQ8-15
Q6
D5
D1
Q2
Q2
D3
Q4
D1
DQ0-7
DES
SR
(u/l)
SW
(l)
DES
SR
(u)
SPD
DES
SPD
SW
(u/l)
DES
SR
(l)
SW
(u)
SPD
H or L
DRAM operation can be freely performed.
Note : Output is transparent.
32
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Registered Output control
( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down )
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMs#
CS#
CC0#
CC1#
WE#
DQC(u / l)
As0-2
As3-9
C1
C1
C2
C2
C3
C3
C4
C4
C5
C6
C6
C7
C7
C8
C8
C5
L
G#
D1
Q4
Q6
Q2
D3
D5
D7
Q8
DQ0-15
DES
SR
SW
SW
SR
SPD
DES
SPD
SW
SR
SR
SW
DES
Note : Output is registered. DRAM operation can be freely performed.
MITSUBISHI ELECTRIC
33
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Buffer Read Transfer (RB2 -> SRAM)
Buffer Read Transfer & SRAM Read (RB2 -> SRAM -> Output)
2
4
6
8
10
12
14
11
1
3
5
7
9
13
K
H
CMs#
CS#
CC0#
L
CC1#
WE#
DQC(u / l)
C1
C2
C3
C4
C5
C6
C7
C8
As0-2
As3-9
(C1) (C1) (C1)
(C1)
(C1)
(C5) (C5)
(C5)
(C5)
G#
L
Q2
Q4
Q5
Q7
Q1
Q3
Q8
Q6
DQ0-15
DES
SR
SR
BRTR
SR
DES
DES DES
DES
BRT
SR
SR
SR
SR
DRAM operation can be freely performed.
Note : Output is transparent.
(REV 1.0) Jul. 1998
34
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Buffer Write Transfer (SRAM -> WB1)
Buffer Write Transfer & SRAM Write (Input -> SRAM -> WB1)
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
H
CMs#
CS#
CC0#
L
CC1#
WE#
DQC(u / l)
C2
C2
As0-2
As3-9
C1
C3
G#
L
WB1(0-7)
DQ0-15
D1
D3
D2
old
D2
DES
BWT
DES
DES
BWT
DES
DES DES
DES
DES
DES
BWTW
DES
DES
DRAM operation can be freely performed.
Note : Output is transparent.
MITSUBISHI ELECTRIC
35
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Buffer Write (Input -> WB1)
Buffer Read (RB2 -> Output)
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
H
L
CMs#
CS#
CC0#
CC1#
WE#
DQC(u / l)
C1
C2
C3
C4
C5
C6
C7
C8
As0-2
As3-9
L
G#
WB1(0-7)
D3
D1
D2
D4
D4
WB1 Mask(0-7)
DQ0-15
D3
D1
D2
Q5
Q7
D2
D4
Q6
Q8
D1
D3
BW
BW
DES
DES
BR
BR
DES DES
BW
BW
DES
DES
BR
BR
Note : Output is transparent.
MITSUBISHI ELECTRIC
DRAM operation can be freely performed.
36
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
NO - Operation of SRAM
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
H
CMs#
CS#
CC0#
CC1#
WE#
DQC(U / l)
AS0-9
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NO-Operation Mode
CMd#
RAS#
CAS#
DRAM operation can be freely performed.
DTD#
Ad0-11
37
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
NO - Operation of DRAM
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
H
CS#
CMd#
RAS#
CAS#
DTD#
Ad0-11
NOP
NOP
NOP
NOP
NOP
NOP
NOP NOP
NOP
NOP
NOP
NOP
NO-Operation Mode
CMs#
CC0#
CC1#
WE#
SRAM operation can be freely performed.
DQC(u/l)
G#
As0-9
DQ0-15
38
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Power Down / DRAM Activate / DRAM Precharge
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMd#
CS#
RAS#
CAS#
DTD#
Row
Ad0-11
DNOP DNOP DNOP DNOP
DPD
DPD
PCG
DPD
DPD
DPD
DPD
ACT
DPD
CMs#
CC0#
CC1#
WE#
SRAM operation can be freely performed.
DQC(u/l)
G#
As0-9
DQ0-15
DPD is recommended during no operation to save power.
39
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
RAS only Refresh cycle
DRAM Power Down / DRAM Activate / DRAM Precharge
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMd#
CS#
tRC
tRAS
tRP
RAS#
CAS#
DTD#
Row
Ad0-11
DNOP DNOP DNOP DNOP
DPD PCG
DPD
PCG
DPD
DPD DPD
DPD
ACT
CMs#
CC0#
CC1#
WE#
SRAM operation can be freely performed.
DQC(u/l)
G#
As0-9
DQ0-15
40
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Auto Refresh
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
H
H
H
H
CMd#
tRC
CS#
RAS#
CAS#
DTD#
Ad0-11
DNOP
DNOPDNOP
DNOP
DPD
DPD
DPD
DPD ARF
DPD
DPD
ARF
DPD
DPD
Note: DRAM must be in Precharge state prior to Auto-Refresh cycle.
DRAM new commands except for NOP,DNOP and DPD can be set
after tRC later from ARF command input.
CMs#
CC0#
CC1#
WE#
SRAM operation can be freely performed.
DQC(u/l)
G#
As0-9
DQ0-15
41
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Self Refresh
1
3
5
2
4
2
4
6
1
3
K
Inhibit falling edge.
L
L
L
CMd#
H
H
CS#
RAS#
L
CAS#
DTD#
H
Row
Ad0-11
DNOP
DNOP
DNOP
DNOP
DNOP ACT
DNOP SRF
Halt
DNOP
Halt
Halt
Self Refresh Mode
SRAM Power Down Mode
tRC for Recovery
Self Refresh
Entry
Self Refresh
SRAM Power Down
Exit
Self Refresh Entry: (Note: DRAM must be in Precharge state prior to Self-Refresh Entry)
Previous CMd#=H, Present CMd#=L, CS#=RAS#=CAS#=L, DTD#=H
(CMd# must remain low to maintain Self Refresh).
Self Refresh Exit (in order):
a) resume K clock
b) CMd#=H
c) Wait tRC for recovery
d) Resume normal operation
42
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=1
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
tRC
CMd#
CS#
tRAS
tRP
RAS#
tRCD
tRSH
CAS#
DTD#
Row
Row
Ad0-2
Ad0-Ad2=Low
**Col
Ad3-11
tCBF
New Data
New Data
Old Data
RB1
Latency x tK
Old Data
RB2
DRAM
SRAM
DNOP
DNOP
DPD PCG
DPD DPD
DRT
DPD
BR
DPD
BR
DPD
BR
DPD
BR
ACT
BR
PCG
BR
DPD
BR
BR
BR
BR
BR
BR
BR
BR
Old
Old
Old
Old
Old
New
New
New New
Old
Old
Old
Old
New
DQ0-15
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
(REV 1.0) Jul. 1998
SRAM operation can be freely performed.
43
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=2
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
tRC
CMd#
CS#
tRAS
tRP
RAS#
tRCD
tRSH
CAS#
DTD#
Row
Row
Ad0-2
Ad3-9
Ad0-Ad2=Low
**Col
tCBF
New Data
New Data
Old Data
RB1
RB2
Latency x tK
Old Data
DRAM
SRAM
DNOP
DNOP
DPD PCG
DPD DPD
DRT
BR
DPD
BR
DPD
BR
DPD
BR
DPD
BR
ACT
BR
PCG
BR
DPD
BR
BR
BR
BR
BR
BR
BR
Old
Old
Old
Old
Old
New
New
New
DQ0-15
Old
Old
Old
Old
Old New
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
SRAM operation can be freely performed.
44
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=3
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
tRC
CMd#
CS#
tRAS
tRP
RAS#
tRCD
tRSH
CAS#
DTD#
Row
Row
Ad0-2
Ad0-Ad2=Low
**Col
Ad3-11
tCBF
Old Data
New Data
New Data
RB1
RB2
Latency x tK
Old Data
DRAM
SRAM
DNOP
DNOP
DPD PCG
DPD DPD
DRT
DPD
DPD
BR
DPD
BR
DPD
BR
ACT
BR
PCG
DPD
BR
BR
BR
BR
BR
BR
BR
BR
BR
BR
Old
Old
Old
Old
Old Old
New
Old New New
DQ0-15
Old
Old
Old
Old
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
45
SRAM operation can be freely performed.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=4
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
tRC
CMd#
CS#
tRAS
tRP
RAS#
tRCD
tRSH
CAS#
DTD#
Row
Row
Ad0-2
Ad0-Ad2=Low
**Col
Ad3-11
tCBF
Old Data
New Data
New Data
RB1
RB2
Latency x tK
Old Data
DRAM
SRAM
DNOP
DNOP
DNOP
DPD PCG
DPD DPD
DRT
BR
DPD
BR
DPD
BR
DPD
BR
ACT
BR
PCG
BR
DPD
BR
BR
BR
BR
BR
BR
BR
BR
Old
Old
Old
Old
Old
Old
New
Old New
DQ0-15
Old
Old
Old
Old
Old
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
46
SRAM operation can be freely performed.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Read Transfer (Pipe-lined Page-Mode) Latency set=1
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMd#
CS#
tRASP
tPC
RAS#
tPC
tPC
tPC
tPC
tRSH
tRCD
CAS#
DTD#
Row
Row
Ad0-2
Ad0-Ad2=Low
**C1
**C2
**C3
**C4
**C5 **C6
Ad3-11
tCBF
tCBF tCBF
tCBF
tCBF
tCBF
C2
C3
C6
C6
C4
C5
C1
Old Data
RB1
RB2
Latency Latency Latency Latency
Latency x tK Latency x tK
C1
x tK
x tK
x tK
x tK
C3
C4
C5
C2
Old Data
DRAM
SRAM
DNOP
DNOP
DNOP
DNOP
DPD ACT
DRT
BR
DRT
BR
DRT
BR
DRT
BR
DRT
BR
DRT
BR
PCG
BR
BR
BR
BR
BR
BR
BR
Q6
BR
Q1
Q2
Q4
Q6
Old
Old
Q1
Q2
Q3
Q5
Q6
DQ0-15
Old
Old
Pipe-lined Page mode
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
47
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Read Transfer Latency set=2
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMd#
CS#
tRASP
tPC
RAS#
tPC
tRSH
tRCD
CAS#
DTD#
Row
Row
Ad0-2
Ad0-Ad2=Low
**C1
**C2
**C3
**C4
**C5 **C6
Ad3-11
tCBF
tCBF tCBF
tCBF
tCBF
tCBF
C1
tCBF
C2
C6
tCBF
C4
C3
C5
Old Data
RB1
tCBF
C1
Old Data
C6
C2
RB
DRAM
DNOP
DNOP
DNOP
DNOP
DPD ACT
DRT
BR
DRT
BR
PCG
BR
DRT
BR
DRT DRT
BR
DRT
BR
SRAM
BR
BR
BR
BR
BR
BR
Q6
BR
BR
Q6
Q1
Q2
Q2
Old
Old
Q2
Q1
Q2
Q2
DQ0-15
Old
Old Old
If next DRT happens within the latency,
new data does not transferred to RB.
However this operation is not guaranteed.
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
(REV 1.0) Jul. 1998
48
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Read Transfer Latency set=3
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMd#
CS#
tRASP
RAS#
tPC
tPC
tRSH
tRCD
CAS#
DTD#
Row
Row
Ad0-2
Ad0-Ad2=Low
**C1
**C2
**C3 **C4
Ad3-11
tCBF
tCBF
tCBF
tCBF
C4
C1
Latency x tK
C2
Latency x tK
C1
C3
Old Data
RB1
Latency x tK
C4
C2
RB2
Old Data
DRAM
SRAM
DNOP
DNOP DNOP
DNOP DNOP
DNOP
DPD ACT
DRT
BR
PCG
BR
DRT
BR
DRT
BR
DRT
BR
BR
BR
BR
BR
BR
BR
Q4
BR
BR
BR
Q1
Q1 Q2
Q2
Old
Old
Q1
Q2
Q2
DQ0-15
Old
Old Old Old
If next DRT happens within the latency,
new data does not transferred to RB.
However this operation is not guaranteed.
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
(REV 1.0) Jul. 1998
49
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Read Transfer Latency set=4
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMd#
CS#
tRASP
RAS#
tPC
tRSH
tRCD
CAS#
DTD#
Row
Row
Ad0-2
Ad0-Ad2=Low
**C1
**C2
**C3
Ad3-11
tCBF
tCBF
tCBF
Old Data
C3
C2
C1
RB
Latency x tK
Latency x tK
C1
RB
C3
BR
Old Data
DRAM
SRAM
DNOP
DNOP DNOP DNOP
DNOP
DNOP DNOP
DPD ACT
DRT
DRT
BR
DRT
BR
PCG
BR
BR
BR
BR
BR
BR BR
BR
BR
BR
BR
Q1
Q1
Old
Old
Old
Q1
Q3
Q1
Old
Old Old Old
Q1 Q1
DQ0-15
If next DRT happens within the latency,
new data does not transferred to RB.
However this operation is not guaranteed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
(REV 1.0) Jul. 1998
SRAM operation can be freely performed.
50
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 1 (WB1->WB2->DRAM)
Buffer Write (DIN->WB1)
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
tRC
CMd#
CS#
tRP
tRAS
RAS#
tRCD
tRWL
CAS#
DTD#
Row
Row
Ad0-2
Ad3-11
WB2
Ad0-Ad2=Low
**Col
New Data[WB1(0-7)]
Old Data
C3
C4
C5
C1
C6
C7
C0
C2
C0
C2
C1
C3
C4
WB1
DRAM
SRAM
DNOP
DNOP
DPD PCG
DPD DPD
DWT1
BW
DPD
BW
DPD
BW
DPD
DPD
BW
ACT
BW
PCG
BW
DPD
BW
BW
BW
DES BW
BW
BW
BW
D0
D2
D4
D6
D0
D2
D4
D1
D3
D5
D7
D1
D3
D5
DQ0-15
Please refer to next page in detail.
SRAM operation can be freely performed.
MITSUBISHI ELECTRIC
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
(REV 1.0) Jul. 1998
51
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 1 (WB1->WB2->DRAM)
Buffer Write (DIN->WB1)
detail
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
tRC
CMd#
CS#
tRP
tRAS
RAS#
tRCD
tRWL
CAS#
DTD#
Ad0-2
Row
Row
Ad0-Ad2=Low
**Col
Ad3-11
WB2 [0-7]
WB1[0]
New Data[from WB1(0-7)]
0
Old Data
0
WB1 mask[0]
1
WB1[1]
1
2
3
WB1 mask[1]
2
WB1[2]
WB1 mask[2]
3
WB1[3]
WB1 masl[3]
4
WB1[4]
4
WB1 mask[4]
5
WB1[5]
WB1 mask[5]
WB1[6]
6
WB1 mask[6]
7
WB1[7]
WB1 mask[7]
DNOP
DNOP
DPD PCG
DPD DPD
DWT1
BW
DPD
BW
DPD
BW
DRAM
SRAM
DPD
DES
DPD
BW
ACT
BW
PCG
BW
DPD
BW
BW
BW
BW
BW
BW
BW
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D7
D5
DQ0-15
52
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 1 (WB1->WB2->DRAM)
Buffer Write Transfer (SRAM->WB1)
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
tRC
CMd#
CS#
tRP
tRAS
RAS#
tRCD
tRWL
CAS#
DTD#
Row
Row
Ad0-2
Ad3-11
WB2
Ad0-Ad2=Low
**Col
Old Data
Old Data
New Data[WB1(0-7)]
New
Data
Next New Data
WB1
DNOP
DNOP
DRAM
SRAM
DPD PCG
DPD DPD
DWT1
BWT
DPD
SW
DPD
SW
DPD
SW
DPD
ACT
SW
PCG
SW
DPD
SW
SW
SW
SW
SW
SW
SW
BWT
D0
D2
D4
D6
D0
D2
D1
D3
D5
D7
D1
D3
DQ0-15
Please refer to next page in detail.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
SRAM operation can be freely performed.
53
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 1 (WB1->WB2->DRAM)
Buffer Write Transfer (SRAM->WB1)
detail
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
tRC
CMd#
CS#
tRP
tRAS
RAS#
CAS#
DTD#
Ad0-2
tRCD
tRWL
Row
Row
Ad0-Ad2=Low
**Col
Ad3-11
WB2 [0-7]
New Data[from WB1(0-7)]
0
Old Data
WB1[0]
0
1
2
WB1 mask[0]
WB1[1]
1
WB1 mask[1]
WB1[2]
2
3
WB1 mask[2]
WB1[3]
3
4
WB1 masl[3]
WB1[4]
4
WB1 mask[4]
5
WB1[5]
5
6
WB1 mask[5]
WB1[6]
6
7
WB1 mask[6]
7
WB1[7]
WB1 mask[7]
DNOP
DNOP
DPD PCG
DPD DPD
DWT1
BWT
DPD
SW
DPD
SW
DPD
DPD
SW
D4
ACT
PCG
SW
DPD
SW
DRAM
SRAM
SW
SW
SW
BWT
SW
SW
D3
SW
D5
SW
D0
D2
D6
D0
D2
DQ0-15
D1
D7
D1
D3
54
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Write Transfer 1 (WB1->WB2->DRAM)
Buffer Write (DIN->WB1)
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMd#
CS#
tRP
tRASP
tPC
RAS#
tRCD
tRWL
CAS#
DTD#
Row
Row
Ad0-2
Ad3-11
WB2
Ad0-Ad2=Low Ad0-Ad2=Low
**Col
**Col
New
Data[WB1(0-7)]
Next Data[WB1(0-1)]
Old Data
C2
C3
C4
C5
C6
C7
C0
C1 C2
C3
C0
C1
C4
WB1
DRAM
SRAM
DPD PCG
DPD DPD
DNOP DWT1 DNOP DWT1 DNOP
DPD
BW
DPD
DPD
BW
ACT
BW
PCG
BW
BW
BW
BW
BW
DES BW
BW
BW
BW
BW
D0 D1 D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4 D5
DQ0-15
Please refer to next page in detail.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
(REV 1.0) Jul. 1998
SRAM operation can be freely performed.
55
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Write Transfer 1 (WB1->WB2->DRAM)
Buffer Write (DIN->WB1)
detail
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMd#
CS#
tRP
tRASP
RAS#
tPC
tRCD
tRWL
CAS#
DTD#
Ad0-2
Row
Row
Ad0-Ad2=Low Ad0-Ad2=Low
**Col
**Col
Ad3-11
New Data
Next Data[WB1(0-1)]
WB2 [0-7]
WB1[0]
Old Data
[from WB1(0-7)]
0
0
WB1 mask[0]
1
WB1[1]
1
WB1 mask[1]
2
WB1[2]
2
WB1 mask[2]
3
WB1[3]
3
WB1 masl[3]
4
WB1[4]
4
WB1 mask[4]
5
WB1[5]
WB1 mask[5]
WB1[6]
6
WB1 mask[6]
7
WB1[7]
WB1 mask[7]
DNOP
BW
7
DNOP
DNOP
DPD
BW
DPD
DES
DPD
BW
ACT
BW
PCG
BW
PCG
BW
DWT1
BW
DWT1
BW
DPD
BW
DRAM
SRAM
DPD DPD
BW
BW
BW
BW
1
3
5
1
3
5
0
2
4
6
0
2
4
DQ0-15
56
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 1&Read (WB1->WB2->DRAM->RB) Latency set=1
Buffer Write (DIN->WB1)
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
tRC
CMd#
CS#
tRP
tRAS
RAS#
tRCD
tRWL
CAS#
DTD#
Ad0=High
Row
Row
Ad0-2
Ad3-11
WB2
Ad1-Ad2=Low
**Col
Old Data
New Data[WB1(0-7)]
2
4
4
6
2
0
1
3
5
7
0
1
3
WB1
tCBF
tCBF
New Data[WB1(0-7)]
New Data[WB1(0-7)]
Old Data
Old Data
RB1
RB2
Latency x tK
tCBF
DWT1R
DNOP
DNOP
DPD PCG
DPD
BW
PCG DPD
DPD
BW
DPD
DPD
BW
DPD ACT
BW
DPD
BW
DRAM
SRAM
BW
BW
BW
DES BW
BW
BW
BW
BW
0
2
4
6
0
2
4
1
3
5
7
1
3
5
DQ0-15
New Data on RB appears as to latency set count. See DRT timing chart.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
(REV 1.0) Jul. 1998
SRAM operation can be freely performed.
57
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 2 (WB2->DRAM)
1
3
5
7
9
11
13
2
4
6
8
10
12
14
K
CMd#
CS#
tRP
tRASP
tPC
RAS#
tRCD
tRWL
CAS#
DTD#
Ad1=High
Row
Row
Ad0-2
Ad3-11
WB2
Ad0-Ad2=Low Ad0,Ad2=Low
**Col
**Col
NoChange
New
Data[WB1(0-7)]
Old Data
2
4
6
0
2
4
0
1
3
5
7
1
3
WB1
DRAM
SRAM
DNOP
DNOP
DNOP
DPD
DPD
BW
DPD
BW
DPD
DPD
BW
DPD ACT
BW
DWT1
BW
DWT2
BW
PCG
PCG
BW
BW
DES BW
0
BW
BW
BW
BW
2
4
6
0
2
4
1
3
5
7
1
3
5
DQ0-15
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
58
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer2 & Read (WB2->DRAM->RB1-> RB2) Latency set=1
1
3
5
7
9
11
13
2
4
6
8
10
12
14
K
CMd#
CS#
tRP
tRASP
tPC
RAS#
tRCD
tRWL
CAS#
DTD#
Ad0,Ad1=High
Row
Row
Ad0-2
Ad3-11
WB2
Ad0-Ad2=Low Ad2=Low
**Col
**Col
NoChange
New
Data[WB1(0-7)]
Old Data
2
4
6
0
2
4
0
1
3
5
7
1
3
WB1
tCBF
New Data[WB1(0-7)]
Latency x tK
RB1
Old Data
Old Data
New Data[WB1(0-7)]
RB1
DNOP
DNOP
DNOP
DPD
PCG
DPD
DPD
BW
DRAM
DPD
DPD
BW
DPD ACT
BW
DWT1
BW
DWT2
BW
PCG
BW
SRAM
BW
DES BW
0
BW
BW
BW
BW
BW
DQ0-15
2
4
6
0
2
4
1
3
5
7
1
3
5
New Data on RB appears as to latency set count. See DRT timing chart.
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
59
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
This page is left blank, so that the Set Command Register
Timing Diagram on the next spread can be seen conveniently.
60
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Set Command Register (1)
2
4
6
8
10
12
14
1
3
5
7
9
11
13
K
CMd#
CS#
RAS#
CAS#
DTD#
CMD
Row
Ad0-11
DNOP DNOP
DNOP
DPD
DPD
DPD
SCR
DPD ACT
DPD
DPD
DPD
DPD
DPD
*Set Command Reg.
Inhibit new command except for DNOP,DPD
DES,SPD and NOP.
61
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Set Command Register(2)
Address Input
Command
Ad11
Ad10 Ad9
Ad7
Ad4
Ad8
Ad6 Ad5
Ad3 Ad2 Ad1 Ad0
L
L
L
L
L
L
L
L
L
L
No operation
Set All WB1 Xfer Masks
Default
H
L
L
L
L
L
L
L
L
L
L
H
L
Output ModeTransparent
Output Mode Latched
Output Mode Registered
Latency 1
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
Latency 2
Latency 3
Latency 4
H
H
L
L
L
L
L
L
L
L
L
L
L
H
Default
BL=1
BL=2
BL=4
BL=8
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
Sequential
Interleave
Default
L
L
L
L
H
L
L
Default
K
CMd#
* Latency is the number of clock
cycles required to transfer new
data from the DRAM to the Read
Buffer . Therefore, it can be
adjusted to the clock frequency of
the system.
CS#
RAS#
(Latency) x (tK) should meet tCBF
min. timing requirement.
CAS#
DTD#
Command
Ad0~11
SCR
Inhibit new read or write function during these 4 clocks.
62
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Burst Mode Address
Initial Address
Interleaved
Sequential
BL
Y1
Y3
Y5
Y7
Y1
Y3
Y5
Y7
As0
Y0
0
1
2
3
4
5
6
7
0
1
2
3
0
Y2
2
3
4
5
6
7
0
1
2
3
0
1
Y4
4
Y6
6
Y0
0
Y2
2
Y4
4
Y6
6
As2 As1
0
1
2
3
4
5
6
7
0
1
2
3
0
1
0
3
4
5
6
7
0
1
2
3
0
1
2
5
6
7
0
1
2
3
4
7
0
1
2
3
4
5
6
1
0
3
2
5
4
7
6
0
0
0
1
5
7
1
2
3
0
5
6
7
4
0
1
6
0
3
2
5
4
1
0
7
6
7
6
1
0
5
4
3
2
0
0
0
1
7
1
1
0
3
4
1
6
7
0
5
2
8
0
2
1
1
0
1
1
3
5
6
7
4
1
2
3
0
0
1
2
4
7
6
5
4
3
2
1
0
1
1
0
1
0
1
3
5
7
0
5
2
3
1
1
0
0
1
1
0
3
2
3
2
1
0
0
-
1
2
3
0
4
2
-
-
0
1
3
0
1
1
-
1
0
-
-
0
1
1
1
-
Note: When SRAM command is executed more than burst length, the Address
repeats with the same sequence.
63
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
70P3S Package Dimension
A
70
36
70P3S-L
70P3S-M
0.125+0.05
35
35
1
1
-0.02
+0.02
)
(0.005
-0.0008
0.5+-0.1
(0.02+-0.004)
Detail A
mm
UNIT :
(INCH)
70
36
*3
0.3
+0.1
-0.05
0.65+-0.1
+0.004
-0.05
(0.026+-0.004)
*2
(0.012
)
23.49+-0.1
(0.925+-0.004)
0.1
(0.004)
Note) Dimension *1, *2
do not include mold flash.
Dimension *3
does not include tie - bar
cut remain.
64
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
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