M5M417400CTP-5S [MITSUBISHI]
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM; 快速页模式16777216位（ 4194304 - WORD 4位）动态RAM
| 型号： | M5M417400CTP-5S |
| 厂家： | 
Mitsubishi Group |
| 描述： | FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM |
| 文件： | 总22页 (文件大小：640K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
PIN DESCRIPTION
DESCRIPTION
Pin name
Function
This is a family of 4194304-word by 4-bit dynamic RAMS,
fabricated with the high performance CMOS process, and is ideal
for large-capacity memory systems where high speed, low power
dissipation, and low costs are essential.
A
~ A
Address inputs
0
11
DQ ~ DQ
1
Data inputs / outputs
4
RAS
CAS
W
Row address strobe input
Column address strobe input
Write control input
The use of double-layer metal process combined with twin-well
CMOS technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density at reduced costs.
Multiplexed address inputs permit both a reduction in pins and an
increase in system densities.
OE
Output enable input
V
Power supply (+5V)
CC
V
Ground (0V)
SS
PIN CONFIGURATION (TOP VIEW)
FEATURES
RAS
CAS
Address
access
OE
Power
access
access
access
Cycle
dissipa-
Type Name
time
time
time
time
time
tion
(max.ns)
(max.ns)
(max.ns)
(max.ns)
(min.ns)
(typ.mW)
M5M417400CXX-5,-5S
M5M417400CXX-6,-6S
M5M417400CXX-7,-7S
50
60
70
13
15
20
25
30
35
13
15
20
90
655
540
475
110
130
XX=J, TP
• Standard 26 pin SOJ, 26 pin TSOP
• Single 5V ± 10% supply
• Low stand-by power dissipation
5.5mW(Max)..................................CMOS Input level
2.2mW (Max)* ...............................CMOS Input level
• Low operating power dissipation
M5M417400Cxx-5,-5S .................... 800.0mW (Max)
M5M417400Cxx-6,-6S .................... 660.0mW (Max)
M5M417400Cxx-7,-7S .................... 580.0mW (Max)
Outline 26P0D-B (300mil SOJ)
•
Self refresh capability *
self refresh current................................ 200.0 µ A(Max)
• Fast-page mode, Read-modify-write, RAS-only refresh
• CAS before RAS refresh, Hidden refresh capabilities
Early-write mode and OE to control output buffer impedance
• All inputs, output TTL compatible and low capacitance
• 2048 refresh cycles every 32ms (A0 ~ A10
)
*Applicable to self refresh version (M5M417400CJ,TP-5S,-6S,
-7S :option) only
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh
memory for CRT
Outline 26P3D-E (300mil TSOP)
NC: NO CONNECTION
1
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
FUNCTION
The M5M417400CJ,TP provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., fast
page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Input/Output
Operation
Refresh
Remark
Row
address
Column
address
RAS
CAS
W
OE
Input
Output
Read
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
DNC
NAC
ACT
ACT
ACT
DNC
NAC
NAC
NAC
DNC
ACT
DNC
DNC
ACT
DNC
ACT
DNC
DNC
DNC
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
APD
APD
APD
APD
DNC
DNC
DNC
DNC
DNC
OPN
VLD
VLD
VLD
DNC
OPN
DNC
DNC
DNC
VLD
OPN
IVD
YES
YES
YES
YES
YES
YES
YES
YES
NO
Fast
page
mode
identical
Write (Early write)
Write (Delayed write)
Read-modify-write
RAS-only refresh
Hidden refresh
VLD
OPN
VLD
OPN
OPN
OPN
Self refresh
CAS before RAS refresh
Stand-by
Note: ACT: active, NAC: nonactive, DNC: don’t care, VLD: valid, IVD: invalid, APD: applied, OPN: open
BLOCK DIAGRAM
2
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
-1 ~ 7
Unit
V
V
Supply voltage
CC
I
V
V
Input voltage
With respect to V
-1 ~ 7
-1 ~ 7
50
V
V
SS
Output voltage
O
I
Output current
mA
mW
°C
O
P
Power dissipation
Operating temperature
Storage temperature
Ta = 25°C
1000
d
T
T
0 ~ 70
-65 ~ 150
opr
stg
°C
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 ~ 70°C, unless otherwise noted) (Note 1)
Limits
Nom
5
Symbol
Parameter
Unit
Min
4.5
Max
5.5
V
Supply voltage
Supply voltage
V
V
V
V
CC
SS
IH
V
V
V
0
0
0
High-level input voltage, all inputs
Low-level input voltage, all inputs
2.4
5.5
0.8
-1.0**
IL
Note 1: All voltage values are with respect to V
.
SS
**:
V
is -2.0V when undershoot width is less than 25ns. (Undershoot width is with respect to V .)
IL(min.) SS
ELECTRICAL CHARACTERISTICS
(Ta = 0 ~ 70°C, V = 5V ± 10%, V = 0V, unless otherwise noted) (Note 2)
CC
SS
Limits
Typ
Symbol
Parameter
Test conditions
Unit
Min
2.4
Max
V
High-level output voltage
Low-level output voltage
Off-state output current
Input current
I
I
= -5.0mA
= 4.2mA
V
CC
V
V
OH
OL
OH
V
0
0.4
10
10
OL
l
Q floating 0V ≤ V
≤ 5.5V
-10
-10
µA
µA
OZ
OUT
I
0V ≤ V ≤5.5V, Other inputs pins = 0V
I
IN
Average supply current
M5M417400C-5,-5S
M5M417400C-6,-6S
RAS, CAS cycling
145
120
I
CC1(AV)
from V , operating
t
= t = min.
WC
mA
CC
RC
(Note 3,4)
M5M417400C-7,-7S
output open
RAS = CAS = V , output open
105
2
IH
I
I
Supply current from V , stand-by
(Note 5)
mA
mA
CC2
CC
RAS = CAS ≥ V -0.2V
0.5
145
120
CC
Average supply current
M5M417400C-5,-5S
M5M417400C-6,-6S
RAS cycling, CAS = V
IH
from V , refreshing
t
= min.
CC3 (AV)
CC
RC
(Note 3)
M5M417400C-7,-7S
M5M417400C-5,-5S
output open
RAS = V , CAS cycling
105
80
Average supply current
IL
I
I
from V , Fast-Page-Mode
M5M417400C-6,-6S
t = min.
PC
70
mA
mA
CC4 (AV)
CC6 (AV)
CC
(Note 3,4)
M5M417400C-7,-7S
M5M417400C-5,-5S
output open
60
Average supply current from V
,
CAS before RAS refresh cycling
145
CC
CAS before RAS refresh mode
M5M417400C-6,-6S
M5M417400C-7,-7S
t
= min.
120
105
RC
(Note 3)
output open
Note 2: Current flowing into an IC is positive, out is negative.
3:
4:
I
I
(AV), I
(AV), I
(AV) and I
(AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
CC6
CC1
CC1
CC3
CC4
(AV) and I
(AV) are dependent on output loading. Specified values are obtained with the output open.
CC4
3
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
CAPACITANCE
(Ta = 0 ~ 70°C, V = 5V ± 10%, V = 0V, unless otherwise noted)
CC
SS
Limits
Typ
Symbol
Parameter
Test conditions
Unit
Min
Max
5
C
Input capacitance, address inputs
Input capacitance, OE input
pF
pF
pF
pF
pF
pF
I(A)
C
C
C
C
C
7
7
7
7
8
I(OE)
I(W)
V = V
I
SS
Input capacitance, write control input
Input capacitance, RAS input
f = 1MHz
I(RAS)
I(CAS)
I/O
V = 25mVrms
I
Input capacitance, CAS input
Input/Output capacitance, data ports
SWITCHING CHARACTERISTICS
(Ta = 0 ~ 70°C, V = 5V ± 10%, V = 0V, unless otherwise noted, see notes 5, 12, 13)
CC
SS
Limits
M5M417400C-6,-6S
Symbol
Parameter
M5M417400C-5,-5S
M5M417400C-7,-7S
Unit
Min
Max
13
Min
Max
15
Min
Max
20
t
t
t
t
t
t
t
t
Access time from CAS
Access time from RAS
(Note 6, 7)
(Note 6, 8)
(Note 6, 9)
(Note 6, 10)
(Note 6)
ns
ns
ns
ns
ns
ns
ns
ns
CAC
50
25
30
13
60
30
35
15
70
35
40
20
RAC
AA
Column address access time
Access time from CAS precharge
Access time from OE
CPA
OEA
CLZ
OFF
OEZ
Output low impedance time from CAS low
Output disable time after CAS high
Output disable time after OE high
(Note 6)
5
0
0
5
0
0
5
0
0
(Note 11)
(Note 11)
13
13
15
15
15
15
Note 5: An initial pause of 500 µ s is required after power-up followed by a minimum of eight initialization RAS cycles. The initialization cycles should be done either by RAS-only
refresh cycles or by CAS before RAS refresh cycles only.
Note the RAS may be cycled during the initial pause. And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 32ms) of RAS inactivity before
proper device operation is achieved.
After the initialization cycles, RAS should be kept either higher than V
6: Measured with a load circuit equivalent to 2 TTL loads and 100pF.
or lower than V
except RAS transition time.
IL(max)
IH(min)
7: Assumes that t
8: Assumes that t
≥ t
≤ t
and t
and t
≥ t
.
ASC(max)
RCD
RCD(max)
ASC
RAD
≤ t
. If t
or t
is greater than the maximum recommended value shown in this table, t
will increase by amount that
RAC
RCD
RCD(max)
RAD(max)
RCD
RAD
t
exceeds the value shown.
RCD
9: Assumes that t
≥ t
and t
≤ t
.
ASC(max)
RAD
RAD(max)
CP(max)
ASC
10: Assumes that t ≤ t
and t
≥ t
.
ASC(max)
CP
ASC
11:
t
and t
defines the time at which the output achieves the high impedance state (I
≤ | ± 10 µA |) and is not reference to V
or V
.
OL(max)
OFF(max)
OEZ(max)
OUT
OH(min)
4
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Fast-Page Mode Cycles)
(Ta = 0 ~ 70°C, V = 5V ± 10%, V = 0V, unless otherwise noted. See notes 12, 13)
CC
SS
Limits
Symbol
Parameter
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
Unit
Min
Max
32
Min
Max
32
Min
Max
32
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Refresh cycle time
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REF
RAS high pulse width
30
18
10
0
40
20
10
0
50
20
10
0
RP
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
(Note 14)
37
45
50
RCD
CRP
RPC
CPN
RAD
ASR
ASC
RAH
CAH
DZC
DZO
CDD
ODD
T
10
13
0
10
15
0
10
15
0
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
(Note 15)
(Note 16)
25
10
30
10
35
10
0
0
0
8
10
15
0
10
15
0
13
0
(Note 17)
(Note 17)
(Note 18)
(Note 18)
(Note 19)
Delay time, data to OE low
0
0
0
Delay time, CAS high to data
13
13
1
15
15
1
15
15
1
Delay time, OE high to data
Transition time
50
50
50
Note 12: The timing requirements are assumed t = 5ns.
T
13:
14:
V
and V
are reference levels for measuring timing of input signals.
IH(min)
IL(max)
t
t
is specified as a reference point only. If t
is less than t
, access time is t
.
If t
is greater than t
, access time is controlled exclusively by
RCD(max)
RCD(max)
RCD
RCD(max)
RAC
RCD
or t
.
t
is specified as t
= t
+ 2t + t
ASC(min)
.
CAC
AA RCD(min)
RCD(min)
RAH(min)
H
15:
16:
t
t
is specified as a reference point only. If t
is specified as a reference point only. If t
≥ t
and t
≤ t
, access time is controlled exclusively by t
.
AA
RAD(max)
ASC(max)
RAD
RCD
RAD(max)
ASC
ASC(max)
≥ t
and t
≥ t
, access time is controlled exclusively by t
.
CAC
RCD(max)
ASC
ASC(max)
17: Either t
18: Either t
or t
must be satisfied.
must be satisfied.
DZC
CDD
DZO
or t
ODD
19:
t
is measured between V
and V
.
IL(max)
T
IH(min)
Read and Refresh Cycles
Limits
M5M417400C-6,-6S
Symbol
Parameter
M5M417400C-5,-5S
M5M417400C-7,-7S
Unit
Min
90
Max
Min
110
Max
Min
130
Max
t
t
t
t
t
t
t
t
t
t
t
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
RAS low pulse width
CAS low pulse width
50
13
50
13
0
10000
10000
60
15
60
15
0
10000
10000
70
20
70
20
0
10000
10000
RAS
CAS
CSH
RSH
RCS
RCH
RRH
RAL
OCH
ORH
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time after CAS high
Read hold time after CAS low
Read hold time after RAS low
Column address to RAS hold time
CAS hold time after OE low
RAS hold time after OE low
(Note 20)
(Note 20)
0
0
0
10
25
13
13
10
30
15
15
10
35
20
20
Note 20: Either t
or t
must be satisfied for a read cycle.
RRH
RCH
5
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
Parameter
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
Unit
Min
90
Max
Min
110
Max
Min
130
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
Write cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
RAS low pulse width
CAS low pulse width
50
13
50
13
0
10000
10000
60
15
60
15
0
10000
10000
70
20
70
20
0
10000
10000
RAS
CAS
CSH
RSH
WCS
WCH
CWL
RWL
WP
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
(Note 22)
8
10
15
15
10
0
10
20
20
10
0
13
13
8
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low
0
DS
8
10
15
15
20
DH
13
OEH
Read-Write and Read-Modify-Write Cycles
Limits
M5M417400C-6,-6S
Symbol
Parameter
M5M417400C-5,-5S
M5M417400C-7,-7S
Unit
Min
131
Max
Min
155
Max
Min
180
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read write/read modify write cycle time
RAS low pulse width
(Note 21)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RWC
91
54
91
54
0
10000
10000
105
60
105
60
0
10000
10000
120
70
120
70
0
10000
10000
RAS
CAS
CSH
RSH
RCS
CWD
RWD
AWD
CWL
RWL
WP
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
CAS hold time after W low
RAS hold time after W low
Write pulse width
(Note 22)
(Note 22)
(Note 22)
36
73
48
13
13
8
40
85
55
15
15
10
0
45
95
60
20
20
10
0
Data setup time before W low
Data hold time after W low
OE hold time after W low
0
DS
8
10
15
15
15
DH
13
OEH
Note 21:
Note 22:
t
t
is specified as t
= t
+ t
+ t
+ t
+ 5t .
RP(min) T
RWC
RWC(min)
RAC(max)
ODD(min)
RWL(min)
, t
, t
and t
and, t
are specified as reference points only. If t
≥ t the cycle is an early write cycle and the DQ pins will remain high impedance
WCS(min)
WCS CWD RWD
AWD
CPWD
WCS
throughout the entire cycle. If t
≥ t
, t
≥ t
, t
≥ t and tCPWD ≥ t
AWD(min)
(for fast page mode cycle only), the cycle is a read-modify-write
CPWD(min)
CWD
CWD(min) RWD
RWD(min) AWD
cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes
back to V ) is indeterminate.
IH
6
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Fast-Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle)
(Note 23)
Limits
Symbol
Parameter
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
Unit
Min
35
Max
Min
40
Max
Min
45
Max
t
t
t
t
t
t
Fast page mode read/write cycle time
ns
ns
ns
ns
ns
ns
PC
Fast page mode read write/read modify write cycle time
76
85
8
85
100
10
95
115
10
PRWC
RAS
RAS low pulse width for read write cycle
CAS high pulse width
(Note 24)
(Note 25)
125000
12
125000
15
125000
15
CP
RAS hold time after CAS precharge
Delay time, CAS precharge to W low
30
53
35
40
CPRH
CPWD
(Note 22)
60
65
Note 23: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle.
24:
25:
t
t
is specified as two cycles of CAS input are performed.
is specified as a reference point only.
RAS(min)
CP(max)
CAS before RAS Refresh Cycle
(Note 26)
Limits
Symbol
Parameter
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
Unit
Min
10
Max
Min
10
Max
Min
10
Max
t
t
t
t
CAS setup time before RAS low
CAS hold time after RAS low
Read setup time before RAS low
Read hold time after RAS low
ns
ns
ns
ns
CSR
10
10
10
10
10
10
15
10
15
CHR
RSR
RHR
Note 26: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
SELF REFRESH SPECIFICATIONS
Self refresh devices are denoted by “S” after speed item, like -5S/-6S/-7S. The other characteristics and requirements than the below are
same as normal devices.
ELECTRICAL CHARACTERISTICS
(Ta = 0 ~ 70°C, V = 5V ± 10%, V = 0V, unless otherwise noted) (Note 2)
CC
SS
Limits
Typ
Symbol
Parameter
Test conditions
Unit
Min
Max
500
CAS before RAS refresh cycling
or RAS cycling & CAS ≤ 0.2V
OE & WE ≤ 0.2V
Average supply current
from VCC
or OE & WE ≥ V - 0.2V
CC
I
Slow-Refresh cycle
M5M417400C (S)
µA
A
~ A ≤ 0.2V
10
CC8(AV)
0
(Note 5)
or A ~ A ≥ V - 0.2V
0 10 CC
t
= 128ms (2048 cycles)
REF
output = OPEN
= t ~ 1µs
t
RAS
RASmin.
Average supply current
from VCC
I
Slow-Refresh cycle
M5M417400C (S)
RAS = CAS ≤ 0.2V
output = OPEN
200
µA
CC9(AV)
(Note 5)
7
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
TIMING REQUIREMENTS
(Ta = 0 ~ 70°C, V = 5V ± 10%, V = 0V, unless otherwise noted, see notes 12, 13)
CC
SS
Limits
Symbol
Parameter
M5M417400C-5S
M5M417400C-6S
M5M417400C-7S
Unit
Min
100
Max
Min
100
Max
Min
100
Max
t
t
t
t
t
Self Refresh RAS low pulse width
Self Refresh RAS high precharge time
Self Refresh RAS hold time
µs
ns
ns
ns
ns
RASS
90
-50
10
110
-50
10
130
-50
10
RPS
CHS
RSR
RHR
Read setup time before RAS low
Read hold time after RAS low
10
10
15
SELF REFRESH ENTRY & EXIT CONDITIONS
1. In case of distributed refresh
The last / first full refresh cycles (2K) must be made within t / t before / after self refresh, on the condition
NS SN
of t ≤ 32ms and t ≤ 32ms.
NS
SN
2. In case of burst refresh
The last / first full refresh cycles (2K) must be made within t / t before / after self refresh, on the condition
NS SN
of t + t ≤ 32ms.
NS
SN
8
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
TEST Mode SET Cycle
Limits
Symbol
Parameter
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
Unit
Min
10
Max
Min
10
Max
Min
10
Max
t
W setup time before RAS low
W hold time after RAS low
ns
ns
WSR
WHR
t
10
10
15
Note 27: The test mode function is initiated by a W and CAS before RAS cycle (WCBR cycle) as specified in timing diagram.
The test mode function is terminated by either a CAS before RAS refresh cycle (CBR refresh cycle) or a RAS only refresh cycle.
During the test mode, the device is internally organized as 16-bits wide (1M bytes depth). No addressing of CA and CA is required.
0
1
During a write cycle, data must be applied to all DQ (input) pins. The data can be different between DQ pins. The data on each DQ pin is written into 4-bits memory cells,
respectively. During a read cycle, each DQ (output) pin shows the test result of the 4-bits, respectively. High state indicates that they are same. Low state indicates that they
are not same.
During the test mode operation, only WCBR cycle can be used to perform refresh.
9
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Timing Diagrams Read Cycle
(Note 28)
10
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Write Cycle (Early Write)
11
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Write Cycle (Delayed Write)
12
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
13
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
14
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle, Slow Refresh Cycle
15
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 29)
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
And in any cycle, t
& t
should be satisfied not to enter TEST MODE.
RHR
RSR
16
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Fast Page Mode Read Cycle
17
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
18
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
19
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Fast Page Mode Read-Write, Read-Modify-Write Cycle
20
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Self Refresh Cycle
21
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
TEST Mode SET Cycle
Note 30: This cycle can be used for initialized cycle after power-up, however entried into Test Mode.
22
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