M5M28F101AFP [MITSUBISHI]
1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY; 1048576 - BIT （ 131072 -字×8位）的CMOS FLASH MEMORY
| 型号： | M5M28F101AFP |
| 厂家： | 
Mitsubishi Group |
| 描述： | 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY |
| 文件： | 总10页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
s
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT(131072-WORDBY 8-BIT) CMOSFLASHMEMORY
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The MITSUBISHI M5M28F101A is high-speed 1048576-bit CMOS
Flash Memories. This is suitable for the applications with micro-
processor or micro-controller where on-board reprogramming is
required. The M5M28F101A is fabricated by N-channel double
polysilicon gate for memory and CMOS technology for peripheral
circuits, and is available in 32pin plastic molded packages.
1
2
VPP
A16
A15
A12
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
WRITE ENABLE
INPUT
3
NC
A14
A13
A8
4
5
FEATURES
ADDRESS
INPUTS
6
A6
ADDRESS
INPUTS
........................................................
Speed item ........................................................ 85 ns (max.)
7
A5
A9
Speed item .......................................................100 ns (max.)
8
A4
A11
OE
...................................
OUTPUT
ENABLE INPUT
ADDRESS INPUT
CHIP ENABLE
INPUT
9
Power supply voltage ................................... VCC = 5V±0.5V
A3
................................
10
11
12
13
14
15
16
A2
Write and erase voltage ................................ VPP = 12V±0.6V
A10
CE
Byte program and Chip erase
A1
Auto program and Auto erase
A0
D7
D6
D5
D4
D3
Program/erase operation controlled by software command
Program/erase pulse controlled by an embedded timer
10000 program/erase cycles
D0
DATA
INPUTS/
OUTPUTS
DATA INPUTS/
OUTPUTS
D1
D2
Tri-state output buffer
GND
TTL-compatible input and output in read and write mode
Contained device-identifier code
Outline 525mil 32pin SOP (32P2M-A)
Incorporated data-protection
Available packaging for Surface Mount
APPLICATION
5
6
29
28
27
26
25
24
23
22
21
A7
A14
A13
A8
Micro-computer system and peripheral equipment
A6
A5
A4
A3
A2
A1
A0
D0
7
8
A9
9
A11
OE
A10
CE
D7
M5M28F101AJ
10
11
12
13
Outline 32pin PLCC (32P0)
OE
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A4
A3
A11
A9
A10
A5
A2
CE
3
A6
A7
A1
A0
A8
4
D7
A13
A14
NC
WE
VCC
VPP
A16
5
D6
A12
A15
A16
VPP
D0
D1
D2
GND
D3
D4
D5
6
D5
7
D4
8
D3
M5M28F101AVP
M5M28F101ARV
9
8
GND
VCC
WE
10
11
12
13
14
15
16
D2
7
6
D1
D0
A0
A1
A2
A3
A15
A12
A7
NC
A14
A13
A8
A9
A11
5
D6
4
D7
CE
3
A6
2
A10
A5
OE
1
A4
Outline 32pin TSOP type-I (8x20mm)
32P3H-E (normal bend)
Outline 32pin TSOP type-I (8x20mm)
32P3H-F (reverse bend)
NC : NO CONNECTION
(970407)
1
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY
BLOCK DIAGRAM
PROGRAM
VOLTAGE SW.
A9
ERASE VOLTAGE SW.
VPP (5V, 12V)
VCC (5V)
A8
A7
GND (0V)
A6
A5
131072 WORD
x8 BIT
CELL MATRIX
X-DECODER
A4
A3
A2
ADDRESS
INPUTS
A1
A0
A16
A15
A14
A13
A12
A11
A10
Y-DECODER
Y-GATE
CHIP ENABLE
OUTPUT ENABLE
CIRCUITS
OUTPUT SENSE
AND
OUTPUT BUFFERS
VERIFY
VOLTAGE
SW.
CONTROL
CIRCUITS
COMMAND
LATCH
TIMER
CE
OE
CHIP ENABLE INPUT
OUTPUT ENABLE INPUT
WE
D0 D1 D2 D3 D4 D5 D6 D7
DATA INPUTS/OUTPUTS
WRITE ENABLE
INPUT
FUNCTION
DATA PROTECTION
M5M28F101A are set to the Read-only mode or Read-write mode
by applying the voltage of VPPL or VPPH, respectively, to VPP pin. In
Read-only mode, three operation modes, Read, Out-put disable
and Stand-by are accessible. While, in Read-Write mode, four
operation modes, Read, Output disable, Stand-by and Write are
functional.
1. Power Supply Voltage
When the power supply voltage (Vcc) is less than 2.5V, the
device ignores WE signal.
2. Write Inhibit
In the cases, as below, write mode is not set.
1) When OE is terminated to the low level.
2) From each mode beginning through finish after 2nd rising
edge of WE for program, auto-program, erase, and auto-
erase.
Read
Set CE and OE terminals to the read mode (low level). Low level
input to CE and OE, and address signals to the address inputs
(A0~A16) make the data contents of the designated address
location available at data input/output(D0~D7).
3. Over-erase Protection
Just after powering up, if erase command is inputted, erase
operation is not executed. Once byte-program is performed or
verified data is not FFH in the erase-verify mode, successive
command input for erase will be accepted. Because of this, it
is applicable to the case of multi-chip erasing simultaneously.
Output Disable
When OE is at high level, output from the devices is disabled. Data
input/output are in a high-impedance (High-Z) state.
Stand-by
When CE is at high level, the devices is in the stand-by mode and
its power consumption is substantially reduced. Data input/output
are in a high-impedance (High-Z) state.
Write
Software command accomplishes program and erase operations
via the command latch in the device, when high voltage is supplied
to VPP. The contents of the latch serve as input to the internal
controller. The controller output dictates the function of device. The
command latch is written by bringing WE to low level, while CE is
at low level and OE is at high level. Addresses are latched on the
falling edge of WE, while data is latched on the rising edge of WE.
Standard micro-processor write timings are used.
(970407)
2
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY
Erase Verify Command
SOFTWARE COMMAND
When VPP is low (VPP = VPPL), the contents of the command latch
are fixed to 00H, and the device is in read-only mode. When VPP is
high (VPP = VPPH), the device enters read/write mode. The device
operations are selected by writing specific software command into
the command latch.
Following each erase, all bytes must be verified. The erase verify
is initiated by writing Erase Verify Command (A0H) to the
command latch, while the address to be verified is latched on the
falling edge of the WE pulse. The erase verify command must be
written to the command latch and each address is latched before
each byte is verified. The operation continues for each byte until a
byte is not erased, or the last address is accessed.
Read Command
The device is in read mode after writing Read Command (00H) to
the command latch. The device continues to be in read mode until
the other commands are written. When VPP powers-up to high
voltage (VPP = VPPH), the default contents of the command latch is
00H. So it is ensured that the false alteration of memory data does
not occur during VPP power transition.
Auto Erase Command
Auto Erase Command is the command for automated erase and
erase-verify of all bytes, and Auto Erase is initiated by twice of the
Erase Command (30H) consecutively to the command latch. First,
the preprogram operation is initiated at the rising edge of WE in
second write cycle, and so all byte become zero data. Second,
erase and erase-verify begin, automatically. So it is not necessary
to preprogram and erase-verify mode. And the complete of Auto
Erase can be indicated by status polling.
Program Command
Program Command is the command for byte-program, and
program is initiated by twice of write cycles. Program Command
(40H) is written to the command latch in first write cycle, and the
address and data to be programmed are latched in second write
cycle. Then the address and data are latched on the falling edge
and the rising edge of WE pulse, respectively. The byte- program
operation is initiated at the rising edge of WE in second write
cycle, and terminates in 10 µs, controlled by the internal timer.
Status polling is the indication of the complete of Auto Erase.
During the Auto Erase, on WE=VIH and CE=OE=VIL , the data of
D7 is "0". When Auto Erase is completed, the data of D7 is "1".
(D0~D7 are "FFH". )
Reset Command
Reset Command is the command to safely abort the erase or
program sequences. Following erase or program command in first
write cycle, the operation is aborted safely by writing the two
consecutive Reset Commands (FFH). Then the device enters read
mode without altering memory contents.
Program Verify Command
Following byte program, the programmed byte must be verified.
The program-verify is initiated by writing Program Verify Command
(C0H) to the command latch. After writing Program Verify
Command, programmed data is verified in read mode. Then the
address information is not needed.
Read Device Identifier Code
Device Identifier operation is initiated by writing 80H into the
command latch. Following the command write, the manufacturer
code (1CH) and the device code (D9H) can be read from address-
00000H and 00001H, respectively.
Auto Program Command
Auto Program Command is the command for automated program
and program-verify of one byte, and Auto Program is initiated by
twice of write cycles.
The M5M28F101A is supported with the Common Device
Identifier Code of MITSUBISHI 1M Flash memory (x8) family.
Common Device Identifier operation is initiated by writing 90H into
the command latch. Under this case, following the command write,
the manufacturer code (1CH) and the device code (D0H) can be
read from address-00000H and 00001H, respectively. Additionally,
Common Device Identifier operation is initiated by rising A9 to high
voltage for PROM programmers.
Auto Program Command (10H or 50H) is written to the command
latch in first write cycle, and the address and data to be
programmed are latched in second write cycle. Then the address
and data are latched on the falling edge and the rising edge of WE
pulse, respectively. The program operation is initiated at the rising
edge of WE in second write cycle, and program-verify begin auto-
matically. So it is not necessary to program-verify mode after this.
And the complete of Auto Program can be indicated by data
polling.
Data polling is the indication of the complete of Auto Program.
During the Auto Program, on WE=VIH and CE=OE=VIL , the data of
D0~D7 are the inverse of written datum. When Auto Program is
completed, the written datum will be output. It is necessary to fix
the address of written byte during data polling.
Erase Command
Erase Command is the command for chip-erase, and chip-erase is
initiated by writing twice of the Erase Command (20H)
consecutively to the command latch. The erase operation is
initiated with the rising edge of the WE pulse and terminates in
9.5ms, controlled by the internal timer. This two-step sequence for
chip-erase prevents from erasing accidentally.
(970407)
3
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY
MODE SELECTION
Pins
CE
OE
WE
VPP
Data I/O
Mode
Read
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
X
VIH
VIH
X
VPPL
VPPL
VPPL
VPPH
VPPH
VPPH
VPPH
Data out
Hi-Z
Read-Only
Output disable
Stand by
Read
Hi-Z
VIL
VIH
X
VIH
VIH
X
Data out
Hi-Z
Output disable
Stand by
Write
Read/Write
Hi-Z
VIH
VIL
Data out
Note 1 : X can be VIL or VIH
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Ratings
–0.6~7
Conditions
Unit
V
All input or output voltage except VPP/A9
VPP supply voltage
VI1
With respect to Ground
–0.6~14.0
–0.6~13.5
–10~80
V
VI2
A9 supply voltage
V
VI3
Topr
Operating temperature
Storage temperature
°C
°C
Tstg
–65~125
SOFTWARE COMMAND DEFINITION
First bus cycle
Second bus cycle
Address
Command
Mode
Write
Address
X
Data I/O
00H
Mode
–––
Data I/O
–––
Read
–––
Program
Program
Address
Write
Write
Write
X
X
X
40H
C0H
Write
Read
Write
Program Data
Verify Data
(Byte Program)
Program verify
X
Program
Address
10H or 50H
Program Data
Auto Program
Erase (Chip Erase)
Erase verify
Write
Write
Write
Write
Write
Write
X
20H
A0H
30H
FFH
80H
90H
Write
Read
Write
Write
Read
Read
X
X
20H
Verify Data
30H
Verify address
X
X
X
X
X
Auto Erase
Reset
X
FFH
ADI
ADI
DDI1
Read device identifier code
Read common device identifier code
DDI2
Note 2 : Write and read mode are defined in mode selection table.
ADI = Address of Device Identifier : 00000H for manufacturer code, 00001H for device code.
DDI1 = Data of Device Identifier : 1CH for manufacturer code, D9H for device code.
DDI2 = Data of Common Device Identifier : 1CH for manufacturer code, D0H for device code.
COMMON DEVICE IDENTIFIER CODE (not use the software command)
Hex.
Data
Pins
A0
D7
D6
D5
D4
D3
D2
D1
D0
Code
Manufacturer Code
Device Code
VIL
VIH
0
1
0
1
0
0
1
1
1
0
1
0
0
0
0
1CH
D0H
0
Note 3 : A9 = 11.5V~13.0V
A1~A8, A10~A16, CE, OE = VIL, WE = VIH
VCC = VPP = 5V±0.5V
CAPACITANCE
Limits
Typ
Parameter
Test conditions
Symbol
Unit
Min
Max
8
pF
pF
Input capacitance (Address, CE, OE, WE)
Output capacitance
CIN
Ta = 25°C, f = 1MHz, Vin = Vout = 0V
12
COUT
(970407)
4
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY
DC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc = 5V±0.5V, unless otherwise noted)
Limits
Typ
Symbol
Parameter
Input leakage current
Test conditions
0V£VIN£VCC
Unit
Min
Max
10
ILI
µA
µA
Output leakage current
0V£VOUT£VCC
10
ILO
VCC = 5.5V, CE = VIH
1
ISB1
ISB2
ICC1
ICC2
ICC3
mA
µA
VCC stand-by current
VCC = 5.5V, CE = VCC±0.2V
VCC = 5.5V, CE = VIL, f = 11.8MHz, IOUT = 0mA
100
30
VCC active read current
VCC program current
VCC erase current
mA
mA
mA
30
VPP = VPPH
VPP = VPPH
30
0V£VPP£VCC
VCC<VPP£6.5V
VPP = VPPH
VPP = VPPH
VPP = VPPH
10
µA
100
100
30
IPP1
VPP read current
VPP program current
VPP erase current
Input low voltage
Input high voltage
Output low voltage
IPP2
IPP3
VIL
mA
mA
V
30
– 0.5
2.0
0.8
Vcc+0.5
0.45
VIH
V
VOL
IOL = 5.8mA
IOH = –2.5mA
IOH = –100µA
V
2.4
Vcc–0.4
0
VOH1
VOH2
VPPL
VPPH
Output high voltage
V
VPP voltage during read-only mode
VPP voltage during read/write mode
6.5
V
V
11.4
12.0
12.6
AC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc = 5V±0.5V, unless otherwise noted)
Read-Only Mode
Limits
M5M28F101A-85 M5M28F101A-10
Parameter
Symbol
Unit
Min
85
Max
Min
100
Max
ns
ns
ns
ns
ns
ns
ns
ns
µs
tRC
tAVAV
Read cycle time
ta (AD) tAVQV
ta (CE) tELQV
ta (OE) tGLQV
85
85
45
Address access time
100
100
50
Chip enable access time
Output enable access time
tCLZ
tOLZ
tDF
tELQX
tGLQX
tGHQZ
tOH
Chip enable to output in low Z
Output enable to output in low Z
Output enable high to output in low Z
Output hold from CE, OE, addresses
Write recovery time before read
0
0
0
0
25
25
0
6
tOH
0
6
tWRR tWHGL
Note 4 : VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
Timing measurements are made under AC WAVEFORMS FOR READ OPERATIONS.
(970407)
5
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY
Read/Write Mode
Limits
Symbol
Parameter
Unit
M5M28F101A-85 M5M28F101A-10
Min
85
Max
Min
100
Max
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
µs
ms
ns
s
tWC
tAS
tAH
tDS
tDH
tAVAV
tAVWL
tWLAX
Write cycle time
0
60
50
10
6
0
60
50
10
6
Address set-up time
Address hold time
tDVWH Data set-up time
tWHDX
Data hold time
tWRR tWHGL
tRRW tGHWL
Write recovery time before read
Read recovery time before write
Chip enable set-up time
Chip enable hold time
0
0
tCS
tCH
tWP
tELWL
tWHEH
tWLWH
20
0
20
0
Write pulse width
60
20
10
9.5
100
1.7
12
1
60
20
10
9.5
100
1.7
12
1
tWPH tWHWL
Write pulse width high
tDP
tDE
tWHWL1
tWHWL2
Duration of program operation
Duration of erase operation
Output enable hold time before status / data polling
Duration of auto erase operation
tOEH
tDAEC
12.5
400
12.5
400
Duration of auto program operation
VPP set-up time to chip enable low
Write pulse width (optional write)
Write enable set-up time (optional write)
Write enable hold time (optional write)
Address set-up time (optional write)
Address hold time (optional write)
Data set-up time (optional write)
µs
µs
ns
ns
ns
ns
ns
ns
ns
tDAP
tVSC
tOWP
tOWS
tOWH
tOAS
tOAH
tODS
tODH
tVPEH
70
0
70
0
0
0
0
0
55
45
20
55
45
20
Data hold time (optional write)
Note 5 : a. Read timing parameters during read/write mode are the same as during read-only mode.
b. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
TEST CONDITIONS
FOR AC CHARACTERISTICS
AC WAVEFORMS FOR READ OPERATIONS
Input voltage : VIL = 0.45V, VIH = 2.4V
Input rise and fall times : £10ns
Reference voltage
at timing measurement : 1.5V
Output load : 1TTL gate + CL
(= 100pF)
VIH
ADDRESS VALID
ADDRE-
VIL
SSES
tRC
VIH
CE
VIL
ta (CE)
or
VIH
OE
VIL
tWRR
tDF
1.3V
VIH
VIL
1N914
3.3kW
WE
ta (OE)
tOLZ
tOH
VOH
VOL
HIGH-Z
HIGH-Z
DUT
DATA
VCC
OUTPUT VALID
tCLZ
ta (AD)
CL = 100pF
5.0V
GND
(970407)
6
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY
AC WAVEFORMS FOR PROGRAM OPERATIONS
PROGRAM VERIFY
PROGRAM
VIH
ADDRESSES
VIL
tWC
tAS
tAH
VIH
CE
VIL
tCS
tCH
VIH
VIL
OE
tWRR
tWPH
tDP
tRRW
VIH
VIL
WE
ta (OE)
ta (CE)
tDH
tWP
tDS
VIH
VIL
DATA
VCC
VPP
40H
DIN
C0H
DATA TO BE VERIFIED
COMMAND SET
DATA SET
COMMAND SET
5.0V
0.0V
tVSC
tODH
tODS
VPPH
VPPL
tOAS
tOWH
tOWS
OPTIONAL WRITE
WE
tOAH
VIH
VIL
tOWP
VIH
VIL
CE
AC WAVEFORMS FOR ERASE OPERATIONS
ERASE
ERASE VERIFY
VIH
ADDRESSES
VIL
tWC
tAH
VIH
CE
VIL
tAS
tCS
tCH
VIH
VIL
OE
tDE
tWRR
tWPH
tRRW
VIH
VIL
WE
ta (OE)
ta (CE)
tDH
tWP
tDS
VIH
VIL
DATA
VCC
VPP
A0H
20H
20H
DATA TO BE VERIFIED
COMMAND SET
COMMAND SET
COMMAND SET
5.0V
0.0V
tVSC
VPPH
VPPL
(970407)
7
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY
AC WAVEFORMS FOR AUTO PROGRAM OPERATION
PROGRAM / DATA POLLING
VIH
VIL
ADDRESS
VALID
ADDRESS VALID
ta (AD)
ADDRESS VALID
ADDRESSES
tWC
tAS
tAH
VIH
VIL
CE
OE
tCS
ta (CE)
tCH
VIH
VIL
tWPH
tOEH
tRRW
ta (OE)
VIH
VIL
WE
tDAP
tDH
tWP
tDS
VIH
VIL
10H
or
DATA
VCC
Din
Din
Din
Din
50H
COMMAND SET
DATA SET
OUTPUT
OUTPUT
5.0V
0.0V
tVSC
VPPH
VPPL
VPP
AC WAVEFORMS FOR AUTO CHIP ERASE OPERATION
ERASE / STATUS POLLING
VIH
ADDRESSES
VIL
tWC
ta (CE)
ta (OE)
VIH
CE
VIL
tCS
tCH
VIH
OE
VIL
tWPH
tOEH
tRRW
VIH
VIL
WE
tDAEC
tDH
tWP
30H
COMMAND SET COMMAND SET
tDS
"1" /(FFH)
VIH
VIL
DATA
VCC
30H
"0"
"0"
D7 /
(D0~D7)OUTPUT
D7OUTPUT
D7OUTPUT
5.0V
0.0V
tVSC
VPPH
VPPL
VPP
(970407)
8
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY
PROGRAMMING AND ERASE ALGORITHM FLOW CHART
PROGRAM :
ERASE :
INPUT DATA
INPUT DATA
START
START
VCC = 5V, VPP = VPPH
ADDR = FIRST LOCATION
X = 0
VCC = 5V, VPP = VPPH
YES
ALL
BYTES = 00H?
NO
WRITE PROGRAM
COMMAND
40H
DIN
PROGRAM ALL
BYTES = 00H
WRITE PROGRAM DATA
DURATION = 10µs
X = X + 1
ADDR = FIRST LOCATION
X = 0
20H
20H
WRITE ERASE COMMAND
WRITE ERASE COMMAND
DURATION = 9.5ms
X = X + 1
WRITE PROGRAM-
VERIFY COMMAND
C0H
DURATION = 6µs
YES
X = 25?
WRITE ERASE-VERIFY
COMMAND
A0H
NO
DURATION = 6µs
FAIL
PASS
VERIFY
BYTE?
VERIFY
BYTE?
YES
X = 1000?
NO
PASS
FAIL
NO
LAST ADDR?
INC ADDR
FAIL
PASS
VERIFY
BYTE?
VERIFY
BYTE?
YES
PASS
FAIL
WRITE READ COMMAND
VPP = VPPL
NO
LAST ADDR?
INC ADDR
DEVICE
PASSED
DEVICE
FAILED
YES
WRITE READ COMMAND
VPP = VPPL
DEVICE
PASSED
DEVICE
FAILED
(Erase Complete)
(970407)
9
MITSUBISHI LSIs
M5M28F101AFP,J,VP,RV-85,-10
1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY
AUTO PROGRAM AND AUTO ERASE OPERATION
AUTO PROGRAM :
AUTO ERASE :
INPUT DATA
INPUT DATA
START
START
VCC = 5.0V, VPP = VPPH
VCC = 5.0V, VPP = VPPH
WRITE AUTO PROGRAM
SETUP COMMAND
WRITE AUTOERASE
SETUP COMMAND
10H OR
50H
30H
30H
WRITE AUTO PROGRAM
ADDRESS DATA
WRITE AUTOERASE
COMMAND
DIN
DATA POLLING
STATUS POLLING
ERASURE
COMPLETE
NO
INCREMENT ADDR
LAST ADDR?
YES
PROGRAMMING
COMPLETE
(970407)
10
相关型号：
M5M28F101AJ-85
Flash, 128KX8, 85ns, PQCC32, 0.450 INCH, 1.27 MM PITCH, PLASTIC, MO-052AE,LCC-32
MITSUBISHI
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