M38034M4H-XXXSP [MITSUBISHI]
Microcontroller, 8-Bit, MROM, MELPS740 CPU, 16.8MHz, CMOS, PDIP64, 0.750 INCH, PLASTIC, SDIP-64;
| 型号： | M38034M4H-XXXSP |
| 厂家： | 
Mitsubishi Group |
| 描述： | Microcontroller, 8-Bit, MROM, MELPS740 CPU, 16.8MHz, CMOS, PDIP64, 0.750 INCH, PLASTIC, SDIP-64 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总83页 (文件大小：1009K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀPower source voltage
DESCRIPTION
The 3803 group (Spec. H) is the 8-bit microcomputer based on the
In high-speed mode
At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V
At 12.5 MHz oscillation frequency ............................ 4.0 to 5.5 V
At 8.4 MHz oscillation frequency) ............................. 2.7 to 5.5 V
At 4.2 MHz oscillation frequency .............................. 2.2 to 5.5 V
At 2.1 MHz oscillation frequency) ............................. 2.0 to 5.5 V
In middle-speed mode
740 family core technology.
The 3803 group (Spec. H) is designed for household products, of-
fice automation equipment, and controlling systems that require
analog signal processing, including the A-D converter and D-A
converters.
At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V
At 12.5 MHz oscillation frequency ............................ 2.7 to 5.5 V
At 8.4 MHz oscillation frequency) ............................. 2.2 to 5.5 V
At 6.3 MHz oscillation frequency) ............................. 1.8 to 5.5 V
In low-speed mode
FEATURES
ꢀBasic machine-language instructions ...................................... 71
ꢀMinimum instruction execution time ................................ 0.24 µs
(at 16.8 MHz oscillation frequency)
ꢀMemory size
At 32 kHz oscillation frequency................................. 1.8 to 5.5 V
ꢀPower dissipation
ROM ............................................................... 16 K to 32 K bytes
RAM ................................................................. 640 to 1024 bytes
ꢀProgrammable input/output ports ............................................ 56
ꢀSoftware pull-up resistors ................................................. Built-in
ꢀInterrupts
In high-speed mode ................................................ 40 mW (typ.)
(at 16.8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ................................................... 45 µW (typ.)
(at 32 kHz oscillation frequency, at 3 V power source voltage)
ꢀOperating temperature range....................................–20 to 85°C
ꢀPackages
21 sources, 16 vectors .................................................................
(external 8, internal 12, software 1)
ꢀTimers ........................................................................... 16-bit ꢀ 1
8-bit ꢀ 4
SP .................................................. 64P4B (64-pin 750 mil SDIP)
FP ....................................... 64P6N-A (64-pin 14 ꢀ 14 mm QFP)
HP ..................................... 64P6Q-A (64-pin 10 ꢀ 10 mm LQFP)
KP ............................... 64P6U-A (ꢀ) (64-pin 14 ꢀ 14 mm LQFP)
(with 8-bit prescaler)
ꢀWatchdog timer ............................................................ 16-bit ꢀ 1
ꢀSerial I/O...................... 8-bit ꢀ 2 (UART or Clock-synchronized)
8-bit ꢀ 1 (Clock-synchronized)
ꢀPWM ............................................8-bit ꢀ 1 (with 8-bit prescaler)
ꢀA-D converter ............................................. 10-bit ꢀ 16 channels
(8-bit reading enabled)
ꢀD-A converter ................................................. 8-bit ꢀ 2 channels
ꢀLED direct drive port .................................................................. 8
ꢀClock generating circuit..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
Currently support products are listed below.
Table 1 Support products
ROM size (bytes)
Product name
RAM size (bytes)
640
Package
Remarks
ROM size for User in (
)
M38034M4H-XXXSP
M38034M4H-XXXFP
M38034M4H-XXXHP
M38034M4H-XXXKP*
M38037M6H-XXXSP
M38037M6H-XXXFP
M38037M6H-XXXHP
M38037M6H-XXXKP*
M38037M8H-XXXSP
M38037M8H-XXXFP
M38037M8H-XXXHP
M38037M8H-XXXKP*
64P4B
64P6N-A
64P6Q-A
64P6U-A
64P4B
16384
(16254)
Mask ROM version
24576
(24446)
64P6N-A
64P6Q-A
64P6U-A
64P4B
1024
1024
Mask ROM version
Mask ROM version
32768
(32638)
64P6N-A
64P6Q-A
64P6U-A
*: KP package is under development.
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
32
49
P20(LED0)
P3
7
/SRDY3
/SCLK3
31
30
29
28
P3
6
P21(LED1)
P22(LED2)
P23(LED3)
P24(LED4)
P25(LED5)
P26(LED6)
50
51
52
53
54
55
56
P3
5
/T
X
D
3
3
P3
4
/R
X
D
P3
3
2
2
P3
27
26
25
24
P3
1
/DA
M38034M4H-XXXFP/HP/KP (*)
P3
0/DA1
P27(LED7)
VCC
57 M38037M6H-XXXFP/HP/KP (*)
V
SS
23
22
21
V
REF
58
X
OUT
M38037M8H-XXXFP/HP/KP (*)
AVSS
/AN
XIN
59
60
61
62
P6
7
7
P4
P4
0
/INT40/XCOUT
20
19
18
17
P6
P6
P6
6/AN
5/AN
4
/AN
6
5
4
1/INT00/XCIN
RESET
CNVSS
63
64
P63/AN3
P42/INT1
Package type : 64P6N-A/64P6Q-A/64P6U-A (*)
Fig. 1 3803 group (Spec. H) pin configuration
Table 2 List of package (Spec. H)
ROM size (bytes)
ROM size for User in (
16384 (16254)
24576 (24446)
32768 (32638)
16384 (16254)
24576 (24446)
32768 (32638)
16384 (16254)
24576 (24446)
32768 (32638)
Product name
Package
Remarks
RAM size (bytes)
)
M38034M4H-XXXFP
640
1024
1024
640
Mask ROM version
M38037M6H-XXXFP
64P6N-A
M38037M8H-XXXFP
M38034M4H-XXXHP
M38037M6H-XXXHP
64P6Q-A
1024
1024
640
Mask ROM version
Mask ROM version
M38037M8H-XXXHP
M38034M4H-XXXKP
64P6U-A (*)
M38037M6H-XXXKP
M38037M8H-XXXKP
1024
1024
*: KP package is under development.
2
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
VREF
AVSS
P30/DA1
P31/DA2
P32
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P57/INT3
P56/PWM
P55/CNTR1
P54/CNTR0
P53/SRDY2
P52/SCLK2
P51/SOUT2
P50/SIN2
P33
P34/RXD3
P35/TXD3
P36/SCLK3
P37/SRDY3
P00/AN8
P01/AN9
P02/AN10
P03/AN11
P04/AN12
P05/AN13
P06/AN14
P07/AN15
P10/INT41
P11/INT01
P12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P13
P14
P15
P16
P47/SRDY1/CNTR2
P46/SCLK1
P45/TXD1
P44/RXD1
P43/INT2
P42/INT1
CNVSS
RESET
P41/INT00/XCIN
P40/INT40/XCOUT
XIN
P17
P20(LED0)
P21(LED1)
P22(LED2)
P23(LED3)
P24(LED4)
P25(LED5)
P26(LED6)
P27(LED7)
XOUT
VSS
Package type : 64P4B
Fig. 2 3803 group (Spec. H) pin configuration
Table 3 List of package (Spec. H)
ROM size (bytes)
Product name
Package
Remarks
RAM size (bytes)
ROM size for User in (
16384 (16254)
24576 (24446)
32768 (32638)
)
M38034M4H-XXXSP
640
1024
1024
Mask ROM version
M38037M6H-XXXSP
64P4B
M38037M8H-XXXSP
3
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK
Fig. 3 Functional block diagram
4
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 4 Pin description
Functions
Pin
Name
Function except a port function
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
Power source
CNVSS input
VCC, VSS
CNVSS
Reference voltage
•Reference voltage input pin for A-D and D-A converters.
•Analog power source input pin for A-D and D-A converters.
•Connect to VSS.
VREF
AVSS
Analog power source
Reset input
Clock input
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
XOUT
Clock output
I/O port P0
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
P00/AN8–
P07/AN15
•A-D converter input pin
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Interrupt input pin
P10/INT01 I/O port P1
P11/INT41
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
P12–P17
P20–P27
I/O port P2
I/O port P3
•P20–P27 are enabled to output large current for LED drive.
P3
P3
0
1
/DA
/DA
1
2
•8-bit CMOS I/O port.
•D-A converter input pin
•I/O direction register allows each pin to be individually
programmed as either input or output.
P32, P33
P34/RxD3
P35/TxD3
P36/SCLK3
P37/SRDY3
•P30, P31, P34–P37 are CMOS 3-state output structure.
•P32, P33 are N-channel open-drain output structure.
•Serial I/O3 function pin
•Pull-up control of P30, P31, P34–P37 is enabled in a bit
unit.
•Interrupt input pin
•8-bit CMOS I/O port.
P40/INT40/
XCOUT
I/O port P4
•Sub-clock generating I/O pin
(resonator connected)
•I/O direction register allows each pin to be individually
programmed as either input or output.
P41/INT00/
XCIN
•CMOS compatible input level.
•Interrupt input pin
P42/INT1
P43/INT2
P44/RxD1
P45/TxD1
P46/SCLK1
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
•Serial I/O1 function pin
P47/SRDY1
/CNTR2
•Serial I/O1, timer Z function pin
•Serial I/O2 function pin
I/O port P5
•8-bit CMOS I/O port.
P50/SIN2
•I/O direction register allows each pin to be individually
programmed as either input or output.
P51/SOUT2
P52/SCLK2
__________
•CMOS compatible input level.
P53/SRDY2
P54/CNTR0
P55/CNTR1
P56/PWM
P57/INT3
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
•Timer X function pin
•Timer Y function pin
•PWM output pin
•Interrupt input pin
P60/AN0–
P67/AN7
I/O port P6
•A-D converter input pin
5
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product name
M3803 7
M
8
H – XXX SP
Package type
SP : 64P4B
FP : 64P6N-A
HP : 64P6Q-A
KP : 64P6U-A (*)
ROM number
– : standard
Omitted in the flash memory version.
H– : Minner spec. change product
ROM size
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
9: 36864 bytes
A: 40960 bytes
B: 45056 bytes
C: 49152 bytes
D: 53248 bytes
E: 57344 bytes
F: 61440 bytes
1
2
3
4
5
6
7
8
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they
cannot be used as a user’s ROM area.
However, they can be programmed or erased in the flash memory version,
so that the users can use them.
Memory type
M : Mask ROM version
F : Flash memory version
RAM size
0: 192 bytes
1: 256 bytes
2: 384 bytes
3: 512 bytes
4: 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 4 Part numbering
*: KP package is under development.
6
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Packages
64P4B ......................................... 64-pin shrink plastic-molded DIP
64P6N-A .................................... 0.8 mm-pitch plastic molded QFP
64P6Q-A .................................. 0.5 mm-pitch plastic molded LQFP
64P6U-A ............................. 0.8 mm-pitch plastic molded LQFP (*)
GROUP EXPANSION
Mitsubishi plans to expand the 3803 group (Spec. H) as follows.
Memory Type
Support for mask ROM version.
Memory Size
Mask ROM size ................................................. 16 K to 32 K bytes
RAM size ............................................................ 640 to 1024 bytes
Memory Expansion Plan
As of Dec. 2002
M38039MF
ROM size (bytes)
: Under development
: Mass production
ROM
exteranal
M38039FF
60K
M38039FFH
48K
32K
28K
24K
20K
M38039MC
M38037M8H
M38037M6H
M38034M4H
16K
12K
8K
384
512
640
768
896
1024
1152
1280
1408
1536
2048
3072
4032
RAM size (bytes)
Note 1: Products under development or planning: the development schedule and specification may be revised
without notice. The development of planning products may be stopped.
Note 2: See the 3803/3804 group data sheet about 3803 group products other than 3803 group (spec. H) because
there are electrical characteristics differences and so on.
Fig. 5 Memory expansion plan
*: KP(64P6U-A) package is under development.
7
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 3803 group (Spec. H) uses the standard 740 Family instruc-
tion set. Refer to the table of 740 Family addressing modes and
machine instructions or the 740 Family Software Manual for de-
tails on the instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 10.
Store registers other than those described in Figure 10 with pro-
gram when the user needs them during interrupts or subroutine
calls.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b7
b0
Y
Index register Y
b7
b0
S
Stack pointer
b15
b7
b7
b0
PCH
PCL
Program counter
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig.6 740 Family CPU register structure
8
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PCH)
(S) (S) – 1
Push return address
on stack
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S)– 1
Subroutine
M (S) (PCL)
(S) (S) – 1
Push return address
on stack
Push contents of processor
status register on stack
M (S) (PS)
(S) (S) – 1
Interrupt
Service Routine
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
(PS)
M (S)
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
POP return
address
from stack
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 7 Register push and pop at interrupt generation and subroutine call
Table 5 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
9
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can execute decimal arithmetic.
Table 6 Set and clear instructions of each bit of processor status register
N flag
C flag
SEC
CLC
Z flag
I flag
SEI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
–
–
–
–
–
–
–
Set instruction
CLI
CLV
Clear instruction
10
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
1
(
CPUM : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 : Not available
1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0
0
1
1
0 : φ = f(XIN)/2 (high-speed mode)
1 : φ = f(XIN)/8 (middle-speed mode)
0 : φ = f(XCIN)/2 (low-speed mode)
1 : Not available
Fig.8 Structure of CPU mode register
11
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MISRG
ꢀMiddle-speed mode automatic switch by program
(1) Bit 0 of address 001016: Oscillation stabilizing time set af-
The middle-speed mode can also be automatically switched by
program while operating in low-speed mode. By setting the
middle-speed automatic switch start bit (bit 3) of MISRG (address
001016) to “1” in the condition that the middle-speed mode auto-
matic switch set bit is “1” while operating in low-speed mode, the
MCU will automatically switch to middle-speed mode. In this case,
the oscillation stabilizing time of the main clock can be selected by
the middle-speed automatic switch wait time set bit (bit 2) of
MISRG (address 001016).
ter STP instruction released bit
When the MCU stops the clock oscillation by the STP instruction
and the STP instruction has been released by an external interrupt
source, usually, the fixed values of Timer 1 and Prescaler 12
(Timer 1 = 0116, Prescaler 12 = FF16) are automatically reloaded
in order for the oscillation to stabilize. The user can inhibit the au-
tomatic setting by setting “1” to bit 0 of MISRG (address 001016).
However, by setting this bit to “1”, the previous values, set just be-
fore the STP instruction was executed, will remain in Timer 1 and
Prescaler 12. Therefore, you will need to set an appropriate value
to each register, in accordance with the oscillation stabilizing time,
before executing the STP instruction.
Figure 9 shows the structure of MISRG.
(2) Bits 1, 2, 3 of address 001016: Middle-speed Mode Auto-
matic Switch Function
In order to switch the clock mode of an MCU which has a sub-
clock, the following procedure is necessary:
set CPU mode register (003B16) --> start main clock oscillation -->
wait for oscillation stabilization --> switch to middle-speed mode
(or high-speed mode).
However, the 3803 group (Spec. H) has the built-in function which
automatically switches from low to middle-speed mode by pro-
gram.
b7
b0
MISRG
(MISRG : address 001016
)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1, “FF16” to
Prescaler 12
1: Automatically set disabled
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enabled (Note)
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start (Note)
Not used (return “0” when read)
(Do not write “1” to this bit)
Note: When automatic switch to middle-speed mode from low-speed mode occurs,
the values of CPU mode register (3B16) change.
Fig. 9 Structure of MISRG
12
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
Access to this area with only 2 bytes is possible in the special
RAM is used for data storage and for stack area of subroutine
page addressing mode.
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(bytes)
Address
XXXX16
000016
SFR area
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
004016
010016
RAM
XXXX16
Not used
0FF016
SFR area
0FFF16
Not used
YYYY16
ROM area
Reserved ROM area
(128 bytes)
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
ZZZZ16
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
FFFE16
Reserved ROM area
FFFF16
Fig. 10 Memory map diagram
13
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Prescaler 12 (PRE12)
Timer 1 (T1)
Port P0 (P0)
000016
000116
000216
002016
002116
002216
Port P0 direction register (P0D)
Port P1 (P1)
Timer 2 (T2)
Port P1 direction register (P1D)
000316
000416
000516
002316 Timer XY mode register (TM)
Prescaler X (PREX)
002416
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
002516
Timer X (TX)
Prescaler Y (PREY)
000616
000716
000816
000916
002616
002716
002816
002916
Port P3 direction register (P3D)
Timer Y (TY)
Port P4 (P4)
Timer Z low-order (TZL)
Port P4 direction register (P4D)
Port P5 (P5)
Timer Z high-order (TZH)
000A16
000B16
000C16
000D16
002A16 Timer Z mode register (TZM)
Port P5 direction register (P5D)
002B16
002C16
PWM control register (PWMCON)
PWM prescaler (PREPWM)
Port P6 (P6)
Port P6 direction register (P6D)
002D16 PWM register (PWM)
002E16
Timer 12, X count source selection register (T12XCSS)
Timer Y, Z count source selection register (TYZCSS)
000E16
000F16
002F16
003016
003116
Baud rate generator 3 (BRG3)
Transmit/Receive buffer register 3 (TB3/RB3)
001016 MISRG
001116
Serial I/O3 status register (SIO3STS)
Serial I/O3 control register (SIO3CON)
Reserved ✽
001216
001316
001416
001516
003216
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
003316 UART3 control register (UART3CON)
AD/DA control register (ADCON)
003516 A-D conversion register 1 (AD1)
003416
D-A1 conversion register (DA1)
D-A2 conversion register (DA2)
A-D conversion register 2 (AD2)
001616
001716
003616
003716
003816
001816 Transmit/Receive buffer register 1 (TB1/RB1)
001916 Serial I/O1 status register (SIO1STS)
003916 Interrupt source selection register (INTSEL)
003A16 Interrupt edge selection register (INTEDGE)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
001A16
001B16
CPU mode register (CPUM)
003B16
003C16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
001C16 Baud rate generator (BRG1)
001D16 Serial I/O2 control register (SIO2CON)
001E16 Watchdog timer control register (WDTCON)
003D16
003E16 Interrupt control register 1 (ICON1)
001F16
003F16
Interrupt control register 2 (ICON2)
Serial I/O2 register (SIO2)
Port P0 pull-up control register (PULL0)
Port P1 pull-up control register (PULL1)
0FF016
0FF116
0FF216 Port P2 pull-up control register (PULL2)
0FF316
Port P3 pull-up control register (PULL3)
Port P4 pull-up control register (PULL4)
Port P5 pull-up control register (PULL5)
Port P6 pull-up control register (PULL6)
0FF416
0FF516
0FF616
✽ Reserved area: Do not write any data to these addresses,
because these areas are reserved.
Fig. 11 Memory map of special function register (SFR)
14
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, and each pin can be set to be input
port or output port.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
When “0” is written to the bit corresponding to a pin, that pin be-
Table 7 I/O port function
Related SFRs
Ref.No.
(1)
Name
I/O Structure
CMOS compatible input level
CMOS 3-state output
Non-Port Function
A-D converter input
External interrupt input
Pin
P00/AN8–P07/AN15
P10/INT41
AD/DA control register
Port P0
Port P1
Interrupt edge selection
register
(2)
P11/INT01
P12–P17
(3)
Port P2
Port P3
P20/LED0–
P27/LED7
CMOS compatible input level
CMOS 3-state output
D-A converter output
Serial I/O3 function I/O
External interrupt input
AD/DA control register
(4)
(5)
P30/DA1
P31/DA2
CMOS compatible input level
N-channel open-drain output
CMOS compatible input level
CMOS 3-state output
P32
P33
Serial I/O3 control
register
(6)
(7)
P34/RxD3
P35/TxD3
P36/SCLK3
P37/SRDY3
P40/INT00/XCIN
P41/INT40/XCOUT
UART3 control register
(8)
(9)
Interrupt edge selection
register
(10)
(11)
CMOS compatible input level
CMOS 3-state output
Port P4
Sub-clock generating
circuit
CPU mode register
Interrupt edge selection
register
(2)
P42/INT1
External interrupt input
P43/INT2
(6)
(7)
Serial I/O1 control
register
P44/RxD1
Serial I/O1 function I/O
P45/TxD1
UART1 control register
(8)
P46/SCLK1
P47/SRDY1/CNTR2
(12)
Serial I/O1 function I/O
Timer Z function I/O
Serial I/O1 control
register
Timer Z mode register
Serial I/O2 control
register
P50/SIN2
Port P5
Serial I/O2 function I/O
(13)
(14)
(15)
(16)
(17)
CMOS compatible input level
CMOS 3-state output
P51/SOUT2
P52/SCLK2
P53/SRDY2
P54/CNTR0
P55/CNTR1
P56/PWM
P57/INT3
Timer X, Y function I/O
Timer XY mode register
PWM control register
PWM output
(18)
(2)
External interrupt input
Interrupt edge selection
register
P60/AN0–P67/AN7
A-D converter input
AD/DA control register
(1)
Port P6
CMOS compatible input level
CMOS 3-state output
Notes 1: Refer to the applicable sections how to use double-function ports as function I/O ports.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
15
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0, P6
(2) Ports P10, P11, P42, P43, P57
Pull-up control bit
Pull-up control bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
A-D converter input
Analog input pin
selection bit
Interrupt input
(3) Ports P1
2
to P1
7
, P2
(4) Ports P30, P31
Pull-up control bit
Pull-up control bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
D-A converter output
DA
DA
1
2
output enable (P3
0
)
)
output enable (P3
1
(6) Ports P34, P44
(5) Ports P32, P33
Pull-up control bit
Serial I/O enable bit
Receive enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O input
(7) Ports P3
5
, P4
5
(8) Ports P36, P46
Pull-up control bit
Serial I/O synchronous clock
selection bit
Pull-up control bit
Serial I/O enable bit
P-channel output
disable bit
Serial I/O mode selection bit
Serial I/O enable bit
Serial I/O enable bit
Transmit enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O clock output
Serial I/O output
Serial I/O external clock input
Fig. 12 Port block diagram (1)
16
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Port P3
7
(10) Port P40
Pull-up control bit
Pull-up control bit
Serial I/O3 mode
selection bit
Serial I/O3 enable bit
Port X
C
switch bit
S
RDY3 output enable bit
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
INT40 interrupt input
Serial I/O3 ready output
Oscillator
Port P4
1
Port XC switch bit
(11) Port P4
1
(12) Port P47
Timer Z operating
mode bits
Bit 2
Pull-up control bit
Pull-up control bit
Bit 1
Bit 0
Port X
C
switch bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
register
SRDY1 output enable bit
Direction
register
Data bus
Port latch
Data bus
Port latch
INT00 interrupt input
Sub-clock generating circuit input
Timer output
Serial I/O1 ready output
CNTR2 interrupt input
(13) Port P5
0
(14) Port P51
Pull-up control bit
Pull-up control bit
Serial I/O2 transmit completion signal
Serial I/O2 port selection bit
P-channel output
disable bit
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
Serial I/O2 input
Serial I/O2 output
Fig. 13 Port block diagram (2)
17
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(15) Port P5
2
(16) Port P53
Pull-up control bit
Pull-up control bit
Serial I/O2 synchronous clock
selection bit
Serial I/O2 port selection bit
S
RDY2 enable bit
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
Serial I/O2 ready output
Serial I/O2 clock output
Serial I/O2 external clock input
(17) Ports P5
4
, P5
5
(18) Port P56
Pull-up control bit
Pull-up control bit
PWM output enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Pulse output mode
Timer output
PWM output
CNTR interrupt input
Fig. 14 Port block diagram (3)
18
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Port P0 pull-up control register
(PULL0: address 0FF016
)
P00 pull-up control bit
0: No pull-up
1: Pull-up
P01 pull-up control bit
0: No pull-up
1: Pull-up
P02 pull-up control bit
0: No pull-up
1: Pull-up
P03 pull-up control bit
0: No pull-up
1: Pull-up
P04 pull-up control bit
0: No pull-up
1: Pull-up
P05 pull-up control bit
0: No pull-up
1: Pull-up
P06 pull-up control bit
0: No pull-up
1: Pull-up
P07 pull-up control bit
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
0: No pull-up
1: Pull-up
b7
b0
Port P1 pull-up control register
(PULL1: address 0FF116
)
P10 pull-up control bit
0: No pull-up
1: Pull-up
P11 pull-up control bit
0: No pull-up
1: Pull-up
P12 pull-up control bit
0: No pull-up
1: Pull-up
P13 pull-up control bit
0: No pull-up
1: Pull-up
P14 pull-up control bit
0: No pull-up
1: Pull-up
P15 pull-up control bit
0: No pull-up
1: Pull-up
P16 pull-up control bit
0: No pull-up
1: Pull-up
P17 pull-up control bit
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
0: No pull-up
1: Pull-up
Fig. 15 Structure of port pull-up control register (1)
19
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Port P2 pull-up control register
(PULL2: address 0FF216
)
P20 pull-up control bit
0: No pull-up
1: Pull-up
P21 pull-up control bit
0: No pull-up
1: Pull-up
P22 pull-up control bit
0: No pull-up
1: Pull-up
P23 pull-up control bit
0: No pull-up
1: Pull-up
P24 pull-up control bit
0: No pull-up
1: Pull-up
P25 pull-up control bit
0: No pull-up
1: Pull-up
P26 pull-up control bit
0: No pull-up
1: Pull-up
P27 pull-up control bit
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
0: No pull-up
1: Pull-up
b7
b0
Port P3 pull-up control register
(PULL3: address 0FF316
)
P30 pull-up control bit
0: No pull-up
1: Pull-up
P31 pull-up control bit
0: No pull-up
1: Pull-up
Not used
(return “0” when read)
P34 pull-up control bit
0: No pull-up
1: Pull-up
P35 pull-up control bit
0: No pull-up
1: Pull-up
P36 pull-up control bit
0: No pull-up
1: Pull-up
P37 pull-up control bit
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
Fig. 16 Structure of port pull-up control register (2)
20
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Port P4 pull-up control register
(PULL4: address 0FF416
)
P40 pull-up control bit
0: No pull-up
1: Pull-up
P41 pull-up control bit
0: No pull-up
1: Pull-up
P42 pull-up control bit
0: No pull-up
1: Pull-up
P43 pull-up control bit
0: No pull-up
1: Pull-up
P44 pull-up control bit
0: No pull-up
1: Pull-up
P45 pull-up control bit
0: No pull-up
1: Pull-up
P46 pull-up control bit
0: No pull-up
1: Pull-up
P47 pull-up control bit
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
0: No pull-up
1: Pull-up
b7
b0
Port P5 pull-up control register
(PULL5: address 0FF516
)
P50 pull-up control bit
0: No pull-up
1: Pull-up
P51 pull-up control bit
0: No pull-up
1: Pull-up
P52 pull-up control bit
0: No pull-up
1: Pull-up
P53 pull-up control bit
0: No pull-up
1: Pull-up
P54 pull-up control bit
0: No pull-up
1: Pull-up
P55 pull-up control bit
0: No pull-up
1: Pull-up
P56 pull-up control bit
0: No pull-up
1: Pull-up
P57 pull-up control bit
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
0: No pull-up
1: Pull-up
Fig. 17 Structure of port pull-up control register (3)
21
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Port P6 pull-up control register
(PULL6: address 0FF616
)
P60 pull-up control bit
0: No pull-up
1: Pull-up
P61 pull-up control bit
0: No pull-up
1: Pull-up
P62 pull-up control bit
0: No pull-up
1: Pull-up
P63 pull-up control bit
0: No pull-up
1: Pull-up
P64 pull-up control bit
0: No pull-up
1: Pull-up
P65 pull-up control bit
0: No pull-up
1: Pull-up
P66 pull-up control bit
0: No pull-up
1: Pull-up
P67 pull-up control bit
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
0: No pull-up
1: Pull-up
Fig. 18 Structure of port pull-up control register (4)
22
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
The 3803 group (Spaec. H)’s interrupts are a type of vector and
occur by 16 sources among 21 sources: eight external, twelve in-
ternal, and one software.
ꢀ Notes
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer XY mode register (address 2316)
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Timer Z mode register (address 2A16)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection register
(address 3916)
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
ꢀSet the corresponding interrupt enable bit to “0” (disabled).
ꢀSet the interrupt edge select bit or the interrupt source select bit
to “1”.
The reset and the BRK instruction cannot be disabled with any
flag or bit. The I (interrupt disable) flag disables all interrupts ex-
cept the reset and the BRK instruction interrupt.
When several interrupt requests occur at the same time, the inter-
rupts are received according to priority.
ꢀSet the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
ꢀSet the corresponding interrupt enable bit to “1” (enabled).
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Source Selection
Which of each combination of the following interrupt sources can
be selected by the interrupt source selection register (address
003916).
1. INT0 or Timer Z
2. CNTR1 or Serial I/O3 reception
3. Serial I/O2 or Timer Z
7. INT4 or CNTR2
8. A-D converter or serial I/O3 transmission
External Interrupt Pin Selection
The occurrence sources of the external interrupt INT0 and INT4
can be selected from either input from INT00 and INT40 pin, or in-
put from INT01 and INT41 pin by the INT0, INT4 interrupt switch bit
of interrupt edge selection register (bit 6 of address 003A16).
23
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Remarks
Non-maskable
Interrupt Source
Priority
High
Low
1
2
FFFD16
FFFB16
FFFC16
FFFA16
Reset (Note 2)
INT0
At reset
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
Timer Z
INT1
At timer Z underflow
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
3
4
5
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT1 input
Serial I/O1
reception
Valid when serial I/O1 is selected
At completion of serial I/O1 data
reception
Serial I/O1
transmission
Valid when serial I/O1 is selected
At completion of serial I/O1
transmission shift or when
transmission buffer is empty
Timer X
Timer Y
Timer 1
Timer 2
CNTR0
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
8
STP release timer underflow
9
10
At detection of either rising or
falling edge of CNTR0 input
External interrupt
(active edge selectable)
CNTR1
At detection of either rising or External interrupt
11
12
FFE816
FFE916
falling edge of CNTR1 input
(active edge selectable)
Serial I/O3
reception
At completion of serial I/O3 data Valid when serial I/O3 is selected
reception
Serial I/O2
FFE716
FFE616
At completion of serial I/O2 data Valid when serial I/O2 is selected
transmission or reception
Timer Z
INT2
At timer Z underflow
13
14
15
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT2 input
FFE516
FFE316
FFE116
FFE416
FFE216
FFE016
INT3
INT4
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT3 input
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT4 input
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR2 input
CNTR2
16
17
At completion of A-D conversion
FFDF16
FFDD16
FFDE16
FFDC16
A-D converter
Valid when serial I/O3 is selected
Non-maskable software interrupt
At completion of serial I/O3
transmission shift or when
transmission buffer is empty
Serial I/O3
transmission
At BRK instruction execution
BRK instruction
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
24
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 19 Interrupt control
25
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
0 : Falling edge active
1 : Rising edge active
INT
INT
0
1
active edge selection bit
active edge selection bit
Not used (returns “0” when read)
INT
INT
INT
INT
2
3
4
0
active edge selection bit
active edge selection bit
active edge selection bit
0 : Falling edge active
1 : Rising edge active
, INT4 interrupt switch bit
0 : INT00, INT40 interrupt
1 : INT01, INT41 interrupt
Not used (returns “0” when read)
b7
b0
b7
b0
Interrupt request register 1
Interrupt request register 2
(IREQ2 : address 003D16
)
(IREQ1 : address 003C16
)
INT
INT
0
1
/Timer Z interrupt request bit
interrupt request bit
CNTR
CNTR
0
interrupt request bit
1
/Serial I/O3 receive interrupt
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
request bit
Serial I/O2/Timer Z interrupt request bit
INT
INT
INT
2 interrupt request bit
3 interrupt request bit
4/CNTR2 interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
AD converter/Serial I/O3 transmit
interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 2
Interrupt control register 1
(ICON2 : address 003F16
)
(ICON1 : address 003E16
)
INT
INT
0
1
/Timer Z interrupt enable bit
interrupt enable bit
CNTR
CNTR
0
1
interrupt enable bit
/Serial I/O3 receive interrupt
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
enable bit
Serial I/O2/Timer Z interrupt enable bit
INT
INT
INT
2 interrupt enable bit
3 interrupt enable bit
4/CNTR2 interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
AD converter/Serial I/O3 transmit
interrupt enable bit
Not used (returns “0” when read)
0 : Interrupts disabled
1 : Interrupts enabled
b0
b7
Interrupt source selection register
(INTSEL: address 003916
)
INT /Timer Z interrupt source selection bit
0
0 : INT interrupt
0
1 : Timer Z interrupt
Serial I/O2/Timer Z interrupt source selection bit
0 : Serial I/O2 interrupt
1 : Timer Z interrupt
Not used
(Do not write “1” to these bits.)
(Do not write “1” to these bits simultaneously.)
INT
4
/CNTR
2 interrupt source selection bit
0 : INT
4
interrupt
1 : CNTR
Not used
(Do not write “1” to this bit.)
2 interrupt
CNTR
0 : CNTR
1 : Serial I/O3 receive interrupt
1
/Serial I/O3 receive interrupt source selection bit
1
interrupt
AD converter/Serial I/O3 transmit interrupt source selection bit
0 : A-D converter interrupt
1 : Serial I/O3 transmit interrupt
Fig. 20 Structure of interrupt-related registers
26
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
Timer X and Timer Y
ꢀ8-bit Timers
The timer X and timer Y can each select one of four operating
The 3803 group (Spec. H) has four 8-bit timers: timer 1, timer 2,
modes by setting the timer XY mode register (address 002316).
timer X, and timer Y.
The timer 1 and timer 2 use one prescaler in common, and the
timer X and timer Y use each prescaler. Those are 8-bit
prescalers. Each of the timers and prescalers has a timer latch or
a prescaler latch.
(1) Timer mode
ꢀMode selection
This mode can be selected by setting “00” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down-counters. When the timer reaches “0016”, an
underflow occurs at the next count pulse and the contents of the
corresponding timer latch are reloaded into the timer and the
count is continued. When the timer underflows, the interrupt re-
quest bit corresponding to that timer is set to “1”.
ꢀExplanation of operation
The timer count operation is started by setting “0” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 002316).
When the timer reaches “0016”, an underflow occurs at the next
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
ꢀTimer divider
The divider count source is switched by the main clock division
ratio selection bits of CPU mode register (bits 7 and 6 at address
003B16). When these bits are “00” (high-speed mode) or “01”
(middle-speed mode), XIN is selected. When these bits are“10”
(low-speed mode), XCIN is selected.
(2) Pulse output mode
ꢀMode selection
This mode can be selected by setting “01” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
ꢀExplanation of operation
ꢀPrescaler 12
The prescaler 12 counts the output of the timer divider. The count
source is selected by the timer 12, X count source selection
register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512,
1/1024 of f(XIN) or f(XCIN).
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR0/CNTR1 pin. Regardless of the timer counting or not
the output of CNTR0/CNTR1 pin is initialized to the level of speci-
fied by their active edge switch bits when writing to the timer.
When the CNTR0 active edge switch bit (bit 2) and the CNTR1 ac-
tive edge switch bit (bit 6) of the timer XY mode register (address
002316) is “0”, the output starts with “H” level. When it is “1”, the
output starts with “L” level.
Timer 1 and Timer 2
The timer 1 and timer 2 counts the output of prescaler 12 and pe-
riodically set the interrupt request bit.
ꢀPrescaler X and prescaler Y
Switching the CNTR0 or CNTR1 active edge switch bit will reverse
the output level of the corresponding CNTR0 or CNTR1 pin.
ꢀPrecautions
The prescaler X and prescaler Y count the output of the timer
divider or f(XCIN). The count source is selected by the timer 12, X
count source selection register (address 000E16) and the timer Y,
Z count source selection register (address 000F16) among 1/2,
1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(XIN)
or f(XCIN); and f(XCIN).
Set the double-function port of CNTR0/CNTR1 pin and port P54/
P55 to output in this mode.
27
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(3) Event counter mode
ꢀMode selection
This mode can be selected by setting “10” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
ꢀExplanation of operation
The operation is the same as the timer mode’s except that the
timer counts signals input from the CNTR0 or CNTR1 pin. The
valid edge for the count operation depends on the CNTR0 active
edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6)
of the timer XY mode register (address 002316). When it is “0”, the
rising edge is valid. When it is “1”, the falling edge is valid.
ꢀPrecautions
Set the double-function port of CNTR0/CNTR1 pin and port P54/
P55 to input in this mode.
(4) Pulse width measurement mode
ꢀMode selection
This mode can be selected by setting “11” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
ꢀExplanation of operation
When the CNTR0 active edge switch bit (bit 2) or the CNTR1 ac-
tive edge switch bit (bit 6) of the timer XY mode register (address
002316) is “1”, the timer counts during the term of one falling edge
of CNTR0/CNTR1 pin input until the next rising edge of input (“L”
term). When it is “0”, the timer counts during the term of one rising
edge input until the next falling edge input (“H” term).
ꢀPrecautions
Set the double-function port of CNTR0/CNTR1 pin and port P54/
P55 to input in this mode.
The count operation can be stopped by setting “1” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 002316). The interrupt request bit
is set to “1” each time the timer underflows.
•Precautions when switching count source
When switching the count source by the timer 12, X and Y count
source selection bits, the value of timer count is altered in incon-
siderable amount owing to generating of thin pulses on the count
input signals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
28
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
IN
“00”
“01”
(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)
Divider
Count source
selection bit
“10”
X
CIN
Data bus
Main clock
division ratio
selection bits
Prescaler X latch (8)
Timer X latch (8)
f(XCIN
)
Pulse width
Timer mode
Pulse output mode
measurement
mode
To timer X interrupt
request bit
Prescaler X (8)
Timer X (8)
CNTR
switch bit
0 active edge
Event
counter
mode
Timer X count stop bit
P5
4
/CNTR
0
“0”
“1”
To CNTR
0 interrupt
request bit
CNTR
edge switch bit
0
active
“1”
Q
Q
T
Toggle flip-flop
R
“0”
Port P5
latch
4
Timer X latch write pulse
Pulse output mode
Port P5
4
direction register
Pulse output mode
Data bus
Count source selection bit
Clock for timer Y
f(XCIN
Timer Y latch (8)
Timer Y (8)
Prescaler Y latch (8)
Pulse width
measurement
mode
)
Timer mode
Pulse output mode
To timer Y interrupt
request bit
Prescaler Y (8)
CNTR
switch bit
1
active edge
Event
counter
mode
Timer Y count stop bit
P55/CNTR1
“0”
“1”
To CNTR
1 interrupt
request bit
CNTR
edge switch bit
1
active
“1”
Q
Q
T
Toggle flip-flop
R
“0”
Port P5
latch
5
Timer Y latch write pulse
Pulse output mode
Port P5
direction register
5
Pulse output mode
Data bus
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
Prescaler 12 latch (8)
Prescaler 12 (8)
To timer 2 interrupt
request bit
Clock for timer 12
To timer 1 interrupt
request bit
Fig. 21 Block diagram of timer X, timer Y, timer 1, and timer 2
29
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Timer XY mode register
(TM : address 002316
)
Timer X operating mode bits
b1 b0
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
CNTR0 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge in event counter mode
1 : Interrupt at rising edge
Count at falling edge in event counter mode
Timer X count stop bit
0 : Count start
1 : Count stop
Timer Y operating mode bits
b5 b4
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
CNTR1 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge in event counter mode
1 : Interrupt at rising edge
Count at falling edge in event counter mode
Timer Y count stop bit
0 : Count start
1 : Count stop
Fig. 22 Structure of timer XY mode register
30
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Timer 12, X count source selection register
(T12XCSS : address 000E16
)
Timer 12 count source selection bits
b3b2b1b0
1010 :
1011 :
1100 :
1101 :
1110 :
1111 :
0 0 0 0 : f(X )/2 or f(X )/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCCIINN)/8
0 0 1 1 : f(XIN)/16 or f(X )/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCCIINN)/64
0 1 1 0 : f(XIN)/128 or f(X )/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCCIINN)/512
1 0 0 1 : f(XIINN)/1024 or f(XCIN)/1024
Not used
Timer X count source selection bits
b7b6b5b4
0 0 0 0 : f(X )/2 or f(X )/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCCIINN)/8
0 0 1 1 : f(XIN)/16 or f(X )/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCCIINN)/64
0 1 1 0 : f(XIN)/128 or f(X )/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCCIINN)/512
1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024
1011 :
1100 :
1101 : Not used
1110 :
1111 :
1 0 1 0 : f(XCININ
)
b7
b0
Timer Y, Z count source selection register
(TYZCSS : address 000F16
)
Timer Y count source selection bits
b3b2b1b0
0 0 0 0 : f(X )/2 or f(X )/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCCIINN)/8
0 0 1 1 : f(XIN)/16 or f(X )/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCCIINN)/64
0 1 1 0 : f(XIN)/128 or f(X )/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCCIINN)/512
1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024
1011 :
1100 :
1101 :
1110 :
1111 :
Not used
1 0 1 0 : f(XCININ
)
Timer Z count source selection bits
b7b6b5b4
0 0 0 0 : f(X )/2 or f(X )/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCCIINN)/8
0 0 1 1 : f(XIN)/16 or f(X )/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCCIINN)/64
0 1 1 0 : f(XIN)/128 or f(X )/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCCIINN)/512
1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024
1011 :
1100 :
1101 : Not used
1110 :
1111 :
1 0 1 0 : f(XCININ
)
Fig. 23 Structure of timer 12, X and timer Y, Z count source selection registers
31
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●16-bit Timer
(2) Event counter mode
The timer Z is a 16-bit timer. When the timer reaches “000016”, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When the timer underflows, the interrupt request bit corresponding
to the timer Z is set to “1”.
●Mode selection
This mode can be selected by setting “000” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “1” to the timer/event
counter mode switch bit (bit 7) of the timer Z mode register (ad-
dress 002A16).
When reading/writing to the timer Z, perform reading/writing to
both the high-order byte and the low-order byte. When reading the
timer Z, read from the high-order byte first, followed by the low-or-
der byte. Do not perform the writing to the timer Z between read
operation of the high-order byte and read operation of the low-or-
der byte. When writing to the timer Z, write to the low-order byte
first, followed by the high-order byte. Do not perform the reading
to the timer Z between write operation of the low-order byte and
write operation of the high-order byte.
The valid edge for the count operation depends on the CNTR2 ac-
tive edge switch bit (bit 5) of the timer Z mode register (address
002A16). When it is “0”, the rising edge is valid. When it is “1”, the
falling edge is valid.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
The operation is the same as the timer mode’s.
Set the double-function port of CNTR2 pin and port P47 to input in
this mode.
The timer Z can select the count source by the timer Z count
source selection bits of timer Y, Z count source selection register
(bits 7 to 4 at address 000F16).
Figure 26 shows the timing chart of the timer/event counter mode.
Timer Z can select one of seven operating modes by setting the
timer Z mode register (address 002A16).
(3) Pulse output mode
●Mode selection
This mode can be selected by setting “001” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
(1) Timer mode
●Mode selection
This mode can be selected by setting “000” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
●Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
●Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
●Interrupt
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of
the timer Z mode register (address 002A16) is “0”, the output starts
with “H” level. When it is “1”, the output starts with “L” level.
●Precautions
When an underflow occurs, the INT0/timer Z interrupt request bit
(bit 0) of the interrupt request register 1 (address 003C16) is set to
“1”.
●Explanation of operation
During timer stop, usually write data to a latch and a timer at the
same time to set the timer value.
Set the double-function port of CNTR2 pin and port P47 to output
in this mode.
The timer count operation is started by setting “0” to the timer Z
count stop bit (bit 6) of the timer Z mode register (address
002A16).
The output from CNTR2 pin is initialized to the level depending on
CNTR2 active edge switch bit by writing to the timer.
When the value of the CNTR2 active edge switch bit is changed,
the output level of CNTR2 pin is inverted.
When the timer reaches “000016”, an underflow occurs at the next
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
Figure 27 shows the timing chart of the pulse output mode.
When writing data to the timer during operation, the data is written
only into the latch. Then the new latch value is reloaded into the
timer at the next underflow.
32
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(4) Pulse period measurement mode
ꢀMode selection
(5) Pulse width measurement mode
ꢀMode selection
This mode can be selected by setting “010” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
This mode can be selected by setting “011” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
ꢀCount source selection
ꢀCount source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected
as the count source.
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected
as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
ꢀInterrupt
ꢀInterrupt
The interrupt at an underflow is the same as the timer mode’s.
When the pulse period measurement is completed, the INT4/
CNTR2 interrupt request bit (bit 5) of the interrupt request register
2 (address 003D16) is set to “1”.
The interrupt at an underflow is the same as the timer mode’s.
When the pulse widths measurement is completed, the INT4/
CNTR2 interrupt request bit (bit 5) of the interrupt request register
2 (address 003D16) is set to “1”.
ꢀExplanation of operation
ꢀExplanation of operation
The cycle of the pulse which is input from the CNTR2 pin is mea-
sured. When the CNTR2 active edge switch bit (bit 5) of the timer
Z mode register (address 002A16) is “0”, the timer counts during
the term from one falling edge of CNTR2 pin input to the next fall-
ing edge. When it is “1”, the timer counts during the term from one
rising edge input to the next rising edge input.
When the valid edge of measurement completion/start is detected,
the 1’s complement of the timer value is written to the timer latch
and “FFFF16” is set to the timer.
The pulse width which is input from the CNTR2 pin is measured.
When the CNTR2 active edge switch bit (bit 5) of the timer Z mode
register (address 002A16) is “0”, the timer counts during the term
from one rising edge input to the next falling edge input (“H” term).
When it is “1”, the timer counts during the term from one falling
edge of CNTR2 pin input to the next rising edge of input (“L” term).
When the valid edge of measurement completion is detected, the
1’s complement of the timer value is written to the timer latch and
“FFFF16” is set to the timer.
Furthermore when the timer underflows, the timer Z interrupt re-
quest occurs and “FFFF16” is set to the timer. When reading the
timer Z, the value of the timer latch (measured value) is read. The
measured value is retained until the next measurement comple-
tion.
When the timer Z underflows, the timer Z interrupt occurs and
“FFFF16” is set to the timer Z. When reading the timer Z, the value
of the timer latch (measured value) is read. The measured value is
retained until the next measurement completion.
ꢀPrecautions
ꢀPrecautions
Set the double-function port of CNTR2 pin and port P47 to input in
this mode.
Set the double-function port of CNTR2 pin and port P47 to input in
this mode.
A read-out of timer value is impossible in this mode. The timer can
be written to only during timer stop (no measurement of pulse
widths).
A read-out of timer value is impossible in this mode. The timer can
be written to only during timer stop (no measurement of pulse pe-
riod).
Since the timer latch in this mode is specialized for the read-out of
measured values, do not perform any write operation during mea-
surement.
Since the timer latch in this mode is specialized for the read-out of
measured values, do not perform any write operation during mea-
surement.
“FFFF16” is set to the timer when the timer underflows or when the
valid edge of measurement start/completion is detected. Conse-
quently, the timer value at start of pulse width measurement
depends on the timer value just before measurement start.
Figure 29 shows the timing chart of the pulse width measurement
mode.
“FFFF16” is set to the timer when the timer underflows or when the
valid edge of measurement start/completion is detected. Conse-
quently, the timer value at start of pulse period measurement
depends on the timer value just before measurement start.
Figure 28 shows the timing chart of the pulse period measurement
mode.
33
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(6) Programmable waveform generating mode
ꢀMode selection
though “H” is output from the CNTR2 pin, “H” output state contin-
ues because an underflow does not occur.
This mode can be selected by setting “100” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
•“L” one-shot pulse; Bit 5 of timer Z mode register = “1”
The output level of the CNTR2 pin is initialized to “H” at mode se-
lection. When trigger generation (input signal to INT1 pin) is
detected, “L” is output from the CNTR2 pin. When an underflow
occurs, “H” is output. The “L” one-shot pulse width is set by the
setting value to the timer Z low-order and high-order. When trigger
generating is detected during timer count stop, although “L” is out-
put from the CNTR2 pin, “L” output state continues because an
underflow does not occur.
ꢀCount source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected
as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
ꢀPrecautions
Set the double-function port of CNTR2 pin and port P47 to output,
and of INT1 pin and port P42 to input in this mode.
This mode cannot be used in low-speed mode.
ꢀInterrupt
The interrupt at an underflow is the same as the timer mode’s.
ꢀExplanation of operation
If the value of the CNTR2 active edge switch bit is changed during
one-shot generating enabled or generating one-shot pulse, then
the output level from CNTR2 pin changes.
The operation is the same as the timer mode’s. Moreover the
timer outputs the data set in the output level latch (bit 4) of the
timer Z mode register (address 002A16) from the CNTR2 pin each
time the timer underflows.
Figure 31 shows the timing chart of the programmable one-shot
generating mode.
Changing the value of the output level latch and the timer latch af-
ter an underflow makes it possible to output an optional waveform
from the CNTR2 pin.
ꢀNotes regarding all modes
ꢀTimer Z write control
ꢀPrecautions
Which write control can be selected by the timer Z write control bit
(bit 3) of the timer Z mode register (address 002A16), writing data
to both the latch and the timer at the same time or writing data
only to the latch.
Set the double-function port of CNTR2 pin and port P47 to output
in this mode.
Figure 30 shows the timing chart of the programmable waveform
generating mode.
When the operation “writing data only to the latch” is selected, the
value is set to the timer latch by writing data to the address of
timer Z and the timer is updated at next underflow. After reset re-
lease, the operation “writing data to both the latch and the timer at
the same time” is selected, and the value is set to both the latch
and the timer at the same time by writing data to the address of
timer Z.
(7) Programmable one-shot generating mode
ꢀMode selection
This mode can be selected by setting “101” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
In the case of writing data only to the latch, if writing data to the
latch and an underflow are performed almost at the same time,
the timer value may become undefined.
ꢀCount source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
ꢀTimer Z read control
A read-out of timer value is impossible in pulse period measure-
ment mode and pulse width measurement mode. In the other
modes, a read-out of timer value is possible regardless of count
operating or stopped.
ꢀInterrupt
The interrupt at an underflow is the same as the timer mode’s.
The trigger to generate one-shot pulse can be selected by the
INT1 active edge selection bit (bit 1) of the interrupt edge selection
register (address 003A16). When it is “0”, the falling edge active is
selected; when it is “1”, the rising edge active is selected.
When the valid edge of the INT1 pin is detected, the INT1 interrupt
request bit (bit 1) of the interrupt request register 1 (address
003C16) is set to “1”.
However, a read-out of timer latch value is impossible.
ꢀSwitch of interrupt active edge of CNTR2 and INT1
Each interrupt active edge depends on setting of the CNTR2 ac-
tive edge switch bit and the INT1 active edge selection bit.
ꢀSwitch of count source
When switching the count source by the timer Z count source se-
lection bits, the value of timer count is altered in inconsiderable
amount owing to generating of thin pulses on the count input sig-
nals.
ꢀExplanation of operation
•“H” one-shot pulse; Bit 5 of timer Z mode register = “0”
The output level of the CNTR2 pin is initialized to “L” at mode se-
lection. When trigger generation (input signal to INT1 pin) is
detected, “H” is output from the CNTR2 pin. When an underflow
occurs, “L” is output. The “H” one-shot pulse width is set by the
setting value to the timer Z register low-order and high-order.
When trigger generating is detected during timer count stop, al-
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
ꢀUsage of CNTR2 pin as normal I/O port
To use the CNTR2 pin as normal I/O port P47, set timer Z operat-
ing mode bits (b2, b1, b0) of timer Z mode register (address
002A16) to “000”.
34
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CNTR2 active edge
Data bus
switch bit
Programmable one-shot
generating mode
“1”
P42/INT1
Programmable one-shot
generating circuit
Programmable one-shot
generating mode
“0”
To INT1 interrupt
request bit
Programmable waveform
generating mode
D
Q
Output level latch
T
Pulse output mode
CNTR2 active edge
switch bit
S
“0”
Q
Q
T
“1”
Pulse output mode
“001”
“100”
“101”
Timer Z operating
mode bits
Timer Z low-order latch Timer Z high-order latch
Timer Z low-order Timer Z high-order
To timer Z interrupt
request bit
Port P47
latch
Port P47
direction register
Pulse period measurement mode
Pulse width measurement mode
Edge detection circuit
To CNTR2 interrupt
request bit
“1”
“1”
f(XCIN
)
P47/CNTR2
“0”
“0”
CNTR2 active edge
Timer Z count stop bit
Timer/Event
counter mode
switch bit
switch bit
X
IN
Count source
selection bit
Divider
(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)
X
CIN
Fig. 24 Block diagram of timer Z
35
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Timer Z mode register
(TZM : address 002A16
)
Timer Z operating mode bits
b2b1b0
0 0 0 : Timer/Event counter mode
0 0 1 : Pulse output mode
0 1 0 : Pulse period measurement mode
0 1 1 : Pulse width measurement mode
1 0 0 : Programmable waveform generating mode
1 0 1 : Programmable one-shot generating mode
1 1 0 : Not available
1 1 1 : Not available
Timer Z write control bit
0 : Writing data to both latch and timer simultaneously
1 : Writing data only to latch
Output level latch
0 : “L” output
1 : “H” output
CNTR active edge switch bit
2
0 : •Event counter mode: Count at rising edge
•Pulse output mode: Start outputting “H”
•Pulse period measurement mode: Measurement
between two falling edges
•Pulse width measurement mode: Measurement of
“H” term
•Programmable one-shot generating mode: After
start outputting “L”, “H” one-shot pulse generated
•Interrupt at falling edge
1 : •Event counter mode: Count at falling edge
•Pulse output mode: Start outputting “L”
•Pulse period measurement mode: Measurement
between two rising edges
•Pulse width measurement mode: Measurement of
“L” term
•Programmable one-shot generating mode: After
start outputting “H”, “L” one-shot pulse generated
•Interrupt at rising edge
Timer Z count stop bit
0 : Count start
1 : Count stop
Timer/Event counter mode switch bit (Note)
0 : Timer mode
1 : Event counter mode
Note: When selecting the modes except the timer/event
counter mode, set “0” to this bit.
Fig. 25 Structure of timer Z mode register
36
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FFFF16
TL
000016
TR
TR
TR
TL : Value set to timer latch
TR : Timer interrupt request
Fig. 26 Timing chart of timer/event counter mode
FFFF16
TL
000016
TR
TR
TR
TR
Waveform output
from CNTR pin
2
CNTR
2
CNTR
2
TL : Value set to timer latch
TR : Timer interrupt request
CNTR
2
: CNTR
2 interrupt request
(CNTR
2
active edge switch bit = “0”; Falling edge active)
Fig. 27 Timing chart of pulse output mode
37
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016
T3
T2
T1
FFFF16
TR
TR
T2
T3
FFFF16 + T1
FFFF16
Signal input from
CNTR pin
2
CNTR
2
CNTR
2
CNTR
2
CNTR2
CNTR
TR : Timer interrupt request
CNTR : CNTR interrupt request
2 of rising edge active
2
2
Fig. 28 Timing chart of pulse period measurement mode (Measuring term between two rising edges)
000016
T3
T2
T1
FFFF16
TR
T1
FFFF16 + T2
T3
Signal input from
CNTR pin
2
CNTR
2
CNTR
interrupt of rising edge active; Measurement of “L” width
TR : Timer interrupt request
CNTR : CNTR interrupt request
2
CNTR2
CNTR
2
2
2
Fig. 29 Timing chart of pulse width measurement mode (Measuring “L” term)
38
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FFFF16
T3
L
T2
T1
000016
Signal output
from CNTR2 pin
L
T3
T1
TR
CNTR2
L : Timer initial value
T2
TR
TR
TR
CNTR2
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
(CNTR2 active edge switch bit = “0”; Falling edge active)
Fig. 30 Timing chart of programmable waveform generating mode
FFFF16
L
TR
TR
TR
Signal input from
INT pin
1
Signal output
from CNTR pin
L
L
L
2
CNTR
2
CNTR2
L : One-shot pulse width
TR : Timer interrupt request
CNTR : CNTR interrupt request
(CNTR active edge switch bit = “0”; Falling edge active)
2
2
2
Fig. 31 Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating)
39
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6 of address 001A16) to “1”.
SERIAL I/O
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Data bus
Serial I/O1 control register
Receive buffer full flag (RBF)
Address 001A16
Address 001816
Receive buffer register 1
Receive shift register 1
Receive interrupt request (RI)
P44/RXD1
Shift clock
Clock control circuit
P46/SCLK1
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
(f(XCIN) in low-speed mode)
f(XIN
)
Baud rate generator 1
Address 001C16
1/4
1/4
Clock control circuit
Falling-edge detector
P47/SRDY1
F/F
Shift clock
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P4
5/T
XD1
Transmit shift register 1
Transmit buffer register 1
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 32 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
1
1
D
0
0
D
1
1
D
2
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
D
D
D
D
D
D
D
D
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1
control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 33 Operation of clock synchronous serial I/O1
40
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
two buffers have the same address in a memory. Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Address 001816
Serial I/O1 control register Address 001A16
Receive buffer register 1
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Character length selection bit
P44/RXD1
ST detector
7 bits
8 bits
Receive shift register 1
1/16
UART control register
PE FE SP detector
Address 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P46/SCLK1
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN
)
Baud rate generator
Address 001C16
(f(XCIN) in low-speed mode)
1/4
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit shift register 1
P45/TXD1
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register 1
Address 001816
Address 001916
Serial I/O1 status register
Data bus
Fig. 34 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
TBE=0
TSC=1]
SP
TBE=1
Serial output TXD1
ST
D0
D1
ST
D0
D1
SP
]
1 start bit
7 or 8 data bit
Generated at 2nd bit in 2-stop-bit mode
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input RXD1
D0
D1
ST
D0
D1
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0.
Fig. 35 Operation of UART serial I/O1
41
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Serial I/O1 Control Register (SIO1CON)]
001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART1 Control Register (UART1CON)]
001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer, and one bit (bit 4) which is al-
ways valid and sets the output structure of the P45/TXD1 pin.
[Serial I/O1 Status Register (SIO1STS)]
001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
[Transmit Buffer Register 1/Receive Buffer
Register 1 (TB1/RB1)] 001816
The transmit buffer register 1 and the receive buffer register 1 are
located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Baud Rate Generator 1 (BRG1)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
42
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b0
b7
Serial I/O1 status register
(SIO1STS : address 001916
Serial I/O1 control register
(SIO1CON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
S
0: P4
1: P4
RDY1 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as normal I/O pin
pin operates as SRDY1 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P4
1: Serial I/O1 enabled
(pins P4 to P4 operate as serial I/O pins)
4 to P47 operate as normal I/O pins)
4
7
b7
b0
UART1 control register
(UARTCON : address 001B16
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD1 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 36 Structure of serial I/O1 control registers
43
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀ Notes concerning serial I/O1
1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
ꢀ Note
ꢀ Note
Clear the transmit enable bit to “0” (transmit disabled). The trans-
mission operation does not stop by clearing the serial I/O1 enable
bit to “0”.
Clear the serial I/O1 enable bit and the transmit enable bit to “0”
(serial I/O and transmit disabled).
ꢀ Reason
ꢀ Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD1 pin and an operation failure occurs.
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD1 pin and an operation failure occurs.
1.2 Stop of receive operation
2.2 Stop of receive operation
ꢀ Note
ꢀ Note
Clear the receive enable bit to “0” (receive disabled), or clear the
serial I/O1 enable bit to “0” (serial I/O disabled).
Clear the receive enable bit to “0” (receive disabled).
2.3 Stop of transmit/receive operation
1.3 Stop of transmit/receive operation
ꢀ Note
ꢀ Note 1 (only transmission operation is stopped)
Clear the transmit enable bit to “0” (transmit disabled). The trans-
mission operation does not stop by clearing the serial I/O1 enable
bit to “0”.
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when data is transmitted and received in the clock synchronous
serial I/O mode, any one of data transmission and reception can-
not be stopped.)
ꢀ Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD1 pin and an operation failure occurs.
ꢀ Reason
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception. If any one of transmission and re-
ception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also oper-
ates for data reception. Accordingly, the transmission circuit does
not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clear-
ing the serial I/O1 enable bit to “0” (serial I/O disabled) (refer to
1.1).
ꢀ Note 2 (only receive operation is stopped)
Clear the receive enable bit to “0” (receive disabled).
44
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3. SRDY1 output of reception side
7. Transmit interrupt request when transmit enable bit is set
ꢀ Note
ꢀ Note
When signals are output from the SRDY1 pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the SRDY1 output enable
bit, and the transmit enable bit to “1” (transmit enabled).
When using the transmit interrupt, take the following sequence.
ꢀ Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
ꢀ Set the transmit enable bit to “1”.
ꢀ Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instruction has executed.
4. Setting serial I/O1 control register again
ꢀ Note
ꢀ Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
ꢀ Reason
Set the serial I/O1 control register again after the transmission and
the reception circuits are reset by clearing both the transmit en-
able bit and the receive enable bit to “0.”
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and the transmit shift register shift completion flag are
also set to “1”. Therefore, regardless of selecting which timing for
the generating of transmit interrupts, the interrupt request is gener-
ated and the transmit interrupt request bit is set at this point.
Clear both the transmit enable bit
(TE) and the receive enable bit
(RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
Can be set with the
↓
LDM instruction at the
same time
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
5. Data transmission control with referring to transmit shift
register completion flag
ꢀ Note
After the transmit data is written to the transmit buffer register, the
transmit shift register completion flag changes from “1” to “0” with
a delay of 0.5 to 1.5 shift clocks. When data transmission is con-
trolled with referring to the flag after writing the data to the transmit
buffer register, note the delay.
6. Transmission control when external clock is selected
ꢀ Note
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the SCLK1
input level. Also, write data to the transmit buffer register at “H” of
the SCLK1 input level.
45
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
Serial I/O2
b0
Serial I/O2 control register
(SIO2CON : address 001D16)
The serial I/O2 function can be used only for clock synchronous
serial I/O.
Internal synchronous clock selection bits
b2 b1 b0
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode)
1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
[Serial I/O2 Control Register (SIO2CON)]
001D16
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 signal output
The serial I/O2 control register contains eight bits which control
various serial I/O2 functions.
SRDY2 output enable bit
0: I/O port
1: SRDY2 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P51/SOUT2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Fig. 37 Structure of serial I/O2 control register
Internal synchronous
clock selection bits
1/8
1/16
Data bus
1/32
f(XIN
)
1/64
(f(XCIN) in low-speed mode)
1/128
1/256
P53 latch
Serial I/O2 synchronous
clock selection bit
“0”
“1”
P53/SRDY2
S
RDY2
Synchronization
circuit
“1”
SRDY2 output enable bit
“0”
External clock
P52 latch
“0”
P52/SCLK2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
“1”
Serial I/O2 port selection bit
P51 latch
“0”
P51/SOUT2
“1”
Serial I/O2 port selection bit
Serial I/O2 register (8)
P50/SIN2
Address 001F16
Fig. 38 Block diagram of serial I/O2
46
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 output
SOUT2
D2
D0
D1
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as the transfer clock, the divide ratio of f(XIN), or f(XCIN) in low-speed mode, can be
selected by setting bits 0 to 2 of the serial I/O2 control register.
2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion.
Fig. 39 Timing of serial I/O2
47
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O3
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O3 mode can be selected by setting
the serial I/O3 mode selection bit of the serial I/O3 control register
(bit 6 of address 003216) to “1”.
Serial I/O3 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Data bus
Serial I/O3 control register
Receive buffer full flag (RBF)
Address 003216
Address 003016
Receive buffer register 3
Receive shift register 3
Receive interrupt request (RI)
P34/RXD3
Shift clock
Clock control circuit
P36/SCLK3
Serial I/O3 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
(f(XCIN) in low-speed mode)
f(XIN
)
Baud rate generator 3
Address 002F16
1/4
1/4
Clock control circuit
Falling-edge detector
P37/SRDY3
F/F
Shift clock
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P3
5/T
XD3
Transmit shift register 3
Transmit buffer register 3
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O3 status register
Address 003116
Address 003016
Data bus
Fig. 40 Block diagram of clock synchronous serial I/O3
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
3
3
D
0
0
D
1
D
2
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
D
D1
D
D
D
D
D
D
Receive enable signal SRDY3
Write pulse to receive/transmit
buffer register (address 003016
)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3
control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 41 Operation of clock synchronous serial I/O3
48
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O3 mode selection bit of the serial I/O3 control
register to “0”.
two buffers have the same address in a memory. Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Serial I/O3 control register Address 003216
Address 003016
Receive buffer register 3
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Character length selection bit
P34/RXD3
ST detector
7 bits
8 bits
Receive shift register 3
1/16
UART3 control register
PE FE SP detector
Address 003316
Clock control circuit
Serial I/O3 synchronous clock selection bit
P36/SCLK3
f(XIN)
Frequency division ratio 1/(n+1)
BRG count source selection bit
Baud rate generator 3
Address 002F16
(f(XCIN) in low-speed mode)
1/4
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit shift register 3
P35/TXD3
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register 3
Address 003016
Address 003116
Serial I/O3 status register
Data bus
Fig. 42 Block diagram of UART serial I/O3
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
TBE=0
TSC=1]
SP
TBE=1
Serial output TXD3
ST
D0
D1
ST
D0
D1
SP
]
1 start bit
7 or 8 data bit
Generated at 2nd bit in 2-stop-bit mode
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input RXD3
D0
D1
ST
D0
D1
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O3 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0.
Fig. 43 Operation of UART serial I/O3
49
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Serial I/O3 Control Register (SIO3CON)]
003216
The serial I/O3 control register consists of eight control bits for the
serial I/O3 function.
[UART3 Control Register (UART3CON)]
003316
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer, and one bit (bit 4) which is al-
ways valid and sets the output structure of the P35/TXD3 pin.
[Serial I/O3 Status Register (SIO3STS)] 003116
The read-only serial I/O3 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O3
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O3
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O3 enable bit SIOE
(bit 7 of the serial I/O3 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O3 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O3 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
[Transmit Buffer Register 3/Receive Buffer
Register 3 (TB3/RB3)] 003016
The transmit buffer register 3 and the receive buffer register 3 are
located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Baud Rate Generator 3 (BRG3)] 002F16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
50
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b0
b7
Serial I/O3 status register
(SIO3STS : address 003116
Serial I/O3 control register
(SIO3CON : address 003216
)
)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O3 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
S
0: P3
1: P3
RDY3 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as normal I/O pin
pin operates as SRDY3 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O3 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O3 enable bit (SIOE)
0: Serial I/O disabled
(pins P3
1: Serial I/O enabled
(pins P3 to P3 operate as serial I/O pins)
4 to P37 operate as normal I/O pins)
4
7
b7
b0
UART3 control register
(UART3CON : address 003316
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P35/TXD3 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 44 Structure of serial I/O3 control registers
51
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀ Notes concerning serial I/O3
1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
ꢀ Note
ꢀ Note
Clear the transmit enable bit to “0” (transmit disabled). The trans-
mission operation does not stop by clearing the serial I/O3 enable
bit to “0”.
Clear the serial I/O3 enable bit and the transmit enable bit to “0”
(serial I/O and transmit disabled).
ꢀ Reason
ꢀ Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O3 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD3 pin and an operation failure occurs.
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O3 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O3 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD3 pin and an operation failure occurs.
1.2 Stop of receive operation
2.2 Stop of receive operation
ꢀ Note
ꢀ Note
Clear the receive enable bit to “0” (receive disabled), or clear the
serial I/O3 enable bit to “0” (serial I/O disabled).
Clear the receive enable bit to “0” (receive disabled).
2.3 Stop of transmit/receive operation
1.3 Stop of transmit/receive operation
ꢀ Note
ꢀ Note 1 (only transmission operation is stopped)
Clear the transmit enable bit to “0” (transmit disabled). The trans-
mission operation does not stop by clearing the serial I/O3 enable
bit to “0”.
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when data is transmitted and received in the clock synchronous
serial I/O mode, any one of data transmission and reception can-
not be stopped.)
ꢀ Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O3 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O3 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD3 pin and an operation failure occurs.
ꢀ Reason
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception. If any one of transmission and re-
ception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also oper-
ates for data reception. Accordingly, the transmission circuit does
not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clear-
ing the serial I/O3 enable bit to “0” (serial I/O disabled) (refer to
1.1).
ꢀ Note 2 (only receive operation is stopped)
Clear the receive enable bit to “0” (receive disabled).
52
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3. SRDY3 output of reception side
7. Transmit interrupt request when transmit enable bit is set
ꢀ Note
ꢀ Note
When signals are output from the SRDY3 pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the SRDY3 output enable
bit, and the transmit enable bit to “1” (transmit enabled).
When using the transmit interrupt, take the following sequence.
ꢀ Set the serial I/O3 transmit interrupt enable bit to “0” (disabled).
ꢀ Set the transmit enable bit to “1”.
ꢀ Set the serial I/O3 transmit interrupt request bit to “0” after 1 or
more instruction has executed.
4. Setting serial I/O3 control register again
ꢀ Note
ꢀ Set the serial I/O3 transmit interrupt enable bit to “1” (enabled).
ꢀ Reason
Set the serial I/O3 control register again after the transmission and
the reception circuits are reset by clearing both the transmit en-
able bit and the receive enable bit to “0.”
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and the transmit shift register shift completion flag are
also set to “1”. Therefore, regardless of selecting which timing for
the generating of transmit interrupts, the interrupt request is gener-
ated and the transmit interrupt request bit is set at this point.
Clear both the transmit enable bit
(TE) and the receive enable bit
(RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O3 control register
Can be set with the
↓
LDM instruction at the
same time
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
5. Data transmission control with referring to transmit shift
register completion flag
ꢀ Note
After the transmit data is written to the transmit buffer register, the
transmit shift register completion flag changes from “1” to “0” with
a delay of 0.5 to 1.5 shift clocks. When data transmission is con-
trolled with referring to the flag after writing the data to the transmit
buffer register, note the delay.
6. Transmission control when external clock is selected
ꢀ Note
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the SCLK3
input level. Also, write data to the transmit buffer register at “H” of
the SCLK input level.
53
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PULSE WIDTH MODULATION (PWM)
The 3803 group (Spec. H) has PWM functions with an 8-bit reso-
lution, based on a signal that is the clock input XIN or that clock
input divided by 2 or the clock input XCIN or that clock input di-
vided by 2 in low-speed mode.
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
Data Setting
The PWM output pin also functions as port P56. Set the PWM pe-
riod by the PWM prescaler, and set the “H” term of output pulse by
the PWM register.
31.875 ꢀ m ꢀ(n+1)
µs
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ꢀ (n+1) / f(XIN)
255
PWM output
= 31.875 ꢀ (n+1) µs (when f(XIN) = 8 MHz)
Output pulse “H” term = PWM period ꢀ m / 255
= 0.125 ꢀ (n+1) ꢀ m µs
T = [31.875 ꢀ (n+1)] µs
(when f(XIN) = 8 MHz)
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM period (when f(XIN) = 8 MHz, count source
is f(XIN))
Fig. 45 Timing of PWM period
Data bus
PWM
prescaler pre-latch
PWM
register pre-latch
Transfer control circuit
PWM
prescaler latch
PWM
register latch
Count source
selection bit
Port P5
6
“0”
X
IN
or
CIN
PWM register
PWM prescaler
X
“1”
1/2
Port P56 latch
PWM enable bit
Fig. 46 Block diagram of PWM function
54
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
PWM control register
(PWMCON : address 002B16)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(XIN)
1: f(XIN)/2
Not used (return “0” when read)
Fig. 47 Structure of PWM control register
B
T
C
T2
=
A
B
C
PWM output
T
T
T2
PWM register
write signal
(Changes “H” term from “A” to “B”.)
PWM prescaler
write signal
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 48 PWM output timing when PWM register or PWM prescaler is changed
55
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
[A-D Conversion Register 1, 2 (AD1, AD2)]
003516, 003816
Channel Selector
The channel selector selects one of ports P67/AN7 to P60/AN0 or
P07/AN15 to P00/AN8, and inputs the voltage to the comparator.
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
Bit 7 of the A-D conversion register 2 is the conversion mode se-
lection bit. When this bit is set to “0,” the A-D converter becomes
the 10-bit A-D mode. When this bit is set to “1,” that becomes the
8-bit A-D mode. The conversion result of the 8-bit A-D mode is
stored in the A-D conversion register 1. As for 10-bit A-D mode,
not only 10-bit reading but also only high-order 8-bit reading of
conversion result can be performed by selecting the reading pro-
cedure of the A-D conversion registers 1, 2 after A-D conversion is
completed (in Figure 50).
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, and then stores the result in the
A-D conversion registers 1, 2. When an A-D conversion is com-
pleted, the control circuit sets the AD conversion completion bit
and the AD interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(XIN) to 500 kHz or more during an A-D conversion.
b7
b0
AD/DA control register
(ADCON : address 003416
As for 10-bit A-D mode, the 8-bit reading inclined to MSB is per-
formed when reading the A-D converter register 1 after A-D
conversion is started; and when the A-D converter register 1 is
read after reading the A-D converter register 2, the 8-bit reading
inclined to LSB is performed.
)
Analog input pin selection bits 1
b2 b1 b0
0 0 0: P6
0 0 1: P6
0 1 0: P6
0 1 1: P6
1 0 0: P6
1 0 1: P6
1 1 0: P6
1 1 1: P6
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
or P0
or P0
or P0
or P0
or P0
or P0
or P0
or P0
0
1
2
3
4
5
6
7
/AN
/AN
8
9
/AN10
/AN11
/AN12
/AN13
/AN14
/AN15
[AD/DA Control Register (ADCON)] 003416
The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Analog input pin selection bit 2
0: AN
1: AN
0
to AN
to AN15 side
7 side
8
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
VREF and AVSS into 1024, and that outputs the comparison voltage
in the 10-bit A-D mode (256 division in 8-bit A-D mode).
The A-D converter successively compares the comparison voltage
Vref in each mode, dividing the VREF voltage (see below), with the
input voltage.
Not used (returns “0” when read)
DA
1
output enable bit
0: DA
1
output disabled
output enabled
1: DA
1
DA
2
output enable bit
0: DA
2
output disabled
output enabled
1: DA
2
• 10-bit A-D mode (10-bit reading)
VREF
Vref =ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀn (n = 0–1023)
Fig. 49 Structure of AD/DA control register
1024
• 10-bit A-D mode (8-bit reading)
VREF
Vref =ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀn (n = 0–255)
10-bit reading
256
(Read address 003816 before 003516
)
• 8-bit A-D mode
b0
b9 b8
b0
b7
VREF
Vref =ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ(n–0.5) (n = 1–255)
A-D conversion register 2
256
0
(AD2: address 003816
)
=0
(n = 0)
b7
A-D conversion register 1
(AD1: address 003516
b7 b6 b5 b4 b3 b2 b1 b0
)
Note : Bits 2 to 6 of address 003816 become “0”
at reading.
8-bit reading
(Read only address 003516
A-D conversion register 1
)
b7
b9 b8 b7 b6 b5 b4 b3 b2
b0
(AD1: address 003516
)
Fig. 50 Structure of 10-bit A-D mode reading
56
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
b7
4
b0
AD/DA control register
(Address 003416
)
AD converter interrupt request
A-D control circuit
P6
P6
0
/AN
0
1
/AN
1
P6
P6
2
3
/AN
/AN
2
3
(Address 003816
(Address 003516
)
)
A-D conversion register 2
Comparator
A-D conversion register 1
10
P6
P6
P6
4
/AN
/AN
/AN
4
5
5
6
6
Resistor ladder
P6
P0
P0
7
0
1
/AN
/AN
/AN
7
8
9
P0
P0
P0
2
/AN10
/AN11
/AN12
3
V
REF AVSS
4
P0
P0
P0
5/AN13
6/AN14
7/AN15
Fig. 51 Block diagram of A-D converter
57
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER
The 3803 group (Spec. H) has two internal D-A converters (DA1
and DA2) with 8-bit resolution.
The D-A conversion is performed by setting the value in each D-A
conversion register. The result of D-A conversion is output from
the DA1 or DA2 pin by setting the DA output enable bit to “1”.
When using the D-A converter, the corresponding port direction
register bit (P30/DA1 or P31/DA2) must be set to “0” (input status).
The output analog voltage V is determined by the value n (decimal
notation) in the D-A conversion register as follows:
D-A1 conversion register (8)
DA
1
output enable bit
P3 /DA
R-2R resistor ladder
0
1
V = VREF ꢀ n/256 (n = 0 to 255)
Where VREF is the reference voltage.
D-A2 conversion register (8)
DA
At reset, the D-A conversion registers are cleared to “0016”, and
the DA output enable bits are cleared to “0”, and the P30/DA1 and
P31/DA2 pins become high impedance.
2
output enable bit
P3 /DA
R-2R resistor ladder
1
2
The DA output does not have buffers. Accordingly, connect an ex-
ternal buffer when driving a low-impedance load.
Fig. 52 Block diagram of D-A converter
DA1
output enable bit
R
“0”
R
2R
R
R
R
R
R
P30/DA1
“1”
2R
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
D-A1 conversion register
“0”
“1”
AVSS
VREF
Fig. 53 Equivalent connection circuit of D-A converter (DA1)
58
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
When bit 6 of the watchdog timer control register is kept at “0”, the
STP instruction is enabled. When that is executed, both the clock
and the watchdog timer stop. Count re-starts at the same time as
the release of stop mode (Note). The watchdog timer does not
stop while a WIT instruction is executed. In addition, the STP in-
struction is disabled by writing “1” to this bit again. When the STP
instruction is executed at this time, it is processed as an undefined
instruction, and an internal reset occurs. Once a “1” is written to
this bit, it cannot be programmed to “0” again.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Watchdog Timer Initial Value
Watchdog timer L is set to “FF16” and watchdog timer H is set to
“FF16” by writing to the watchdog timer control register (address
001E16) or at a reset. Any write instruction that causes a write sig-
nal can be used, such as the STA, LDM, CLB, etc. Data can only
be written to bits 6 and 7 of the watchdog timer control register.
Regardless of the value written to bits 0 to 5, the above-mentioned
value will be set to each timer.
The following shows the period between the write execution to the
watchdog timer control register and the underflow of watchdog
timer H.
Bit 7 of the watchdog timer control register is “0”:
when XCIN = 32.768 kHz; 32 s
Watchdog Timer Operations
when XIN = 16 MHz; 65.536 ms
The watchdog timer stops at reset and a countdown is started by
the writing to the watchdog timer control register. An internal reset
occurs when watchdog timer H underflows. The reset is released
after its release time. After the release, the program is restarted
from the reset vector address. Usually, write to the watchdog timer
control register by software before an underflow of the watchdog
timer H. The watchdog timer does not function if the watchdog
timer control register is not written to at least once.
Bit 7 of the watchdog timer control register is “1”:
when XCIN = 32.768 kHz; 125 ms
when XIN = 16 MHz; 256 µs
Note: The watchdog timer continues to count even while waiting for a stop
release. Therefore, make sure that watchdog timer H does not un-
derflow during this period.
“FF16” is set when
Data bus
watchdog timer
control register is
written to.
“FF16” is set when
watchdog timer
control register is
written to.
XCIN
“0”
“1”
“10”
Watchdog timer L (8)
Main clock division
ratio selection bits
(Note)
Watchdog timer H (8)
1/16
“00”
“01”
Watchdog timer H count
source selection bit
XIN
STP instruction disable bit
STP instruction
Reset
circuit
Internal reset
RESET
Reset release time waiting
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 54 Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 001E16
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 55 Structure of Watchdog timer control register
59
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
Poweron
To reset the microcomputer, RESET pin should be held at an "L"
level for 16 cycles or more of XIN. Then the RESET pin is returned
to an "H" level (the power source voltage should be between 1.8 V
and 5.5 V, and the oscillation should be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage is
less than 0.36 V for VCC of 1.8 V.
(Note)
Power source
voltage
0V
RESET
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 56 Reset circuit example
XIN
φ
RESET
Internal
reset
Address
AD
H L
,
?
?
?
?
FFFC
FFFD
Reset address from the vector table.
Data
ADH
?
?
?
ADL
?
SYNC
XIN: 10.5 to 18.5 clock cycles
Notes
1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 57 Reset sequence
60
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address
Register contents
Address Register contents
0016
(1)
Port P0 (P0)
FF16
FF16
0016
0016
(34)Timer Z (low-order) (TZL)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
(PS)
0016
(2)
Port P0 direction register (P0D)
Port P1 (P1)
(35)Timer Z (high-order) (TZH)
0016
(3)
(36)Timer Z mode register (TZM)
(37)PWM control register (PWMCON)
(38)PWM prescaler (PREPWM)
(39)PWM register (PWM)
0016
(4)
Port P1 direction register (P1D)
Port P2 (P2)
0016
(5)
X X X X X X X X
X X X X X X X X
X X X X X X X X
0016
(6)
Port P2 direction register (P2D)
Port P3 (P3)
0016
(7)
(40)Baud rate generator 3 (BRG3)
(41)Transmit/Receive buffer register 3 (TB3/RB3)
(42)Serial I/O3 status register (SIO3STS)
(43)Serial I/O3 control register (SIO3CON)
(44)UART3 control register (SIO3CON)
(45)AD/DA control register (ADCON)
(46)A-D conversion register 1 (AD1)
(47)D-A1 conversion register (DA1)
(48)D-A2 conversion register (DA2)
(49)A-D conversion register 2 (AD2)
(50)Interrupt source selection register (INTSEL)
(51)Interrupt edge selection register (INTEDGE)
(52)CPU mode register (CPUM)
(53)Interrupt request register 1 (IREQ1)
(54)Interrupt request register 2 (IREQ2)
(55)Interrupt control register 1 (ICON1)
(56)Interrupt control register 2 (ICON2)
(57)Port P0 pull-up control register (PULL0)
(58)Port P1 pull-up control register (PULL1)
(59)Port P2 pull-up control register (PULL2)
(60)Port P3 pull-up control register (PULL3)
(61)Port P4 pull-up control register (PULL4)
(62)Port P5 pull-up control register (PULL5)
(63)Port P6 pull-up control register (PULL6)
(64)Processor status register
(8)
0016
Port P3 direction register (P3D)
Port P4 (P4)
X X X X X X X X
1 0 0 0 0 0 0 0
0016
(9)
0016
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
0016
Port P4 direction register (P4D)
Port P5 (P5)
0016
1 1 1 0 0 0 0 0
0016
0016
Port P5 direction register (P5D)
Port P6 (P6)
0 0 0 0 1 0 0 0
X X X X X X X X
0016
Port P6 direction register (P6D)
Timer 12, X count source selection register (T12XCSS)
Timer Y, Z count source selection register (TYZCSS)
MISRG
0016
0 0 1 1 0 0 1 1
0 0 1 1 0 0 1 1
0016
0016
0 0 0 0 0 0 X X
0016
Transmit/Receive buffer register 1 (TB1/RB1)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
Baud rate generator 1 (BRG1)
Serial I/O2 control register (SIO2CON)
Watchdog timer control register (WDTCON)
Serial I/O2 register (SIO2)
Prescaler 12 (PRE12)
0016
X X X X X X X X
1 0 0 0 0 0 0 0
0016
0 1 0 0 1 0 0 0
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
1 1 1 0 0 0 0 0
X X X X X X X X
0016
0 0 1 1 1 1 1 1
X X X X X X X X
FF16
0116
FF16
0016
FF16
FF16
FF16
FF16
Timer 1 (T1)
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
X X X X X 1 X X
Prescaler Y (PREY)
(65)Program counter
(PCH)
FFFD16 contents
FFFC16 contents
Timer Y (TY)
(PCL)
Note : X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
Fig. 58 Internal status at reset
61
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Oscillation Control
The 3803 group (Spec. H) has two built-in oscillation circuits: main
clock XIN-XOUT oscillation circuit and sub clock XCIN-XCOUT oscil-
lation circuit. An oscillation circuit can be formed by connecting a
resonator between XIN and XOUT (XCIN and XCOUT). Use the cir-
cuit constants in accordance with the resonator manufacturer’s
recommended values. No external resistor is needed between XIN
and XOUT since a feed-back resistor exists on-chip. However, an
external feed-back resistor is needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. When the oscillation
stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1.
After STP instruction is released, the input of the prescaler 12 is
connected to count source which had set at executing the STP in-
struction, and the output of the prescaler 12 is connected to timer
1. Set the timer 1 interrupt enable bit to disabled (“0”) before ex-
ecuting the STP instruction. Oscillator restarts when an external
interrupt is received, but the internal clock φ is not supplied to the
CPU (remains at “H”) until timer 1 underflows. The internal clock φ
is supplied for the first time, when timer 1 underflows. Therefore
make sure not to set the timer 1 interrupt request bit to “1” before
the STP instruction stops the oscillator. When the oscillator is re-
started by reset, apply “L” level to the RESET pin until the
oscillation is stable since a wait time will not be generated.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re-
set is released, this mode is selected.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
(2) Wait mode
(4) Low power dissipation mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts when an interrupt is received. Since the oscillator does not
stop, normal operation can be started immediately after the clock
is restarted.
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1.” When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
■Note
•If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub clock to stabilize, especially immediately
after power on and at returning from stop mode. When switching
the mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(XIN) > 3f(XCIN).
•When using the quartz-crystal oscillator of high frequency, such
as 16 MHz etc., it may be necessary to select a specific oscillator
with the specification demanded.
62
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
CIN
X
COUT
X
IN
XOUT
Rf
Rd
COUT
CCOUT
CIN
C
CIN
Fig. 59 Ceramic resonator circuit
X
CIN
X
COUT
XIN
XOUT
Open
Open
External oscillation
circuit
External oscillation
circuit
V
CC
SS
V
CC
SS
V
V
Fig. 60 External clock input circuit
63
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
COUT
XCIN
“0”
“1”
Port X
C
switch bit
Main clock division ratio
selection bits (Note 1)
Low-speed
X
OUT
X
IN
Divider
mode
Prescaler 12
(Note 3)
Timer 1
0116
1/2
1/4
High-speed or
middle-speed
mode
Reset or
STP instruction
(Note 2)
FF16
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Q
S
R
S
R
Q
Q
S
R
STP instruction
STP instruction
WIT instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset. The count source before executing the STP
instruction is supplied as the count source at executing STP instruction.
3: When bit 0 of MISRG is “0”, timer 1 is set “0116” and prescaler 12 is set “FF16” automatically. When bit 0 of MISRG is
“1”, set the appropriate value to them in accordance with oscillation stablizing time required by the using oscillator
because nothing is automatically set into timer 1 and prescaler 12.
Fig. 61 System clock generating circuit block diagram
64
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
High-speed mode
Middle-speed mode
(f(φ)=4 MHz)
(f(φ)=1 MHz)
CM
6
“1”←→“0”
CM
CM
CM
CM
7
6
5
4
=0
=1
CM
CM
CM
CM
7
=0
6
5
4
=0
=0(8 MHz oscillating)
=0(32 kHz stopped)
=0(8 MHz oscillating)
=0(32 kHz stopped)
C
M
“
”
4
0
0
”
“
←
C
4
→
M
→
M
“
”
6
C
1
←
“
”
0
”
1
”
“
←
1
6
M
“
→
→
C
←
“
”
0
1
”
“
Middle-speed mode
(f(φ)=1 MHz)
High-speed mode
(f(φ)=4 MHz)
CM
6
“1”←→“0”
CM
CM
CM
CM
7
=0
CM
CM
CM
CM
7
=0
6=1
6
5
4
=0
5
=0(8 MHz oscillating)
=1(32 kHz oscillating)
=0(8 MHz oscillating)
=1(32 kHz oscillating)
4
C
M
“
7
0
”
←
C
M
→
“
6
1
“
1
”
←
”
→
“
0
”
Low-speed mode
(f(φ)=16 kHz)
CM
CM
CM
CM
7
=1
6
5
4
=0
b7
b4
=0(8 MHz oscillating)
=1(32 kHz oscillating)
CPU mode register
(CPUM : address 003B16
)
CM
CM
CM
4
5
7
: Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
: Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
, CM
6: Main clock division ratio selection bit
Low-speed mode
(f(φ)=16 kHz)
b7 b6
0
0
1
1
0 : φ = f(XIN)/2 ( High-speed mode)
1 : φ = f(XIN)/8 (Middle-speed mode)
0 : φ = f(XCIN)/2 (Low-speed mode)
1 : Not available
CM
CM
CM
CM
7
=1
=0
6
5
4
=1(8 MHz stopped)
=1(32 kHz oscillating)
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 62 State transitions of system clock
65
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON USAGE
Handling of Power Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin), and between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the pins
to be connected, a ceramic capacitor of 0.01 µF–0.1 µF is recom-
mended.
66
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Absolute maximum ratings
Table 9 Absolute maximum ratings
Symbol
Parameter
Power source voltageS
Conditions
Ratings
Unit
V
VCC
–0.3 to 6.5
VI
Input voltage P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
–0.3 to VCC +0.3
V
P50–P57, P60–P67, VREF
VI
Input voltage P32, P33
Input voltage RESET, XIN
Input voltage CNVSS
–0.3 to 5.8
V
V
V
All voltages are based on VSS.
Output transistors are cut off.
VI
–0.3 to VCC +0.3
–0.3 to VCC +0.3
VI
VO
Output voltage P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
–0.3 to VCC +0.3
V
P50–P57, P60–P67, XOUT
VO
Output voltage P32, P33
Power dissipation
–0.3 to 5.8
1000 (Note)
–20 to 85
V
mW
°C
Pd
Ta = 25 °C
Topr
Tstg
Operating temperature
Storage temperature
–65 to 125
°C
Note: In flat package, this value is 300 mW.
67
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Recommended operating conditions
Table 10 Recommended operating conditions
(VCC = 1.8 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Power source voltage
Conditions
When start oscillating (Note 2)
Unit
Min.
2.2
2.0
2.2
2.7
4.0
4.5
1.8
2.2
2.7
4.5
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
V
V
V
V
V
V
V
VCC
High-speed mode
f(XIN) ≤ 2.1 MHz
f(XIN) ≤ 4.2 MHz
f(XIN) ≤ 8.4 MHz
f(XIN) ≤ 12.5 MHz
f(XIN) ≤ 16.8 MHz
f(XIN) ≤ 6.3 MHz
f(XIN) ≤ 8.4 MHz
f(XIN) ≤ 12.5 MHz
f(XIN) ≤ 16.8 MHz
(Note 1)
f(φ) = f(XIN)/2
Middle-speed mode
f(φ) = f(XIN)/8
VSS
VIH
Power source voltage
“H” input voltage
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
0.85VCC
0.8VCC
VCC
VCC
P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
P50–P57, P60–P67
“H” input voltage
V
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC < 2.7 V
VIH
VIH
VIL
0.85VCC
0.8VCC
0.85VCC
0.8VCC
0
5.5
5.5
V
V
V
V
V
P32, P33
“H” input voltage
VCC
____________
RESET, XIN, XCIN, CNVSS
“L” input voltage
VCC
0.16VCC
P00–P07, P10–P17, P20–P27,
P30–P37,P40–P47,
2.7 ≤ VCC ≤ 5.5 V
0
0.2VCC
V
P50–P57, P60–P67
“L” input voltage
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC ≤ 5.5 V
0
0
0.16VCC
0.2VCC
0.16VCC
VIL
VIL
V
V
V
____________
RESET, CNVSS
“L” input voltage
XIN, XCIN
Notes 1: When using A-D converter, see A-D converter recommended operating conditions.
2: The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating
temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation.
68
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 11 Recommended operating conditions
(VCC = 1.8 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Conditions
Main clock input oscillation High-speed mode
Symbol
f(XIN)
Parameter
Unit
Min.
Typ.
Max.
(20ꢀVCC-36)ꢀ1.05
MHz
MHz
MHz
MHz
2.0 ≤ VCC < 2.2 V
2.2 ≤ VCC < 2.7 V
2.2 ≤ VCC < 4.0 V
4.0 ≤ VCC < 4.5 V
2
frequency (Note 1)
f(φ) = f(XIN)/2
(24ꢀVCC-40.8)ꢀ1.05
3
(9ꢀVCC-0.3)ꢀ1.05
3
(24ꢀVCC-60)ꢀ1.05
3
16.8
MHz
MHz
4.5 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC < 2.2 V
(15ꢀVCC-9)ꢀ1.05
Middle-speed mode
3
f(φ) = f(XIN)/8
(24ꢀVCC-28.8)ꢀ1.05
MHz
MHz
2.2 ≤ VCC < 2.7 V
2.7 ≤ VCC < 4.5 V
4.5 ≤ VCC ≤ 5.5 V
3
(15ꢀVCC+39)ꢀ1.1
7
16.8
50
MHz
kHz
Sub-clock input oscillation
32.768
f(XCIN)
frequency (Notes 1, 2)
Notes 1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
69
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 12 Recommended operating conditions
(VCC = 1.8 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
–P0 , P1 –P1
Min.
Typ.
Max.
–80
–80
80
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
P0
P40–P47, P50–P57, P60–P67 (Note 1)
P0 –P0 , P1 –P1 , P3 –P3 (Note 1)
P20–P27 (Note 1)
P40–P47,P50–P57, P60–P67 (Note 1)
–P0 , P1 –P1 , P2 –P2 , P3 , P3 , P3
“H” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
“L” total average output current P0 –P0 , P1 –P1 , P3 –P3 (Note 1)
“L” total average output current P20–P27 (Note 1)
“L” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
0
7
0
7
, P2
0
–P2
7
, P3
0
, P3
1
, P3
4
–P3
7
7
(Note 1)
(Note 1)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
0
7
0
7
0
7
80
80
“H” total average output current P0
0
7
0
7
0
7
0
1
4
–P3
–40
–40
40
0
7
0
7
0
7
40
40
“H” peak output current
P00–P07, P10–P17, P20–P27, P30, P31, P34–P37,
P40–P47, P50–P57, P60–P67 (Note 2)
IOH(peak)
–10
mA
“L” peak output current
P00–P07, P10–P17, P30–P37, P40–P47, P50–P57,
P60–P67 (Note 2)
IOL(peak)
IOL(peak)
IOH(avg)
10
20
–5
mA
mA
mA
“L” peak output current
P20–P27 (Note 2)
“H” average output current
P00–P07, P10–P17, P20–P27, P30, P31, P34–P37,
P40–P47, P50–P57, P60–P67 (Note 3)
“L” average output current
“L” average output current
P00–P07, P10–P17, P30–P37, P40–P47, P50–P57,
P60–P67 (Note 3)
IOL(avg)
IOL(avg)
5
mA
mA
P20–P27 (Note 3)
10
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver-
age value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
70
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Electrical characteristics
Table 13 Electrical characteristics (1)
(VCC = 1.8 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
“H” output voltage
P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
P50–P57, P60–P67 (Note 1)
Unit
Test conditions
IOH = –10 mA
VCC = 4.0–5.5 V
IOH = –1.0 mA
VCC = 1.8–5.5 V
Min.
Max.
V
V
VCC–2.0
VCC–1.0
VOH
VOL
“L” output voltage
IOL = 10 mA
VCC = 4.0–5.5 V
IOL = 1.6 mA
2.0
1.0
V
V
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67
VCC = 1.8–5.5 V
Hysteresis
CNTR0, CNTR1, CNTR2,
INT0–INT4
VT+–VT–
V
0.4
Hysteresis
RxD1, SCLK1, SIN2, SCLK2, RxD3,
SCLK3
V
V
VT+–VT–
VT+–VT–
0.5
0.5
Hysteresis RESET
“H” input current
VI = VCC
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67
(Pin floating. Pull-up
transistors “off”)
IIH
µA
5.0
5.0
IIH
IIH
“H” input current RESET, CNVSS
“H” input current XIN
VI = VCC
VI = VCC
µA
µA
4.0
“L” input current
VI = VSS
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67
(Pin floating. Pull-up
transistors “off”)
µA
IIL
–5.0
–5.0
IIL
IIL
µA
µA
“L” input current RESET,CNVSS
VI = VSS
VI = VSS
–4.0
–210
–70
“L” input current
XIN
“L” input current (at Pull-up)
P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
P50–P57, P60–P67
VI = VSS
VCC = 5.0 V
VI = VSS
µA
–80
–420
IIL
µA
–30
1.8
–140
VCC
VCC = 3.0 V
VRAM
V
RAM hold voltage
When clock stopped
Note 1: P35 is measured when the P35/TxD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”.
P45 is measured when the P45/TxD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
71
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Electrical characteristics (2)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, f(XCIN)=32.768kHZ (Stoped in middle-speed mode), Output transistors “off”,
AD converter not operated)
Limits
Unit
Symbol
ICC
Test conditions
VCC = 5V
Parameter
Max.
15.0
12.0
9.0
5.0
3.6
3.8
2.0
1.2
7.0
6.0
5.0
3.3
3.0
2.4
2.0
200
70
Typ.
8.0
6.5
5.0
2.5
2.0
1.9
1.0
0.6
4.0
3.0
2.5
1.8
1.5
1.2
1.0
55
Min.
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
f(XIN) = 16.8 MHz
f(XIN) = 12.5 MHz
f(XIN) = 8.4 MHz
f(XIN) = 4.2 MHz
f(XIN) = 16.8 MHz (in WIT state)
f(XIN) = 8.4 MHz
f(XIN) = 4.2 MHz
f(XIN) = 2.1 MHz
f(XIN) = 16.8 MHz
f(XIN) = 12.5 MHz
f(XIN) = 8.4 MHz
f(XIN) = 16.8 MHz (in WIT state)
f(XIN) = 12.5 MHz
f(XIN) = 8.4 MHz
f(XIN) = 6.3 MHz
f(XIN) = stopped
In WIT state
Power source
current
High-speed
mode
VCC = 3V
VCC = 5V
Middle-speed
mode
VCC = 3V
VCC = 5V
VCC = 3V
VCC = 2V
Low-speed
mode
µA
40
µA
15
40
f(XIN) = stopped
In WIT state
µA
8
15
µA
6
15
f(XIN) = stopped
In WIT state
µA
3
6
µA
0.1
In STP state
1.0
10
Ta = 25 °C
Ta = 85 °C
µA
(All oscillation stopped)
µA
Increment when A-D conversion
is executed
500
f(XIN) = 16.8 MHz, VCC = 5V
In Middle-, high-speed mode
72
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D converter characteristics
Table 15 A-D converter recommended operating conditions
(VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V,Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Conditions
8-bit A-D mode (Note 1)
Symbol
VCC
Parameter
Max.
Min.
Typ.
5.0
5.0
V
Power source voltage
2.0
2.2
2.0
5.0
5.0
(When A-D converter is used)
Analog reference voltage
Analog power source voltage
Analog input voltage
10-bit A-D mode (Note 2)
V
V
VREF
AVSS
VIA
VCC
0
V
0
VCC
High-speed mode
f(φ) = f(XIN)/2
MHZ
Main clock oscillation frequency
f(XIN)
2.0 ≤ VCC < 2.2 V
2.2 ≤ VCC < 2.7V
2.7 ≤ VCC < 4.0 V
4.0 ≤ VCC < 4.5 V
0.5
(20ꢀVCC-36)ꢀ1.05
2
(When A-D converter is used)
0.5
0.5
0.5
(24ꢀVCC-40.8)ꢀ1.05
3
(9ꢀVCC-0.3)ꢀ1.05
3
(24ꢀVCC-60)ꢀ1.05
3
4.5 ≤ VCC ≤ 5.5 V
2.0 ≤ VCC < 2.2 V
0.5
2.0
16.8
Middle-speed mode
(15ꢀVCC-9)ꢀ1.05
f(φ) = f(XIN)/8
3
2.2 ≤ VCC < 2.7V
2.7 ≤ VCC < 4.5 V
4.5 ≤ VCC ≤ 5.5 V
2.0
2.0
2.0
(24ꢀVCC-28.8)ꢀ1.05
3
(15ꢀVCC+39)ꢀ1.1
7
16.8
Note 1: 8-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”.
2: 10-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”.
Table 16 A-D converter characteristics
(VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Unit
Parameter
Test conditions
8-bit A-D mode (Note 1)
Typ.
Max.
8
Min.
–
Resolution
bits
10-bit A-D mode (Note 2)
8-bit A-D mode (Note 1)
10
±3
±2
±5
±4
50
61
100
200
5
–
Absolute accuracy
2.0 ≤ VCC < 2.2 V
2.2 ≤ VCC ≤ 5.5 V
2.2 ≤ VCC < 2.7 V
2.7 ≤ VCC < 5.5V
LSB
(excluding quantization error)
10-bit A-D mode (Note 2)
8-bit A-D mode (Note 1)
10-bit A-D mode (Note 2)
tCONV
Conversion time
2tc(XIN)
35
RLADDER Ladder resistor
12
50
kΩ
µA
µA
µA
VREF = 5.0 V
VREF = 5.0 V
150
IVREF
Reference power
at A-D converter operated
at A-D converter stopped
source input current
A-D port inout current
5
II(AD)
Note 1: 8-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”.
2: 10-bit A-D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”.
73
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A converter characteristics
Table 17 D-A converter characteristics
(VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
8
–
–
Resolution
Bits
%
VCC = 4.0–5.5 V
VCC = 2.7–4.0 V
1.0
2.5
3
Absolute accuracy
%
tsu
Setting time
µs
RO
Output resistor
2
3.5
5
kΩ
mA
IVREF
Reference power source input current (Note 1)
3.2
Note 1: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”.
74
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing requirements and switching characteristics
Table 18 Timing requirements (1) (In high-speed mode)
(VCC = 2.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Typ.
Max.
Min.
16
Reset input “L” pulse width
tW(RESET)
tC(XIN)
XIN cycle
Main clock XIN input cycle time
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
59.5
10000/(86VCC-219)
2.6ꢀ103/(82VCC-3)
ns
10000/(84VCC-143)
10000/(105VCC-189)
25
Main clock XIN input “H” pulse width
Main clock XIN input “L” pulse width
tWH(XIN)
tWL(XIN)
4000/(86VCC-219)
10000/(82VCC-3)
ns
ns
4000/(84VCC-143)
4000/(105VCC-189)
25
4000/(86VCC-219)
10000/(82VCC-3)
4000/(84VCC-143)
4000/(105VCC-189)
20
5
Sub-clock XCIN input cycle time
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0–CNTR2 input cycle time
tC(XCIN)
µs
µs
µs
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
5
120
160
250
500
1000
48
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
ns
ns
ns
ns
ns
CNTR0–CNTR2 input “H” pulse width
CNTR0–CNTR2 input “L” pulse width
tWH(CNTR)
tWL(CNTR)
tWH(INT)
64
115
230
460
48
64
115
230
460
48
INT00, INT01, INT1, INT2, INT3, INT40, INT41
64
input “H” pulse width
115
230
460
48
INT00, INT01, INT1, INT2, INT3, INT40, INT41
tWL(INT)
64
input “L” pulse width
115
230
460
75
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 19 Timing requirements (2) (In high-speed mode)
(VCC = 2.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Typ.
Min.
250
320
500
1000
2000
120
150
240
480
950
120
150
240
480
950
70
Max.
Serial I/O1, serial I/O3
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
2.2≤VCC<2.7 V
2.0≤VCC<2.2V
t
t
t
C(SCLK1), tC(SCLK3)
clock input cycle time (Note)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O1, serial I/O3
WH(SCLK1), tWH(SCLK3
)
clock input “H” pulse width (Note)
Serial I/O1, serial I/O3
WL(SCLK1), tWL(SCLK3
)
clock input “L” pulse width (Note)
Serial I/O1, serial I/O3
clock input setup time
tsu(RxD1-SCLK1),
tsu(RxD3-SCLK3)
90
100
200
400
32
Serial I/O1, serial I/O3
clock input hold time
th(SCLK1-RxD1),
th(SCLK3-RxD3)
40
50
100
200
500
650
1000
2000
4000
200
260
400
950
2000
200
260
400
950
2000
100
130
200
400
800
100
130
150
300
600
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
tC(SCLK2)
tWH(SCLK2)
tCL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Note : When bit 6 of address 001A16 and bit 6 of address 003216 are “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are “0” (UART).
76
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 20 Timing requirements (3) (In middle-speed mode)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Typ.
Max.
Min.
Reset input “L” pulse width
tW(RESET)
tC(XIN)
XIN cycle
16
Main clock XIN Input cycle time
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
59.5
ns
10000/(24VCC+61)
10000/(82VCC-96)
10000/(52VCC-31)
Main clock XIN input “H” pulse width
Main clock XIN input “L” pulse width
tWH(XIN)
tWL(XIN)
25
ns
ns
4000/(24VCC+61)
4000/(82VCC-96)
4000/(52VCC-31)
25
4000/(24VCC+61)
4000/(82VCC-96)
4000/(52VCC-31)
Sub-clock XCIN input cycle time
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0–CNTR2 input cycle time
tC(XCIN)
µs
µs
µs
20
5
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
5
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
120
160
250
320
48
ns
ns
ns
ns
ns
CNTR0–CNTR2 input “H” pulse width
CNTR0–CNTR2 input “L” pulse width
tWH(CNTR)
tWL(CNTR)
tWH(INT)
64
115
150
48
64
115
150
48
INT00, INT01, INT1, INT2, INT3, INT40, INT41
input “H” pulse width
64
115
150
48
INT00, INT01, INT1, INT2, INT3, INT40, INT41
tWL(INT)
input “L” pulse width
64
115
150
77
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 21 Timing requirements (4) (In middle-speed mode)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Typ.
Min.
250
320
500
650
120
150
240
310
120
150
240
310
70
Max.
Serial I/O1, serial I/O3
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
4.5≤VCC≤5.5 V
2.7≤VCC<4.5 V
2.2≤VCC<2.7 V
1.8≤VCC<2.2V
t
t
t
C(SCLK1), tC(SCLK3)
ns
ns
ns
ns
ns
ns
clock input cycle time (Note)
Serial I/O1, serial I/O3
WH(SCLK1), tWH(SCLK3
)
clock input “H” pulse width (Note)
Serial I/O1, serial I/O3
WL(SCLK1), tWL(SCLK3
)
clock input “L” pulse width (Note)
Serial I/O1, serial I/O3
clock input setup time
tsu(RxD1-SCLK1),
tsu(RxD3-SCLK3)
90
100
130
32
Serial I/O1, serial I/O3
clock input hold time
th(SCLK1-RxD1),
th(SCLK3-RxD3)
40
50
65
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
500
650
1000
1300
200
260
400
520
200
260
400
520
100
130
200
260
100
130
150
200
tC(SCLK2)
tWH(SCLK2)
tCL(SCLK2)
ns
ns
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
ns
ns
Note : When bit 6 of address 001A16 and bit 6 of address 003216 are “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are “0” (UART).
78
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing diagram in single-chip mode
t
C(CNTR)
t
WL(CNTR)
t
WH(CNTR)
0.8VCC
CNTR
0
, CNTR
1
, CNTR
2
0.2VCC
0.2VCC
t
WL(INT)
t
WH(INT)
INT
1
, INT
2, INT
3
INT00, INT40
INT01, INT41
0.8VCC
t
W(RESET)
0.8VCC
RESET
0.2VCC
t
t
C(XIN)
t
t
WL(XIN)
t
WH(XIN)
0.8VCC
X
IN
0.2VCC
0.2VCC
C(XCIN
)
WL(XCIN
)
t
WH(XCIN)
0.8VCC
XCIN
t
C(SCLK1),
t
C(SCLK2),
t
C(SCLK3
)
t
r
tWH(SCLK1),
t
f
t
WL(SCLK1),
t
WL(SCLK2),
t
WL(SCLK3
)
tWH(SCLK2), tWH(SCLK3)
SCLK1
SCLK2
SCLK3
0.8VCC
0.2VCC
t
t
t
h(SCLK1-
h(SCLK2-
h(SCLK3-
R
x
D1),
IN2),
D3)
t
t
t
su(R
su(SIN2-
su(R D3
x
D1
-
S
CLK1),
CLK2),
CLK3
S
S
R
x
x
-
S
)
R
R
X
X
S
D1
D3
0.8V
0.2VCCCC
IN2
t
t
t
v(SCLK1-T
v(SCLK2-
v(SCLK3-T
X
D1),
OUT2),
D3)
S
t
d(SCLK1-TXD1),td(SCLK2-SOUT2),td(SCLK3-TXD3)
X
T
T
X
X
OUT2
D1
D3
S
Fig. 63 Timing diagram (in single-chip mode)
79
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
64P6N-A
Plastic 64pin 14ꢀ14mm body QFP
EIAJ Package Code
QFP64-P-1414-0.80
JEDEC Code
Weight(g)
1.11
Lead Material
Alloy 42
–
MD
HD
D
64
49
1
48
I2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.3
0.13
13.8
13.8
–
16.5
16.5
0.4
–
Nom
–
Max
3.05
0.2
–
0.45
0.2
14.2
14.2
–
17.1
17.1
0.8
–
0.1
10°
–
A
A1
A2
b
c
D
0.1
2.8
0.35
0.15
14.0
14.0
0.8
16.8
16.8
0.6
1.4
–
–
0.5
–
14.6
14.6
16
33
A
E
e
17
32
L1
HD
HE
L
L1
y
–
0°
–
1.3
–
F
e
b
b2
I2
MD
ME
L
–
–
–
y
Detail F
–
64P4B
Plastic 64pin 750mil SDIP
EIAJ Package Code
SDIP64-P-750-1.78
JEDEC Code
Weight(g)
7.9
Lead Material
Alloy 42
–
64
33
1
32
Dimension in Millimeters
Symbol
Min
–
0.38
–
Nom
–
–
Max
5.08
–
D
A
A1
A2
b
b1
b2
c
D
E
e
e1
3.8
–
0.4
0.9
0.65
0.2
56.2
16.85
–
–
2.8
0°
0.5
1.0
0.6
1.3
1.05
0.32
56.6
17.15
–
–
–
15°
0.75
0.25
56.4
17.0
1.778
19.05
–
e
b1
b
b2
SEATING PLANE
L
–
80
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MMP
EIAJ Package Code
LQFP64-P-1010-0.50
64P6Q-A
Plastic 64pin 10ꢀ10mm body LQFP
Weight(g)
Lead Material
Cu Alloy
JEDEC Code
MD
–
–
HD
D
64
49
I2
Recommended Mount Pad
1
48
Dimension in Millimeters
Symbol
Min
–
0
Nom
–
0.1
Max
1.7
0.2
–
0.28
0.175
10.1
10.1
–
A
A1
A2
b
c
D
–
1.4
0.13
0.105
9.9
9.9
–
0.18
0.125
10.0
10.0
0.5
16
33
E
e
17
32
A
HD
HE
L
L1
Lp
A3
x
11.8
11.8
0.3
–
0.45
–
–
–
0°
–
12.0
12.0
0.5
1.0
0.6
0.25
–
–
12.2
12.2
0.7
–
0.75
–
0.08
0.1
10°
–
F
e
L1
y
y
–
L
b
b2
I2
MD
ME
0.225
–
10.4
10.4
x
M
Lp
1.0
–
–
–
–
–
Detail F
MMP
64P6U-A
Plastic 64pin 14ꢀ14mm body LQFP
EIAJ Package Code
LQFP64-P-1414-0.8
JEDEC Code
Weight(g)
Lead Material
Cu Alloy
–
MD
HD
D
64
49
l2
1
48
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
Nom
–
0.1
Max
1.7
0.2
–
0.45
0.175
14.1
14.1
–
A
A1
A2
b
c
D
–
1.4
0.32
0.105
13.9
13.9
–
0.37
0.125
14.0
14.0
0.8
16
33
E
e
17
32
A
16.0
16.0
0.5
1.0
0.6
0.25
–
–
HD
HE
L
L1
Lp
A3
x
15.8
15.8
0.3
–
0.45
–
–
–
0°
–
16.2
16.2
0.7
–
0.75
–
0.2
0.1
8°
–
–
–
–
L1
F
e
L
b
y
y
M
x
–
Lp
b2
I2
MD
ME
0.225
–
14.4
14.4
0.95
–
–
Detail F
81
MITSUBISHI MICROCOMPUTERS
3803 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
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© 2003 MITSUBISHI ELECTRIC CORP.
New publication, effective Jan. 2003.
Specifications subject to change without notice.
REVISION HISTORY
3803 GROUP (Spec. H) DATA SHEET
Rev.
1.0
Date
Description
Summary
Page
01/09/03
First Edition
(1/1)
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