M37477M2-XXXSP [MITSUBISHI]
Microcontroller, 8-Bit, MROM, 8MHz, CMOS, PDIP32, 0.400 INCH, SHRINK, PLASTIC, DIP-32;
| 型号： | M37477M2-XXXSP |
| 厂家： | 
Mitsubishi Group |
| 描述： | Microcontroller, 8-Bit, MROM, 8MHz, CMOS, PDIP32, 0.400 INCH, SHRINK, PLASTIC, DIP-32 时钟 微控制器 光电二极管 外围集成电路 装置 |
| 文件： | 总47页 (文件大小：660K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7477/7478 group is the single-chip microcomputer designed
with CMOS silicon gate technology.
PIN CONFIGURATION (TOP VIEW)
The single-chip microcomputer is useful for business equipment
and other consumer applications.
1
2
3
4
5
6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P07
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
P13/T1
P12/T0
P11
P06
In addition to its simple instruction set, the ROM, RAM, and I/O
addresses are placed on the same memory map to enable easy
programming.
P05
P04
In addition, built-in PROM type microcomputers with built-in elec-
trically writable PROM, and additional functions equivalent to the
mask ROM version are also available.
P03
P02
7
8
P01
7477/7478 group products are shown noted below.
The 7477 and the 7478 differ in the number of I/O ports, package
outline, and clock generating circuit only.
P10
P00
9
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P41
10
P40
11
12
13
14
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
VCC
Version
Mask ROM version
Product
M37477M4-XXXSP/FP
M37477M8-XXXSP/FP
M37477E8SP/FP
XIN
15
16
XOUT
One Time PROM version
VSS
(Built-in PROM type microcomputers)
M37477E8-XXXSP/FP
M37478M4-XXXSP/FP
M37478M8-XXXSP/FP
M37478E8SP/FP
Outline 32P4B
Mask ROM version
One Time PROM version
(Built-in PROM type microcomputers)
PROM version
M37478E8-XXXSP/FP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
P07
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
P13/T1
P12/T0
P11
M37478E8SS
P06
(Built-in PROM type microcomputer)
P05
P04
FEATURES
P03
●Basic machine-language instructions ...................................... 71
●Memory size
ROM.............................. 8192 bytes (M37477M4, M37478M4)
RAM ................................ 192 bytes (M37477M4, M37478M4)
●The minimum instruction execution time
......................................0.5µs (at 8MHz oscillation frequency)
●Power source voltage
.......... 2.7 to 4.5V (at 2.2VCC – 2.0MHz oscillation frequency)
............................. 4.5 to 5.5V (at 8MHz oscillation frequency)
●Power dissipation in normal mode
P02
7
8
P01
P10
P00
9
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P41
10
11
12
13
14
P40
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
VCC
XIN
15
16
XOUT
.................................... 35mW (at 8MHz oscillation frequency)
●Subroutine nesting
VSS
................................. 96 levels max. (M37477M4, M37478M4)
●Interrupt ................................................... 13 sources, 11 vectors
●8-bit timers ................................................................................. 4
●Programmable I/O ports
Outline 32P2W-A
Note : The only differences between the 32P4B package prod-
uct and the 32P2W-A package product are package
shape and absolute maximum ratings.
(Ports P0, P1, P4) .......................................... 18 (7477 group)
20 (7478 group)
●Input ports (Ports P2, P3) .................................... 8 (7477 group)
(Ports P2, P3, P5) ............................ 16 (7478 group)
●8-bit serial I/O ........................... 1 (UART or clock-synchronized)
●8-bit A-D converter ................................ 4 channels (7477 group)
8 channels (7478 group)
APPLICATIONS
Audio-visual equipment, VCR, Tuner,
Office automation equipment
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
1
2
3
42
41
40
P5
7/SRDY
/SCLK
3
P5
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P4
P4
P3
P3
P3
P3
RESET
P5
P5
2
7
6
5
4
3
2
1
0
3
2
1
0
P1
P1
P1
P1
P1
P1
6
4
5
6
39
38
37
36
5
/T
/R
X
D
D
4
X
45
28
NC
RESET
NC
3
2
/T
/T
1
0
1
0
7
6
5
4
3
2
1
0
46
47
27
P0
P0
P0
P5
5
6
7
2
7
26
P5
P5
1
/XCOUT
/XCIN
35
34
33
8
9
P1
P1
/IN
/IN
/IN
/IN
/IN
/IN
/IN
/IN
48
49
25
24
23
22
21
20
19
18
17
0
NC
M37478M4-XXXFP
M37478M8-XXXFP
M37478E8-XXXFP
10
11
12
13
14
P2
7
6
5
4
3
2
1
0
V
50
51
52
NC
V
V
CC
32
31
30
P2
P2
P2
P2
P2
P2
P2
V
SS
SS
P5
3
AVSS
NC
53
54
P1
P1
P1
7/SRDY
/SCLK
29
28
27
26
3
2
/CNTR
/CNTR
1
0
X
X
OUT
6
15
16
55
56
IN
5
/T
X
D
1
0
/INT
/INT
1
NC
NC
17
18
19
20
21
0
25
24
23
22
REF
IN
OUT
SS
X
1
/XCOUT
/XCIN
X
0
V
VCC
Outline 42P4B
42S1B-A (Window)
Outline 56P6N-A
Note : The only differences between the 42P4B package product and the 56P6N-A package product are package shape, ab-
solute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.
2
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
4
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
5
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONS OF 7477/7478 GROUP
Parameter
Basic machine-language instructions
Instruction execution time
Functions
71
0.5µs (The minimum instructions, at 8 MHz oscillation frequency)
Clock input oscillation frequency
8 MHz (max.)
M37477M4
M37478M4
M37477M8/E8
M37478M8/E8
P0, P1
ROM
8192 bytes
RAM
(P)ROM
RAM
I/O
192 bytes
Memory size
16384 bytes
384 bytes
8-bit ✕ 2
P2
Input
Input
I/O
8-bit ✕ 1 (4-bit ✕ 1 for the 7477 group)
Input/Output port
P3, P5
4-bit ✕ 2 (Port P5 is not included in the 7477 group)
P4
4-bit ✕ 1 (2-bit ✕ 1 for the 7477 group)
Serial I/O
Timers
8-bit ✕ 1
8-bit timer ✕ 4
A-D converter
8-bit ✕ 1 (8 channels) (8-bit ✕ 1 (4 channels) for the 7477 group)
96 (max.)
M37477M4, M37478M4
Subroutine nesting
192 (max.)
M37477M8/E8, M37478M8/E8
Interrupt
5 external interrupts, 7 internal interrupts, 1 software interrupt
Built-in circuit with internal feedback resistor (a ceramic or a quartz-
crystal oscillator)
Clock generating circuit
2.7 to 4.5V (at 2.2VCC–2.0MHz oscillation frequency), 4.5 to 5.5V
(at 8MHz oscillation frequency)
Power source circuit
Power dissipation
35mW (at 8MHz oscillation frequency)
5V
Input/Output voltage
Output current
Input/Output characters
–5 to 10mA (P0, P1, P4 : CMOS tri-states)
–20 to 85°C
Operating temperature range
Device structure
CMOS silicon gate
32-pin shrink plastic molded DIP
32-pin plastic molded SOP
42-pin shrink plastic molded DIP
56-pin plastic molded QFP
42-pin ceramic DIP
M37477M4/M8/E8-XXXSP
M37477M4/M8/E8-XXXFP
M37478M4/M8/E8-XXXSP
M37478M4/M8/E8-XXXFP
M37478E8SS
Package
6
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Input/
Output
Pin
Name
Functions
Apply voltage of 2.7 to 5.5V to VCC, and 0V to VSS.
VCC, VSS
Power source
AVSS
(Note 1)
Analog power
source
Ground level input pin for A-D converter.
Same voltage as VSS is applied.
RESET
Reset input
Input
To enter the reset state, the reset input pin must be kept at “L” for 2µs or more
(under normal VCC conditions).
XIN
Clock input
Input
These are I/O pins of internal clock generating circuit for main clock. To
control generating frequency, an external ceramic or a quartz crystal oscillator
is connected between the XIN and XOUT pins. If an external clock is used, the
clock source should be connected the XIN pin and the XOUT pin should be left
open. Feedback resistor is connected between XIN and XOUT.
XOUT
Clock output
Output
VREF
Reference voltage
input
Input
I/O
Reference voltage input pin for A-D converter.
P00 – P07
I/O port P0
Port P0 is an 8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistor can be connected in
units of 1-bit and a key on wake up function is provided.
P10 – P17
I/O port P1
I/O
Port P1 is an 8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistor can be connected in
units of 4-bit. P12 and P13 are in common with timer output pins T0 and T1.
P14, P15, P16 and P17 are in common with serial I/O pins RXD, TXD, SCLK
____
and SRDY, respectively.
P20 – P27
(Note 2)
Input port P2
Input port P3
Input
Input
Port P2 is an 8-bit input port.
This port is in common with analog input pins IN0 to IN7.
P30 – P33
Port P3 is a 4-bit input port. P30, P31 are in common with external interrupt
input pins INT0, INT1, and P32, P33 are in common with timer input pins
CNTR0, CNTR1.
P40 – P43
(Note 3)
I/O port P4
I/O
Port P4 is a 4-bit I/O port. The output structure is CMOS output, When this
port is selected for input, pull-up transistor can be connected in units of 4-bit.
P50 – P53
(Note 4)
Input port P5
Input
Port P5 is a 4-bit input port and pull-up transistor can be connected in units of
4-bit. P50, P51 are in common with input/output pins of clock for clock function
XCIN, XCOUT. When P50, P51 are used as XCIN, XCOUT, connect a ceramic or a
quartz crystal oscillator between XCIN and XCOUT. If an external clock input is
used, connect the clock input to the XCIN pin and open the XCOUT pin.
Feedback resistor is connected between XCIN and XCOUT pins.
Notes 1 : AVSS for M37478M4/M8/E8-XXXFP.
2 : Only P20–P23 (IN0–IN3) 4-bit for the 7477 group.
3 : Only P40 and P41 2-bit for the 7477 group.
4 : This port is not included in the 7477 group.
7
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 7477/7478 group uses the standard 740 family instruction set.
Refer to the table of 740 family addressing modes and machine in-
structions or the SERIES 740 <Software> User’s Manual for
details on the instruction set.
CPU Mode Register
The CPU mode register is allocated at address 00FB16.
This register contains the stack page selection bit.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The MUL, DIV, WIT, and STP instruction can be used.
b7
b0
CPU mode register (Address 00FB 16
)
These bits must always be set to “0”.
Stack page selection bit (Note 1)
0 : In page 0 area
1 : In page 1 area
P5
0 : P5
1 : XCIN, XCOUT
0
, P5
1/XCIN, XCOUT selection bit (Note 2)
0
, P5
1
X
COUT drive capacity selection bit (Note 2)
0 : Low
1 : High
Clock (XIN-XOUT) stop bit (Note 2)
0 : Oscillates
1 : Stops
Internal system clock selection bit (Note 2)
0 : XIN-XOUT selected (normal mode)
1 : XCIN-XCOUT selected (low-speed mode)
Notes 1 : In the M37477M4-XXXSP/FP, M37478M4-XXXSP/FP, set this bit to “0”.
2 : In the 7477 group, set this bit to “0”.
Fig. 1 Structure of CPU mode register
8
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Interrupt Vector Area
MEMORY
The interrupt vector area is for storing jump destination ad-
dresses used at reset or when an interrupt is generated.
• Zero Page
• Special Function Register (SFR) Area
The special function register (SFR) area contains the registers
relating to functions such as I/O ports and timers.
• RAM
Zero page addressing mode is useful because it enables access
to this area with fewer instruction cycles.
RAM is used for data storage as well as a stack area.
• ROM
• Special Page
Special page addressing mode is useful because it enables ac-
cess to this area with fewer instruction cycles.
ROM is used for storing user programs as well as the interrupt
vector area.
000016
RAM (192 bytes)
for
M37477M4
M37477M8/E8
M37478M4
M37478M8/E8
Zero
page
00BF16
SFR area
00FF16
010016
RAM (192 bytes)
for
M37477M8/E8
M37478M8/E8
01BF16
Not used
C00016
E00016
ROM (16K bytes)
for
M37477M8/E8
M37478M8/E8
M37478M4
ROM (8K bytes)
for
M37477M4
FF0016
Special
page
FFE816
FFFF16
Interrupt vector area
Fig. 2 Memory map
9
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
Port P0
Transmit/receive buffer register
Serial I/O status register
Serial I/O control register
UART control register
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
Port P0 direction register
Port P1
Port P1 direction register
Port P2
Baud rate generator
Port P3
Port P4
Port P4 direction register
Port P5 (Note 1)
P0 pull-up control register
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
Timer 1
Timer 2
Timer 3
Timer 4
P1–P5 pull-up control register (Note 2)
Edge polarity selection register
Input latch register
Timer FF register
Timer 12 mode register
Timer 34 mode register
Timer mode register 2
CPU mode register
A-D control register
A-D conversion register
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Notes 1 : This address is not used in the 7477 group.
2 : This address is allocated P1–P4 pull-up control register for the 7477 group.
Fig. 3 SFR (Special Function Register) memory map
10
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
When the device is put into power-down state by the STP instruc-
tion or the WIT instruction, if bit 5 in the edge polarity selection
register is “1”, the INT1 interrupt becomes a key on wake up inter-
rupt. When a key on wake up interrupt is valid, an interrupt request
is generated by applying the “L” level to any pin in port P0. In this
case , the port used for interrupt must have been set for the input
mode.
Interrupts can be caused by 13 different sources consisting of five
external, seven internal, and one software sources.
Interrupts are vectored interrupts with priorities shown in Table 1.
Reset is also included in the table because its operation is similar
to an interrupt.
When an interrupt is accepted, the registers are pushed, interrupt
disable flag I is set, and the program jumps to the address speci-
fied in the vector table. The interrupt request bit is cleared
automatically. The reset and BRK instruction interrupt can never
be disabled. Other interrupts are disabled when the interrupt dis-
able flag is set.
If bit 5 in the edge polarity selection register is “0” when the device
is in power-down state, the INT1 interrupt is selected. Also, if bit 5
in the edge polarity selection register is set to “1” when the device
is not in a power-down state, neither key on wake up interrupt re-
quest nor INT1 interrupt request is generated.
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits
are in interrupt request registers 1 and 2 and the interrupt enable
bits are in interrupt control registers 1 and 2. External interrupts
INT0 and INT1 can be asserted on either the falling or rising edge
as set in the edge polarity selection register. When “0” is set to this
register, the interrupt is activated on the falling edge; when “1” is
set to the register, the interrupt is activated on the rising edge.
The CNTR0/CNTR1 interrupts function in the same as INT0 and
INT1. The interrupt input pin can be specified for either CNTR0 or
CNTR1 pin by setting bit 4 in the edge polarity selection register.
Figure 4 shows the structure of the edge polarity selection regis-
ter, interrupt request registers 1 and 2, and interrupt control
registers 1 and 2.
Interrupts other than the BRK instruction interrupt and reset are
accepted when the interrupt enable bit is “1”, interrupt request bit
is “1”, and the interrupt disable flag is “0”. The interrupt request bit
can be reset with a program, but not set. The interrupt enable bit
can be set and reset with a program.
Reset is treated as a non-maskable interrupt with the highest pri-
ority. Figure 5 shows interrupts control.
Table 1. Interrupt vector address and priority.
Interrupt source
Priority
Vector addresses
Remarks
______
RESET
1
2
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
Non-maskable
INT0 interrupt
External interrupt (polarity programmable)
External interrupt (INT1 is polarity programmable)
External interrupt (polarity programmable)
INT1 interrupt or key on wake up interrupt
CNTR0 interrupt or CNTR1 interrupt
Timer 1 interrupt
3
4
5
Timer 2 interrupt
6
Timer 3 interrupt
7
Timer 4 interrupt
8
Serial I/O receive interrupt
Serial I/O transmit interrupt
A-D conversion completion interrupt
BRK instruction interrupt
9
10
11
12
Non-maskable software interrupt
11
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Edge polarity selection register (EG)
(Address 00D416)
INT0 edge selection bit
INT1 edge selection bit
CNTR0 edge selection bit
CNTR1 edge selection bit
0 : Falling edge
1 : Rising edge
CNTR0/CNTR1 interrupt selection bit
0 : CNTR0
1 : CNTR1
INT1 source selection bit (at power-down state)
0 : P31/INT1
1 : P00 – P07 “L” level (for key-on wake-up)
Nothing is allocated (The value is undefined at reading)
b7
b0
b7
Interrupt request register 1
b0
Interrupt request register 2
(Address 00FD16)
(Address 00FC16)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
INT0 interrupt request bit
INT1 interrupt request bit
CNTR0 or CNTR1 interrupt request bit
0 : No interrupt request
1 : Interrupt requested
Nothing is allocated
(The value is undefined at reading)
Nothing is allocated
(The value is undefined at reading)
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
A-D conversion completion interrupt request bit
b7
b0
b7
Interrupt control register 1
b0
Interrupt control register 2
(Address 00FF16)
(Address 00FE16)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
INT0 interrupt enable bit
INT1 interrupt enable bit
CNTR0 or CNTR1 interrupt enable bit
0 : Interrupt disable
1 : Interrupt enabled
Nothing is allocated
(The value is undefined at reading)
Nothing is allocated
(The value is undefined at reading)
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
A-D conversion completion interrupt enable bit
Fig. 4 Structure of registers related to interrupt
Interrupt request bit
Interrupt enable bit
Interrupt request
Interrupt disable flag I
BRK instruction
Reset
Fig. 5 Interrupt control
12
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMER
is selected; when the bit is “1”, CNTR1 input is selected.
Timer 4 can be operated in the timer mode, event count mode,
pulse output mode, pulse width measuring mode, or PWM mode.
Timer 4 starts counting when bit 3 in the timer 34 mode register is
set to “0” when bit 6 in this register is “0”. When bit 6 is “1”, the
pulse width measuring mode is selected. The count source can be
selected from timer 3 overflow, f(XIN) divided by 16, f(XCIN) divided
by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from
P33/CNTR1 pin according to the statuses of bit 4 and bit 5 in the
timer 34 mode register, bit 6 in the timer mode register 2, and bit 7
in the CPU mode register. Do not select f(XCIN) as the count
source in the 7477 group. Note, however, that if timer 1 overflow or
timer 2 overflow is selected for the count source of timer 4 when
timer 1 overflow is selected for the count source of timer 2, timer 1
overflow is always selected regardless of the status of bit 6 in the
timer mode register 2. Event inputs are selected depending on bit
3 in the edge polarity selection register.
The 7477/7478 group has four timers; timer 1, timer 2, timer 3,
and timer 4.
A block diagram of timer 1 through 4 is shown in Figure 6.
Timer 1 can be operated in the timer mode, event count mode, or
pulse output mode. Timer 1 starts counting when bit 0 in the timer
12 mode register (address 00F816) is set to “0”.
The count source can be selected from the f(XIN) divided by 16,
f(XCIN) divided by 16, f(XCIN), or event input from P32/CNTR0 pin.
Do not select f(XCIN) as the count source in the 7477 group. When
bit 1 and bit 2 in the timer 12 mode register are “0”, f(XIN) divided
by 16 or f(XCIN) divided by 16 is selected. Selection between
f(XIN) and f(XCIN) is done by bit 7 in the CPU mode register (ad-
dress 00FB16). When bit 1 in the timer 12 mode register is “0” and
bit 2 is “1”, f(XCIN) is selected. And, when bit 1 in the timer 12
mode register is “1”, an event input from the CNTR0 pin is se-
lected. Event inputs are selected depending on bit 2 in the edge
polarity selection register (address 00D416). When this bit is “0”,
the inverted value of CNTR0 input is selected; when the bit is “1”,
CNTR0 input is selected.
When this bit is “0”, the inverted value of CNTR1 input is selected;
when the bit is “1”, CNTR1 input is selected.
When bit 7 in the timer 34 mode register is set to “1”, the P13 pin
becomes timer output T1. When the direction register of P13 is set
for the output mode at this time, the timer 4 overflow divided by 2
is output from T1 when bit 7 in the timer mode register 2 is “0”.
Please set the initial output value in the following procedure.
➀ Set “1” to bit 3 of the timer 34 mode register.
When bit 3 in the timer 12 mode register is set to “1”, the P12 pin
becomes timer output T0. When the direction register of P12 is set
for the output mode at this time, the timer 1 overflow divided by 2
is output from T0.
Please set the initial output value in the following procedure.
➀ Set “1” to bit 0 of the timer 12 mode register.
(Timer 4 count stop.)
(Timer 1 count stop.)
➁ Set “1” to bit 1 of the timer mode register 2.
➁ Set “1” to bit 0 of the timer mode register 2.
➂ Set the output value to bit 0 of the timer FF register.
➃ Set the count value to the timer 1.
➂ Set the output value to bit 1 of the timer FF register.
➃ Set the count value to the timer 4.
➄ Set “0” to bit 3 of the timer 34 mode register.
➄ Set “0” to bit 0 of the timer 12 mode register.
(Timer 4 count start.)
(Timer 1 count start.)
(1) Timer mode
Timer 2 can only be operated in the timer mode. Timer 2 starts
counting when bit 4 in the timer 12 mode register is set to “0”.
The count source can be selected from the divide by 16, divide by
64, divide by 128, or divide by 256 frequency of f(XIN) or f(XCIN),
and timer 1 overflow. Do not select f(XCIN) as the count source in
the 7477 group. When bit 5 in the timer 12 mode register is “0”,
any of the divide by 16, divide by 64, divide by 128, or divide by
256 frequency of f(XIN) or f(XCIN) is selected. The divide ratio is
selected according to bit 6 and bit 7 in the timer 12 mode register,
and selection between f(XIN) and f(XCIN) is made according to bit
7 in the CPU mode register. When bit 5 in the timer 12 mode reg-
ister is “1”, timer 1 overflow is selected as the count source.
Timer 3 can be operated in the timer mode, event count mode, or
PWM mode. Timer 3 starts counting when bit 0 in the timer 34
mode register (address 00F916) is set to “0”.
Timer performs down count operations with the dividing ratio being
1/(n+1). Writing a value to the timer latch sets a value to the timer.
When the value to be set to the timer latch is nn16, the value to be
set to a timer is nn16, which is down counted at the falling edge of
the count source from nn16 to (nn16-1) to (nn16-2) to ...0116 to 0016
to FF16. At the falling edge of the count source immediately after
timer value has reached FF16, value (nn16-1) obtained by subtract-
ing one from the timer latch value is set (reloaded) to the timer to
continue counting. At the rising edge of the count source immedi-
ately after the timer value has reached FF16, an overflow occurs
and an interrupt request is generated.
(2) Event count mode
Timer operates in the same way as in the timer mode except that
it counts input from the CNTR0 or CNTR1 pin.
(3) Pulse output mode
The count source can be selected from the f(XIN) divided by 16,
f(XCIN) divided by 16, f(XCIN), timer 1 or timer 2 overflow, or an
event input from P33/CNTR1 pins according to the statuses of bit 1
and bit 2 in the timer 34 mode register, bit 6 in the timer mode reg-
ister 2 (address 00FA16) and bit 7 in the CPU mode register. Do
not select f(XCIN) as the count source in the 7477 group. Note,
however, that if timer 1 overflow or timer 2 overflow is selected for
the count source of timer 3 when timer 1 overflow is selected for
the count source of timer 2, timer 1 overflow is always selected re-
gardless of the status of bit 6 in the timer mode register 2. Event
inputs are selected depending on bit 3 in the edge polarity selec-
tion register. When this bit is “0”, the inverted value of CNTR1 input
In this mode, duty 50% pulses are output from the T0 or T1 pin.
When the timer overflows, the polarity of the T0 or T1 pin output
level is inverted.
(4) Pulse width measuring mode
The 7477/7478 group can measure the “H” or “L” width of the
CNTR0 or CNTR1 input waveform by using the pulse width mea-
suring mode of timer 4. The pulse width measuring mode is
selected by writing “1” to bit 6 in the timer 34 mode register. In the
pulse width measuring mode, the timer counts the count source
while the CNTR0 or CNTR1 input is “H” or “L”. Whether the CNTR0
input or CNTR1 input to be measured can be specified by the sta-
tus of bit 4 in the edge polarity selection register; whether the “H”
13
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
width or “L” width to be measured can be specified by the status of
bit 2 (CNTR0) and bit 3 (CNTR1) in the edge polarity selection reg-
ister.
INPUT LATCH FUNCTION
The 7477/7478 group can latch the P30/INT0, P31/INT1, P32/
CNTR0, and P33/CNTR1 pin level into the input latch register (ad-
dress 00D616) when timer 4 overflows. The polarity of each pin
latched to the input latch register can be selected by using the
edge polarity selection register.
(5) PWM mode
The PWM mode can be entered for timer 3 and timer 4 by setting
bit 7 in the timer mode register 2 to “1”. In the PWM mode, the P13
pin is set for timer output T1 to output PWM waveforms by setting
bit 7 in the timer 34 mode register to “1”. The direction register of
P13 must be set for the output mode before this can be done.
In the PWM mode, timer 3 is counting and timer 4 is idle while the
PWM waveform is “L”. When timer 3 overflows, the PWM wave-
form goes “H”. At this time, timer 3 stops counting simultaneously
and timer 4 starts counting. When timer 4 overflows, the PWM
waveform goes “L”, and timer 4 stops and timer 3 starts counting
again. Consequently, the “L” duration of the PWM waveform is de-
termined by the value of timer 3; the “H” duration of the PWM
waveform is determined by the value of timer 4.
When bit 0 in the edge polarity selection register is “0”, the in-
verted value of the P30/INT0 pin level is latched; when the bit is
“1”, the P30/INT0 pin level is latched as it is.
When bit 1 in the edge polarity selection register is “0”, the in-
verted value of the P31/INT1 pin level is latched; when the bit is
“1”, the P31/INT1 pin level is latched as it is. When bit 2 in the
edge polarity selection register is “0”, the inverted value of the
P32/CNTR0 pin level is latched; when the bit is “1“, the P32/CNTR0
pin level is latched as it is. When bit 3 in the edge polarity selec-
tion register is “0”, the inverted value of the P33/CNTR1 pin level is
latched; when the bit is “1”, the P33/CNTR1 pin level is latched as
it is.
When a value is written to the timer in operation during the PWM
mode, the value is only written to the timer latch, and not written to
the timer. In this case, if the timer overflows, a value one less the
value in the timer latch is written to the timer. When any value is
written to an idle timer, the value is written to both the timer latch
and the timer.
In this mode, do not select timer 3 overflow as the count source for
timer 4.
14
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
CIN
Data bus
(Note)
1/2
Timer 1 latch (8)
1/2
T12M
2
1/8
XIN
CM
7
T12M
0
Timer 1
interrupt request
P3
2
/CNTR
0
0
Timer 1 (8)
EG
Port latch
2
T12M
1
TM2
0
1/2
P12/T
T12M
3
Timer 2 latch (8)
Timer 2 (8)
T12M
T12M
6
7
T12M
4
Timer 2
interrupt request
T12M
5
1/4
1/8
TM2
6
T34M
T34M
1
2
1/16
Timer 3 latch (8)
Timer 3 (8)
T34M
0
Timer 3
interrupt request
P3
2/CNTR
1
EG
3
T34M
T34M
4
5
Timer 4 latch (8)
Timer 4 (8)
Timer 4
interrupt request
T34M
6
Port latch
EG
4
F/F
1/2
T34M
3
P13/T1
T34M
7
TM2
7
TM2
1
EG
EG
EG
EG
3
2
1
0
P3
3
2
/CNTR
/CNTR
1
0
C
P3
D3 Q3
D2 Q2
D1 Q1
D0 Q0
P3
P3
1
0
/INT
/INT
1
0
(
Select gate : At reset, shaded side is connected.)
Note : The 7477 group does not have XCIN input.
Fig. 6 Block diagram of timer 1 through 4
15
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Timer 34 mode register (T34M)
Timer mode register 2 (TM2)
(Address 00FA16
(Address 00F916
)
)
Timer 3 count stop bit
0 : Count start
Timer 1 overflow FF set enable bit
0 : Set disable
1 : Count stop
1 : Set enable
Timer 3 count source selection bits (Note 3)
00 : f(XIN) divided by 16 or
f(XCIN) divided by 16
Timer 4 overflow FF set enable bit
0 : Set disable
1 : Set enable
01 : f(XCIN
10 : Timer 1 overflow or timer 2 overflow
11 : P3 /CNTR external clock
)
Nothing is allocated
(The value is undefined at reading)
Timer 3, timer 4 count overflow signal
selection bit
3
1
Timer 4 count stop bit
0 : Count start
0 : Timer 1 overflow
1 : Count stop
1 : Timer 2 overflow
Timer 4 count source selection bits (Note 3)
00 : Timer 3 overflow
Timer 3, timer 4 function selection bit
0 : Normal mode
01 : f(XIN) divided by 16 or
f(XCIN) divided by 16
1 : PWM mode
10 : Timer 1 overflow or timer 2 overflow
b7
b0
11 : P33/CNTR1 external clock
Timer 4 pulse width measuring mode
selection bit
Timer 12 mode register (T12M)
(Address 00F816
)
0 : Timer mode
1 : Pulse width measuring mode
Timer 1 count stop bit
0 : Count start
1 : Count stop
Timer 1 count source selection bit
0 : Internal clock (Note 1)
P1
0 : P1
3
/T
1
port output selection bit
port output
3
1 : Timer 4 overflow divided by 2
or PWM output
1 : P3
Timer 1 internal clock source
selection bit (Note 2)
0 : f(XIN) divided by 16 or
f(XCIN) divided by 16
2/CNTR0 external clock
1 : f(XCIN
P1 /T port output selection bit
0 : P1 port output
)
2
0
2
1 : Timer 1 overflow divided by 2
Timer 2 count stop bit
0 : Count start
1 : Count stop
Timer 2 count source selection bit
0 : Internal clock
1 : Timer 1 overflow
Timer 2 internal clock source
selection bits (Note 3)
00 : f(XIN) divided by 16 or
f(XCIN) divided by 16
01 : f(XIN) divided by 64 or
f(XCIN) divided by 64
10 : f(XIN) divided by 128 or
f(XCIN) divided by 128
11 : f(XIN) divided by 256 or
f(XCIN) divided by 256
Notes 1 : f(XIN) divided by 16 in the 7477 group.
2 : The 7477 group does not use this bit (bit 2). Set this bit to “0”.
3 : Do not select f(XCIN) as the count source in the 7477 group.
Fig. 7 Structure of timer mode registers
16
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
Clock Synchronous Serial I/O Mode
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O control register to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit or receive buffer.
Data bus
Address 00E216
Serial I/O control register
Address 00E016
Receive buffer register
P1
4
P1
6
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
Shift clock
RXD
RE
Clock control circuit
S
CLK
Serial I/O synchronous
SIOE
Frequency dividing
ratio 1/(n+1)
clock selection
CSS
bit (SCS)
Baud rate generator
Address 00E416
1/4
f(XIN
)
1/4
1/4
Fall detect
SRDY
Clock control circuit
S
RDY
F/F
TE
Shift clock
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Transmit shift register
TXD
TIC
Transmit buffer register
P1
5
P1
7
Address 00E016
Data bus
Serial I/O status register
Address 00E116
Fig. 8 Clock synchronous serial I/O block diagram
Transfer shift clock
(1/8 to 1/8192 of the internal
clock, or an external clock)
Serial output TxD
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Serial input RxD
Receive enable signal SRDY
Write signal to
receive/transmit buffer
TBE = 1
TSC = 0
RBF = 1
TSC = 1
TBE = 0
Overrun error (OE) detection
Notes 1 : The transmit interrupt request (TI) can be selected to occur either when the transmit buffer has emptied (TBE = 1) or after the
transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control
register.
2 : If data is written to the transmit buffer when TSC = 0, the transmit clock is generated continuously and serial data is output
continuously from the TxD pin.
3 : The receive interrupt request (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Fig. 9 Operation of clock synchronous serial I/O function
17
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical. The
transmit and receive shift registers each have a buffer, but the two
buffers have the same address in memory. Since the shift register
cannot be written to or read from directly, transmit data is written
to the transmit buffer, and receive data is read from the receive
buffer. The transmit buffer can also hold the next data to be trans-
mitted, and the receive buffer can hold a character while the next
character is being received.
Data bus
Serial I/O control register
P1
4
Address 00E216
RXD
RE
Address 00E016
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
ST detection
7-bit
8-bit
Receive shift register
UART control register
SP detection
1/16
PE FE
Address 00E316
Clock control circuit
Serial I/O synchronous clock
selection bit
S
CLK
Frequency dividing ratio 1/(n+1)
f(XIN
)
1/4
P1
Baud rate generator
1/4
1/16
ST/SP/PA generation
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
TE
TIC
Transmit shift register
TXD
Character
length
selection
Transmit buffer register
Transmit buffer empty flag (TBE)
Serial I/O status register
P1
5
6
Address 00E116
bit
Address 00E016
Data bus
Fig. 10 UART serial I/O block diagram
Transmit or receive clock
Transmit buffer write signal
TBE=0
TBE=0
TSC=0
TBE=1
✽
TBE=1
TSC=1
SP
Serial output TxD
D
0
D
1
D0
D
1
ST
ST
ST
SP
1 start bit
✽
Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit(s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
Serial input RxD
ST
D
0
D
0
D1
D
1
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1,” depending on the
setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
Fig. 11 Operation of UART serial I/O function
18
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O Control Register SIOCON
The serial I/O control register consists of eight control bits for the
serial I/O function.
UART Control Register UARTCON
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of a data transfer.
Serial I/O Status Register SIOSTS
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in selected UART.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer, and
the receive buffer full flag is set. Writing to the serial I/O status
register clears all the error flags OE, PE, FE, and SE(bit 3 to bit 6,
respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of
the serial I/O control register) also clears all the status flags, in-
cluding the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift completion flag (bit 2) and
the transmit buffer empty flag (bit 0) become “1”.
Transmit Buffer/Receive Buffer TB/RB
The transmit buffer and the receive buffer are located at the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored
in the receive buffer is “0”.
Baud Rate Generator BRG
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n+1), where n is the value written to the baud rate generator.
19
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Serial I/O status register
(SIOSTS: address 00E116
Serial I/O control register
(SIOCON: address 00E216
)
)
BRG count source selection bit (CSS)
0 : f(XIN)divided by 4
1 : f(XIN)divided by16
Transmit buffer empty flag (TBE)
0 : Buffer full
1 : Buffer empty
Serial I/O synchronous clock selection bit (SCS)
0 : BRG output divided by 4 (when clock synchronous
serial I/O is selected)
Receive buffer full flag (RBF)
0 : Buffer empty
1 : Buffer full
BRG output divided by 16 (when UART is selected)
1 : External clock input (when clock synchronous
serial I/O is selected )
Transmit shift completion flag (TSC)
0 : Transmit shift in progress
1 : Transmit shift completed
Overrun error flag (OE)
0 : No error
1 : Overrun error
Parity error flag (PE)
0 : No error
1 : Parity error
External clock input divided by16 (when UART is selected
)
S
RDY output enable bit (SRDY)
0 : P1
7
7
pin operates as ordinary I/O pin
pin operates as SRDY output pin
1 : P1
Transmit interrupt source selection bit (TIC)
0 : Interrupt when transmit buffer has emptied.
1 : Interrupt when transmit shift operation is completed.
Transmit enable bit (TE)
0 : Transmit disabled
1 : Transmit enabled
Framing error flag (FE)
0 : No error
1 : Framing error
Summing error flag (SE)
0 : (OE)U(PE)U(FE)=0
1 : (OE)U(PE)U(FE)=1
Receive enable bit (RE)
0 : Receive disabled
1 : Receive enabled
Not used (returns “1” when read)
Serial I/O mode selection bit (SIOM)
0 : Asynchronous serial I/O (UART)
1 : Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0 : Serial I/O disabled
b7
b0
(pins P1
I/O pins)
1 : Serial I/O enabled
(pins P1
to P1 operate as serial
I/O pins)
4 to P17 operate as ordinary
UART control register
(UARTCON: address 00E316
)
Character length selection bit (CHAS)
0 : 8 bits
1 : 7 bits
4
7
Parity enable bit (PARE)
0 : Parity checking disabled
1 : Parity checking enabled
Parity selection bit (PARS)
0 : Even parity
1 : Odd parity
Stop bit length selection bit (STPS)
0 : 1 stop bit
1 : 2 stop bits
Not used (returns “1” when read)
Fig. 12 Structure of serial I/O control registers
20
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D conversion register (address 00DA16) contains informa-
tion on the results of conversion, so that it is possible to know the
results of conversion by reading the contents of this register.
The following explains the procedure to execute A-D conversion.
First, set values to bit 2 to bit 0 in the A-D control register to select
the pins that you want to execute A-D conversion. Next, clear the
A-D conversion end bit to “0”. When the above is done, A-D con-
version is initiated. The A-D conversion is completed after an
elapse of 50 machine cycles (12.5µs when f(XIN) = 8MHz), the A-
D conversion end bit is set to “1”, and the interrupt request bit is
set to “1”. The results of conversion are contained in the A-D con-
version register.
The A-D conversion uses an 8-bit successive comparison method.
Figure 13 shows a block diagram of the A-D conversion circuit.
Conversion is automatically carried out once started by the pro-
gram.
There are eight analog input pins which are shared with P20 to
P27 of port P2 (Only P20 to P23 4-bit for 7477 group).
Which analog inputs are to be A-D converted is specified by using
bit 2 to bit 0 in the A-D control register (address 00D916). Pins for
inputs to be A-D converted must be set for input by setting the di-
rection register bit to “0”. Bit 3 in the A-D control register is an A-D
conversion end bit. This is “0” during A-D conversion; it is set to “1“
when the conversion is terminated. Therefore, it is possible to
know whether A-D conversion is terminated by checking this bit.
Figure 14 shows the relationship between the contents of A-D
control register and the selected input pins.
Data bus
bit 3
bit 0
A-D control register
(address 00D916)
A-D conversion
completion
interrupt request
P20/IN0
P21/IN1
P22/IN2
P23/IN3
P24/IN4
P25/IN5
P26/IN6
P27/IN7
A-D control circuit
A-D conversion register
(address 00DA16)
Comparator
Switch tree
Ladder resistor
VSS (Note 1)
VREF
Notes 1 : AVSS for M37478M4/M8/E8-XXXFP.
2 : The 7477 group does not have P2 4/IN4 to P27/IN7 pins.
Fig. 13 A-D converter circuit
21
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
A-D control register
(Address 00D916)
Analog input selection bits
000 : IN0
001 : IN1
010 : IN2
011 : IN3
100 : IN4
101 : IN5
110 : IN6
(Note)
111 : IN7
A-D conversion end bit
0 : Under conversion
1 : End conversion
Nothing is allocated
(The value is undefined at reading)
This bit must be set to “0”.
Note : Do not select IN4 to IN7 in the 7477 group.
Fig. 14 Structure of A-D control register
22
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The key on wake up interrupt is common with the INT1 interrupt.
When EG5 is set to “1”, the key on wake up function is selected.
However, key on wake up cannot be used in the normal operating
state. When the microcomputer is in the normal operating state,
both key on wake up and INT1 are invalid.
KEY ON WAKE UP
“Key on wake up” is one way of returning from a power down state
caused by the STP or WIT instruction. If any terminal of port P0
has “L” level applied, after bit 5 of the edge polarity selection reg-
ister (EG5) is set to “1”, an interrupt is generated and the
microcomputer is returned to the normal operating state. A key
matrix can be connected to port P0 and the microcomputer can be
returned to a normal state by pushing any key.
P33/CNTR1
Port P33 data read circuit
EG
3
2
CNTR interrupt request signal
EG
P32/CNTR0
EG4
Port P32 data read circuit
X
CIN
(P50)
1/2
1/2
X
IN
CM
7
P3
P3
0
1
/INT
0
Port P3
0
data read circuit
interrupt request signal
Noise
eliminating
circuit
INT
0
EG
0
/INT
1
Port P31 data read circuit
Noise
eliminating
circuit
EG5
INT1 interrupt request signal
EG1
CPU halt state signal
Pull-up control
register
P0
7
Direction register
Pull-up control
register
P0
P0
1
0
Direction register
Port P0 data read circuit
Pull-up control
register
Direction register
(
Select gate: At reset, shaded side is connected.).
Note: The 7477 group does not have XCIN input.
Fig. 15 Block diagram of interrupt input and key on wake up circuit
23
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
Address
The 7477/7478 group is reset according to the sequence shown in
Figure 18. It starts the program from the address formed by using
the content of address FFFF16 as the high order address and the
content of the address FFFE16 as the low order address, when the
RESET pin is held at “L” level for no less than 2µs while the power
voltage is in the recommended operating condition and then re-
turned to “H” level.
0016
0016
0
(1) Port P0 direction register
(2) Port P1 direction register
(3) Port P4 direction register
(4) P0 pull-up control register
(C116) …
(C316) …
(C916) …
(D016) …
0
0
0
0016
0
0
0
0
0
0
0
0
0
0
0
(5) P1–P5 pull-up control register (Note 1) (D116) …
The internal initializations following reset are shown in Figure 17.
Example of reset circuit is Figure 16. Immediately after reset, timer
3 and timer 4 are connected, and counts the f(XIN) divided by 16.
At this time, FF16 is set to timer 3, and 0716 is set to timer 4. The
reset is cleared when timer 4 overflows.
0
0
0
0
1
0
0
0
0
(6) Edge selection register (EG)
(7) A-D control register
(D416) …
(D916) …
(E116) …
(E216) …
(E316) …
0
0
(8) Serial I/O status register
(9) Serial I/O control register
(10) UART control register
0016
0
0
0
0
0016
0016
(11) Timer 12 mode register (T12M) (F816) …
(12) Timer 34 mode register (T34M) (F916) …
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(13) Timer mode register 2 (TM2)
(14) CPU mode register (CM)
(15) Interrupt request register 1
(16) Interrupt request register 2
(17) Interrupt control register 1
(18) Interrupt control register 2
(19) Program counter
(FA16) …
(FB16) …
(FC16) …
(FD16) …
(FE16) …
(FF16) …
(PCH) …
(PCL) …
(PS) …
0
0
0
0
0
0
0
0
7477/7478 group
RESET
VCC
0
0
0
Contents of address FFFF16
Contents of address FFFE16
1
(20) Processor status register
Notes 1 : This address is allocated P1–P4 pull-up control register for the
7477 group. Bit 6 is not used.
2 : Since the contents of both registers other than those listed
above (including timers and the transmit/receive buffer register)
are undefined at reset, it is necessary to set initial values.
Fig. 16 Example of reset circuit
Fig. 17 Internal state of microcomputer at reset
XIN
φ
RESET
Internal RESET
SYNC
Address
Data
?
?
00, S
00, S-1 00, S-2
ADH,L
FFFE16 FFFF16
Reset address from
the vector table
?
?
PCH
PCL
PS
ADL
ADH
Notes 1 : Frequency relation of XIN and φ is f(XIN)=2·φ.
32768 counts of f(XIN)
2 : The mark “?” means that the address is changeable depending
upon the previous state.
Fig. 18 Timing diagram at reset
24
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
(5) Port P4
(1) Port P0
Port P4 is a 4-bit I/O port and has basically the same func-
tions as port P0. In the 7477 group, this port is P40 and P41,
a 2-bit I/O port. When this port is selected for input, pull-up
transistor can be connected in units of 4-bit .
Port P0 is an 8-bit I/O port with CMOS outputs. As shown in
Figure 2, P0 can be accessed as memory through zero page
address 00C016. Port P0’s direction register allows each bit to
be programmed individually as input or output. The direction
register (zero page address 00C116) can be programmed as
input with “0”, or as output with “1”. When in the output mode,
the data to be output is latched to the port latch and output.
When data is read from the output port, the output pin level is
not read, only the latched data of the port latch is read.
Therefore, a previously output value can be read correctly
even though the output voltage level has been shifted up or
down. Port pins set as input are in the high impedance state
so the signal level can be read. When data is written into the
input port, the data is latched only to the output latch and the
pin still remains in the high impedance state. Following the
execution of STP or WIT instruction, key matrix with port P0
can be used to generate the interrupt to bring the microcom-
puter back in its normal state. When this port is selected for
input, pull-up transistor can be connected in units of 1-bit.
(6) Port P5
Port P5 is a 4-bit input port and pull-up transistor can be con-
nected in units of 4-bit. P50 and P51 are shared with clock
generating circuit input/output pins.
The 7477 group does not have this port.
(7) INT0 pin (P30/INT0 pin)
This is an interrupt input pin, and is shared with port P30.
When “H” to “L” or “L” to “H” transition input is applied to this
pin, the INT0 interrupt request bit (bit 0 of address 00FD16) is
set to “1”.
(8) INT1 pin (P31/INT1 pin)
This is an interrupt input pin, and is shared with port P31.
When “H” to “L” or “L” to “H” transition input is applied to this
pin, the INT1 interrupt request bit (bit 1 of address 00FD16) is
set to “1”.
(9) Counter input CNTR0 pin (P32/CNTR0 pin)
This is a timer input pin, and is shared with port P32.
When this pin is selected to CNTR0 or CNTR1 interrupt input
pin and “H” to “L” or “L” to “H” transition input is applied to this
pin, the CNTR0 or CNTR1 interrupt request bit (bit 2 of ad-
dress 00FD16) is set to “1”.
(2) Port P1
Port P1 has the same function as port P0. P12 – P17 serve
dual functions, and the desired function can be selected by
the program. When this port is selected for input, pull-up tran-
sistor can be connected in units of 4-bit.
(3) Port P2
(10) Counter input CNTR1 pin (P33/CNTR1 pin)
This is a timer input pin, and is shared with port P33.
When this pin is selected to CNTR0 or CNTR1 interrupt input
pin and “H” to “L” or “L” to “H” transition input is applied to this
pin, the CNTR0 or CNTR1 interrupt request bit (bit 2 of ad-
dress 00FD16) is set to “1”.
Port P2 is an 8-bit input port. In the 7477 group, this port is
P20 – P23, a 4-bit input port. This port can also be used as
the analog voltage input pins.
(4) Port P3
Port P3 is a 4-bit input port.
25
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0
Pull-up control
register
Tr1
Direction register
Data bus
Port latch
Port P0
Interrupt control circuit
Ports P10 – P13
Pull-up control
register
Data bus
Tr2
T34M7
Direction register
Data bus
Data bus
Data bus
Port latch
Port P13
T1
Tr3
T12M3
Direction register
Port latch
Port P12
T0
Tr4
Direction register
Port latch
Port P11
Tr5
Direction register
Data bus
Port latch
Port P10
Tr1 to Tr5 are pull-up transistors.
Fig. 19 Block diagram of ports P0, P10–P13
26
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Ports P14 – P17
SIOE
SIOM
SRDY
Tr6
Direction register
Data bus
Port latch
Port P1
7
S
RDY
SCS
SIOE
SIOM
SIOE
Tr7
Direction register
Data bus
Port latch
Port P1
6
CLK input
CLK output
SIOE
TE
Tr8
Direction register
Data bus
Port latch
Port P1
5
TXD
SIOE
RE
Tr9
Direction register
Data bus
Data bus
Port latch
Port P1
4
RXD
Pull-up control
register
Tr6 to Tr9 are pull-up transistors.
Fig. 20 Block diagram of ports P14 – P17
27
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P2
Data bus
Port P2
Multi-
plexer
A-D conversion circuit
Port P3
Data bus
Port P3
INT0, INT1
CNTR0, CNTR1
Port P4
* : Control in units of 4-bit (Control in units of 2-bit for the 7477 group)
Pull-up control register*
Data bus
Tr10
Direction register
Port latch
Data bus
Port P4
Tr10 is pull-up transistor
Fig. 21 Block diagram of ports P2 – P4
28
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P5
Pull-up
control register
Data bus
Tr11
Data bus
Port P5
3
Tr12
Data bus
Port P5
2
CM4
Tr13
Data bus
Port P5
1
CM4
CM4
X
CIN
CM
4
Tr14
Data bus
Port P5
0
Tr11 to Tr14 are pull-up transistors
Note : The 7477 group does not have this port.
Fig. 22 Block diagram of port P5
29
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 7477 group has one internal clock generating circuit and 7478
group has two internal clock generating circuits.
M37477M4-XXXSP/FP
Figure 27 shows a block diagram of the clock generating circuit.
Normally, the frequency applied to the clock input pin XIN divided
by two is used as the internal clock φ. Bit 7 of CPU mode register
can be used to switch the internal clock φ to 1/2 the frequency ap-
plied to the clock input pin XCIN in the 7478 group.
XIN
XOUT
R
d
Figure 23, 24 show a circuit example using a ceramic resonator
(or quartz crystal oscillator). Use the manufacturer’s recom-
mended values for constants such as capacitance which will differ
depending on each oscillator. When using an external clock sig-
nal, input from the XIN(XCIN) pin and leave the XOUT(XCOUT) pin
open. A circuit example is shown in Figure 25, 26.
C
IN
COUT
Fig. 23 Example of ceramic resonator circuit (7477 group)
The 7477/7478 group has two low power dissipation modes; stop
and wait. The microcomputer enters a stop mode when the STP
instruction is executed. The oscillator (both XIN clock and XCIN
clock) stops with the internal clock φ held at “H” level. In this case
timer 3 and timer 4 are forcibly connected and FF16 is automati-
cally set in timer 3 and 0716 in timer 4.
M37478M4-XXXSP/FP
X
OUT
X
COUT
X
IN
XCIN
Although oscillation is restarted when an external interrupt is ac-
cepted, the internal clock φ remains in the “H” state until timer 4
overflows. In other words, the internal clock φ is not supplied until
timer 4 overflows. This is because when a ceramic or similar other
oscillator is used, a finite time is required until stable oscillation is
obtained after restart.
R
d
Rd
C
OUT
CCOUT
C
IN
C
CIN
The microcomputer enters an wait mode when the WIT instruction
is executed. The internal clock φ stops at “H” level, but the oscilla-
tor does not stop. φ is re-supplied (wait mode release) when the
microcomputer receives an interrupt.
Fig. 24 Example of ceramic resonator circuit (7478 group)
Instructions can be executed immediately because the oscillator is
not stopped. The interrupt enable bit of the interrupt used to reset
the wait mode or the stop mode must be set to “1” before execut-
ing the WIT or the STP instruction.
M37477M4-XXXSP/FP
Low power dissipation operation is also achieved when the XIN
clock is stopped and the internal clock φ is generated from the
XCIN clock (30µA typ. at f(XCIN) = 32kHz). This operation is only
7478 group. XIN clock oscillation is stopped when the bit 6 of CPU
mode register is set and restarted when it is cleared. However, the
wait time until the oscillation stabilizes must be generated with a
program when restarting. Figure 29 shows the transition of states
for the system clock.
X
IN
XOUT
Open
V
V
CC
SS
External oscillation circuit
Fig. 25 External clock input circuit (7477 group)
M37478M4-XXXSP/FP
X
OUT
XCOUT
X
IN
XCIN
Open
Open
External oscillation External oscillation circuit
circuit
or external pulse
V
V
CC
SS
V
V
CC
SS
Fig. 26 External clock input circuit (7478 group)
30
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCIN
XCOUT
X
IN
XOUT
1/2
T34M
0
1/8
Timer 3
Timer 4
1/2
CM
7
T34M
T34M
1
2
CM
CM
6
7
Internal clock φ
Q S
R
S Q
R
Q S
R
Reset
STP instruction
WIT
instruction
STP
instruction
Reset
Interrupt disable flag I
Interrupt request
Select gate : At reset, shaded
side is connected.
Note : The 7477 group does not have X CIN input and XCOUT output.
Fig. 27 Block diagram of clock generating circuit
b7
b0
CPU mode register
(Address 00FB16
)
These bits must always be set to “0”.
Stack page selection bit (Note 1)
0 : In page 0 area
1 : In page 1 area
P5
0 : P5
0
, P5
1
/XCIN, XCOUT selection bit (Note 2)
, P5
0
1
1 : XCIN, XCOUT
XCOUT drive capacity selection bit (Note 2)
0 : Low
1 : High
Clock (XIN-XOUT) stop bit (Note 2)
0 : Oscillates
1 : Stops
Internal system clock selection bit (Note 2)
0 : XIN-XOUT selected (normal mode)
1 : XCIN-XCOUT selected (low-speed mode)
Notes 1 : In the M37477M4, M37478M4, set this bit to “0”.
2 : In the 7477 group, set this bit to “0”.
Fig. 28 Structure of CPU mode register
31
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
CM
CM
CM
CM
4
5
6
7
= 0
= 0
= 0
= 0
f(XIN) oscillation
f(XCIN) stop
φ stop
f(XIN) oscillation
f(XCIN) stop
WIT instruction
Interrupt
STP instruction
f(XIN) stop
f(XCIN) stop
P5
0, P51 input
φ stop
Timer operation
φ = f(XIN)/2
Interrupt (Note 1)
CM
CM
5
4
= 1
= 1
CM
4
= 0
(Note 2)
f(XIN) oscillation
f(XCIN) oscillation
φ stop
WIT instruction
Interrupt
STP instruction
f(XIN) stop
f(XCIN) stop
φ stop
f(XIN) oscillation
f(XCIN) oscillation
φ = f(XIN)/2
Timer operation
Interrupt (Note 1)
(CM
CM
5
= 0)
CM7 = 0
7
= 1
CM5 = 1
f(XIN) oscillation
f(XCIN) oscillation
φ stop
WIT instruction
Interrupt
STP instruction
f(XIN) stop
f(XCIN) stop
φ stop
f(XIN) oscillation
f(XCIN) oscillation
φ = f(XCIN)/2
Timer operation
Interrupt (Note 1)
CM
6 = 0
CM6 = 1
(Note 2)
CM5 = 1
f(XIN) stop
WIT instruction
Interrupt
STP instruction
f(XIN) stop
f(XCIN) stop
φ stop
f(XIN) stop
f(XCIN) oscillation
φ stop
f(XCIN) oscillation
φ = f(XCIN)/2
Timer operation
Interrupt (Note 1)
Notes 1 : Latency time is automatically generated upon release from the STP instruction due to the connections of timer 3
and 4.
2 : When the system clock is switched over by restarting clock oscillation, a certain wait time required for oscillation
to stabilize must be inserted by the program.
Fig. 29 Transition of states for the system clock.
32
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
<An example of flow for system>
Power on reset
↓
Clock X oscillation
↓
Internal system clock start (X→1/2→ φ)
↓
Program start from RESET vector
Normal program
Operating at f(XIN)
Clock for clock function XC oscillation start (CM4 = 1, CM5 = 1)
↓
←
Latency time for oscillation to stabilize (by program)
Operating at f(XIN)
↓
→
XC clock power down (CM5 : 1 0)
↓
→ →
XC (CM7 : 0 1)
Internal clock φ source switching
X
↓
Clock X halt (XC in operation) (CM6 = 1)
↓
Internal clock halt (WIT instruction)
↓
Timer 4 (clock count) overflow
↓
Internal clock operation start (WIT instruction released)
←
Clock processing routine
Operating at f(XCIN)
Internal clock halt (WIT instruction)
Interrupts from INT0, INT1, CNTR0/CNTR1, timer 1, timer 2, timer 3, timer 4, serial I/O, key on wake up
↓
Internal clock operation start (WIT instruction released)
↓
Program start from interrupt vector
↓
Clock X oscillation start (CM6 = 0)
↓
←
Latency time for oscillation to stabilize (by program)
Operating at f(XCIN)
↓
→
→
Internal clock φ source switching (XC X) (CM7 : 1 0)
→
Normal program
Operating at f(XIN)
33
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
STP instruction preparation (pushing registers)
↓
Timer 3, timer 4 interrupt disable
↓
X/16 or XC/16 selected for timer 3 count source; timer 3 overflow selected for timer 4 count source
↓
Timer 3, timer 4 start counting
↓
Values set to timer 3, timer 4 that do not cause timer 4 to overflow until STP instruction is executed
↓
Interrupt for return from STP enabled
↓
Timer 4 interrupt request bit cleared
↓
Clock X and clock for clock function XC halt (STP instruction)
RAM backup status
Interrupts from INT0, INT1, CNTR0/CNTR1, timer 1, timer 2, serial I/O, key on wake up
↓
Clock X and clock for clock function XC oscillation start
↓
Timer 4 overflow (X/16 or XC/16→timer 3→timer 4)
↓
Internal system clock start
↓
Program start from interrupt vector
Normal program
34
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
BUILT-IN PROM TYPE MICROCOMPUTERS
PIN DESCRIPTION
Input/
output
Pin
Mode
Name
Functions
VCC,VSS
Single-chip Power source
/EPROM
Apply voltage of 2.7 to 5.5 V to VCC and 0 V to VSS.
AVSS
Single-chip Analog power
Ground level input pin for A-D converter. Same voltage as VSS is applied.
(Note 1)
/EPROM
source
RESET
Single-chip Reset input
Input To enter the reset state, the reset input pin must be kept at a “L” for 2µs or more
(under normal VCC conditions).
EPROM
Reset input
Input
Connect to VSS.
XIN
Single-chip Clock input
/EPROM
Input These are I/O pins of internal clock generating circuit for main clock. To control
generating frequency, an external ceramic or a quartz crystal oscillator is con-
nected between the XIN and XOUT pins. If an external clock is used, the clock
Output source should be connected the XIN pin and the XOUT pin should be left open.
Feedback resistor is connected between XIN and XOUT.
XOUT
VREF
Single-chip Clock output
/EPROM
Single-chip Reference
voltage input
Input Reference voltage input pin for the A-D converter.
EPROM
Select mode
Input
I/O
VREF works as CE input.
P00 – P07
P10 – P17
Single-chip I/O port P0
Port P0 is an 8-bit I/O port. The output structure is CMOS output. When this port
is selected for input, pull-up transistor can be connected in units of 1-bit and a
key on wake up function is provided.
EPROM
Data I/O D0–D7
I/O
I/O
Port P0 works as an 8-bit data bus (D0 to D7).
Single-chip I/O port P1
Port P1 is an 8-bit I/O port. The output structure is CMOS output. When this port
is selected for input, pull-up transistor can be connected in units of 4-bit. P12 and
P13 are in common with timer output pins T0, T1. P14, P15, P16 and P17 are in
common with serial I/O pins RxD, TxD, SCLK, SRDY, respectively.
EPROM
Address input
A4–A10
Input
Input
P11 to P17 works as the 7-bit address input (A4 to A10). P10 must be opened.
P20 – P27
(Note 2)
Single-chip Input port P2
Port P2 is an 8-bit input port. This port is in common with analog input pins IN0 to IN7.
EPROM
Address input
A0–A3
Input P20 to P23 works as the lower 4-bit address input (A0 to A3).
P24 to P27 must be opened.
P30 – P33
Single-chip Input port P3
Input
Input
Port P3 is a 4-bit input port. P3
0
and P3
1
are in common with external interrupt in-
, CNTR
put pins INT , INT and P3 , P3
0
1
2
3
are in common with timer input pins CNTR
0
1.
EPROM
Address input
A11, A12 Select
mode VPP input
P30, P31 works as the 2-bit address input (A11, A12).
P32 works as OE input. Connect to P33 to VPP when programming or verifying.
P40 – P43
(Note 3)
Single-chip I/O port P4
I/O
Port P4 is a 4-bit I/O port. The output structure is CMOS output. When this port is
selected for input, pull-up transistor can be connected in units of 4-bit.
EPROM
Address input
A13, A14
Input
P40 and P41 works as the higher 2-bit address input (A13, A14).
P42 and P43 must be opened.
P50 – P53
(Note 4)
Single-chip Input port P5
Input Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4-
bit. P50, P51 are in common with input/output pins of clock for clock function XCIN,
XCOUT. When P50, P51 are used as XCIN, XCOUT, connect a ceramic or a quartz
crystal oscillator between XCIN and XCOUT. If an external clock input is used, con-
nect the clock input to the XCIN pin and open the XCOUT pin. Feedback resistor is
connected between XCIN and XCOUT pins.
EPROM
Notes 1 : AVSS for M37478M4/M8/E8-XXXFP.
Open.
2 : Only P20–P23 (IN0–IN3) 4-bit for the 7477 group.
3 : Only P40 and P41 2-bit for the 7477group.
4 : This port is not included in the 7477 group.
35
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2. Pin function in EPROM mode
M37477E8, M37478E8
EPROM MODE
The M37477E8, M37478E8 feature an EPROM mode in addition
to its normal modes. When the RESET signal level is low (“L”), the
chip automatically enters the EPROM mode. Table 2 lists the cor-
respondence between pins and Figure 30 to 32 give the pin
connection in the EPROM mode. When in the EPROM mode,
ports P0, P11 to P17, P20 to P23, P3, P40, P41 and VREF are used
for the PROM (equivalent to the M5L27C256). When in this mode,
the built-in PROM can be written to or read from using these pins
in the same way as with the M5L27C256K. The oscillator should
be connected to the XIN and XOUT pins, or external clock should
be connected to the XIN pin.
M5L27C256K
VCC
VPP
VSS
VCC
VCC
VPP
VSS
P33
VSS
Ports P11 – P17,
Address input
P20 – P23, P30,
A0 – A14
P31, P40, P41
Port P0
VREF
Data I/O
CE
D0 – D7
CE
OE
P32
OE
1
42
P52
P53
2
3
4
5
6
7
8
9
41
40
A10
A9
D7
D6
P07
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
P13/T1
P12/T0
P11
P06
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A8
P05
D5
D4
A7
A6
A5
A4
P04
D3
D2
D1
D0
P03
P02
P01
P10
P00
10
11
12
13
14
15
16
17
18
19
20
21
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P43
P42
A14
A13
VPP
OE
P41
P40
A3
A2
A1
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
P51/XCOUT
P50/XCIN
VCC
A12
A11
A0
CE
Oscillation
circuit
XIN
VSS
XOUT
VSS
VCC
VSS
: Same functions as M5L27C256
Fig. 30 Pin connection in EPROM mode
36
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
45
28
RESET
NC
P05/D5
P06/D6
P07/D7
P52
46
47
27
D5
D6
D7
NC
P51/XCOUT
P50/XCIN
NC
VCC
VSS
AVSS
NC
XOUT
XIN
VSS
26
48
49
25
24
50
23
NC
VSS
P53
VCC
VSS
M37478E8-XXXFP
22
21
20
19
18
17
51
52
VSS
53
54
A10
A9
P17/S
RDY/A10
Oscillation
circuit
P16/SCLK/A9
P15/TXD/A8
NC
55
56
A8
NC
: Same functions as M5L27C256
Fig. 31 Pin connection in EPROM mode
1
32
31
A
10
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P3
P3
P3
P3
7
6
5
4
3
2
1
0
1
0
3
2
1
0
D
D
7
6
P17/SRDY
2
3
A
9
P1
P1
P1
6
5
4
/SCLK
D
D
D
D
D
D
5
4
30
29
28
27
26
A
A
A
A
A
8
7
6
5
4
/TX
D
4
5
/RX
D
3
2
1
0
P1
P1
3
2
/T
1
0
1
0
6
/T
7
P1
P1
8
25
24
23
22
9
A
A
A
A
3
2
A
A
14
13
P2
3
2
1
0
/IN
/IN
/IN
/IN
3
2
1
0
10
P2
P2
P2
V
PP
1
0
11
12
13
14
15
/CNTR
/CNTR
1
0
21
20
19
18
OE
A
A
12
11
CE
V
REF
IN
OUT
SS
/INT
/INT
1
Oscillation
circuit
X
0
X
RESET
V
SS
V
16
17
V
CC
V
CC
V
SS
: Same functions as M5L27C256
Fig. 32 Pin connection in EPROM mode
37
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PROM READING AND WRITING
NOTES ON HANDLING
Reading
(1) Sunlight and fluorescent light contain wave lengths capable of
erasing data. For ceramic package types, cover the transpar-
ent window with a seal (provided) when this chip is in use.
However, this seal must not contact the lead pins.
To read the PROM, set the CE and OE pins to “L” level. Input the
address of the data (A0 to A14) to be read and the data will be out-
put to the I/O pins (D0 to D7). The data I/O pins will be floating
when either the CE or OE pin is in the “H” state.
(2) Before erasing, the glass should be cleaned and stains such
as finger prints should be removed thoroughly. If these stains
are not removed, complete erasure of the data could be pre-
vented.
Writing
To write to the PROM, set the OE pin to “H” level. The CPU will en-
ter the program mode when VPP is applied to the VPP pin. The
address to be written to is selected with pins A0 to A14, and the
data to be written is input to pins D0 to D7. Set the CE pin to “L”
level to begin writing.
(3) Since a high voltage (12.5V) is used to write data, care should
be taken when turning on the PROM programmer’s power.
(4) For the programmable microcomputer (shipped in One Time
PROM version), Mitsubishi does not perform PROM write test
and screening in the assembly process and following pro-
cesses. To improve reliability after write, performing write and
test according to the flow below before use is recommended.
Note on Writing
When using a PROM programmer, the address range should be
between 400016 and 7FFF16. When data is written between ad-
dresses 000016 and 7FFF16, fill addresses 000016 to 3FFF16 with
FF16.
Writing with PROM programmer
Screening (Caution) (Leave at 150°C for 40 hours.)
Verify test with PROM programmer
Erasing
Data can only erased on the M37478E8SS ceramic package,
which includes a window. To erase data on this chip, use an ultra-
violet light source with a 2537 Angstrom wave length. The
2
minimum radiation power necessary for erasing is 15W·s/cm .
Function check in target device
Caution : Since the screening temperature is higher than storage
temperature, never expose to 150°C exceeding 100
hours.
Table 3. I/O signal in each mode
Pin
__
CE
__
OE
VPP
VCC
Data I/O
Mode
Read-out
VIL
VIL
VIL
VIH
VIH
VIL
VIH
VIH
VIL
VIH
VCC
VCC
VPP
VPP
VPP
VCC
VCC
VCC
VCC
VCC
Output
Floating
Input
Output disable
Programming
Programming verify
Program disable
Output
Floating
Note : VIL and VIH indicate an “L” and an “H” input voltage, respectively.
38
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PROGRAMMING NOTES
(1) The frequency ratio of the timer is 1/(n+1).
(2) The contents of the interrupt request bits are not modified im-
mediately after they have been written. After writing to an
interrupt request register, execute at least one instruction be-
fore executing a BBC or BBS instruction.
(3) To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. Only the ADC
and SBC instruction yield proper decimal results. After execut-
ing an ADC or SBC instruction, execute at least one
instruction before executing a SEC, CLC, or CLD instruction.
(4) An NOP instruction must be used after the execution of a PLP
instruction.
(5) Do not execute the STP instruction during A-D conversion.
(6) In the 7477 group, set bit 0, bit 1, and bit 3 – bit 7 to “0” of the
CPU mode register.
(7) Multiply/Divide instructions
The index X mode (T) and the decimal mode (D) flag do not
affect the MUL and DIV instruction.
The execution of these instructions does not modify the con-
tents of the processor status register.
DATA REQUIRED FOR MASK ORDERING
Please send the following data for mask orders.
(1) mask ROM confirmation form
(2) mark specification form
(3) ROM data ......................................................... EPROM 3 sets
39
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37477M4/M8/E8-XXXSP/FP
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Power source voltage
Conditions
Ratings
–0.3 to 7
Unit
V
VCC
VI
VI
Input voltage XIN
–0.3 to VCC +0.3
V
All voltages are based on VSS.
Output transistors are cut off
Input voltage P00 – P07, P10 – P17, P20 –
P23, P30 – P33, P40, P41, VREF,
–0.3 to VCC +0.3
V
RESET
VO
Output voltage P0
0
– P0
7
, P1
0
– P1
7
, P4
0
, P4
1
, XOUT
–0.3 to VCC +0.3
1000 (Note)
–20 to 85
V
mW
°C
Pd
Power dissipation
Ta = 25°C
Topr
Tstg
Operating temperature
Storage temperature
–40 to 150
°C
Note : 500mW for M37477M4/M8/E8-XXXFP
RECOMMENDED OPERATING CONDITIONS
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C unless otherwise noted)
Limits
Typ.
Symbol Parameter
Unit
V
Min.
2.7
Max.
4.5
f(XIN) = 2.2VCC – 2.0 MHz
f(XIN) = 8 MHz
VCC
Power source voltage
Power source voltage
4.5
5
0
5.5
VSS
V
V
VIH
“H” input voltage P00 – P07, P10 – P17, P30 – P33, RESET, XIN
“H” input voltage P20 – P23, P40, P41
0.8 VCC
VCC
VCC
VIH
0.7 VCC
V
VIL
“L” input voltage P00 – P07, P10 – P17, P30 – P33
“L” input voltage P20 – P23, P40, P41
0
0
0
0
0.2 VCC
V
VIL
0.25 VCC
V
VIL
“L” input voltage RESET
V
0.12 VCC
VIL
“L” input voltage XIN
V
0.16 VCC
IOH(sum)
IOH(sum)
IOL(sum)
IOL(sum)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
“H” sum output current P00 – P07, P40, P41
“H” sum output current P10 – P17
mA
mA
mA
mA
mA
mA
mA
mA
–30
–30
“L” sum output current P00 – P07, P40, P41
“L” sum output current P10 – P17
60
60
“H” peak output current P00 – P07, P10 – P17, P40, P41
“L” peak output current P00 – P07, P10 – P17, P40, P41
“H” average output current P00 – P07, P10 – P17, P40, P41 (Note 1)
“L” average output current P00 – P07, P10 – P17, P40, P41 (Note1)
f(XIN) = 4 MHz
–10
20
–5
10
1
Timer input frequency CNTR
0
(P32), CNTR1 (P33)
f(CNTR)
f(SCLK)
f(XIN)
MHz
kHz
(Note 2)
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 8 MHz
VCC = 2.7 to 4.5 V
VCC = 4.5 to 5.5 V
2
Use as clock
250
synchronous serial
I/O mode
Serial I/O clock input
frequency SCLK (P16)
(Note 2)
500
1
Use as UART mode
MHz
MHz
2
2.2VCC – 2
8
Clock input oscillation frequency (Note 2)
Notes 1 : The average output current IOH (avg) and IOL (avg) are the average value during a 100ms.
2 : Oscillation frequency is at 50% duty cycle.
40
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37477M4/M8/E8-XXXSP/FP
ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test Conditions
Unit
V
Min.
Typ.
Max.
“H” output voltage
VCC = 5 V, IOH = –5 mA
3
VOH
P00 – P07, P10 – P17, P40, P41
“L” output voltage
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
VCC = 3 V, IOL = 3 mA
VCC = 5 V
2
2
VOL
V
P00 – P07, P10 – P17, P40, P41
Hysteresis P00 – P07,
P30 – P33
1
0.5
0.3
0.5
0.3
0.5
0.3
VT + – VT–
VT + – VT–
VT + – VT–
V
VCC = 3 V
VCC = 5 V
V
Hysteresis RESET
Hysteresis P16/SCLK
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
use as SCLK input
V
VI = 0 V,
–5
–3
–1.0
–0.35
–5
–3
–5
–3
–5
–3
5
”H“ input current
P00-P07, P10-P17
P30-P32, P40-P41
µA
mA
µA
µA
µA
µA
µA
µA
µA
not use pull-up transistor
VI = 0 V,
IIL
–0.25
–0.08
–0.5
use pull-up transistor
–0.18
IIL
IIL
IIL
IIH
IIH
IIH
IIH
VI = 0 V
“L” input current P33
VI = 0 V,
“L” input current P20 – P23
not use as analog input
VI = 0 V
“L” input current RESET, XIN
(XIN is at stop mode)
VI = VCC,
“H” input current P00 – P07,
not use pull-up transistor
3
P10 – P17, P30 – P32, P40, P41
5
“H” input current, P33
VI = VCC
3
VI = VCC,
5
“H” input current P20 – P23
“H” input current RESET XIN,
not use as analog input
VI = VCC,
3
5
(XIN is at stop mode)
3
f(XIN)=8MHz
At normal
mode, A-D
conversion is
not executed.
14
7
7
3.5
1.8
7.5
4
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
mA
mA
mA
f(XIN)=4MHz
f(XIN)=8MHz
f(XIN)=4MHz
f(XIN)=8MHz
f(XIN)=4MHz
3.6
15
8
At normal
mode, A-D
conversion is
executed.
4
2
ICC
Power source current
4
2
At wait mode.
2
1
VCC = 3 V
Ta = 25°C
Ta = 85°C
1
0.5
0.1
1
1
At stop mode,
µA
f(XIN)=0, VCC=5V
Stop all oscillation
10
2
V
VRAM
RAM retention voltage
41
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37477M4/M8/E8-XXXSP/FP
A-D CONVERSION CHARACTERISTICS
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
——
——
bits
Resolution
8
LSB
Absolute accuracy
±3
VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz
VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz
25
TCONV
µs
Conversion time
12.5
V
VREF
Reference input voltage
0.5 VCC
VCC
2
0
kΩ
Ladder resistance value
Analog input voltage
5
10
RLADDER
VIA
V
VREF
42
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37478M4/M8/E8-XXXSP/FP, M37478E8SS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Power source voltage
Input voltage XIN
Input voltage P0 – P07, P10 – P17, P2 – P27
Conditions
Ratings
–0.3 to 7
Unit
V
VCC
VI
VI
–0.3 to VCC +0.3
V
All voltages are based on VSS.
Output transistors are cut off
0
,0_____,
3, VREF
RESET
–0.3 to VCC +0.3
V
P3 – P3 , P4 – P4 , P5
0
3
0
3
0
– P5
VO
Output voltage P0 – P0 , P1
0
7
0
– P1
7
, P4
0
– P4
3
, XOUT
–0.3 to VCC +0.3
1000 (Note)
–20 to 85
V
mW
°C
Pd
Power dissipation
Ta = 25°C
Topr
Tstg
Operating temperature
Storage temperature
–40 to 150
°C
Note : 500mW for M37478M4/M8/E8-XXXFP
RECOMMENDED OPERATING CONDITIONS
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C unless otherwise noted)
Limits
Typ.
Symbol Parameter
Unit
V
Min.
2.7
Max.
4.5
f(XIN) = 2.2VCC – 2.0 MHz
f(XIN) = 8 MHz
Power source voltage
VCC
4.5
5
0
0
5.5
Power source voltage
VSS
V
V
Analog power source voltage
AVSS
VIH
“H” input voltage P00 – P07, P10 – P17 , P30 – P33, RESET, XIN
“H” input voltage P20 – P27, P40 – P43, P50 – P53 (Note 1)
“L” input voltage P00 – P07, P10 – P17, P30 – P33
“L” input voltage P20 – P27, P40 – P43, P50–P53 (Note 1)
“L” input voltage RESET
0.8 VCC
VCC
VCC
V
VIH
0.7 VCC
V
VIL
0
0
0
0
0.2 VCC
V
VIL
0.25 VCC
V
VIL
V
0.12 VCC
“L” input voltage XIN
VIL
V
0.16 VCC
“H” sum output current P00 – P07, P40 – P43
“H” sum output current P10 – P17
IOH(sum)
IOH(sum)
IOL(sum)
IOL(sum)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
mA
mA
mA
mA
mA
mA
mA
mA
– 30
– 30
“L” sum output current P00 – P07, P40 – P43
“L” sum output current P10 – P17
60
60
“H” peak output current P00 – P07, P10 – P17, P40 – P43
“L” peak output current P00 – P07, P10 – P17, P40 – P43
“H” average output current P00 – P07, P10 – P17, P40 – P43 (Note 2)
“L” average output current P00 – P07, P10 – P17, P40 – P43 (Note 2)
f(XIN) = 4 MHz
– 10
20
– 5
10
1
Timer input frequency CNTR
(Note 3)
0
(P32), CNTR1 (P33)
f(CNTR)
MHz
kHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 8 MHz
VCC = 2.7 to 4.5 V
VCC = 4.5 to 5.5 V
2
Use as clock
250
synchronous serial
I/O mode
Serial I/O clock input
frequency SCLK (P16)
(Note 2)
500
f(SCLK)
1
Use as UART mode
MHz
2
2.2VCC – 2
Main clock input oscillation frequency (Note 3)
f(XIN)
MHz
kHz
8
f(XCIN)
Sub-clock input oscillation frequency for clock function (Note 3,4)
32
50
Notes 1 : It is except to use P50 as XCIN.
2 : The average output current IOH (avg) and IOL (avg) are the average value during a 100ms.
3 : Oscillation frequency is at 50% duty cycle.
4 : When used in the low-speed mode, the clock oscillation frequency for clock function should be f(XCIN) < f(XIN) / 3.
43
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37478M4/M8/E8-XXXSP/FP, M37478E8SS
ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test Conditions
Unit
V
Min.
Typ.
Max.
“H” output voltage
VCC = 5 V, IOH = –5 mA
3
VOH
P00 – P07, P10 – P17, P40 – P43
“L” output voltage
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
VCC = 3 V, IOL = 3 mA
VCC = 5 V
2
2
V
VOL
P00 – P07, P10 – P17, P40 – P43
Hysteresis P00 – P07,
P30 – P33
1
0.5
0.3
0.5
0.3
0.5
0.3
V
VT + – VT–
VT + – VT–
VT + – VT–
VCC = 3 V
VCC = 5 V
Hysteresis RESET
Hysteresis P16/SCLK
V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
V
used as SCLK input
VI = 0 V,
–5
–3
–1.0
–0.35
–5
–3
–5
–3
–5
–3
5
“L” input current
µA
mA
µA
µA
µA
µA
µA
µA
µA
not use pull-up transistor
VI = 0 V,
P00 – P07, P10 – P17, P30 – P32,
P40 – P43, P50 – P53
IIL
–0.25
–0.08
–0.5
use pull-up transistor
–0.18
“L” input current P33
VI = 0 V
IIL
IIL
IIL
IIH
IIH
IIH
IIH
VI = 0 V,
“L” input current P20 – P27
“L” input current RESET, XIN
not use as analog input
VI = 0 V
(XIN is at stop mode)
VI = VCC,
“H” input current P0
0
– P0
, P5
7
, P1
0
– P1
7,
not use pull-up transistor
3
P3 – P3 , P4 – P4
0
2
0
3
0
– P5
3
5
VI = VCC
“H” input current P33
3
VI = VCC,
5
“H” input current P20 – P27
not use as analog input
VI = VCC,
3
5
“H” input current RESET, XIN
(XIN is at stop mode)
3
7
3.5
1.8
7.5
4
14
7
At normal
mode, A-D
conversion is
not executed.
f(XIN)=8MHz
VCC = 5 V
VCC = 3 V
VCC = 5 V
mA
f(XIN)=4MHz
f(XIN)=8MHz
3.6
15
8
At normal
mode, A-D
conversion is
executed.
mA
f(XIN)=4MHz
2
4
VCC = 3 V
VCC = 5 V
VCC = 3 V
At low-speed mode, T
f(XCIN)=32kHz, low-power mode, A-D
conversion is not executed.
a
=25°C, f(XIN)=0,
30
15
2
80
40
4
µA
ICC
Power source current
f(XIN)=8MHz
VCC = 5 V
At wait mode.
f(XIN)=4MHz
1
2
mA
0.5
3
1
VCC = 3 V
VCC = 5 V
VCC = 3 V
Ta = 25°C
Ta = 85°C
At wait mode, Ta=25°C,
f(XIN)=0, f(XCIN)=32kHz, low-
power mode
12
8
µA
2
0.1
1
1
At stop mode,
f(XIN)=0, f(XCIN)=0, VCC=5V
µA
10
V
2
VRAM
RAM retention voltage
Stop all oscillation
44
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37478M4/M8/E8-XXXSP/FP, M37478E8SS
A-D CONVERTER CHARACTERISTICS
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
——
——
Resolution
8
bits
Absolute accuracy
±3
LSB
VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz
VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz
25
TCONV
Conversion time
µs
12.5
0.5 VCC
VREF
Reference input voltage
VCC
V
RLADDER
VIA
Ladder resistance value
Analog input voltage
2
0
5
10
kΩ
VREF
V
45
MITSUBISHI MICROCOMPUTERS
7477/7478 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
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Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
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Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1997 MITSUBISHI ELECTRIC CORP.
New publication, effective Dec. 1997.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
7477/7478 GROUP DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
971226
(1/1)
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