M37471M8-619SP [MITSUBISHI]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M37471M8-619SP |
| 厂家： | 
Mitsubishi Group |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总46页 (文件大小：643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The 7470/7471 group is a single-chip microcomputer designed
with CMOS silicon gate technology. It is housed in a 32-pin shrink
plastic molded DIP. The M37471M2-XXXSP/FP is a single-chip mi-
crocomputer designed with CMOS silicon gate technology. It is
housed in a 42-pin shrink plastic molded DIP or a 56-pin plastic
molded QFP.
1
2
3
4
5
6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P17/SRDY
P16/CLK
P07
P06
P05
P15/SOUT
P14/SIN
P04
These single-chip microcomputer are useful for business equip-
ment and other consumer applications.
P03
P13/T1
P12/T0
P02
In addition to its simple instruction set, the ROM, RAM, and I/O
addresses are placed on the same memory map to enable easy
programming .
7
8
P11
P10
P01
P00
9
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P41
The differences between the M37471M2-XXXSP and the
M37471M2-XXXFP are the package outline and the power dissi-
pation ability (absolute maximum ratings).
10
P40
11
12
13
14
15
16
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
VCC
The differences among M37470M2-XXXSP, M37470M4-XXXSP,
M37470M8-XXXSP, M37471M2-XXXSP/FP, M37471M4-XXXSP/
FP and M37471M8-XXXSP/FP are noted below.
XIN
XOUT
VSS
Type name
ROM size
4096 bytes
RAM size
128 bytes
I/O ports
26
Outline 32P4B
M37470M2-XXXSP
M37471M2-XXXSP/FP
M37470M4-XXXSP
M37471M4-XXXSP/FP
M37470M8-XXXSP
M37471M8-XXXSP/FP
36
26
8192 bytes
192 bytes
384 bytes
36
APPLICATION
26
16384 bytes
Audio-visual equipment, VCR, Tuner,
36
Office automation equipment
FEATURES
●Basic machine-language instructions ...................................... 71
●Memory size
ROM ..................................................... 4096 bytes (M37471M2)
RAM ........................................................ 128 bytes (M37471M2)
●The minimum instruction execution time
....................................... 0.5 µs (at 8 MHz oscillation frequency)
●Power source voltage
.............. 2.7 to 4.5 V (at 2.2VCC–2.0 MHz oscillation frequency)
............................... 4.5 to 5.5 V (at 8 MHz oscillation frequency)
●Power dissipation in normal mode
................................... 35 mW (at 8.0 MHz oscillation frequency)
●Subroutine nesting ...... 64 levels max. (M37470M2, M37471M2)
●Interrupt ................................................... 12 sources, 10 vectors
●8-bit timers .................................................................................. 4
●Programmable I/O ports
(Ports P0, P1, P2, P4) ......................................... 22(7470 group)
28(7471 group)
●Input port (Port P3) ............................................... 4(7470 group)
(Ports P3, P5)....................................... 8(7471 group)
●Serial I/O (8-bit) .......................................................................... 1
●A-D converter ............................... 8-bit, 4channels (7470 group)
8-bit, 8channels (7471 group)
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
P52
P07
P06
P05
P04
P03
P02
P01
P00
P43
P42
P41
P40
P53
P17/SRDY
P16/CLK
P15/SOUT
P14/SIN
P13/T1
P12/T0
P11
1
2
42
41
40
3
4
5
6
39
38
37
36
45
28
RESET
NC
P51/XCOUT
P50/XCIN
NC
VCC
VSS
AVSS
NC
XOUT
XIN
NC
NC
P05
7
46
47
27
35
34
33
8
9
26
P06
P07
P52
NC
VSS
P53
48
49
25
P10
M37471M2-XXXFP
M37471M4-XXXFP
M37471E4-XXXFP
M37471M8-XXXFP
24
10
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
50
23
11
12
32
31
30
22
51
52
21
M37471E8-XXXFP
13
14
53
54
20
P17/SRDY
P16/CLK
19
29
28
27
26
P33/CNTR1
P32/CNTR0
55
56
18
P15/SOUT
NC
15
16
17
P31/INT1
P30/INT0
RESET
P51/XCOUT
P50/XIN
VCC
17
18
19
20
21
25
24
23
XIN
XOUT
22
VSS
Outline 42P4B
Outline 56P6N-A
42S1B-A (Window)
Note : The differences between 42P4B package type of 7471 group and 56P6N-A package type of 7471 group are package outline, power
dissipation ability (absolute maximum ratings), and the provision of an AV SS pin by the 56P6N-A package type.
NC : No connection
2
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
4
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
5
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONS OF 7470/7471 GROUP
Parameter
Functions
Basic machine-language instructions
Instruction execution time
71
0.5 µs (the minimum instructions, at 8 MHz oscillation frequency)
Clock input oscillation frequency
8 MHz (max.)
M37470M2
M37471M2
M37470M4/E4
M37471M4/E4
M37470M8/E8
M37471M8/E8
P0, P1
ROM
4096 bytes
RAM
ROM
RAM
ROM
RAM
I/O
128 bytes
8192 bytes
Memory size
192 bytes
16384 bytes
384 bytes
8-bit ✕ 2
P2
I/O
8-bit ✕ 1 (4-bit ✕ 1 for 7470 group)
4-bit ✕ 2 (Port P5 is not included in 7470 group)
4-bit ✕ 1 (2-bit ✕ 1 for 7470 group)
8-bit ✕ 1
Input/Output port
P3, P5
Input
I/O
P4
Serial I/O
Timers
8-bit timer ✕ 4
A-D converter
8-bit ✕ 1 (8 channels) (8-bit ✕ 1 (4 channels) for M37470M2/M4/M8)
64 level max. (M37470M2, M37471M2)
96 level max. (M37470M4/E4, M37471M4/E4)
192 level max. (M37470M8/E8, M37471M8/E8)
5 external interrupts, 6 internal interrupts, 1 software interrupt
Subroutine nesting
Interrupt
Built-in circuit with internal feedback resistor (a ceramic or a quartz-
crystal oscillator)
Clock generating circuit
2.7 to 4.5 V (at 2.2VCC–2.0 MHz oscillation frequency),
4.5 to 5.5 V (at 8 MHz oscillation frequency)
Power source voltage
Power dissipation
35 mW (at 8 MHz oscillation frequency)
5 V
Input/Output voltage
Output current
Input/Output characters
–5 to 10 mA (P0, P1, P2, P4 : CMOS tri-states)
–20 to 85°C
Operating temperature range
Device structure
CMOS silicon gate
M37470M2/M4/M8/E4/E8-XXXSP
32-pin shrink plastic molded DIP
42-pin shrink plastic molded DIP
56-pin plastic molded QFP
42-pin ceramic DIP
M37471M2/M4/M8/E4/E8-XXXSP
M37471M2/M4/M8/E4/E8-XXXFP
M37471E8SS
Package
6
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Input/
Output
Pin
Name
Functions
Apply voltage of 2.7 to 5.5 V to VCC, and 0 V to VSS.
Power source voltage
VCC, VSS
Analog power
source
AVSS
(Note 1)
Ground level input pin for A-D converter.
Same voltage as VSS is applied.
Reset input
Input
RESET
To enter the reset state, the reset input pin must be kept at “L” for 2 µs or more
(under normal VCC conditions).
Clock input
Input
XIN
These are I/O pins of internal clock generating circuit for main clock. To control
generating frequency, an external ceramic or a quartz-crystal oscillator is
connected between the XIN and XOUT pins. If an external clock is used, the
clock source should be connected the XIN pin and the XOUT pin should be left
open. Feedback resistor is connected between XIN and XOUT.
Clock output
Output
XOUT
Reference voltage
input
Input
I/O
VREF
Reference voltage input pin for the A-D converter.
I/O port P0
P00–P07
Port P0 is an 8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistor can be connected in
units of 1-bit and a key on wake up function is provided.
I/O port P1
I/O
P10–P17
Port P1 is an 8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistor can be connected in
units of 4-bit. P12, P13 are in common with timer output pins T0, T1, P14, P15,
P16, P17 are in common with serial I/O pins SIN, SOUT, CLK, SRDY, respec-
tively. The output structure of SOUT and SRDY can be changed to N-channel
open drain output.
I/O port P2
I/O
P20–P27
(Note 2)
Port P2 is an 8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistor can be connected in
units of 4-bit.
This port is in common with analog input pins IN0–IN7.
Input port P3
Input
P30–P33
Port P3 is a 4-bit input port. P30, P31 are in common with external interrupt
input pins INT0, INT1, and P32, P33 are in common with timer input pins
CNTR0, CNTR1.
I/O port P4
I/O
P40–P43
(Note 3)
Port P4 is a 4-bit I/O port. The output structure is CMOS output. When this
port is selected for input, pull-up transistor can be connected in units of 4-bit.
Input port P5
Input
P50–P53
(Note 4)
Port P5 is a 4-bit input port and pull-up transistor can be connected in units of
4-bit. P50, P51 are in common with input/output pins of clock for clock function
XCIN, XCOUT. When P50, P51 are used as XCIN, XCOUT, connect a ceramic or a
quartz-crystal oscillator between XCIN and XCOUT.
If an external clock input is used, connect the clock input to the XCIN pin and
open the XCOUT pin. Feedback resistor is connected between XCIN and XCOUT
pins.
Notes 1 : AVSS for M37471M2/M4/M8/E4/E8-XXXFP.
2 : Only P20–P23 (IN0–IN3) 4-bit for 7470 group.
3 : Only P40 and P41 2-bit for 7470 group.
4 : This port is not included in 7470 group.
7
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CPU Mode Register
Central Processing Unit (CPU)
The CPU mode register is allocated at address 00FB16.
The 7470/7471 group uses the standard 740 family instruction set.
Refer to the table of 740 family addressing modes and machine in-
structions or the SERIES 740 <Software> User’s Manual for
details on the instruction set.
This register contains the stack page selection bit.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The MUL, DIV, WIT, and STP instruction can be used.
b7
b0
CPU mode register (Address 00FB16)
These bits must always be set to “0”.
Stack page selection bit (Note 1)
0 : In page 0 area
1 : In page 1 area
P50, P51/XCIN, XCOUT selection bit (Note 2)
0 : P50, P51
1 : XCIN, XCOUT
XCOUT drive capacity selection bit (Note 2)
0 : Low
1 : High
Clock (XIN-XOUT) stop bit (Note 2)
0 : Oscillates
1 : Stops
Internal system clock selection bit (Note 2)
0 : XIN-XOUT selected (normal mode)
1 : XCIN-XCOUT selected (low-speed mode)
Notes 1 : In the M37470M2, M37470M4/E4, M37471M2, M37471M4/E4, set this bit to “0”.
2 : In the 7470 group, set this bit to “0”.
Fig. 1 Structure of CPU mode register
8
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
• Interrupt Vector Area
• Special Function Register (SFR) Area
The special function register (SFR) area contains the registers
relating to functions such as I/O ports and timers.
• RAM
The interrupt vector area is for storing jump destination ad-
dresses used at reset or when an interrupt is generated.
• Zero Page
Zero page addressing mode is useful because it enables access
to this area with fewer instruction cycles.
RAM is used for data storage as well as a stack area.
• ROM
• Special Page
ROM is used for storing user programs as well as the interrupt
vector area.
Special page addressing mode is useful because it enables ac-
cess to this area with fewer instruction cycles.
000016
RAM (128 bytes)
for
M37470M2
M37471M2
RAM (192 bytes)
for
M37470M4/E4
M37470M8/E8
M37471M4/E4
M37471M8/E8
007F16
00BF16
Not used
SFR area
Zero page
00FF16
010016
RAM (192 bytes)
for
M37470M8/E8
M37471M8/E8
01BF16
Not used
C00016
E00016
F00016
ROM
(16K bytes)
for
M37470M8/E8
M37471M8/E8
FF0016
FFEA16
ROM
(8K bytes)
for
M37470M4/E8
M37471M4/E8
ROM
(4K bytes)
for
M37470M2
M37471M2
Special page
Interrupt vector area
FFFF16
Fig. 2 Memory map
9
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
Port P0
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
Port P0 direction register
Port P1
Port P1 direction register
Port P2
Port P2 direction register
Port P3
Port P4
Port P4 direction register
Port P5 (Note 1)
P0 pull-up control register
00F016
Timer 1
P1–P5 pull-up control register (Note 2)
00F116 Timer 2
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
Timer 3
Timer 4
Edge polarity selection register
Input latch register
Timer FF register
Timer 12 mode register
Timer 34 mode register
Timer mode register 2
CPU mode register
A-D control register
A-D conversion register
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Serial I/O mode register
Serial I/O register
Serial I/O counter
Byte counter
Notes 1 : This address is not used in the 7470 group.
2 : This address is allocated P1–P4 pull-up control register for the 7470 group.
Fig. 3 SFR (Special Function Register) memory map
10
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
When the device is put into power-down state by the STP instruc-
tion or the WIT instruction, if bit 5 in the edge polarity selection
register is “1”, the INT1 interrupt becomes a key on wake up inter-
rupt. When a key on wake up interrupt is valid, an interrupt request
is generated by applying the “L” level to any pin in port P0. In this
case, the port used for interrupt must have been set for the input
mode.
Interrupts can be caused by 12 different sources consisting of five
external, six internal, and one software sources.
Interrupts are vectored interrupts with priorities shown in Table 1.
Reset is also included in the table because its operation is similar
to an interrupt.
When an interrupt is accepted, the registers are pushed, interrupt
disable flag I is set, and the program jumps to the address speci-
fied in the vector table. The interrupt request bit is cleared
automatically. The reset and BRK instruction interrupt can never
be disabled. Other interrupts are disabled when the interrupt dis-
able flag is set.
If bit 5 in the edge polarity selection register is “0” when the device
is in power-down state, the INT1 interrupt is selected. Also, if bit 5
in the edge polarity selection register is set to “1” when the device
is not in a power-down state, neither key on wake up interrupt re-
quest nor INT1 interrupt request is generated.
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits
are in interrupt request registers 1 and 2 and the interrupt enable
bits are in interrupt control registers 1 and 2. External interrupts
INT0 and INT1 can be asserted on either the falling or rising edge
as set in the edge polarity selection register. When “0” is set to this
register, the interrupt is activated on the falling edge; when “1” is
set to the register, the interrupt is activated on the rising edge.
The CNTR0/CNTR1 interrupts function in the same as INT0 and
INT1. The interrupt input pin can be specified for either CNTR0 or
CNTR1 pin by setting bit 4 in the edge polarity selection register.
Figure 4 shows the structure of the edge polarity selection regis-
ter, interrupt request registers 1 and 2, and interrupt control
registers 1 and 2.
Interrupts other than the BRK instruction interrupt and reset are
accepted when the interrupt enable bit is “1”, interrupt request bit
is “1”, and the interrupt disable flag is “0”. The interrupt request bit
can be reset with a program, but not set. The interrupt enable bit
can be set and reset with a program.
Reset is treated as a non-maskable interrupt with the highest pri-
ority. Figure 5 shows interrupts control.
Table 1. Interrupt vector address and priority
Interrupt source
Priority
Vector addresses
Remarks
RESET
1
2
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
Non-maskable
INT0 interrupt
External interrupt (polarity programmable)
External interrupt (INT1 is polarity programmable)
External interrupt (polarity programmable)
INT1 interrupt or key on wake up interrupt
CNTR0 interrupt or CNTR1 interrupt
Timer 1 interrupt
3
4
5
Timer 2 interrupt
6
Timer 3 interrupt
7
Timer 4 interrupt
8
Serial I/O interrupt
9
A-D conversion completion interrupt
BRK instruction interrupt
10
11
Non-maskable software interrupt
11
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Edge polarity selection register (EG)
(Address 00D416
)
INT
INT
0
1
edge selection bit
edge selection bit
CNTR
CNTR
0
edge selection bit
edge selection bit
1
0 : Falling edge
1 : Rising edge
CNTR0/CNTR1 interrupt selection bit
0 : CNTR
1 : CNTR
0
1
INT1 source selection bit (at power-down state)
0 : P3
1 : P0
1
0
/INT
–P0
1
7
“L” level (for key-on wake-up)
Nothing is allocated (The value is undefined at reading)
b7
b0
b7
b0
Interrupt request register 1
Interrupt request register 2
(Address 00FD16)
(Address 00FC16
)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
INT
INT
0
1
interrupt request bit
interrupt request bit
CNTR0 or CNTR1 interrupt request bit
0 : No interrupt request
1 : Interrupt requested
Nothing is allocated
(The value is undefined at reading)
Nothing is allocated
(The value is undefined at reading)
Serial I/O transmit interrupt request bit
A-D conversion completion interrupt request bit
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(Address 00FF16)
(Address 00FE16
)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR0 or CNTR1 interrupt enable bit
0 : Interrupt disable
1 : Interrupt enabled
Nothing is allocated
(The value is undefined at reading)
Nothing is allocated
(The value is undefined at reading)
Serial I/O receive interrupt enable bit
A-D conversion completion interrupt enable bit
Fig. 4 Structure of registers related to interrupt
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 5 Interrupt control
12
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMER
The count source can be selected from the f(XIN) divided by 16,
f(XCIN) divided by 16, f(XCIN), timer 1 or timer 2 overflow, or an
event input from P33/CNTR1 pin according to the statuses of bit 1
and bit 2 in the timer 34 mode register, bit 6 in the timer mode reg-
ister 2 (address 00FA16) and bit 7 in the CPU mode register. Do
not select f(XCIN) as the count source in the 7470 group. Note,
however, that if timer 1 overflow or timer 2 overflow is selected for
the count source of timer 3 when timer 1 overflow is selected for
the count source of timer 2, timer 1 overflow is always selected re-
gardless of the status of bit 6 in the timer mode register 2. Event
inputs are selected depending on bit 3 in the edge polarity selec-
tion register. When this bit is “0”, the inverted value of CNTR1 input
is selected; when the bit is “1”, CNTR1 input is selected.
Timer 4 can be operated in the timer mode, event count mode,
pulse output mode, pulse width measuring mode, or PWM mode.
Timer 4 starts counting when bit 3 in the timer 34 mode register is
set to “0” when bit 6 in this register is “0”. When bit 6 is “1”, the
pulse width measuring mode is selected. The count source can be
selected from timer 3 overflow, f(XIN) divided by 16, f(XCIN) divided
by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from
P33/CNTR1 pin according to the statuses of bit 4 and bit 5 in the
timer 34 mode register, bit 6 in the timer mode register 2, and bit 7
in the CPU mode register. Do not select f(XCIN) as the count
source in the 7470 group. Note, however, that if timer 1 overflow or
timer 2 overflow is selected for the count source of timer 4 when
timer 1 overflow is selected for the count source of timer 2, timer 1
overflow is always selected regardless of the status of bit 6 in the
timer mode register 2. Event inputs are selected depending on bit
3 in the edge polarity selection register.
The 7470/7471 group has four timers; timer 1, timer 2, timer 3, and
timer 4.
A block diagram of timer 1 through 4 is shown in Figure 6.
Timer 1 can be operated in the timer mode, event count mode, or
pulse output mode. Timer 1 starts counting when bit 0 in the timer
12 mode register (address 00F816) is set to “0”.
The count source can be selected from the f(XIN) divided by 16,
f(XCIN) divided by 16, f(XCIN), or event input from P32/CNTR0 pin.
Do not select f(XCIN) as the count source in the 7470 group. When
bit 1 and bit 2 in the timer 12 mode register are “0”, f(XIN) divided
by 16 or f(XCIN) divided by 16 is selected. Selection between f(XIN)
and f(XCIN) is done by bit 7 in the CPU mode register (address
00FB16). When bit 1 in the timer 12 mode register is “0” and bit 2
is “1”, f(XCIN) is selected. And, when bit 1 in the timer 12 mode
register is “1”, an event input from the CNTR0 pin is selected.
Event inputs are selected depending on bit 2 in the edge polarity
selection register (address 00D416). When this bit is “0”, the in-
verted value of CNTR0 input is selected; when the bit is “1”,
CNTR0 input is selected.
When bit 3 in the timer 12 mode register is set to “1”, the P12 pin
becomes timer output T0. When the direction register of P12 is set
for the output mode at this time, the timer 1 overflow divided by 2
is output from T0.
Please set the initial output value in the following procedure.
➀ Set “1” to bit 0 of the timer 12 mode register.
(Timer 1 count stop.)
➁ Set “1” to bit 0 of the timer mode register 2.
➂ Set the output value to bit 0 of the timer FF register.
➃ Set the count value to the timer 1.
When this bit is “0”, the inverted value of CNTR1 input is selected;
when the bit is “1”, CNTR1 input is selected.
➄ Set “0” to bit 0 of the timer 12 mode register.
(Timer 1 count start.)
When bit 7 in the timer 34 mode register is set to “1”, the P13 pin
becomes timer output T1. When the direction register of P13 is set
for the output mode at this time, the timer 4 overflow divided by 2
is output from T1 when bit 7 in the timer mode register 2 is “0”.
Please set the initial output value in the following procedure.
➀ Set “1” to bit 3 of the timer 34 mode register.
Timer 2 can only be operated in the timer mode. Timer 2 starts
counting when bit 4 in the timer 12 mode register is set to “0”.
The count source can be selected from the divide by 16, divide by
64, divide by 128, or divide by 256 frequency of f(XIN) or f(XCIN),
and timer 1 overflow. Do not select f(XCIN) as the count source in
the 7470 group. When bit 5 in the timer 12 mode register is “0”,
any of the divide by 16, divide by 64, divide by 128, or divide by
256 frequency of f(XIN) or (XCIN) is selected. The divide ratio is se-
lected according to bit 6 and bit 7 in the timer 12 mode register,
and selection between f(XIN) and f(XCIN) is made according to bit
7 in the CPU mode register. When bit 5 in the timer 12 mode reg-
ister is “1”, timer 1 overflow is selected as the count source.
Timer 3 can be operated in the timer mode, event count mode, or
PWM mode. Timer 3 starts counting when bit 0 in the timer 34
mode register (address 00F916) is set to “0”.
(Timer 4 count stop.)
➁ Set “1” to bit 1 of the timer mode register 2.
➂ Set the output value to bit 1 of the timer FF register.
➃ Set the count value to the timer 4.
➄ Set “0” to bit 3 of the timer 34 mode register.
(Timer 4 count start.)
(1) Timer mode
Timer performs down count operations with the dividing ratio being
1/(n+1). Writing a value to the timer latch sets a value to the timer.
When the value to be set to the timer latch is nn16, the value to be
set to a timer is nn16, which is down counted at the falling edge of
the count source from nn16 to (nn16-1) to (nn16-2) to ...0116 to
0016 to FF16. At the falling edge of the count source immediately
after timer value has reached FF16, value (nn16-1) obtained by
subtracting one from the timer latch value is set (reloaded) to the
timer to continue counting. At the rising edge of the count source
immediately after the timer value has reached FF16, an overflow
occurs and an interrupt request is generated.
13
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Event count mode
INPUT LATCH FUNCTION
Timer operates in the same way as in the timer mode except that
it counts input from the CNTR0 or CNTR1 pin.
The 7470/7471 group can latch the P30/INT0, P31/INT1, P32/
CNTR0, and P33/CNTR1 pin level into the input latch register (ad-
dress 00D616) when timer 4 overflows. The polarity of each pin
latched to the input latch register can be selected by using the
edge polarity selection register. When bit 0 in the edge polarity se-
lection register is “0”, the inverted value of the P30/INT0 pin level is
latched; when the bit is “1”, the P30/INT0 pin level is latched as it
is. When bit 1 in the edge polarity selection register is “0”, the in-
verted value of the P31/INT1 pin level is latched; when the bit is
“1”, the P31/INT1 pin level is latched as it is. When bit 2 in the edge
polarity selection register is “0”, the inverted value of the P32/
CNTR0 pin level is latched; when the bit is “1”, the P32/CNTR0 pin
level is latched as it is. When bit 3 in the edge polarity selection
register is “0”, the inverted value of the P33/CNTR1 pin level is
latched; when the bit is “1”, the P33/CNTR1 pin level is latched as
it is.
(3) Pulse output mode
In this mode, duty 50% pulses are output from the T0 or T1 pin.
When the timer overflows, the polarity of the T0 or T1 pin output
level is inverted.
(4) Pulse width measuring mode
The 7470/7471 group can measure the “H” or “L” width of the
CNTR0 or CNTR1 input waveform by using the pulse width mea-
suring mode of timer 4. The pulse width measuring mode is
selected by writing “1” to bit 6 in the timer 34 mode register. In the
pulse width measuring mode, the timer counts the count source
while the CNTR0 or CNTR1 input is “H” or “L”. Whether the CNTR0
input or CNTR1 input to be measured can be specified by the sta-
tus of bit 4 in the edge polarity selection register; whether the “H”
width or “L” width to be measured can be specified by the status of
bit 2 (CNTR0) and bit 3 (CNTR1) in the edge polarity selection reg-
ister.
(5) PWM mode
The PWM mode can be entered for timer 3 and timer 4 by setting
bit 7 in the timer mode register 2 to “1”. In the PWM mode, the P13
pin is set for timer output T1 to output PWM waveforms by setting
bit 7 in the timer 34 mode register to “1”. The direction register of
P13 must be set for the output mode before this can be done.
In the PWM mode, timer 3 is counting and timer 4 is idle while the
PWM waveform is “L”. When timer 3 overflows, the PWM waveform
goes “H”. At this time, timer 3 stops counting simultaneously and
timer 4 starts counting. When timer 4 overflows, the PWM wave-
form goes “L”, and timer 4 stops and timer 3 starts counting again.
Consequently, the “L” duration of the PWM waveform is deter-
mined by the value of timer 3; the “H” duration of the PWM
waveform is determined by the value of timer 4.
When a value is written to the timer in operation during the PWM
mode, the value is only written to the timer latch, and not written to
the timer. In this case, if the timer overflows, a value one less the
value in the timer latch is written to the timer. When any value is
written to an idle timer, the value is written to both the timer latch
and the timer.
In this mode, do not select timer 3 overflow as the count source for
timer 4.
14
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
CIN
Data bus
(Note 1)
1/2
Timer 1 latch (8)
1/2
T12M
2
1/8
XIN
CM
7
T12M
0
Timer 1
interrupt request
P3
2
/CNTR
0
0
Timer 1 (8)
EG
Port latch
2
T12M
1
TM2
0
1/2
P12/T
T12M
3
Timer 2 latch (8)
Timer 2 (8)
T12M
T12M
6
7
T12M
4
Timer 2
interrupt request
T12M
5
1/4
1/8
TM2
6
T34M
T34M
1
2
1/16
Timer 3 latch (8)
Timer 3 (8)
T34M
0
Timer 3
interrupt request
P3
3/CNTR
1
EG
3
T34M
T34M
4
5
Timer 4 latch (8)
Timer 4 (8)
Timer 4
interrupt request
T34M
6
Port latch
EG
4
F/F
1/2
T34M
3
P13/T1
T34M
7
TM2
7
TM2
1
EG
EG
EG
EG
3
2
1
0
P3
3
2
/CNTR
/CNTR
1
0
C
P3
D3 Q3
D2 Q2
D1 Q1
D0 Q0
P3
P3
1
0
/INT
/INT
1
0
(
Select gate : At reset, shaded side is connected.)
Note 1 : The 7470 group does not have
XCIN input.
Fig. 6 Block diagram of timer 1 through 4
15
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Timer mode register 2 (TM2)
(Address 00FA16
Timer 34 mode register (T34M)
)
(Address 00F916
)
Timer 3 count stop bit
0 : Count start
Timer 1 overflow FF set enable bit
0 : Set disable
1 : Count stop
1 : Set enable
Timer 4 overflow FF set enable bit
0 : Set disable
Timer 3 count source selection bits (Note 3)
00 : f(XIN) divided by 16 or
1 : Set enable
f(XCIN) divided by 16
01 : f(XCIN
10 : Timer 1 overflow or timer 2 overflow
11 : P3 /CNTR external clock
)
Nothing is allocated
(The value is undefined at reading)
Timer 3, timer 4 count overflow signal
selection bit
3
1
Timer 4 count stop bit
0 : Count start
0 : Timer 1 overflow
1 : Timer 2 overflow
1 : Count stop
Timer 4 count source selection bits (Note 3)
00 : Timer 3 overflow
Timer 3, timer 4 function selection bit
0 : Normal mode
01 : f(XIN) divided by 16 or
f(XCIN) divided by 16
1 : PWM mode
10 : Timer 1 overflow or timer 2 overflow
11 : P33/CNTR1 external clock
Timer 4 pulse width measuring mode
selection bit
b7
b0
Timer 12 mode register (T12M)
(Address 00F816
)
0 : Timer mode
1 : Pulse width measuring mode
Timer 1 count stop bit
0 : Count start
1 : Count stop
Timer 1 count source selection bit
0 : Internal clock (Note 1)
P1
0 : P1
3
/T
1
port output selection bit
port output
3
1 : Timer 4 overflow divided by 2
or PWM output
1 : P3
Timer 1 internal clock source
selection bit (Note 2)
0 : f(XIN) divided by 16 or
f(XCIN) divided by 16
2/CNTR0 external clock
1 : f(XCIN
P1 /T port output selection bit
0 : P1 port output
)
2
0
2
1 : Timer 1 overflow divided by 2
Timer 2 count stop bit
0 : Count start
1 : Count stop
Timer 2 count source selection bit
0 : Internal clock
1 : Timer 1 overflow
Timer 2 internal clock source
selection bits (Note 3)
00 : f(XIN) divided by 16 or
f(XCIN) divided by 16
01 : f(XIN) divided by 64 or
f(XCIN) divided by 64
10 : f(XIN) divided by 128 or
f(XCIN) divided by 128
11 : f(XIN) divided by 256 or
f(XCIN) divided by 256
Notes 1 : f(XIN) divided by 16 in the 7470 group.
2 : The 7470 group does not use this bit (bit 2). Set this bit to “0”.
3 : Do not select f(XCIN) as the count source in the 7470 group.
Fig. 7 Structure of timer mode registers
16
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
tween f(XIN) and f(XCIN) is mode according to bit 7 in the CPU
mode register.
The block diagram of serial I/O is shown in Figure 8. In the serial
I/O mode, the receive ready signal (SRDY), synchronous input/out-
put clock (CLK), and the serial I/O (SOUT, SIN) pins are used as
P17, P16, P15, and P14, respectively.
Bits 3 and 4 decide whether parts of P1 will be used as a serial
I/O or not. When bit 3 is “1”, P16 becomes an I/O pin of the syn-
chronous clock. When an internal synchronous clock is selected,
the clock is output from P16. If the external synchronous clock is
selected, the clock is input to P16.
The serial I/O mode register (address 00DC16) is an 8-bit register.
Bit 2 of this register is used to select a synchronous clock source.
When this bit is “0”, an external clock from P16 is selected. When
this bit is “1”, an internal clock is selected.
And P15 will be a serial output. To use P14 as a serial input, set
the direction register bit which corresponds to P14, to “0”. For
more information on the direction register, refer to the I/O pin sec-
tion.
The internal clock can be selected from among the divide by 8, di-
vide by 16, divide by 32, divide by 512 frequency of the oscillator
frequency f(XIN) or f(XCIN). Do not select f(XCIN) as the count
source in the 7470 group. The divide ratio is selected according to
bit 0 and bit 1 in the serial I/O mode register, and selection be-
(Note 1)
XCIN
1/2
Counter
XIN
1/2
1/4
CM7
1/2
1/4
1/64
SARDY
SM1
SM0
SM2
SRDY
Sync. circuit
SM5
CLK input
Serial I/O
interrupt request
Serial I/O counter (3)
CLK output
SC
SM6
Byte counter (4)
Data bus
SIN
Serial I/O register (8)
SOUT
S
R
Q
(
Select gate : At reset, shaded side is connected.)
Note 1 : The 7470 group does not have XCIN input.
Fig. 8 Block diagram of serial I/O
17
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bit 4 determines if P17 is used as an output pin for the receive
ready signal (bit 4=“1”, SRDY) or used as a normal I/O pin (bit
4=“0”).
Internal Clock – The serial I/O counter is set to 7 when data is
stored in the serial I/O register. At each falling edge of the transfer
clock, serial data is output to P15. During the rising edge of this
clock, data can be input from P14 and the data in the serial I/O
register will be shifted 1 bit. Data is output starting with the LSB.
After the transfer clock has counted 8 times, the serial I/O register
will be empty and the transfer clock will remain at a high level. At
this time the interrupt request bit will be set.
When the P17 pin is used as the SRDY output pin, output signal
can be selected between SRDY signal and SARDY signal by using
bit 5 in the serial I/O mode register. The SRDY signal is driven “L”
by a signal written into the serial I/O register to inform that the de-
vice is ready to receive. Then, the SRDY signal is driven “H” on the
first falling edge of the transfer clock.
External Clock – If an external clock is used, the interrupt request
bit will be set after the transfer clock has counted 8 times but the
transfer clock will not stop. Due to this reason, the external clock
must be controlled from the outside.
The SARDY signal is driven “H” by a signal written into the serial
I/O register, and driven “L” on the last rising edge of the transfer
clock.
The function of serial I/O differs depending on the clock source;
external clock or internal clock.
Timing diagrams are shown in Figure 9.
Synchronous clock
Transfer clock
Serial I/O register write
signal
Serial I/O output
D0
D1
D2
D3
D4
D5
D6
D7
SOUT
Serial I/O input
SIN
Receive ready signal
SRDY
Interrupt request bit set
Fig. 9 Serial I/O timing
18
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O mode register (SM)
(Address 00DC16
)
Internal clock selection bits
00 : f(XIN) or f(XcIN) divided by 8
01 : f(XIN) or f(XcIN) divided by 16
10 : f(XIN) or f(XcIN) divided by 32
11 : f(XIN) or f(XcIN) divided by 512
Synchronous clock selection bit
0 : External clock
1 : Internal clock
Serial I/O port selection bit
0 : Normal I/O port
1 : SOUT, CLK pins
S
RDY signal output selection bit
0 : Normal I/O port
1 : SRDY signal output pin
S
RDY signal selection bit
0 : SRDY signal
1 : SARDY signal
Serial I/O byte specify mode selection bit
0 : Normal mode
1 : Byte specify mode
P15/SOUT, P17/SRDY output structure selection bit
0 : CMOS output
1 : N-channel open drain output
Note : Do not select f(XCIN) as the count source in the 7470 group.
Fig. 10 Structure of serial I/O mode register
BYTE SPECIFY MODE
The serial I/O has a byte specify mode that allows one specific
byte data to be selected for transmission or reception when serial
I/O circuits of two or more microcomputers are connected to send
or receive data through one bus. The data to be sent or received
can be specified by writing a value into the byte counter. The value
written in the byte counter is decremented by one each time eight
cycles of transfer clock are input. When the value in the byte
counter becomes “0”, serial transmission/reception is done by the
next eight cycles of transfer clock. When the value in the byte
counter is not “0”, the output on the SOUT pin is driven “H” by the
falling edge of the first transfer clock pulse to inhibit transmission/
reception.
Serial I/O interrupt requests are generated only when serial trans-
mission/reception is done after the value in the byte counter is
decremented to “0”. When the SARDY signal output is selected, the
SARDY signal is driven “L” by the last rising edge of the transfer
clock after the value in the byte counter is decremented to “0”.
Note that in the byte mode, an external clock must be used as the
sync. clock for the purpose of the mode.
19
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D conversion register (address 00DA16) contains informa-
tion on the results of conversion, so that it is possible to know the
results of conversion by reading the contents of this register.
The following explains the procedure to execute A-D conversion.
First, set values to bit 2 to bit 0 in the A-D control register to select
the pins that you want to execute A-D conversion. Next, clear the
A-D conversion end bit to “0”.
The A-D conversion uses an 8-bit successive comparison method.
Figure 11 shows a block diagram of the A-D conversion circuit.
Conversion is automatically carried out once started by the pro-
gram.
There are eight analog input pins which are shared with P20 to
P27 of port P2 (Only P20 to P23 4-bit for 7470 group. Which ana-
log inputs are to be A-D converted is specified by using bit 2 to bit
0 in the A-D control register (address 00D916). Pins for inputs to
be A-D converted must be set for input by setting the direction reg-
ister bit to “0”. Bit 3 in the A-D control register is an A-D conversion
end bit. This is “0” during A-D conversion; it is set to “1” when the
conversion is terminated. Therefore, it is possible to know whether
A-D conversion is terminated by checking this bit. Bit 4 in the A-D
control register is a VREF connection selection bit.
When the above is done, A-D conversion is initiated. The A-D con-
version is completed after an elapse of 50 machine cycles
(12.5 µs when f(XIN)= 8 MHz), the A-D conversion end bit is set to
“1”, and the interrupt request bit is set to “1”. The results of conver-
sion are contained in the A-D conversion register.
During A-D conversion, this bit must be set “1” for the ladder resis-
tor and VREF pin to be connected; after the A-D conversion is
terminated, this bit can be reset to “0” to separate the ladder resis-
tor from the VREF pin. In this way, power consumption in the ladder
resistor can be suppressed while no A-D conversion is performed.
Figure 13 shows the relationship between the contents of A-D
control register and the selected input pins.
Data bus
bit 4
bit 0
A-D control register
(Address 00D916
)
P20/IN0
A-D conversion completion
interrupt request
A-D control circuit
P21
P22
P23
P24
P25
P26
P27
/IN1
/IN2
/IN3
/IN4
/IN5
/IN6
/IN7
A-D conversion register
Comparator
(Address 00DA16
)
Switch tree
Ladder resistor
V
SS (Note 1)
V
REF
Notes 1 : AVSS for M37471M2/M4/M8/E4/E8-XXXFP
2 : 7470 group does not have P2 /IN to P2 /IN7 pins.
4
4
7
Fig. 11 A-D converter circuit
20
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
A-D control register
(Address 00D916
)
Analog input selection bits
000 : IN
001 : IN 1
0
010 : IN
011 : IN
100 : IN
101 : IN
110 : IN
111 : IN
2
3
4
5
6
7
(Note)
A-D conversion end bit
0 : Under conversion
1 : End conversion
VREF connection selection bit
0 : VREF is separated
1 : VREF is connected
Nothing is allocated
(The value is undefined at reading)
This bit must be set to “0”.
to IN7 in the 7470 group.
Note : Do not select IN
4
Fig. 12 Structure of A-D control register
21
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
KEY ON WAKE UP
The key on wake up interrupt is common with the INT1 interrupt.
When EG5 is set to “1”, the key on wake up function is selected.
However, key on wake up cannot be used in the normal operating
state. When the microcomputer is in the normal operating state,
both key on wake up and INT1 are invalid.
“Key on wake up” is one way of returning from a power down state
caused by the STP or WIT instruction. If any terminal of port P0
has “L” level applied, after bit 5 of the edge polarity selection regis-
ter (EG5) is set to “1”, an interrupt is generated and the
microcomputer is returned to the normal operating state. A key
matrix can be connected to port P0 and the microcomputer can be
returned to a normal state by pushing any key.
P33/CNTR1
Port P33 data read circuit
EG3
EG2
CNTR interrupt request signal
P32/CNTR0
EG4
Port P32 data read circuit
XCIN
(P50)
1/2
XIN
P30/INT0
1/2
CM7
Port P30 data read circuit
INT0 interrupt request signal
Noise
eliminating
circuit
EG0
P31/INT1
Port P31 data read circuit
EG5
Noise
eliminating
circuit
INT1 interrupt request signal
EG1
CPU halt state signal
Pull-up control
register
P07
Direction register
Pull-up control
register
P01
P00
(
Direction register
Port P0 data read circuit
Pull-up control
register
Direction register
Select gate: At reset, shaded side is connected.)
Note : The 7470 group does not have XCIN input.
Fig. 13 Block diagram of interrupt input and key on wake up circuit
22
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
The 7470/7471 group are reset according to the sequence shown
in Figure 15. It starts the program from the address formed by us-
ing the content of address FFFF16 as the high order address and
the content of the address FFFE16 as the low order address, when
the RESET pin is held at “L” level for no less than 2 µs while the
power voltage is in the recommended operating condition and
then returned to “H” level.
Address
0016
0016
0016
(1) Port P0 direction register
(2) Port P1 direction register
(3) Port P2 direction register
(4) Port P4 direction register
(5) P0 pull-up control register
(C116) …
(C316) …
(C516) …
(C916) …
(D016) …
0
0
0
0
0016
The internal initializations following reset are shown in Figure 16.
Example of reset circuit is Figure 14. Immediately after reset, timer
3 and timer 4 are connected, and counts the f(XIN) divided by 16.
At this time, FF16 is set to timer 3, and 0716 is set to timer 4. The
reset is cleared when timer 4 overflows.
(6) P1–P5 pull-up control register (Note 1)(D116) …
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
(7) Edge selection register
(8) A-D control register
(EG) (D416) …
(D916) …
0
0016
0016
0016
(9) Serial I/O mode register
(SM) (DC16) …
(10) Timer 12 mode register (T12M) (F816) …
(11) Timer 34 mode register (T34M) (F916) …
(12) Timer mode register 2
(13) CPU mode register
(TM2) (FA16) …
(CM) (FB16) …
(FC16) …
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(14) Interrupt request register 1
(15) Interrupt request register 2
(16) Interrupt control register 1
(17) Interrupt control register 2
(18) Program counter
7470/7471 group
(FD16) …
(FE16) …
0
0
0
RESET
VCC
(FF16) …
Contents of address
FFFF16
(PC
H
) …
) …
Contents of address
FFFE16
(PC
L
(19) Processor status register
(PS) …
1
Notes
1 : This address is allocated P1–P4 pull-up control register for
7470 group. Bit 6 is not used.
2 : Since the contents of both registers other than those listed
above (including timers and the serial I/O register) are
undefined at reset, it is necessary to set initial values.
Fig. 14 Example of reset circuit
Fig. 16 Internal state of microcomputer at reset
XIN
φ
RESET
Internal
RESET
SYNC
ADH,ADL
FFFF
?
?
00, S
FFFE
00, S-1 00, S-2
Address
Reset address
from the vector table
?
?
PCL
PS
ADL
ADH
PCH
Data
Notes 1 : Frequency relation of XIN and φ is f(XIN)=2·φ.
2 : The mark “?” means that the address is changeable
depending upon the previous state.
32768 counts of f(XIN)
Fig. 15 Timing diagram at reset
23
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
(4) Port P3
Port P3 is a 4-bit input port.
(5) Port P4
(1) Port P0
Port P0 is an 8-bit I/O port with CMOS outputs. As shown in
Figure 2, P0 can be accessed as memory through zero page
address 00C016. Port P0’s direction register allows each bit to
be programmed individually as input or output. The direction
register (zero page address 00C116) can be programmed as
input with “0”, or as output with “1”. When in the output mode,
the data to be output is latched to the port latch and output.
When data is read from the output port, the output pin level is
not read, only the latched data of the port latch is read. There-
fore, a previously output value can be read correctly even
though the output voltage level has been shifted up or down.
Port pins set as input are in the high impedance state so the
signal level can be read. When data is written into the input
port, the data is latched only to the output latch and the pin
still remains in the high impedance state. Following the ex-
ecution of STP or WIT instruction, key matrix with port P0 can
be used to generate the interrupt to bring the microcomputer
back in its normal state. When this port is selected for input,
pull-up transistor can be connected in units of 1-bit.
Port P4 is a 4-bit I/O port and has basically the same func-
tions as port P0. In the 7470 group, this port is P40 and P41,
a 2-bit I/O port. When this port is selected for input, pull-up
transistor can be connected in units of 4-bit .
(6) Port P5
Port P5 is a 4-bit input port and pull-up transistor can be con-
nected in units of 4-bit. P50 and P51 are shared with clock
generating circuit input/output pins.
The 7470 group does not have this port.
(7) INT0 pin (P30/INT0 pin)
This is an interrupt input pin, and is shared with port P30.
When “H” to “L” or “L” to “H” transition input is applied to this
pin, the INT0 interrupt request bit (bit 0 of address 00FD16) is
set to “1”.
(8) INT1 pin (P31/INT1 pin)
This is an interrupt input pin, and is shared with port P31.
When “H” to “L” or “L” to “H” transition input is applied to this
pin, the INT1 interrupt request bit (bit 1 of address 00FD16) is
set to “1”.
(2) Port P1
Port P1 has the same function as port P0. P12–P17 serve
dual functions, and the desired function can be selected by
the program. When this port is selected for input, pull-up tran-
sistor can be connected in units of 4-bit.
(9) Counter input CNTR0 pin (P32/CNTR0 pin)
This is a timer input pin, and is shared with port P32.
When this pin is selected to CNTR0 or CNTR1 interrupt input
pin and “H” to “L” or “L” to “H” transition input is applied to this
pin, the CNTR0 or CNTR1 interrupt request bit (bit 2 of ad-
dress 00FD16) is set to “1”.
(3) Port P2
Port P2 has the same function as port P0. In the 7470 group,
this port is P20–P23, a 4-bit I/O port. This port can also be
used as the analog voltage input pins. When this port is se-
lected for input, pull-up transistor can be connected in units of
4-bit.
(10) Counter input CNTR1 pin (P33/CNTR1 pin)
This is a timer input pin, and is shared with port P33.
When this pin is selected to CNTR0 or CNTR1 interrupt input
pin and “H” to “L” or “L” to “H” transition input is applied to this
pin, the CNTR0 or CNTR1 interrupt request bit (bit 2 of ad-
dress 00FD16) is set to “1”.
24
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0
Pull-up control
register
Tr1
Direction register
Port latch
Data bus
Port P0
Interrupt control circuit
Ports P10–P13
Pull-up control
register
Data bus
Data bus
Tr2
T34M7
Direction register
Port latch
Port P13
T1
Tr3
T12M3
Direction register
Port latch
Data bus
Port P12
T0
Tr4
Direction register
Port latch
Data bus
Port P11
Tr5
Direction register
Port latch
Data bus
Port P10
Tr1–Tr5 are pull-up transistors
Fig. 17 Block diagram of ports P0, P10–P13
25
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Ports P14–P17
SM7
Tr6
SM4
Direction register
Port latch
Data bus
Port P17
SRDY
SM2
SM3
Tr7
Direction register
Port latch
Data bus
Port P16
CLK output
CLK input
SM3
Tr8
SM7
Direction register
Port latch
Data bus
Port P15
SOUT
Tr9
Direction register
Port latch
Data bus
Data bus
Port P14
SIN
Pull-up control
register
Tr6–Tr9 are pull-up transistors
Fig. 18 Block diagram of ports P14–P17
26
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P2
* : Control in units of 4-bit
Data bus
Pull-up control register*
Tr10
Direction register
Port latch
Data bus
Port P2
Multi-
plexer
A-D conversion circuit
Port P3
Data bus
Port P3
INT0, INT1
CNTR0, CNTR1
Port P4
* : Control in units of 4-bit (Control in units of 2-bit for 7470 group)
Data bus
Pull-up control register*
Tr11
Direction register
Port latch
Data bus
Port P4
Tr10–Tr11 are pull-up transistors
Fig. 19 Block diagram of ports P2–P4
27
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P5
Pull-up
control register
Data bus
Tr12
Data bus
Port P53
Tr13
Data bus
Port P52
CM4
Tr14
Data bus
Port P51
CM4
CM4
XCIN
CM4
Tr15
Data bus
Port P50
Tr12–Tr15 are pull-up transistors
Note : 7470 group does not have this port.
Fig. 20 Block diagram of port P5
28
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 7470 group has one internal clock generating circuit and 7471
group has two internal clock generating circuits.
M37470M2-XXXSP
Figure 25 shows a block diagram of the clock generating circuit.
Normally, the frequency applied to the clock input pin XIN divided
by two is used as the internal clock φ. Bit 7 of CPU mode register
can be used to switch the internal clock φ to 1/2 the frequency ap-
plied to the clock input pin XCIN in the 7471 group.
XIN
XOUT
Rd
CIN
COUT
Figure 21, 22 show a circuit example using a ceramic resonator
(or a quartz-crystal oscillator). Use the manufacturer’s recom-
mended values for constants such as capacitance which will differ
depending on each oscillator. When using an external clock signal,
input from the XIN(XCIN) pin and leave the XOUT(XCOUT) pin open.
A circuit example is shown in Figure 23, 24.
Fig. 21 Example of ceramic resonator circuit (7470 group)
The 7470/7471 group has two low power dissipation modes; stop
and wait. The microcomputer enters a stop mode when the STP
instruction is executed. The oscillator (both XIN clock and XCIN
clock) stops with the internal clock φ held at “H” level. In this case
timer 3 and timer 4 are forcibly connected and FF16 is automati-
cally set in timer 3 and 0716 in timer 4.
M37471M2-XXXSP/FP
XOUT
XCOUT
XIN
XCIN
Although oscillation is restarted when an external interrupt is ac-
cepted, the internal clock φ remains in the “H” state until timer 4
overflows. In other words, the internal clock φ is not supplied until
timer 4 overflows. This is because when a ceramic or similar other
oscillator is used, a finite time is required until stable oscillation is
obtained after restart.
Rd
COUT
Rd
CCOUT
CIN
CCIN
The microcomputer enters an wait mode when the WIT instruction
is executed. The internal clock φ stops at “H” level, but the oscilla-
tor does not stop. φ is re-supplied (wait mode release) when the
microcomputer receives an interrupt.
Fig. 22 Example of ceramic resonator circuit (7471 group)
Instructions can be executed immediately because the oscillator is
not stopped. The interrupt enable bit of the interrupt used to reset
the wait mode or the stop mode must be set to “1” before execut-
ing the WIT or the STP instruction.
M37470M2-XXXSP
XIN
XOUT
Open
Low power dissipation operation is also achieved when the XIN
clock is stopped and the internal clock φ is generated from the
XCIN clock (30 µA typ. at f(XCIN) = 32 kHz). This operation is only
7471 group. XIN clock oscillation is stopped when the bit 6 of CPU
mode register is set and restarted when it is cleared. However, the
wait time until the oscillation stabilizes must be generated with a
program when restarting. Figure 27 shows the transition of states
for the system clock.
VCC
VSS
External oscillating circuit
Fig. 23 External clock input circuit (7470 group)
M37471M2-XXXSP/FP
XIN
XOUT
XCOUT
XCIN
Open
Open
External oscillating External oscillating circuit or
circuit external pulse
VCC
VSS
VCC
VSS
Fig. 24 External clock input circuit (7471 group)
29
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
CIN
XCOUT
X
IN
XOUT
1/2
T34M
0
(Note 1)
1/8
Timer 3
Timer 4
1/2
CM
7
T34M
T34M
1
2
CM
6
7
CM
Internal clock φ
S
S
R
Q
Q
Q
S
R
Reset
WIT
instruction
STP
instruction
R
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Select gate : At reset, shaded
side is connected
Notes 1 : Refer to Timer 3 of [Figure 6 Block diagram of timer 1 through 4]
2 : 7470 group does not have XCIN input and XCOUT output.
Fig. 25 Block diagram of clock generating circuit
b7
b0
CPU mode register
(Address 00FB16)
These bits must always be set to “0”.
Stack page selection bit (Note 1)
0 : In page 0 area
1 : In page 1 area
Nothing is allocated (The value is undefined at reading)
S50, P51/XCIN, XCOUT selection bit (Note 2)
0 : P50, P51
1 : XCIN, XCOUT
XCOUT drive capacity selection bit (Note 2)
0 : Low
1 : High
Clock (XIN-XOUT) stop bit (Note 2)
0 : Oscillates
1 : Stops
Internal system clock selection bit (Note 2)
0 : XIN-XOUT selected (normal mode)
1 : XCIN-XCOUT selected (low-speed mode)
Notes 1 : In the M37470M2, M37470M4/E4, M37471M2, M37471M4/E4, set this bit to “0”.
2 : In the 7470 group, set this bit to “0”.
Fig. 26 Structure of CPU mode register
30
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
CM
4
5
6
7
= 0
= 0
= 0
= 0
CM
CM
CM
f(XIN) oscillation
f(XCIN) stop
φ stop
f(XIN) oscillation
f(XCIN) stop
WIT instruction
Interrupt
STP instruction
f(XIN) stop
f(XCIN) stop
P5
0, P51 input
φ stop
Timer operation
φ = f(XIN)/2
Interrupt (Note 1)
CM
5
4
= 1
= 1
CM
CM
4
= 0
(Note 2)
f(XIN) oscillation
f(XCIN) oscillation
φ stop
WIT instruction
Interrupt
STP instruction
f(XIN) stop
f(XIN) oscillation
f(XCIN) oscillation
φ = f(XIN)/2
f(XCIN) stop
φ stop
Timer operation
Interrupt (Note 1)
(CM
CM
5
= 0)
CM7 = 0
7
= 1
CM5 = 1
f(XIN) oscillation
f(XCIN) oscillation
φ stop
WIT instruction
Interrupt
STP instruction
f(XIN) stop
f(XIN) oscillation
f(XCIN) oscillation
φ = f(XCIN)/2
f(XCIN) stop
φ stop
Timer operation
Interrupt (Note 1)
CM
6 = 0
CM6 = 1
(Note 2)
CM5 = 1
f(XIN) stop
WIT instruction
Interrupt
STP instruction
f(XIN) stop
f(XCIN) stop
φ stop
f(XIN) stop
f(XCIN) oscillation
φ stop
f(XCIN) oscillation
φ = f(XCIN)/2
Timer operation
Interrupt (Note 1)
Notes 1 : Latency time is automatically generated upon release from the STP instruction due to the connections of timer 3
and 4.
2 : When the system clock is switched over by restarting clock oscillation, a certain wait time required for oscillation
to stabilize must be inserted by the program.
Fig. 27 Transition of states for the system clock
31
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
<An example of flow for system>
Power on reset
↓
Clock X oscillation
↓
Internal system clock start (X→1/2→ φ)
↓
Program start from RESET vector
Normal program ← Operating at f(XIN)
Clock for clock function XC oscillation start (CM4 = 1, CM5 = 1)
↓
Latency time for oscillation to stabilize (by program) ← Operating at f(XIN)
↓
XC clock power down (CM5 : 1→0)
↓
Internal clock φ source switching X→XC (CM7 : 0→1)
↓
Clock X halt (XC in operation) (CM6 = 1)
↓
Internal clock halt (WIT instruction)
↓
Timer 4 (clock count) overflow
↓
Internal clock operation start (WIT instruction released)
Clock processing routine
← Operating at f(XCIN)
Internal clock halt (WIT instruction)
Interrupts from INT0, INT1, CNTR0/CNTR1, timer 1, timer 2, timer 3, timer 4, serial I/O, key on wake up
↓
Internal clock operation start (WIT instruction released)
↓
Program start from interrupt vector
↓
Clock X oscillation start (CM6 = 0)
↓
Latency time for oscillation to stabilize (by program)
← Operating at f(XCIN)
↓
Internal clock φ source switching (XC→X) (CM7 : 1→0)
Normal program → Operating at f(XIN)
32
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
STP instruction preparation (pushing registers)
↓
Timer 3, timer 4 interrupt disable
↓
X/16 or XC/16 selected for timer 3 count source; timer 3 overflow selected for timer 4 count source
↓
Timer 3, timer 4 start counting
↓
Values set to timer 3, timer 4 that do not cause timer 4 to overflow until STP instruction is executed
↓
Interrupt for return from STP enabled
↓
Timer 4 interrupt request bit cleared
↓
Clock X and clock for clock function XC halt (STP instruction)
RAM backup status
Interrupts from INT0, INT1, CNTR0/CNTR1, timer 1, timer 2, serial I/O, key on wake up
↓
Clock X and clock for clock function XC oscillation start
↓
Timer 4 overflow (X/16 or XC/16→timer 3→timer 4)
↓
Internal system clock start
↓
Program start from interrupt vector
Normal program
33
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
BUILT-IN PROM TYPE MICROCOMPUTERS
PIN DESCRIPTION
Input/
Output
Pin
Mode
Name
Functions
VCC,VSS
Single-chip Power source
/EPROM
Power source voltage inputs 2.7 to 5.5 V to VCC and 0 V to VSS.
AVSS
Single-chip Analog power
Ground level input pin for A-D converter. Same voltage as VSS is applied.
(Note 1)
/EPROM
source
RESET
Single-chip Reset input
Input To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more
(under normal VCC conditions).
EPROM
Reset input
Connect to VSS.
XIN
Single-chip Clock input
/EPROM
Input These are I/O pins of internal clock generating circuit for main clock. To control
generating frequency, an external ceramic or a quartz-crystal oscillator is con-
nected between the XIN and XOUT pins. If an external clock is used, the clock
Output source should be connected the XIN pin and the XOUT pin should be left open.
Feedback resistor is connected between XIN and XOUT.
XOUT
VREF
Clock output
Single-chip Reference
voltage input
Input Reference voltage input pin for the A-D converter.
EPROM
Select mode
Input
I/O
VREF works as CE input.
P00–P07
P10–P17
Single-chip I/O port P0
Port P0 is an 8-bit I/O port. The output structure is CMOS output. When this port
is selected for input, pull-up transistor can be connected in units of 1-bit and a key
on wake up function is provided.
EPROM
Data input/output D
0–D
7
I/O
I/O
Port P0 works as an 8-bit data bus (D0–D7).
Single-chip I/O port P1
Port P1 is an 8-bit I/O port. The output structure is CMOS output. When this port
is selected for input, pull-up transistor can be connected in units of 4-bit. P12, P13
are in common with timer output pins T0, T1. P14, P15, P16, P17 are in common
with serial I/O pins SIN, SOUT, CLK, SRDY, respectively. The output structure of
SOUT and SRDY can be changed to N-channel open drain output.
EPROM
Address input A
4–A10
Input
I/O
P11–P17 works as the 7-bit address input (A4–A10). P10 must be opened.
P20–P27
(Note 2)
Single-chip I/O port P2
Port P2 is an 8-bit input port. This port is in common with analog input pins IN0–IN7.
EPROM
Address input
A0–A3
Input P20–P23 works as the lower 4-bit address input (A0–A3).
P24–P27 must be opened.
P30–P33
Single-chip Input port P3
Input
Input
Port P3 is a 4-bit input port. P3
0
, P3
1
are in common with external interrupt input
, CNTR
pins INT , INT and P3 , P3 are in common with timer input pins CNTR
0
1
2
3
0
1.
EPROM
Address input
A11, A12
P30, P31 works as the 2-bit address input (A11, A12).
P32 works as OE input. Connect to P33 to VPP when programming or verifying.
Select mode
VPP input
P40–P43
(Note 3)
Single-chip I/O port P4
I/O
Port P4 is a 4-bit I/O port. The output structure is CMOS output. When this port is
selected for input, pull-up transistor can be connected in units of 4-bit.
EPROM
Address input
A13, A14
Input
P40, P41 works as the higher 2-bit address input (A13, A14).
P42, P43 must be opened.
P50–P53
(Note 4)
Single-chip Input port P5
Input Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4-
bit. P50, P51 are in common with input/output pins of clock for clock function XCIN,
XCOUT. When P50, P51 are used as XCIN, XCOUT, connect a ceramic or a quartz-
crystal oscillator between XCIN and XCOUT. If an external clock input is used, con-
nect the clock input to the XCIN pin and open the XCOUT pin. Feedback resistor is
connected between XCIN and XCOUT pins.
EPROM
Open.
Notes 1 : AVSS for M37471M2/M4/M8/E4/E8-XXXFP.
2 : Only P20–P23 (IN0–IN3) 4-bit for the 7470 group.
3 : Only P40 and P41 2-bit for the 7470 group.
4 : This port is not included in the 7470 group.
34
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2. Pin function in EPROM mode
M37470E4/E8, M37471E4/E8
EPROM MODE
The M37470E4/E8, M37471E4/E8 feature an EPROM mode in ad-
dition to its normal modes. When the RESET signal level is low
(“L”), the chip automatically enters the EPROM mode. Table 2 lists
the correspondence between pins and Figure 30 to 32 give the pin
connection in the EPROM mode. When in the EPROM mode,
ports P0, P11–P17, P20–P23, P3, P40, P41, VREF are used for the
PROM (equivalent to the M5L27256). When in this mode, the built-
in PROM can be written to or read from using these pins in the
same way as with the M5L27256. The oscillator should be con-
nected to the XIN and XOUT pins, or external clock should be
connected to the XIN pin.
M5L27256
VCC
VCC
VPP
VSS
VCC
P33
VSS
VPP
VSS
Ports P11–P17, P20–P23,
P30, P31, P40, P41
Address input
A0–A14
Data I/O
CE
Port P0
VREF
P32
D0–D7
CE
OE
OE
1
42
41
40
P52
P53
2
3
4
5
6
7
8
9
A10
A9
P07
D7
D6
P17/SRDY
P16/CLK
P15/SOUT
P14/SIN
P06
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A8
P05
D5
D4
P04
A7
A6
A5
A4
P03
T1
T0
P13/
P12/
D3
D2
D1
D0
P02
P11
P10
P01
P00
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
10
11
12
13
14
15
16
17
18
P43
P42
P41
A14
P40
A13
VPP
OE
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
P51/XCOUT
P50/XCIN
VCC
A3
A2
A1
A12
A11
A0
CE
XIN
19
20
21
VSS
XOUT
VSS
VSS
VCC
: Same functions as M5L27256
Fig. 28 Pin connection in EPROM mode
35
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
45
46
47
28
RESET
NC
NC
D
D
D
5
6
7
27
26
P0
5
P5
1/XCOUT
P0
P0
P5
6
48
49
25
24
23
7
P5
0/XCIN
NC
2
50
V
CC
SS
M37471E4-XXXFP
M37471E8-XXXFP
VCC
NC
51
52
22
21
20
19
VSS
V
V
SS
V
SS
AVSS
NC
P5
3
53
54
A
10
P1
P1
P1
7
/SRDY
/SCLK
XOUT
A
A
9
8
6
55
56
18
17
XIN
5
/SOUT
NC
NC
: Same functions as M5L27256
Fig. 29 Pin connection in EPROM mode
1
32
31
P07
P06
P05
P04
P03
P02
P01
P00
P41
P40
D7
D6
P17/SRDY
P16/CLK
P15/SOUT
P14/SIN
A10
A9
2
3
30
29
28
27
26
25
24
23
D5
D4
A8
A7
A6
A5
A4
4
5
P13/ T1
D3
D2
6
P12/
T0
7
D1
P11
P10
8
D0
9
A14
A13
VPP
A3
A2
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
10
22
11
12
13
14
15
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
A1
A0
21
20
19
18
OE
A12
CE
A11
XIN
XOUT
VSS
VSS
16
17
VCC
VCC
VSS
: Same functions as M5L27256
Fig. 30 Pin connection in EPROM mode
36
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PROM READING AND WRITING
Reading
To read the PROM, set the CE and OE pins to “L” level. Input the
address of the data (A0–A14) to be read and the data will be out-
put to the I/O pins (D0–D7). The data I/O pins will be floating when
either the CE or OE pin is in the “H” state.
NOTES ON HANDLING
(1) Sunlight and fluorescent light contain wave lengths capable of
erasing data. For ceramic package types, cover the transpar-
ent window with a seal (provided) when this chip is in use.
However, this seal must not contact the lead pins.
(2) Before erasing, the glass should be cleaned and stains such
as finger prints should be removed thoroughly. If these stains
are not removed, complete erasure of the data could be pre-
vented.
Writing
To write to the PROM, set the OE pin to “H” level. The CPU will en-
ter the program mode when VPP is applied to the VPP pin. The
address to be written to is selected with pins A0–A14, and the
data to be written is input to pins D0–D7. Set the CE pin to “L” level
to begin writing.
(3) Since a high voltage (12.5 V) is used to write data, care should
be taken when turning on the PROM programmer’s power.
(4) For the programmable microcomputer (shipped in One Time
PROM version), Mitsubishi does not perform PROM write test
and screening in the assembly process and following pro-
cesses. To improve reliability after write, performing write and
test according to the flow below before use is recommended.
Notes on Writing
• M37470E4, M37471E4
When using a PROM programmer, the address range should be
between 600016 and 7FFF16. Addresses 000016 to 5FFF16 can-
not be written to or read from correctly.
Writing with PROM programmer
• M37470E8, M37471E8
When using a PROM programmer, the address range should be
between 400016 and 7FFF16. When data is written between ad-
dresses 000016 and 7FFF16, fill addresses 000016 to 3FFF16
with FF16.
Screening (Caution) (Leave at 150°C for 40 hours)
Verify test with PROM programmer
Function check in target device
Erasing
Data can only erased on the M37471E8SS ceramic package,
which includes a window. To erase data on this chip, use an ultra-
violet light source with a 2537 Angstrom wave length. The
2
minimum radiation power necessary for erasing is 15W·s/cm .
Caution : Since the screening temperature is higher than storage
temperature, never expose to 150°C exceeding 100
hours.
Table 3. I/O signal in each mode
Pin
CE
OE
VPP
VCC
Data I/O
Mode
Read-out
VIL
VIL
VIL
VIH
VIH
VIL
VIH
VIH
VIL
VIH
VCC
VCC
VPP
VPP
VPP
VCC
VCC
VCC
VCC
VCC
Output
Floating
Input
Output disable
Programming
Programming verify
Program disable
Output
Floating
Note : VIL and VIH indicate a “L” and “H” input voltage, respectively.
37
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PROGRAMMING NOTES
(1) The frequency ratio of the timer is 1/(n+1).
(2) The contents of the interrupt request bits are not modified im-
mediately after they have been written. After writing to an
interrupt request register, execute at least one instruction be-
fore executing a BBC or BBS instruction.
(3) To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. Only the ADC
and SBC instruction yield proper decimal results. After execut-
ing an ADC or SBC instruction, execute at least one
instruction before executing a SEC, CLC, or CLD instruction.
(4) An NOP instruction must be used after the execution of a PLP
instruction.
(5) Do not execute the STP instruction during A-D conversion.
(6) In the M37470, set bit 0, bit 1, and bit 3–bit 7 to “0” of the CPU
mode register.
(7) Multiply/Divide instructions
The index X mode (T) and the decimal mode (D) flag do not
affect the MUL and DIV instruction.
The execution of these instructions does not modify the con-
tents of the processor status register.
DATA REQUIRED FOR MASK ORDERING
Please send the following data for mask orders.
(1) mask ROM confirmation form
(2) mark specification form
(3) ROM data ......................................................... EPROM 3 sets
38
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37470M2/M4/M8-XXXSP, M37470E4/E8-XXXSP
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Power source voltage
Conditions
Ratings
–0.3 to 7
Unit
V
VCC
VI
VI
Input voltage XIN
–0.3 to VCC +0.3
V
All voltages are based on VSS.
Output transistors are cut off.
Input voltage P00–P07, P10–P17, P20–P23,
–0.3 to VCC +0.3
–0.3 to VCC +0.3
V
V
P30–P33, P40, P41, VREF,
RESET
Output voltage P00–P07, P10–P17, P20–P23,
P40, P41, XOUT
VO
Pd
Power dissipation
1000
mW
°C
Ta = 25°C
Topr
Tstg
Operating temperature
Storage temperature
–20 to 85
–40 to 150
°C
RECOMMENDED OPERATING CONDITIONS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C unless otherwise noted)
Limits
Symbol
Parameter
Unit
V
Min.
2.7
Typ.
Max.
4.5
f(XIN) = 2.2VCC–2.0 MHz
f(XIN) = 8 MHz
VCC
Power source voltage
Power source voltage
4.5
5
0
5.5
VSS
V
V
VIH
“H” input voltage P00–P07, P10–P17, P30–P33, RESET, XIN
“H” input voltage P20–P23, P40, P41
0.8VCC
VCC
VIH
0.7VCC
VCC
V
VIL
“L” input voltage P00–P07, P10–P17, P30–P33
“L” input voltage P20–P23, P40, P41
0
0
0
0
0.2VCC
V
VIL
0.25VCC
V
VIL
“L” input voltage RESET
0.12VCC
V
VIL
“L” input voltage XIN
0.16VCC
V
IOH(sum)
IOH(sum)
IOL(sum)
IOL(sum)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
“H” sum output current P00–P07, P40, P41
mA
mA
mA
mA
mA
mA
mA
mA
–30
“H” sum output current P10–P17, P20–P23
–30
“L” sum output current P00–P07, P40, P41
60
“L” sum output current P10–P17, P20–P23
60
“H” peak output current P00–P07, P10–P17, P20–P23, P40, P41
“L” peak output current P00–P07, P10–P17, P20–P23, P40, P41
“H” average output current P00–P07, P10–P17, P20–P23, P40, P41 (Note 2)
“L” average output current P00–P07, P10–P17, P20–P23, P40, P41 (Note 2)
–10
20
–5
10
f(XIN) = 4 MHz
1
Timer input frequency CNTR0 (P32),
CNTR1 (P33) (Note 1)
f(CNTR)
f(CLK)
f(XIN)
MHz
MHz
MHz
f(XIN) = 8 MHz
2
f(XIN) = 4 MHz
1
Serial I/O clock input frequency
SCLK (P16) (Note 1)
f(XIN) = 8 MHz
2
2.2VCC – 2.0
8
VCC = 2.7 to 4.5 V
Clock input oscillation frequency (Note 1)
VCC = 4.5 to 5.5 V
Notes 1 : Oscillation frequency is at 50% duty cycle.
2 : The average output current IOH (avg) and IOL (avg) are the average value during a 100 ms.
39
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37470M2/M4/M8-XXXSP, M37470E4/E8-XXXSP
ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test Conditions
Unit
V
Min.
Typ.
Max.
VCC = 5 V, IOH = –5 mA
3
“H” output voltage P00–P07,
P10–P17, P20–P23, P40, P41
VOH
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
VCC = 3 V, IOL = 3 mA
VCC = 5 V
2
2
“L” output voltage P00–P07,
P10–P17, P20–P23, P40, P41
VOL
V
1
0.5
Hysteresis P00 – P07,
P30 – P33
VT + – VT–
VT + – VT–
VT + – VT–
V
VCC = 3 V
0.3
0.5
0.3
0.5
0.3
VCC = 5 V
Hysteresis RESET
Hysteresis P16/CLK
V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
use as CLK input
V
–5
–3
–1.0
–0.35
–5
–3
–5
–3
–1.0
–0.35
–5
–3
5
VI = 0 V,
µA
mA
µA
µA
mA
µA
µA
µA
µA
µA
not use pull-up transistor
“L” input current P00–P07,
P10–P17, P30–P32, P40–P41
IIL
IIL
IIL
–0.25
–0.08
–0.5
VI = 0 V,
use pull-up transistor
–0.18
VI = 0 V
“L” input current P33
VI = 0 V, not use as analog input,
not use pull-up transistor
“L” input current P20–P23
–0.25
–0.08
–0.5
VI = 0 V, not use as analog input,
use pull-up transistor
–0.18
VI = 0 V
IIL
“L” input current RESET, XIN
(XIN is at stop mode)
“H” input current P00–P07,
P10–P17, P30–P32, P40, P41
VI = VCC,
IIH
IIH
IIH
IIH
not use pull-up transistor
3
5
“H” input current P33
VI = VCC
3
5
VI = VCC, not use as analog input,
not use pull-up transistor
“H” input current P20–P23
“H” input current RESET, XIN
3
5
VI = VCC,
(XIN is at stop mode)
3
f(XIN)=8 MHz
At normal
14
7
7
3.5
1.8
7.5
4
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
mode, A-D
conversion is
not executed.
mA
mA
mA
f(XIN)=4 MHz
f(XIN)=8 MHz
f(XIN)=4 MHz
f(XIN)=8 MHz
f(XIN)=4 MHz
3.6
15
8
At normal
mode, A-D
conversion is
executed.
ICC
Power source current
4
2
4
2
At wait mode.
2
1
VCC = 3 V
Ta = 25°C
Ta = 85°C
1
0.5
0.1
1
1
At stop mode,
µA
f(XIN)=0, VCC=5 V
Stop all oscillation
10
V
2
5.5
VRAM
RAM retention voltage
40
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER CHARACTERISTICS
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, f(XIN)=4 MHz, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
–
–
–
bits
LSB
LSB
Resolution
8
Non-linearity error
±2
±0.9
2
Differential non-linearity error
VCC = VREF = 5.12 V, IOL(sum) = 0 mA
VCC = VREF = 3.072 V, IOL(sum) = 0 mA
VCC = VREF = 5.12 V
VOT
Zero transition error
Full-scale transition error
Conversion time
LSB
LSB
µs
3
4
VFST
7
VCC = VREF = 3.072 V
25
12.5
VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz
VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz
tCONV
Reference input voltage
Ladder resistance value
Analog input voltage
VCC
V
kΩ
V
VREF
0.5VCC
10
RLADDER
VIA
5
2
0
VREF
41
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37471M2/M4/M8-XXXSP/FP, M37471E4/E8-XXXSP/FP, M37471E8SS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Power source voltage
Input voltage XIN
nput voltage P00–P07, P10–P17, P20–P27,
Conditions
Ratings
–0.3 to 7
Unit
V
VCC
VI
VI
–0.3 to VCC +0.3
V
All voltages are based on VSS.
Output transistors are cut off.
I
–0.3 to VCC +0.3
–0.3 to VCC +0.3
V
V
P3 –P3 , P4 –P4 , P5 –P53, VREF,
0
3
0
3
0
RESET
Output voltage P00–P07, P10–P17,
P20–P27, P40–P43, XOUT
VO
Pd
Power dissipation
1000 (Note 1)
–20 to 85
mW
°C
Ta = 25°C
Topr
Tstg
Operating temperature
Storage temperature
–40 to 150
°C
Note 1 : 500 mW for M37471M2/M4/M8-XXXFP.
RECOMMENDED OPERATING CONDITIONS (VCC = 2.7 to 5.5 V, VSS =AVSS = 0 V, Ta = –20 to 85°C unless otherwise noted)
Limits
Symbol
Parameter
Unit
V
Min.
2.7
Typ.
Max.
4.5
f(XIN) = 2.2VCC – 2.0 MHz
f(XIN) = 8 MHz
Power source voltage
VCC
4.5
5
0
0
5.5
Power source voltage
VSS
V
V
Analog power source voltage
AVSS
VIH
“H” input voltage P00–P07, P10–P17, P30–P33, RESET, XIN
“H” input voltage P20–P27, P40–P43, P50–P53 (Note 1)
“L” input voltage P00–P07, P10–P17, P30–P33
“L” input voltage P20–P27, P40–P43, P50–P53 (Note 1)
“L” input voltage RESET
0.8VCC
VCC
V
VIH
0.7VCC
VCC
V
VIL
0
0
0
0
0.2VCC
V
VIL
0.25VCC
V
VIL
0.12VCC
V
“L” input voltage XIN
VIL
0.16VCC
V
“H” sum output current P00–P07, P40–P43
IOH(sum)
IOH(sum)
IOL(sum)
IOL(sum)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
mA
mA
mA
mA
mA
mA
mA
mA
– 30
“H” sum output current P10–P17, P20–P27
– 30
“L” sum output current P00–P07, P40–P43
60
“L” sum output current P10–P17, P20–P27
60
“H” peak output current P00–P07, P10–P17, P20–P27, P40–P43
“L” peak output current P00–P07, P10–P17, P20–P27, P40–P43
“H” average output current P00–P07, P10–P17, P20–P27, P40–P43 (Note 2)
“L” average output current P00–P07, P10–P17, P20–P27, P40–P43 (Note 2)
– 10
20
– 5
10
f(XIN) = 4 MHz
1
Timer input frequency CNTR0 (P32),
CNTR1 (P33) (Note 3)
f(CNTR)
f(CLK)
MHz
MHz
f(XIN) = 8 MHz
2
f(XIN) = 4 MHz
1
Serial I/O clock input frequency
SCLK (P16) (Note 3)
f(XIN) = 8 MHz
2
VCC = 2.7 to 4.5 V
Main clock input oscillation frequency (Note 3)
VCC = 4.5 to 5.5 V
2.2VCC – 2.0
f(XIN)
MHz
kHz
8
f(XCIN)
Sub-clock input oscillation frequency for clock function (Note 3, 4)
32
50
Notes 1 : It is except to use P50 as XCIN.
2 : The average output current IOH (avg) and IOL (avg) are the average value during a 100 ms.
3 : Oscillation frequency is at 50% duty cycle.
4 : When used in the low-speed mode, the clock oscillation frequency for clock function should be f(XCIN) < f(XIN) / 3.
42
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37471M2/M4/M8-XXXSP/FP, M37471E4/E8-XXXSP/FP, M37471E8SS
ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test Conditions
Unit
V
Min.
Typ.
Max.
“H” output voltage P00–P07,
P10–P17, P20–P27, P40–P43
“L” output voltage P00–P07,
P10–P17, P20–P27, P40–P43
Hysteresis P00–P07,
P30–P33
VCC = 5 V, IOH = –5 mA
3
VOH
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
VCC = 3 V, IOL = 3 mA
VCC = 5 V
2
2
VOL
V
1
0.5
0.3
0.5
0.3
0.5
0.3
VT + – VT–
VT + – VT–
VT + – VT–
V
VCC = 3 V
VCC = 5 V
Hysteresis RESET
Hysteresis P16/CLK
V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
used as CLK input
V
–5
–3
–1.0
–0.35
–5
–3
–5
–3
–1.0
–0.35
–5
–3
5
VI = 0 V,
“L” input current
µA
mA
µA
µA
mA
µA
µA
µA
µA
µA
not use pull-up transistor
IIL
IIL
IIL
P00–P07, P10–P17, P30–P32,
P40–P43, P50–P53
–0.25
–0.08
–0.5
VI = 0 V,
use pull-up transistor
–0.18
“L” input current P33
VI = 0 V
VI = 0 V, not use as analog input,
not use pull-up transistor
“L” input current P20–P27
“L” input current RESET, XIN
–0.25
–0.08
–0.5
VI = 0 V, not use as analog input,
use pull-up transistor
–0.18
VI = 0 V
IIL
(XIN is at stop mode)
“H” input current P0
0–P0
7
, P1
0
–P1
7,
VI = VCC,
IIH
IIH
IIH
IIH
not use pull-up transistor
P3 –P3 , P4
0
2
0–P4
3
, P5
0
–P5
3
3
5
VI = VCC
“H” input current P33
3
5
VI = VCC, not use as analog input,
not use pull-up transistor
“H” input current P20–P27
3
5
VI = VCC,
“H” input current RESET, XIN
(XIN is at stop mode)
3
At normal
f(XIN)=8 MHz
7
3.5
1.8
7.5
4
14
7
VCC = 5 V
VCC = 3 V
VCC = 5 V
mode, A-D
conversion is
not executed.
mA
f(XIN)=4 MHz
f(XIN)=8 MHz
3.6
15
8
At normal
mode, A-D
conversion is
executed.
mA
µA
f(XIN)=4 MHz
2
4
VCC = 3 V
VCC = 5 V
VCC = 3 V
At low-speed mode, T
f(XCIN)=32 kHz, XCOUT drive capacity
is low, A-D conversion is not executed.
a
=25°C, f(XIN)=0,
30
15
2
80
40
4
ICC
Power source current
f(XIN)=8 MHz
VCC = 5 V
At wait mode.
f(XIN)=4 MHz
mA
1
2
0.5
3
1
VCC = 3 V
VCC = 5 V
VCC = 3 V
Ta = 25°C
Ta = 85°C
At wait mode, XIN = 0 Hz, XCIN
= 32 kHz, XCOUT is low-power
mode, Ta=25°C
12
8
2
µA
0.1
1
1
Stop all oscillation
VCC = 5 V
10
Stop all oscillation
V
VRAM
RAM retention voltage
2
43
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER CHARACTERISTICS
(VCC = 2.7 to 5.5 V, VSS =AVSS= 0 V, Ta = –20 to 85°C, f(XIN) = 4 MHz, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
–
–
–
bits
LSB
LSB
Resolution
8
Non-linearity error
±2
±0.9
2
Differential non-linearity error
VCC = VREF = 5.12 V, IOL(sum) = 0 mA
VCC = VREF = 3.072 V, IOL(sum) = 0 mA
VCC = VREF = 5.12 V
VOT
Zero transition error
Full-scale transition error
Conversion time
LSB
LSB
µs
3
4
VFST
7
VCC = VREF = 3.072 V
25
12.5
VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz
VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz
tCONV
VREF
Reference input voltage
Ladder resistance value
Analog input voltage
VCC
V
kΩ
V
0.5VCC
10
RLADDER
VIA
5
2
0
VREF
44
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
•
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
•
•
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1998 MITSUBISHI ELECTRIC CORP.
New publication, effective Jan. 1998.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
7470/7471 GROUP DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
980110
(1/1)
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SI9137DB
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