M37272M6-205SP [MITSUBISHI]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER; 单片8位CMOS单片机结合闭合字幕解码器和屏幕显示控制器型号: | M37272M6-205SP |
厂家: | Mitsubishi Group |
描述: | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
文件: | 总142页 (文件大小:1418K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
1. DESCRIPTION
●OSD function
Display characters ................................... 32 characters ✕ 2 lines
The M37272M6/M8-XXXSP/FP and M37272MA-XXXSP are single-
(It is possible to display 3 lines or more by software)
Kinds of characters ........................................................ 254 kinds
Character display area............................ CC mode: 16 ✕ 26 dots
OSD mode: 16 ✕ 20 dots
chip microcomputers designed with CMOS silicon gate technology.
2
They have a OSD, data slicer, and I C-BUS interface, so it is useful
for a channel selection system for TV with a closed caption decoder.
The features of the M37272E8SP/FP and M37272EFSP are similar
to those of the M37272M6-XXXSP except that the chip has a built-in
PROM which can be written electrically. The difference between
M37272M6-XXXSP/FP, M37272M8-XXXSP/FP and M37272MA-
XXXSP are the ROM size and RAM size. Accordingly, the following
descriptions will be for the M37272M6-XXXSP/FP.
Kinds of character sizes..................................... CC mode: 1 kind
OSD mode: 8 kinds
Kinds of character colors .................................. 8 colors (R, G, B)
Coloring unit ................... character, character background, raster
Display position
Horizontal: 128 levels
Vertical: 512 levels
Attribute ........................................................................................
2. FEATURES
CC mode: smooth italic, underline, flash, automatic solid space
●Number of basic instructions .................................................... 71
OSD mode: border
Smoth roll-up
●Memory size
ROM .............. 24K bytes
Window function
(M37272M6-XXXSP/FP)
32K bytes
3. APPLICATION
TV with a closed caption decoder
(M37272M8-XXXSP/FP, M37272E8SP/FP)
40K bytes
(M37272MA-XXXSP)
60K bytes
(M37272EFSP)
RAM ............... 1024 bytes
(
M37272M6-XXXSP/FP
1152 bytes
M37272M8-XXXSP/FP, M37272E8SP/FP
1472 bytes
M37272MA-XXXSP, M37272EFSP
)
(
)
(
)
(*ROM correction memory included)
●Minimum instruction execution time
......................................... 0.5 µs (at 8 MHz oscillation frequency)
●Power source voltage ................................................. 5 V ± 10 %
●Subroutine nesting ............................................. 128 levels (Max.)
●Interrupts ....................................................... 17 types, 16 vectors
●8-bit timers .................................................................................. 6
●Programmable I/O ports (Ports P0, P1, P2, P30, P31) ............. 26
●Input ports (Ports P50, P51) ........................................................ 2
●Output ports (Ports P52–P55) ..................................................... 4
●12 V withstand ports ................................................................... 6
●LED drive ports ........................................................................... 4
●Serial I/O ............................................................ 8-bit ✕ 1 channel
2
●Multi-master I C-BUS interface .............................. 1 (2 systems)
●A-D comparator (6-bit resolution) ................................ 6 channels
●PWM output circuit......................................................... 8-bit ✕ 6
●Power dissipation
In high-speed mode ......................................................... 165 mW
(at VCC = 5.5V, 8 MHz oscillation frequency, OSD on, and Data
slicer on)
In low-speed mode ......................................................... 0.33 mW
(at VCC = 5.5V, 32 kHz oscillation frequency)
●ROM correction function ................................................ 2 vectors
●Closed caption data slicer
Rev. 1.4
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
TABLE OF CONTENTS
9. PROGRAMMING NOTES ........................................................96
10. ABSOLUTE MAXIMUM RATINGS .........................................97
11. RECOMMENDED OPERATING CONDITIONS .....................97
12. ELECTRIC CHARACTERISTICS ..........................................98
13. A-D COMPARISON CHARACTERISTICS ...........................100
14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS ......... 100
15. PROM PROGRAMMING METHOD .....................................101
16. DATA REQUIRED FOR MASK ORDERS ............................102
17. MASK CONFIRMATION FORM ...........................................103
18. MARK SPECIFICATION FORM ........................................... 112
19. ONE TIME PROM VERSIONS M37272E8SP/FP,
1. DESCRIPTION ..........................................................................1
2. FEAUTURES .............................................................................1
3. APPLICATION ............................................................................1
4. PIN CONFIGURATION ..............................................................3
5. FUNCTIONAL BLOCK DIAGRAM .............................................4
6. PERFORMANCE OVERVIEW ...................................................5
7. PIN DESCRIPTION ...................................................................7
8. FUNCTIONAL DESCRIPTION................................................. 11
8.1 CENTRAL PROCESSING UNIT (CPU) .................... 11
8.2 MEMORY ..................................................................12
8.3 INTERRUPTS ...........................................................18
8.4 TIMERS .....................................................................23
8.5 SERIAL I/O ................................................................26
M37272EFSP MARKING..................................................... 114
20. APPENDIX ........................................................................... 115
21. PACKAGE OUTLINE ...........................................................140
2
8.6 MULTI-MASTER I C-BUS INTERFACE....................29
8.7 PWM OUTPUT CIRCUIT ..........................................42
8.8 A-D COMPARATOR ..................................................46
8.9 ROM CORRECTION FUNCTION .............................48
8.10 DATA SLICER .........................................................49
8.11 OSD FUNCTIONS ...................................................60
8.11.1 Display Position .......................................65
8.11.2 Dot size ....................................................69
8.11.3 Clock for OSD ..........................................70
8.11.4 Field Determination Display .....................71
8.11.5 Memory For OSD.....................................73
8.11.6 Character Color .......................................77
8.11.7 Character Background Color ...................77
8.11.8 OUT1, OUT2 Signals ...............................78
8.11.9 Attribute....................................................79
8.11.10 Multiple Display......................................84
8.11.11 Automatic Solid Space Function ............85
8.11.12 Window Function ...................................86
8.11.13 OSD Output Pin Control ........................88
8.11.14 Raster Coloring Function .......................89
8.12. SOFTWARE RUNAWAY DETECT FUNCTION .....91
8.13. RESET CIRCUIT ....................................................92
8.14. CLOCK GENERATING CIRCUIT ...........................93
8.15. DISPLAY OSCILLATION CIRCUIT ........................96
8.16. AUTO-CLEAR CIRCUIT .........................................96
8.17. ADDRESSING MODE ............................................96
8.18. MACHINE INSTRUCTIONS ...................................96
Rev. 1.3
2
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
4. PIN CONFIGURATION
1
2
42
41
40
39
P5
0
/HSYNC
P5
P5
P5
P5
2
/R
P5
1
/VSYNC
/PWM0
/PWM1
/PWM2
/PWM3
/PWM4
/PWM5
3
4
5
/G
3
4
5
P0
P0
P0
P0
P0
P0
0
/B
1
2
3
4
5
/OUT1
38
37
36
P2
P2
0
/SCLK
/SOUT
6
7
1
P2
2/SIN
8
9
35
34
P1
P1
0
/OUT2
/SCL1
1
P0
6
/INT2/AD4
P0 /INT1
10
33
32
31
7
P1
P1
P1
P1
P1
P1
P3
2
3
4
5
6
7
0
/SCL2
/SDA1
/SDA2
/AD1/INT3
/AD2
11
12
P2
P2
3
/TIM3
/TIM2
4
P2
5
13
14
15
30
29
28
AVCC
HLF
/AD3
16
17
27
26
/AD5
VHOLD
CVIN
P3
1/AD6
18
19
25
24
RESET
CNVSS
IN
OUT
P2
P2
6
/OSC1/XCIN
X
20
21
23
22
7/OSC2/XCOUT
X
VCC
VSS
Outline 42P4B
Fig. 4.1 Pin Configuration (1) (Top View)
1
42
41
40
39
P5
0
/HSYNC
P5
2
/R
2
P5
1
/VSYNC
/PWM0
/PWM1
/PWM2
/PWM3
/PWM4
/PWM5
P5
P5
P5
3
4
5
/G
3
4
5
6
7
/B
P0
0
1
2
3
4
5
/OUT1
P0
P0
P0
P0
P0
38
37
36
P2
0/SCLK
P2
P2
1
/SOUT
/SIN
2
8
9
35
34
P1
P1
P1
0
/OUT2
/SCL1
/SCL2
1
P0
6
/INT2/AD4
P0 /INT1
10
11
33
32
2
3
4
7
P2
P2
3
/TIM3
P1
P1
/SDA1
/SDA2
12
31
30
29
4
/TIM2
P2
5
13
14
P1
P1
P1
5
6
7
/AD1/INT3
/AD2
AVCC
15
16
28
27
/AD3
HLF
V
HOLD
P3
P3
0
/AD5
/AD6
17
18
19
26
25
24
CVIN
1
RESET
CNVSS
IN
OUT
X
P2
P2
6/OSC1/XCIN
20
21
23
22
X
7/OSC2/XCOUT
V
SS
VCC
Outline 42P2R-A/E
Fig. 4.2 Pin Configuration (2) (Top View)
Rev. 1.4
3
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
5. FUNCTIONAL BLOCK DIAGRAM
C N Y S H
C N Y S V
R
G
B
1 T U O
0 M W P
1 M W P
2 M W P
3 M W P
4 M W P
5 M W P
T U O S
K L C S
N I S
1 L C S
2 L C S
1 A D S
2 A D S
6 – 1 D A
3 T N I
2 T N I
1 T N I
Fig. 5.1 Functional Block Diagram of M37272
Rev. 1.3
4
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
6. PERFORMANCE OVERVIEW
Table 6.1 Performance Overview
Parameter
Number of basic instructions
Instruction execution time
Functions
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation fre-
quency)
Clock frequency
8 MHz (maximum)
Memory size
ROM
RAM
M37272M6-XXXSP/FP
24K bytes
M37272M8-XXXSP/FP,M37272E8SP/FP 32K bytes
M37272MA-XXXSP
M37272EFSP
40K bytes
60K bytes
M37272M6-XXXSP/FP
1024 bytes (ROM correction memory included)
M37272M8-XXXSP/FP,M37272E8SP/FP 1152 bytes (ROM correction memory included)
M37272MA-XXXSP, M37272EFSP 1472 bytes (ROM correction memory included)
OSD ROM
OSD RAM
P0
10K bytes
128 bytes
Input/Output
ports
8-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM
output pins, INT input pins, A-D input pin)
I/O
I/O
P10–P17
P20–P27
P30, P31
8-bit ✕ 1 (CMOS input/output structure, however, N-channel open-drain
output structure, when P11–P14 are used as multi-master I C-BUS inter-
2
face, can be used as OSD output pin, A-D input pins, INT input pin, multi-
2
master I C-BUS interface)
I/O
I/O
8-bit ✕ 1 (P2 is CMOS input/output structure, however, N-channel open-
drain output structure when P20 and 21 are used as serial output, can be
used as serial input/output pins, timer external clock input pins, OSD clock
input/output pin, sub-clock input/output pins)
2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure,
can be used as A-D input pins)
P50, P51
P52–P55
2-bit ✕ 1 (can be used as OSD input pins)
Input
4-bit ✕ 1 (CMOS output structure, can be used as OSD output pins)
Output
8-bit ✕ 1
Serial I/O
2
1 (2 systems)
6 channels (6-bit resolution)
8-bit ✕ 6
Multi-master I C-BUS interface
A-D comparator
PWM output circuit
Timers
8-bit timer ✕ 6
2 vectors
ROM correction function
Subroutine nesting
Interrupt
128 levels (maximum)
<17 types>
INT external interrupt ✕ 3, Internal timer interrupt ✕6, Serial I/O interrupt ✕
1, OSD interrupt ✕ 1, Multi-master I C-BUS interface interrupt ✕ 1, Data
2
slicer interrupt ✕ 1, f(XIN)/4096 interrupt ✕ 1, VSYNC interrupt ✕ 1, BRK
instruction interrupt ✕ 1, reset ✕ 1
Clock generating circuit
Data slicer
2 built-in circuits (externally connected to a ceramic resonator or a quartz-
crystal oscillator)
Built-in
Rev. 1.3
5
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Table 6.2 Performance Overview (Continued)
Parameter
Number of display characters
Functions
32 characters ✕ 2 lines
OSD function
Dot structure
CC mode: 16 ✕ 26 dots (character display area : 16 ✕ 20 dots)
OSD mode: 16 ✕ 20 dots
Kinds of characters
254 kinds
Kinds of character sizes
1 screen : 8
CC mode: 1 kinds
OSD mode: 8 kinds
Character font coloring
Display position
1 screen: 8 kinds (per character unit)
Horizontal: 128 levels, Vertical: 512 levels
5V ± 10%
Power source voltage
Power
dissipation
In high-speed
mode
OSD ON
Data slicer ON
165 mW typ. ( at oscillation frequency f(XIN) = 8 MHz, fOSC = 27 MHz)
82.5 mW typ. ( at oscillation frequency f(XIN) = 8 MHz)
0.33 mW typ. ( at oscillation frequency f(XCIN) = 32 kHz, f(XIN) = stopped)
OSD OFF Data slicer OFF
OSD OFF Data slicer OFF
In low-speed
mode
In stop mode
0.055 mW ( maximum )
–10 °C to 70 °C
Operating temperature range
Device structure
CMOS silicon gate process
42-pin plastic molded DIP
42-pin plastic molded SSOP
Package
Rev. 1.3
6
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
7. PIN DESCRIPTION
Table 7.1 Pin Description
Input/
Output
Pin
Name
Functions
VCC, AVCC, Power source
VSS
Apply voltage of 5 V ± 10 % to (typical) VCC and AVCC, and 0 V to VSS.
CNVSS
RESET
CNVSS
This is connected to VSS.
Reset input
Input
Input
To enter the reset state, the reset input pin must be kept at a LOW for 2 µs or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should
be maintained for the required time.
XIN
Clock input
This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and
XOUT
Clock output
Output
I/O
XOUT. If an external clock is used, the clock source should be connected to the XIN pin and
the XOUT pin should be left open.
P00
/PWM0– I/O port P0
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
is N-channel open-drain output. (See note 1)
P05/PWM5,
P06/INT2/AD4,
P07/INT1
PWM output
Output
Input
Pins P00–P05 are also used as PWM output pins PWM0–PWM5 respectively. The output
structure is N-channel open-drain output.
External interrupt
input
Pins P06 and P07 are also used as INT external interrupt input pins INT2 and INT1 respectively.
Analog input
Input
I/O
P06 pin is also used as analog input pin AD4.
P10/OUT2, I/O port P1
P11/SCL1,
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output. (See note 1)
P12/SCL2, OSD output
Output
I/O
Pins P10 is also used as OSD output pin OUT2. The output structure is CMOS output.
Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
I C-BUS interface is used. The output structure is N-channel open-drain output.
P13/SDA1, Multi-master
2
2
I C-BUS interface
P14/SDA2,
P1
5
/AD1/INT3, Analog input
Input
Input
Pins P10, P15–P17 are also used as analog input pin AD8, AD1–AD3 respectively.
P15 pin is also used as INT external interrupt input pin INT3.
P16/AD2,
P17/AD3
External interrupt
input
P20/SCLK, I/O port P2
P21/SOUT,
I/O
I/O
I/O
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output. (See note 1)
P22/SIN,
P23/TIM3,
Serial I/O synchronous
clock input/output port
P20 pin is also used as serial I/O synchronous clock input/output pin SCLK. The output
structure is N-channel open-drain output.
P24/TIM2, Serial I/O data
output
/OSC1/ Serial I/O data input
XCIN,
P2 /OSC2/ input for timer
P21 pin is also used as serial I/O data output pin SOUT. The output structure is open-drain
output.
P25,
P2
6
Input
Input
P22 pin is also used as serial I/O data input pin SIN.
External clock
Pins P23 and P24 are also used as timer external clock input pins TIM3 and TIM2
respectively.
7
XCOUT
Clock input for OSD
Clock output for OSD
Input
P26 pin is also used as OSD clock input pin OSC1. (See note 2)
Output
P27 pin is also used as OSD clock input pin OSC2. The output structure is CMOS output.
(See note 2)
Sub-clock input
Sub-clock output
Input
P26 pin is also used as sub-clock input pin XCIN.
P27 pin is also used as sub-clock output pin XCOUT.
Output
Rev. 1.4
7
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Table 7.2 Pin Description (continued)
Input/
Output
Pin
Name
Functions
P30/AD5,
P31/AD6
I/O port P3
I/O
Ports P30 and P31 are a 2-bit I/O port and has basically the same functions as port 0.
The output structure can be selected either CMOS output or N-channel open-drain output
structure. (See notes 1, 3)
Analog input
/HSYNC, Input port P5
Input
Input
Input
Input
Pins P30 and P31 are also used as analog input pins AD5 and AD6 respectively.
Pin P50 and P51 are 2-bit input ports.
P5
0
1
P5
/VSYNC HSYNC input
VSYNC input
Pin P50 is also used as HSYNC input. This is a horizontal synchronous signal input for OSD.
Pin P51 is also used as VSYNC input. This is a vertical synchronous signal input for OSD.
P52/R,
P53/G,
Output port P5
Output
Ports P52–P55 are a 4-bit output port. The output structure is CMOS output.
P54/B,
OSD output
Output
Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output
structure is CMOS output.
P55/OUT1
CVIN
VHOLD
HLF
I/O for data slicer
Input
Input
I/O
Input composite video signal through a capacitor.
Connect a capacitor between VHOLD and Vss.
Connect a filter using of a capacitor and a resistor between HLF and Vss.
Notes 1: Port Pi (i = 0 to 3) has the port Pi direction register which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1”
in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data
are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read.
This allows a previously-output value to be read correctly even if the output LOW voltage has risen, for example, because a light emitting diode was directly
driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port
latch, while the pin remains in the floating state.
2: To switch output functions, set the raster color register and OSD control register. When pins P26 and P27 are used as the OSD clock input/output pins, set
the corresponding bits of the port P2 direction register to “0” (input mode).
3: To switch output structures, set bits 2 and 3 of the port P3 direction register, When “0,” CMOS output ; when “1,” N-channel open-drain output.
Rev. 1.4
8
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Ports P00–P05
N-channel open-drain output
Direction register
Ports P00–P05
Note : Each port is also used as follows :
Port latch
Data bus
P00–P05 : PWM0–PWM5
Ports P1, P2, P30, P31
Direction register
Port latch
CMOS output
Ports P1, P2, P30, P31
Data bus
Notes 1: Each port is also used as follows :
P10 : OUT2
P11 : SCL1
P12 : SCL2
P13 : SDA15
P14 : SDA2
P15 : AD1/INT3
P16 : AD2
P20 : SCLK
P21 : SOUT
P22 : SIN
P23 : TIM3
P24 : TIM2
P30 : AD5
P31 : AD6
P17 : AD3
2: The output structure of ports P30 and P31 can be selected either CMOS output or N-channel open-
drain output structure (when selecting N-channel open-drain, it is the same with P06 and P07).
3: The output structure of ports P11–P14 is N-channel open-drain output when using as multi-master
I2C-BUS interface (it is the same with P06 and P07).
4: The output structure of ports P20 and P21 is N-channel open-drain output when using as serial
output (it is the same as P06 and P07).
Fig. 7.1 I/O Pin Block Diagram (1)
Rev. 1.3
9
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Ports P06, P07
N-channel open-drain output
Direction register
Ports P06, P07
Data bus
Note : Each port is also used
as follows :
Port latch
P06 : INT2/AD4
P07 : INT1
P50, P51
P52–P55
CMOS input
CMOS output
Ports P52–P55
Internal circuit
Ports P50, P51
Internal circuit
Note : Each pin is also used
as follows :
Note : Each pin is also used
as follows :
P52 : R
P50 : HSYNC
P51 : VSYNC
P53 : G
P54 : B
P55 : OUT1
Fig. 7.2 I/O Pin Block Diagram (2)
Rev. 1.4
10
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8. FUNCTIONAL DESCRIPTION
8.1.1 CPU Mode Register
8.1 CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allo-
cated at address 00FB16.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
CPU Mode Register
b7b6 b5b4b3 b2b1b0
1 1
0 0
CPU mode register (CM) [Address 00FB16
]
B
Name
Functions
After reset R W
Processor mode bits
(CM0, CM1)
b1 b0
0, 1
0
R W
0 0: Single-chip mode
0 1:
1 0:
1 1:
Not available
0: 0 page
1: 1 page
Stack page selection
bit (CM2) (See note)
2
1
R W
3, 4 Fix these bits to “1.”
1
1
R W
R W
0: LOW drive
1: HIGH drive
X
COUT drivability
5
6
selection bit (CM5)
Main Clock (XIN–XOUT
stop bit
)
0
0
R W
R W
0: Oscillating
1: Stopped
(CM6)
Internal system clock
selection bit
(CM7)
7
0: XIN–XOUT selected
(high-speed mode)
1: XCIN–XCOUT selected
(high-speed mode)
Note: This bit is set to “1” after the reset release.
Fig. 8.1.1 CPU Mode Register
Rev. 1.3
11
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.2 MEMORY
8.2.6 Interrupt Vector Area
8.2.1 Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
The interrupt vector area contains reset and interrupt vectors.
8.2.7 Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
8.2.2 RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
8.2.3 ROM
ROM is used for storing user programs as well as the interrupt vector
area.
8.2.8 Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the spe-
cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
8.2.4 OSD RAM
RAM for display is used for specifying the character codes and col-
ors to display.
8.2.5 OSD ROM
ROM for display is used for storing character data.
8.2.9 ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
■M37272M6/M8-XXXSP/FP, M37272E8SP/FP
000016
1000016
Zero page
00BF16
00C016
SFR1 area
M37272M8-
XXXSP/FP,
M37272E8SP/FP
RAM
00FF16
010016
M37272M6-
XXXSP/FP
RAM
01FF
02001166
(1024 bytes)
(1152 bytes)
SFR2 area
Not used
020F16
030016
032016
ROM correction function
053F16
05BF16
Vector 1: address 030016
Vector 2: address 032016
Not used
Not used
OSD RAM
(128 bytes)
(See note)
080016
087F16
Not used
OSD ROM
(10K bytes)
140016
3BFF16
Not used
M37272M8-
XXXSP/FP,
M37272E8SP/FP
ROM
(32K bytes)
800016
A00016
M37272M6-
XXXSP/FP
ROM
FF0016
FFDE16
Special page
1FFFF16
(24K bytes)
Interrupt vector area
FFFF16
Note: Refer to Table 8.11.3 OSD RAM.
Fig. 8.2.1 Memory Map (M37272M6/M8-XXXSP/FP, M37272E8SP/FP)
Rev. 1.4
12
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■M37272MA-XXXSP, M37272EFSP
1000016
000016
Zero page
00BF16
00C016
00FF16
010016
SFR1 area
02001166
01FF
RAM
(1472 bytes)
SFR2 area
Not used
020F16
030016
032016
Not used
ROM correction functrion
Vector 1: address 030016
Vector 2: address 032016
06FF16
Not used
Not used
OSD RAM
(128 bytes)
(See note)
080016
087F16
100016
1140016
13BFF16
OSD ROM
(10K bytes)
M37272EFSP
ROM
(60K bytes)
600016
Not used
M37272MA-XXXSP
ROM
(40K bytes)
FF0016
FFDE16
Special page
Interrupt vector area
FFFF16
1FFFF16
Note: Refer to Table 8.11.3 OSD RAM.
Fig. 8.2.2 Memory Map (M37272MA-XXXSP, M37272EFSP)
Rev. 1.3
13
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■SFR1 Area (addresses C016 to DF16)
<Bit allocation>
<State immediately after reset>
:
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
Name
:
: No function bit
: Indeterminate immediately
after reset
: Fix this bit to “0”
(do not write “1”)
0
1
: Fix this bit to “1”
(do not write “0”)
Register
Bit allocation
State immediately after reset
Address
b7
b0 b7
b0
?
0016
?
Port P0 (P0)
C016
C116
Port P0 direction register (D0)
C216 Port P1 (P1)
0016
?
0016
C316
Port P1 direction register (D1)
Port P2 (P2)
C416
C516
Port P2 direction register (D2)
P31 P30
P31CP30CP31DP30D
0
0
0
0
0016
0
0
?
?
C616 Port P3 (P3)
T3SC
Port P3 direction register (D3)
C716
C816
C916
CA16
CB16
CC16
?
?
?
Port P5 (P5)
PF7
PF5 PF4 PF3 PF2
0016
0016
0016
?
0
0
OSD port control register (PF)
CD16
CE16
CF16
D016
CDL27CDL26CDL25CDL24CDL23CDL22CDL21CDL20
CDH27CDH26CDH25CDH24CDH23CDH22CDH21CDH20
?
?
Caption data register 3 (CD3)
Caption data register 4 (CD4)
OSD control register (OC)
OC6
HP6
OC5 OC4 OC3 OC2 OC1 OC0
HP5 HP4 HP3 HP2 HP1 HP0
0
0016
0016
Horizontal position register (HP)
Block control register 1 (BC1)
Block control register 2 (BC2)
Vertical position register 1 (VP1)
Vertical position register 2 (VP2)
Window register 1 (WN1)
D116
D216
D316
D416
D516
D616
D716
BC11BC10
BC17BC16BC15BC14BC13BC12
?
?
?
?
?
BC27BC26BC25BC24BC23BC22BC21BC20
VP17VP16VP15VP14VP13VP12VP11VP10
VP27VP26VP25VP24VP23VP22VP21VP20
WN17WN16WN15WN14WN13WN12WN11WN10
WN27WN26WN25WN24WN23WN22WN21WN20
?
Window register 2 (WN2)
PC6
PC5 PC4 PC3 PC2 PC1 PC0
4016
0016
?
0
RC7
D816 I/O polarity control register (PC)
RC4 RC3 RC2 RC1 RC0
0
0
Raster color register (RC)
D916
DA16
DB16
DC16
DD16
DE16
DF16
?
INT3 INT2 INT1
0016
0016
0016
Interrupt input polarity control register (RE)
0016
0016
0016 (See note 1)
0016 (See note 2)
Notes 1: This is only M37272MA-XXXSP and M37272EFSP.
2: As for M37272M6/M8-XXXSP/FP and M37272E8SP/FP, the reset value is ? (indeterminate).
Fig. 8.2.3 Memory Map of Special Function Register 1 (SFR1) (1)
Rev. 1.4
14
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■SFR1 Area (addresses E016 to FF16
)
<Bit allocation>
:
<State immediately after reset>
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
Name
:
: No function bit
: Indeterminate immediately
after reset
: Fix this bit to “0”
(do not write “1”)
0
1
: Fix this bit to “1”
(do not write “0”)
Bit allocation
State immediately after reset
Address
Register
b7
0
b0 b7
b0
Data slicer control register 1 (DSC1)
Data slicer control register 2 (DSC2)
Caption data register 1 (CD1)
Caption data register 2 (CD2)
Clock run-in detect register (CRD)
Data clock position register (DPS)
Caption position register (CPS)
Data slicer test register 2
DSC12DSC11DSC10
0016
E016
E116
E216
E316
1
0
1
0
0
DSC25DSC24DSC23
DSC20
1
?
0
?
0
?
?
0
?
CDL17CDL16CDL15CDL14CDL13CDL12CDL11CDL10
CDH17CDH16CDH15CDH14CDH13CDH12CDH11CDH10
CRD7CRD6CRD5CRD4CRD3
0016
0016
0016
0916
E416
E516
E616
DPS7 DPS6 DPS5 DPS4 DPS3
1
0
0
CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
0
0
?
0
0
0
0
0
0
0016
0016
0016
E716
E816
E916
EA16
EB16
EC16
Data slicer test register 1
HC5 HC4 HC3 HC2 HC1 HC0
Synchronous signal counter register (
Serial I/O register (SIO)
?
Serial I/O mode register (SM)
0
SM6 SM5
SM3 SM2 SM1 SM0
0016
?
0
ADC14
ADC12 ADC11ADC10
A-D control register 1 (AD1)
A-D control register 2 (AD2)
Timer 5 (T5)
0
0
0
0
0
0
ADC25 ADC24ADC23 ADC22ADC21 ADC20
0016
0716
ED16
EE16
EF16
F016
Timer 6 (T6)
FF16
FF16
0716
FF16
0716
Timer 1 (T1)
Timer 2 (T2)
F116
F216
F316
F416
F516
Timer 3 (T3)
Timer 4 (T4)
TM17 TM16 TM15TM14 TM13 TM12 TM11 TM10
TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
Timer mode register 1 (TM1)
0016
Timer mode register 2 (TM2)
2
0016
?
0016
D7 D6 D5 D4 D3 D2 D1 D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0RBW
F616 I C data shift register (S0)
2
F716
F816
I C address register (S0D)
MST TRX BB PIN AL AAS AD0 LRB
10BIT
2
0
0
0
1
0
0
0
?
I C status register (S1)
BSEL1BSEL0
ALS ESO BC2 BC1 BC0
CCR4CCR3CCR2 CCR1CCR0
CM2
2
0016
I C control register (S1D)
SAD
FAST
MODE
F916
FA16
FB16
FC16
FD16
FE16
FF16
ACK
ACK
2
0016
3C16
0016
0016
0016
0016
I C clock control register (S2)
BIT
CM7 CM6 CM5
1
1
0
0
CPU mode register (CPUM)
VSCR OSDRTM4RTM3RTM2RTM1R
IN3R
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
TM56R
DSR
IICR IN2R CKR S1R
IN1R
0
VSCEOSDE TM4ETM3ETM2ETM1E
IICE IN2E CKE S1E DSE IN1E
IN3E
Interrupt control register 2 (ICON2) TM56CTM56E
Fig. 8.2.4 Memory Map of Special Function Register 1 (SFR1) (2)
Rev. 1.3
15
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■SFR2 Area (addresses 20016 to 20F16
)
<Bit allocation>
:
<State immediately after reset>
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
Name
:
: No function bit
: Indeterminate immediately
after reset
: Fix this bit to “0”
(do not write “1”)
0
1
: Fix this bit to “1”
(do not write “0”)
Register
Bit allocation
State immediately after reset
Address
b7
b0 b7
b0
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM4 register (PWM4)
PWM5 register (PWM5)
20016
20116
20216
20316
?
?
?
?
?
?
?
?
20416
20516
20616
0016
0016
20716
20816
20916
20A16
PM13
PM10
PWM mode register 1 (PM1)
PWM mode register 2 (PM2)
ROM correction address 1 (high-order)
?
?
?
?
0
?
?
0
PM25 PM24 PM23 PM22 PM21 PM20
0
0
0016
0016
0016
0016
0016
0016
?
20B16 ROM correction address 1 (low-order)
20C16
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
20D16
20E16
20F16
RC1 RC0
Fig. 8.2.5 Memory Map of Special Function Register 2 (SFR2)
Rev. 1.3
16
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
<
State immediately after reset>
<
Bit allocation
:
>
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
:
:
Name
No function bit
: Indeterminate immediately
after reset
: Fix to this bit to “0”
(do not write to “1”)
0
1
: Fix to this bit to “1”
(do not write to “0”)
Register
Bit allocation
State immediately after reset
b0
b0
b7
N
b7
Processor status register (PS)
V
T
B
D
I
Z
C
?
?
?
?
?
1
?
?
Program counter (PC
H)
Contents of address FFFF16
Contents of address FFFE16
Program counter (PC
L
)
Fig. 8.2.6 Internal State of Processor Status Register and Program Counter at Reset
Rev. 1.3
17
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.3 INTERRUPTS
8.3.1 Interrupt Causes
Interrupts can be caused by 17 different sources consisting of 4 ex-
ternal, 11 internal, 1 software, and reset. Interrupts are vectored in-
terrupts with priorities as shown in Table 8.3.1. Reset is also included
in the table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) VSYNC, OSD interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
① The contents of the program counter and processor status regis-
ter are automatically stored into the stack.
(2) INT1 to INT3 external interrupts
The INT1 to INT3 interrupts are external interrupt inputs, the sys-
tem detects that the level of a pin changes from LOW to HIGH or
from HIGH to LOW, and generates an interrupt request. The in-
put active edge can be selected by bits 3 to 5 of the interrupt
input polarity register (address 00DC16) : when this bit is “0,” a
change from LOW to HIGH is detected; when it is “1,” a change
from HIGH to LOW is detected. Note that both bits are cleared to
“0” at reset.
➁ The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
➂ The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the
interrupt-related registers.
(3) Timers 1 to 4 interrupts
An interrupt is generated by an overflow of timers 1 to 4.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 8.3.1 shows interrupt control.
Table 8.3.1 Interrupt Vector Addresses and Priority
Priority
Interrupt Source
Vector Addresses
Remarks
1
2
Reset
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE716, FFE616
FFE516, FFE416
FFE316, FFE216
FFDF16, FFDE16
Non-maskable
OSD interrupt
3
INT1 external interrupt
Data slicer interrupt
Serial I/O interrupt
Timer 4 interrupt
Active edge selectable
4
5
6
7
f(XIN)/4096 interrupt
VSYNC interrupt
8
9
Timer 3 interrupt
10
11
12
13
14
15
16
Timer 2 interrupt
Timer 1 interrupt
INT3 external interrupt
INT2 external interrupt
Active edge selectable
Active edge selectable
2
Multi-master I C-BUS interface interrupt
Timer 5 • 6 interrupt
Source switch by software (see note)
Non-maskable
BRK instruction interrupt
Note: Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.
Rev. 1.3
18
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial I/O
function.
Interrupt request bit
Interrupt enable bit
(5) f(XIN)/4096 interrupt
The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 pe-
riod. Set bit 0 of the PWM mode register 1 to “0.”
Interrupt disable flag I
(6) Data slicer interrupt
An interrupt occurs when slicing data is completed.
Interrupt
request
BRK instruction
Reset
(7) Multi-master I2C-BUS interface interrupt
2
This is an interrupt request related to the multi-master I C-BUS
interface.
(8) Timer 5 • 6 interrupt
Fig. 8.3.1 Interrupt Control
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(9) BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af-
fected by the interrupt disable flag I (non-maskable).
Rev. 1.3
19
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Request Register 1
b7b6 b5b4b3 b2b1b0
Interrupt request register 1 (IREQ1) [Address 00FC16
]
After reset
0
B
0
Name
Functions
R W
R
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt
request bit (TM1R)
✽
1
2
3
4
5
6
7
Timer 2 interrupt
0 : No interrupt request issued
0
0
0
0
0
0
0
R
R
R
R
R
R
✽
✽
✽
✽
✽
✽
request bit (TM2R) 1 : Interrupt request issued
Timer 3 interrupt 0 : No interrupt request issued
request bit (TM3R) 1 : Interrupt request issued
Timer 4 interrupt 0 : No interrupt request issued
request bit (TM4R) 1 : Interrupt request issued
OSD interrupt request 0 : No interrupt request issued
bit (OSDR)
SYNC interrupt
1 : Interrupt request issued
V
0 : No interrupt request issued
request bit (VSCR) 1 : Interrupt request issued
INT3 external interrupt
request bit (VSCR)
0 : No interrupt request issued
1 : Interrupt request issued
R —
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
✽: “0” can be set by software, but “1” cannot be set.
Fig. 8.3.2 Interrupt Request Register 1
Interrupt Request Register 2
b7 b6b5b4b3 b2b1b0
0
Interrupt request register 2 (IREQ2) [Address 00FD16]
After reset
0
B
0
Name
Functions
R W
INT1 external interrupt
request bit (INIR)
0 : No interrupt request issued
1 : Interrupt request issued
R
R
R
R
R
R
✽
✽
✽
✽
✽
✽
Data slicer interrupt
request bit (DSR)
1
2
3
4
5
6
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
0
0
0
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O interrupt
request bit (S1R)
f(XIN)/4096 interrupt
request bit (CKR)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
INT2 external interrupt
request bit (IN2R)
Multi-master I2C-BUS
interrupt request bit (IICR)
Timer 5 • 6 interrupt
request bit (TM56R)
0 : No interrupt request issued
1 : Interrupt request issued
R
✽
7
Fix this bit to “0.”
0
R W
✽: “0” can be set by software, but “1” cannot be set.
Fig. 8.3.3 Interrupt Request Register 2
Rev. 1.3
20
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register 1
b7b6 b5b4b3 b2b1b0
Interrupt control register 1 (ICON1) [Address 00FE16
]
After reset
0
B
0
Name
Functions
R W
R W
Timer 1 interrupt
enable bit (TM1E)
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
enable bit (TM2E)
1
2
3
4
5
6
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
R W
R W
R W
R W
R W
R W
Timer 3 interrupt
enable bit (TM3E)
0 : Interrupt disabled
1 : Interrupt enabled
Timer 4 interrupt
enable bit (TM4E)
OSD interrupt enable bit
(OSDE)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
VSYNC interrupt enable
0 : Interrupt disabled
1 : Interrupt enabled
bit (VSCE)
INT3 external interrupt
enable bit (IN3E)
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
7
0
R —
Fig. 8.3.4 Interrupt Control Register 1
Interrupt Control Register 2
b7b6 b5b4b3 b2b1b0
Interrupt control register 2 (ICON2) [Address 00FF16
]
After reset
0
B
0
Name
Functions
R W
R W
INT1 external interrupt
enable bit (IN1E)
0 : Interrupt disabled
1 : Interrupt enabled
Data slicer interrupt
enable bit (DSE)
1
2
3
4
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
R W
R W
R W
R W
Serial I/O interrupt
enable bit (S1E)
f(XIN)/4096 interrupt
enable bit (CKE)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
INT2 external interrupt
enable bit (IN2E)
0 : Interrupt disabled
1 : Interrupt enabled
Multi-master I2C-BUS
interface interrupt enable
bit (IICE)
0
R W
5
0 : Interrupt disabled
1 : Interrupt enabled
Timer 5 • 6 interrupt
enable bit (TM56E)
6
7
0 : Interrupt disabled
1 : Interrupt enabled
0
0
R W
R W
Timer 5 • 6 interrupt
switch bit (TM56C)
0 : Timer 5
1 : Timer 6
Fig. 8.3.5 Interrupt Control Register 2
Rev. 1.3
21
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt input polarity register (RE) [Address 00DC16
]
B
0
Name
Functions
After reset
0
R
R
W
W
INT1 polarity switch bit
(INT1)
0 : Positive polarity
1 : Negative polarity
0
0
0
R
R
R
W
W
—
4
5
INT2 polarity switch bit
(INT2)
0 : Positive polarity
1 : Negative polarity
INT3 polarity switch bit
(INT3)
0 : Positive polarity
1 : Negative polarity
4
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Fig. 8.3.6 Interrupt Input Polarity Register
Rev. 1.3
22
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.4 TIMERS
8.4.5 Timer 5
This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4,
timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer
latch. The timer block diagram is shown in Figure 8.4.3.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the correspond-
ing timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses
00EE16 and 00EF16 : timers 5 and 6), the value is also set to a timer,
simultaneously.
Timer 5 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 2 overflow signal
• Timer 4 overflow signal
The count source of timer 3 is selected by setting bit 6 of timer mode
register 1 (address 00F416) and bit 7 of the timer mode register 2
(address 00F516). When overflow of timer 2 or 4 is a count source
for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either
f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse, after the
count value reaches “0016”.
8.4.6 Timer 6
8.4.1 Timer 1
Timer 1 can select one of the following count sources:
Timer 6 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/16 or f(XCIN)/16
• Timer 5 overflow signal
• f(XIN)/4096 or f(XCIN)/4096
The count source of timer 6 is selected by setting bit 7 of the timer
mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected
by bit 7 of the CPU mode register. When timer 5 overflow signal is a
count source for timer 6, the timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.
• External clock from the TIM2 pin
The count source of timer 1 is selected by setting bits 5 and 0 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF16” is
✽
8.4.2 Timer 2
automatically set in timer 3; “0716” in timer 4. The f(XIN) /16 is se-
Timer 2 can select one of the following count sources:
lected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
• f(XIN)/16 or f(XCIN)/16
• Timer 1 overflow signal
• External clock from the TIM2 pin
✽
The count source of timer 2 is selected by setting bits 4 and 1 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8-
bit prescaler.
However, the f(XIN) /16 is not selected as the timer 3 count source.
So set both bit 0 of timer mode register 2 (address 00F516) and bit 6
at address 00C716 to “0” before the execution of the STP instruction
✽
(f(XIN) /16 is selected as timer 3 count source). The internal STP
state is released by timer 4 overflow in this state and the internal
clock is connected.
Timer 2 interrupt request occurs at timer 2 overflow.
As a result of the above procedure, the program can start under a
stable clock.
8.4.3 Timer 3
Timer 3 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
✽: When bit 7 of the CPU mode register (CM7) is “1,” f(XIN) becomes
• f(XCIN)
f(XCIN).
• External clock from the TIM3 pin
The count source of timer 3 is selected by setting bit 0 of timer mode
register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN)
or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
The timer-related registers is shown in Figures 8.4.1 and 8.4.2.
8.4.4 Timer 4
Timer 4 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/2 or f(XCIN)/2
• f(XCIN)
The count source of timer 3 is selected by setting bits 1 and 4 of the
timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8-
bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
Rev. 1.3
23
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register 1
b7b6 b5b4b3 b2b1b0
Timer mode register 1 (TM1) [Address 00F4 16]
After reset
0
B
0
Name
Functions
R
R
W
W
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Count source selected by bit 5 of TM1
Timer 1 count source
selection bit 1 (TM10)
0: Count source selected by bit 4 of TM1
1: External clock from TIM2 pin
0
R
W
1
Timer 2 count source
selection bit 1 (TM11)
Timer 1 count
stop bit (TM12)
2
3
4
0: Count start
1: Count stop
0
0
0
R
R
R
W
W
W
Timer 2 count stop
bit (TM13)
0: Count start
1: Count stop
Timer 2 count source
selection bit 2
(TM14)
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Timer 1 overflow
5
Timer 1 count source
selection bit 2 (TM15)
0: f(XIN)/4096 or f(XCIN)/4096 (See note)
1: External clock from TIM2 pin
0
R
W
6
7
Timer 5 count source
selection bit 2 (TM16)
0: Timer 2 overflow
1: Timer 4 overflow
0
0
R
R
W
W
Timer 6 internal count 0: f(XIN)/16 or f(XCIN)/16 (See note)
source selection bit
(TM17)
1: Timer 5 overflow
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Fig. 8.4.1 Timer Mode Register 1
Timer Mode Register 2
b7b6 b5b4b3 b2b1b0
Timer mode register 2 (TM2) [Address 00F5 16
]
After reset
0
B
0
Name
Functions
R
W
W
Timer 3 count source
selection bit (TM20)
R
(b6 at address 00C716
)
b0
0
0
1
1
0 : f(XIN)/16 or f(XCIN)/16 (See note)
1 : f(XCIN
)
0 :
1 :
External clock from TIM3 pin
b4 b1
1, 4
Timer 4 count source
selection bits
(TM21, TM24)
0
R
W
0
0
1
1
0 : Timer 3 overflow signal
1 : f(XIN)/16 or f(XCIN)/16 (See note)
0 : f(XIN)/2 or f(XCIN)/2 (See note)
1 : f(XCIN
)
Timer 3 count
stop bit (TM22)
2
3
0: Count start
1: Count stop
0
0
R
R
W
W
Timer 4 count stop bit
(TM23)
0: Count start
1: Count stop
Timer 5 count stop bit
(TM25)
5
6
0: Count start
1: Count stop
0
0
R
R
W
W
Timer 6 count stop bit
(TM26)
0: Count start
1: Count stop
Timer 5 count source
selection bit 1
(TM27)
7
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Count source selected by bit 6
of TM1
0
R
W
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Fig. 8.4.2 Timer Mode Register 2
Rev. 1.3
24
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data bus
8
XCIN
XIN
CM7
TM15
Timer 1 latch (8)
1/4096
8
Timer 1
interrupt request
1/2
1/8
Timer 1 (8)
TM10
TM14
TM12
8
8
Timer 2 latch (8)
8
Timer 2
interrupt request
TIM2
Timer 2 (8)
TM11
TM13
8
8
Reset
STP instruction
FF16
T3SC
Timer 3 latch (8)
8
Timer 3
interrupt request
Timer 3 (8)
TIM3
TM20
TM22
8
8
0716
TM21
Timer 4 latch (8)
8
Timer 4
interrupt request
Timer 4 (8)
TM21
TM24
TM23
8
8
TM16
Timer 5 latch (8)
8
Selection gate: Connected to
black side at
reset
Timer 5
interrupt request
Timer 5 (8)
TM27
TM25
TM1 : Timer mode register 1
TM2 : Timer mode register 2
T3SC : Timer 3 count source
8
8
switch bit (address 00C716)
CM : CPU mode register
Timer 6 latch (8)
8
Timer 6
interrupt request
Timer 6 (8)
8
TM17
TM26
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal.
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 8.4.3 Timer Block Diagram
Rev. 1.3
25
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.5 SERIAL I/O
The operation of the serial I/O is described below. The operation of
This microcomputer has a built-in serial I/O which can either transmit
or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 8.5.1. The synchro-
nous clock I/O pin (SCLK), and data output pin (SOUT) also function
as port P4, data input pin (SIN) also functions as port P20–P22.
Bit 3 of the serial I/O mode register (address 00EB16) selects whether
the synchronous clock is supplied internally or externally (from the
SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use the SIN
pin for serial I/O, set the corresponding bit of the port P2 direction
register (address 00C516) to “0.”
the serial I/O differs depending on the clock source; external clock or
internal clock.
XCIN
1/2
Data bus
XIN
Frequency divider
1/2 1/4 1/8 1/16
1/2
1/2
CM7
SM1
Selection gate: Connect to
black side at
reset.
SM2
SM0
Synchronous
circuit
S
CM : CPU mode register
SM : Serial I/O mode register
P20
Latch
SM3
Serial I/O
interrupt request
S
CLK
Serial I/O counter (8)
MSB
P21
Latch
SM3
SM5 : LSB
S
OUT
(See note)
SIN
Serial I/O shift register (8)
SM6
8
Note : When the data is set in the serial I/O register (address 00EA16), the register functions as the serial I/O shift register.
Fig. 8.5.1 Serial I/O Block Diagram
Rev. 1.3
26
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Internal clock : The serial I/O counter is set to “7” during the write
External clock : The an external clock is selected as the clock source,
the interrupt request is set to “1” after the transfer clock has been
counted 8 counts. However, transfer operation does not stop, so the
clock should be controlled externally. Use the external clock of 1 MHz
or less with a duty cycle of 50%.
cycle into the serial I/O register (address 00EA16), and the transfer
clock goes HIGH forcibly. At each falling edge of the transfer clock
after the write cycle, serial data is output from the SOUT pin. Transfer
direction can be selected by bit 5 of the serial I/O mode register. At
each rising edge of the transfer clock, data is input from the SIN pin
and data in the serial I/O register is shifted 1 bit.
The serial I/O timing is shown in Figure 8.5.2. When using an exter-
nal clock for transfer, the external clock must be held at HIGH for
initializing the serial I/O counter. When switching between an inter-
nal clock and an external clock, do not switch during transfer. Also,
be sure to initialize the serial I/O counter after switching.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
Notes 1: On programming, note that the serial I/O counter is set by writing to
the serial I/O register with the bit managing instructions, such as SEB
and CLB.
2: When an external clock is used as the synchronous clock, write trans-
mit data to the serial I/O register when the transfer clock input level is
HIGH.
Synchronous clock
Transfer clock
Serial I/O register
write signal
(Note)
Serial I/O output
D0
D1
D2
D3
D4
D5
D6
D7
SOUT
Serial I/O input
S
IN
Interrupt request bit is set to “1”
Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed.
Fig. 8.5.2 Serial I/O Timing (for LSB first)
Rev. 1.3
27
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Serial I/O Mode Register
b7b6 b5b4b3 b2b1b0
0
0
Serial I/O mode register (SM) [Address 00EB16
]
After reset
B
Name
Functions
R W
R W
0
b1 b0
0, 1
Internal synchronous
clock selection bits
(SM0, SM1)
0 0: f(XIN)/4 or f(XCIN)/4
0 1: f(XIN)/16 or f(XCIN)/16
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/64
0
0
R W
R W
2
3
0: External clock
1: Internal clock
Synchronous clock
selection bit (SM2)
0: P20, P21
1: SCLK, SOUT
Port function
selection bit (SM3)
0
0
R W
R W
Fix this bit to “0.”
4
5
6
7
0: LSB first
1: MSB first
Transfer direction
selection bit (SM5)
Transfer clock input
pin selection bit (SM6)
0: Input signal from SIN pin
1: Input signal from SOUT pin
0
0
R W
R W
Fix this bit to “0.”
Fig. 8.5.3 Serial I/O Mode Register
Rev. 1.3
28
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
2
8.6 MULTI-MASTER I C-BUS INTERFACE
Table 8.6.1 Multi-master I C-BUS Interface Functions
2
The multi-master I C-BUS interface is a serial communications cir-
Item
Function
2
cuit, conforming to the Philips I C-BUS data transfer format. This
2
In conformity with Philips I C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Format
2
Figure 8.6.1 shows a block diagram of the multi-master I C-BUS in-
2
terface and Table 8.6.1 shows multi-master I C-BUS interface func-
2
tions.
In conformity with Philips I C-BUS
standard:
2
2
This multi-master I C-BUS interface consists of the I C address reg-
Master transmission
Master reception
Slave transmission
Slave reception
2
2
2
ister, the I C data shift register, the I C clock control register, the I C
Communication mode
2
control register, the I C status register and other control circuits.
SCL clock frequency 16.1 kHz to 400 kHz (at φ = 4 MHz)
φ : System clock = f(XIN)/2
Note : We are not responsible for any third party’s infringement of patent rights
or other rights attributable to the use of the control function (bits 6 and 7
of the I2C control register at address 00F916) for connections between
the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
I2C address register (S0D)
b7
b0
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Address comparator
Serial
data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b7
b0
I2C data shift register
b7
b0
S0
AL AAS AD0 LRB
MST TRX BB PIN
I2C status
AL
register (S1)
circuit
Internal data bus
BB
circuit
Noise
elimination
circuit
Serial
clock
(SCL)
Clock
control
circuit
b7
b0
b7
BSEL1 BSEL0
b0
FAST
MODE
10BIT
SAD
ACK
BIT
ALS
CCR4 CCR3 CCR2 CCR1 CCR0
ACK
ESO BC2 BC1 BC0
I2C control register (S1D)
System clock (φ)
I2C clock control register (S2)
Clock division
Bit counter
2
Fig. 8.6.1 Block Diagram of Multi-master I C-BUS Interface
Rev. 1.3
29
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
8.6.1 I C Data Shift Register
2
The I C data shift register (S0 : address 00F616) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
2
The I C data shift register is in a write enable status only when the
2
ESO bit of the I C control register (address 00F916) is “1.” The bit
2
counter is reset by a write instruction to the I C data shift register.
2
When both the ESO bit and the MST bit of the I C status register
(address 00F816) are “1,” the SCL is output by a write instruction to
2
2
the I C data shift register. Reading data from the I C data shift regis-
ter is always enabled regardless of the ESO bit value.
Note: To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
2
I C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C data shift register1(S0) [Address 00F616
]
B
Name
Functions
After reset
R
R
W
W
0
to
7
D0 to D7 This is an 8-bit shift register to store
receive data and write transmit data.
Indeterminate
2
Note:
To write data into the I C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 8.6.2 Data Shift Register
Rev. 1.3
30
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
8.6.2 I C Address Register
2
The I C address register (address 00F716) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition are detected.
(1) Bit 0: read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
2
is compared with the contents (SAD6 to SAD0 + RBW) of the I C
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
(2) Bits 1 to 7: slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
2
I C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716
]
B
Name
Functions
After reset R W
<Only in 10-bit addressing (in slave) mode>
The last significant bit of address data is
compared.
0
Read/write bit
(RBW)
0
R —
0: Wait the first byte of slave address after
START condition
(read state)
1: Wait the first byte of slave address after
RESTART condition
(write state)
Slave address
(SAD0 to SAD6)
<In both modes>
The address data is compared.
1
to
7
0
R W
2
Fig. 8.6.3 I C Address Register
Rev. 1.3
31
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
8.6.3 I C Clock Control Register
(4) Bit 7: ACK clock bit (ACK)
2
The I C clock control register (address 00FA16) is used to set ACK
This bit specifies a mode of acknowledgment which is an acknowl-
edgment response of data transmission. When this bit is set to “0,”
the no ACK clock mode is set. In this case, no ACK clock occurs
after data transmission. When the bit is set to “1,” the ACK clock
mode is set and the master generates an ACK clock upon comple-
tion of each 1-byte data transmission.The device for transmitting
address data and control data releases the SDA at the occurrence of
anACK clock (make SDAHIGH) and receives the ACK bit generated
by the data receiving device.
control, SCL mode and SCL frequency.
(1) Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency.
(2) Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the stan-
dard clock mode is set. When the bit is set to “1,” the high-speed
clock mode is set.
Note: Do not write data into the I2C clock control register during transmission.
If data is written during transmission, the I2C clock generator is reset, so
that data cannot be transmitted normally.
(3) Bit 6: ACK bit (ACK BIT)
This bit sets the SDAstatus when anACK clock is generated. When
✽
this bit is set to “0,” the ACK return mode is set and SDA goes to
LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status
at the occurrence of an ACK clock.
However, when the slave address matches the address data in the
reception of address data at ACK BIT = “0,” the SDAis automatically
made LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA is automatically made
HIGH (ACK is not returned).
✽ACK clock: Clock for acknowledgement
2
I C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C clock control register (S2 : address 00FA16
)
After reset
0
B
Name
Functions
R W
R W
0
to
4
Setup value Standard clock High speed
SCL frequency control
bits
(CCR0 to CCR4)
of CCR4–
CCR0
00 to 02
mode
clock mode
Setup disabled Setup disabled
Setup disabled
333
03
04
05
06
Setup disabled
250
400 (See note)
100
83.3
166
500/CCR value 1000/CCR value
17.2
16.6
16.1
34.5
33.3
32.3
1D
1E
1F
(at φ = 4 MHz, unit : kHz)
5
SCL mode
specification bit
(FAST MODE)
0: Standard clock mode
1: High-speed clock mode
0
R W
6
7
ACK bit
(ACK BIT)
0: ACK is returned.
1: ACK is not returned.
0
0
R W
R W
ACK clock bit
(ACK)
0: No ACK clock
1: ACK clock
Note: At 4000kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
2
Fig. 8.6.4 I C Address Register
Rev. 1.3
32
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
8.6.4 I C Control Register
(3) Bit 4: data format selection bit (ALS)
2
The I C control register (address 00F916) controls the data commu-
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that ad-
dress data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a gen-
nication format.
(1) Bits 0 to 2: bit counter (BC0–BC2)
2
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
eral call (refer to “8.6.5 I C Status Register,” bit 1) is received, trans-
mission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recog-
nized.
When a START condition is received, these bits become “0002” and
the address data is always transmitted and received in 8 bits.
(4) Bit 5: addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
2
(2) Bit 3: I C interface use enable bit (ESO)
2
This bit enables usage of the multimaster I C BUS interface. When
2
this bit is set to “0,” the use disable status is provided, so the SDA
and the SCL become high-impedance. When the bit is set to “1,” use
of the interface is enabled.
the high-order 7 bits (slave address) of the I C address register (ad-
dress 00F716) are compared with address data. When this bit is set
2
to “1,” the 10-bit addressing format is selected, all the bits of the I C
When ESO = “0,” the following is performed.
address register are compared with address data.
2
• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I C
status register at address 00F816 ).
(5) Bits 6 and 7: connection control bits between
I2C-BUS interface and ports
(BSEL0, BSEL1)
2
• Writing data to the I C data shift register (address 00F616) is dis-
abled.
These bits controls the connection between SCL and ports or SDA
and ports (refer to Figure 8.6.5).
“0”
“1” BSEL0
SCL/P1
1
“0”
“1” BSEL1
SCL
SCL2/P1
2
Multi-master
I2C-BUS
interface
“0”
“1” BSEL0
SDA1/P1
SDA2/P1
3
4
“0”
“1” BSEL1
SDA
Note: Set the corresponding direction register to “1” to use the
2
port as multi-master I C-BUS interface.
Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1
Rev. 1.3
33
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
I C Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D address 00F916)
B
Name
Functions
After reset R W
Bit counter
(Number of transmit/recieve
bits)
(BC0 to BC2)
b2 b1 b0
0
0
to
2
R W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 :8
1 :7
0 :6
1 :5
0 :4
1 :3
0 :2
1 :1
I2C-BUS interface use
enable bit (ESO)
0 :Disabled
1 :Enabled
3
4
5
0
R W
Data format selection
bit(ALS)
0
0 :Addressing mode
1 :Free data format
R W
Addressing format selection
bit (10BIT SAD)
0
0 :7-bit addressing format
1 :10-bit addressing format
R W
b7 b6 Connection port (See note)
0
6, 7 Connection control bits
between I2C-BUS interface
and ports
R W
0
0
1
1
0 :None
1 :SCL1, SDA1
0 :SCL2, SDA2
1 :SCL1, SDA1
SCL2, SDA2
Note: When using ports P11-P14 as I2C-BUS interface, the output structure changes
automatically from CMOS output to N-channel open-drain output.
2
Fig. 8.6.6 I C Control Register
Rev. 1.3
34
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
8.6.5 I C Status Register
(5) Bit 4: I2C-BUS interface interrupt request bit (PIN)
2
2
The I C status register (address 00F816) controls the I C-BUS inter-
face status. The low-order 4 bits are read-only bits and the high-
order 4 bits can be read out and written to.
This bit generates an interrupt request signal. Each time 1-byte data
is transmitted, the state of the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal is sent to the CPU. The PIN bit
is set to “0” in synchronization with a falling edge of the last clock
(including the ACK clock) of an internal clock and an interrupt re-
quest signal occurs in synchronization with a falling edge of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock
generation is disabled. Figure 8.6.8 shows an interrupt request sig-
nal generating timing chart.
(1) Bit 0: last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is
set to “1.” Except in theACK mode, the last bit value of received data
is input. The state of this bit is changed from “1” to “0” by executing a
The PIN bit is set to “1” in any one of the following conditions.
2
2
write instruction to the I C data shift register (address 00F616).
• Executing a write instruction to the I C data shift register (address
00F616).
(2) Bit 1: general call detecting flag (AD0)
• When the ESO bit is “0”
✽
This bit is set to “1” when a general call whose address data is all
• At reset
“0” is received in the slave mode. By a general call of the master
device, every slave device receives control data after the general
call. The AD0 bit is set to “0” by detecting the STOP condition or
START condition.
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ-
ing when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after
completion of slave address or general call address reception
• In the slave reception mode, with ALS = “1” and immediately after
completion of address data reception
✽General call: The master transmits the general call address “0016”
to all slaves.
(3) Bit 2: slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
(6) Bit 5: bus busy flag (BB)
■In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions.
• The address data immediately after occurrence of a START con-
dition matches the slave address stored in the high-order 7 bits
This bit indicates the status of use of the bus system. When this bit is
set to “0,” this bus system is not busy and a START condition can be
generated. When this bit is set to “1,” this bus system is busy and the
occurrence of a START condition is disabled by the START condition
duplication prevention function (See note).
2
of the I C address register (address 00F716).
• A general call is received.
This flag can be written by software only in the master transmission
mode. In the other modes, this bit is set to “1” by detecting a START
condition and set to “0” by detecting a STOP condition. When the
■In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition.
2
2
• When the address data is compared with the I C address regis-
ESO bit of the I C control register (address 00F916) is “0” and at
ter (8 bits consists of slave address and RBW), the first bytes
match.
reset, the BB flag is kept in the “0” state.
■The state of this bit is changed from “1” to “0” by executing a write
(7) Bit 6: communication mode specification bit
(transfer direction specification bit: TRX)
2
instruction to the I C data shift register (address 00F616).
This bit decides the direction of transfer for data communication. When
this bit is “0,” the reception mode is selected and the data of a trans-
mitting device is received. When the bit is “1,” the transmission mode
is selected and address data and control data are output into the
SDA in synchronization with the clock generated on the SCL.
✽
(4) Bit 3: arbitration lost detecting flag (AL)
n the master transmission mode, when a device other than the mi-
crocomputer sets the SDA to “L,”, arbitration is judged to have been
lost, so that this bit is set to “1.”At the same time, the TRX bit is set to
“0,” so that immediately after transmission of the byte whose arbitra-
tion was lost is completed, the MST bit is set to “0.” When arbitration
is lost during slave address transmission, the TRX bit is set to “0” and
the reception mode is set. Consequently, it becomes possible to re-
ceive and recognize its own slave address transmitted by another
master device.
2
When theALS bit of the I C control register (address 00F916) is “0” in
the slave reception mode is selected, the TRX bit is set to “1” (trans-
mit) if the least significant bit (R/W bit) of the address data transmit-
ted by the master is “1.” When the ALS bit is “0” and the R/W bit is
“0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
✽Arbitration lost: The status in which communication as a master is
• When a STOP condition is detected.
disabled.
• When occurence of a START condition is disabled by the START
condition duplication prevention function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
Rev. 1.3
35
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Note:The START condition duplication prevention function disables the START
(8) Bit 7: Communication mode specification bit
condition generation, reset of bit counter reset, and SCL output, when
the following condition is satisfied:
a START condition is set by another master device.
(master/slave specification bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the
clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when
arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START
condition duplication preventing function (Note).
• At reset
2
I C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816
]
B
Name
Functions
After reset R W
0
Last receive bit (LRB)
(See note)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
Indeterminate
R —
(See note)
1
2
General call detecting flag
(AD0) (See note)
0 : No general call detected
1 : General call detected
0
R —
(See note)
Slave address comparison
flag (AAS) (See note)
0 : Address mismatch
1 : Address match
0
R —
(See note)
(See note)
3
4
5
Arbitration lost detecting flag 0 : Not detected
(AL) (See note)
0
R —
1 : Detected
I2C-BUS interface interrupt
request bit (PIN)
0 : Interrupt request issued
1 : No interrupt request issued
1
R W
Bus busy flag (BB)
0 : Bus free
1 : Bus busy
0
R W
0
6, 7
Communication mode
specification bits
(TRX, MST)
b7 b6
R W
0
0
1
1
0 : Slave recieve mode
1 : Slave transmit mode
0 : Master recieve mode
1 : Master transmit mode
Note : These bits and flags can be read out, but cannnot be written.
2
Fig. 8.6.7 I C Status Register
SCL
PIN
IICIRQ
Fig. 8.6.8 Interrupt Request Signal Generation Timing
Rev. 1.3
36
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.6.6 START Condition Generation Method
2
When the ESO bit of the I C control register (address 00F916) is “1,”
I2C status register
write signal
2
execute a write instruction to the I C status register (address 00F816)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “0002” and an SCL
for 1 byte is output. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 8.6.9 for the START condition
generation timing diagram, and Table 8.6.2 for the START condition/
STOP condition generation timing table.
SCL
SDA
Setup
time
Hold time
Set time
for BB flag
BB flag
Fig. 8.6.9 START Condition Generation Timing Diagram
8.6.7 STOP Condition Generation Method
2
When the ESO bit of the I C control register (address 00F916) is “1,”
I2C status register
write signal
2
execute a write instruction to the I C status register (address 00F816)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A
STOP condition will then be generated. The STOP condition genera-
tion timing and the BB flag reset timing are different in the standard
clock mode and the high-speed clock mode. Refer to Figure 8.6.10
for the STOP condition generation timing diagram, and Table 8.6.2
for the START condition/STOP condition generation timing table.
SCL
Setup
time
Hold time
SDA
Reset time
for BB flag
BB flag
Fig. 8.6.10 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Tim-
ing Table
Item
Standard Clock Mode High-speed Clock Mode
Setup time
(START condition)
Setup time
(STOP condition)
Hold time
5.0 µs (20 cycles)
2.5 µs (10 cycles)
4.25 µs (17 cycles)
5.0 µs (20 cycles)
3.0 µs (12 cycles)
1.75 µs (7 cycles)
2.5 µs (10 cycles)
1.5 µs (6 cycles)
Set/reset time
for BB flag
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
Rev. 1.3
37
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.6.8 START/STOP Condition Detect Conditions
8.6.9 Address Data Communication
The START/STOP condition detect conditions are shown in
Figure 8.6.11 and Table 8.6.3. Only when the 3 conditions of Table
8.6.3 are satisfied, a START/STOP condition can be detected.
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
Note: When
a STOP condition is detected in the slave mode
(1) 7-bit addressing format
(MST = 0), an interrupt request signal “IICIRQ” is generated to the
CPU.
2
To meet the 7-bit addressing format, set the 10BIT SAD bit of the I C
control register (address 00F916) to “0.” The first 7-bit address data
transmitted from the master is compared with the high-order 7-bit
2
slave address stored in the I C address register (address 00F716).
At the time of this comparison, address comparison of the RBW bit of
2
the I C address register (address 00F716) is not made. For the data
transmission format when the 7-bit addressing format is selected,
refer to Figure 8.6.12, (1) and (2).
SCL release time
SCL
Setup
Hold time
time
SDA
(2) 10-bit addressing format
(START condition)
Setup
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
Hold time
time
2
I C control register (address 00F916) to “1.” An address comparison
SDA
(STOP condition)
is made between the first-byte address data transmitted from the
2
master and the 7-bit slave address stored in the I C address register
(address 00F716). At the time of this comparison, an address com-
Fig. 8.6.11 START Condition/STOP Condition Detect Timing Dia-
gram
2
parison between the RBW bit of the I C address register (address
00F716) and the R/W bit which is the last bit of the address data
transmitted from the master is made. In the 10-bit addressing mode,
the R/W bit which is the last bit of the address data not only specifies
the direction of communication for control data but also is processed
as an address data bit.
Table 8.6.3 START Condition/STOP Condition Detect Conditions
Standard Clock Mode
High-speed Clock Mode
When the first-byte address data matches the slave address, the
6.5 µs (26 cycles) < SCL
1.0 µs (4 cycles) < SCL
2
AAS bit of the I C status register (address 00F816) is set to “1.” After
release time
release time
2
the second-byte address data is stored into the I C data shift register
3.25 µs (13 cycles) < Setup time
3.25 µs (13 cycles) < Hold time
0.5 µs (2 cycles) < Setup time
0.5 µs (2 cycles) < Hold time
(address 00F616), make an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd bytes matches the slave address, set the RBW bit of
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the num-
ber of φ cycles.
2
the I C address register (address 00F716) to “1” by software. This
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
2
of the I C address register (address 00F716). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 8.6.12, (3) and (4).
Rev. 1.3
38
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.6.10 Example of Master Transmission
8.6.11 Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
2
2
➀ Set a slave address in the high-order 7 bits of the I C address
➀ Set a slave address in the high-order 7 bits of the I C address
register (address 00F716) and “0” in the RBW bit.
register (address 00F716) and “0” in the RBW bit.
➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in
➁Set the noACK clock mode and SCL = 400 kHz by setting “2516” in
2
2
the I C clock control register (address 00FA16).
the I C clock control register (address 00FA16).
2
2
➂ Set “1016” in the I C status register (address 00F816) and hold the
➂Set “1016” in the I C status register (address 00F816) and hold the
SCL at the HIGH.
SCL at the HIGH.
2
2
➃Set a communication enable status by setting “4816” in the I C
➃Set a communication enable status by setting “4816” in the I C
control register (address 00F916).
control register (address 00F916).
➄ Set the address data of the destination of transmission in the high-
➄When a START condition is received, an address comparison is
made.
2
order 7 bits of the I C data shift register (address 00F616) and set
“0” in the least significant bit.
➅•When all transmitted address are“0” (general call):
2
2
➅ Set “F016” in the I C status register (address 00F816) to generate
AD0 of the I C status register (address 00F816) is set to “1”and
a START condition. At this time, an SCL for 1 byte and an ACK
an interrupt request signal occurs.
clock automatically occurs.
•When the transmitted addresses match the address set in ➀:
2
2
➆ Set transmit data in the I C data shift register (address 00F616). At
ASS of the I C status register (address 00F816) is set to “1” and
this time, an SCL and an ACK clock automatically occurs.
an interrupt request signal occurs.
•In the cases other than the above:
➇When transmitting control data of more than 1 byte, repeat step ➆.
2
2
➈ Set “D016” in the I C status register (address 00F816). After this, if
AD0 and AAS of the I C status register (address 00F816) are set
ACK is not returned or transmission ends, a STOP condition will
be generated.
to “0” and no interrupt request signal occurs.
2
➆ Set dummy data in the I C data shift register (address 00F616).
➇When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
Rev. 1.3
39
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
S
Slave address R/W
7 bits “0”
A
Data
A
Data
A/A
P
P
A
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
R/W
“1”
S
Slave address
7 bits
A
Data
A
Data
A
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
Slave address
1st 7 bits
Slave address
2nd byte
S
R/W
“0”
A
A
Data
1 to 8 bits
Data
A/A
P
7 bits
8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
Slave address
1st 7 bits
Slave address
2nd byte
Slave address
1st 7 bits
S
R/W
“0”
A
A
Sr
R/W Data
A
Data
A
P
7 bits
8 bits
7 bits
“1” 1 to 8 bits
1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
From master to slave
From slave to master
Fig. 8.6.12 Address Data Communication Format
8.6.12 Precautions when using multi-master
(2) START condition generating procedure us-
ing multi-master
2
I C-BUS interface
➀Procedure example (The necessary conditions of the generating
(1) Read-modify-write instruction
The precautions when the raead-modify-write instruction such as SEB,
procedure are described as the following ➁ to ➄).
2
CLB etc. is executed for each register of the multi-master I C-BUS
•
•
interface are described below.
2
•I C data shift register (S0)
LDA
SEI
—
(Taking out of slave address value)
(Interrupt disabled)
When executing the read-modify-write instruction for this register
during transfer, data may become a value not intended.
BBS 5,S1,BUSBUSY (BB flag confirming and branch process)
BUSFREE:
STA S0
2
•I C address register (S0D)
When the read-modify-write instruction is executed for this register
at detecting the STOP condition, data may become a value not
intended. It is because hardware changes the read/write bit (RBW)
at the above timing.
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
LDM #$F0, S1
CLI
•
•
2
•I C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
BUSBUSY:
CLI
(Interrupt enabled)
2
•I C control register (S1D)
•
•
When the read-modify-write instruction is executed for this register
at detecting the START condition or at completing the byte transfer,
data may become a value not intended. Because hardware changes
the bit counter (BC0–BC2) at the above timing.
➁Use “STA,” “STX” or “STY” of the zero page addressing instruction
2
for writing the slave address value to the I C data shift register.
2
•I C clock control register (S2)
➂Use “LDM” instruction for setting trigger of START condition gener-
ating.
The read-modify-write instruction can be executed for this register.
➃Write the slave address value of above ➁and set trigger of START
condition generating of above ➂ continuously shown the above
procedure example.
➄Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
Rev. 1.3
40
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(3) RESTART condition generating procedure
(4) STOP condition generating procedure
➀Procedure example (The necessary conditions of the generating
procedure are described as the following ➁ to ➃.)
➀Procedure example (The necessary conditions of the generating
procedure are described as the following ➁ to ➅.)
Execute the following procedure when the PIN bit is “0.”
•
•
•
•
SEI
(Interrupt disabled)
LDM #$00, S1
(Select slave receive mode)
(Taking out of slave address value)
(Interrupt disabled)
LDM #$C0, S1
NOP
(Select master transmit mode)
(Set NOP)
LDA
SEI
—
LDM #$D0, S1
CLI
(Trigger of STOP condition generating)
(Interrupt enabled)
STA
S0
(Writing of slave address value)
(Trigger of RESTART condition generating)
(Interrupt enabled)
LDM #$F0, S1
•
CLI
•
•
•
➁Write “0” to the PIN bit when master transmit mode is select.
➂Execute “NOP” instruction after setting of master transmit mode.
Also, set trigger of STOP condition generating within 10 cycles af-
ter selecting of master trasmit mode.
➁Select the slave receive mode when the PIN bit is “0.” Do not write
“1” to the PIN bit. Neither “0” nor “1” is specified for the writing to
the BB bit.
➃Disable interrupts during the following two process steps:
• Select of master transmit mode
The TRX bit becomes “0” and the SDA pin is released.
➂The SCL pin is released by writing the slave address value to the
• Trigger of STOP condition generating
2
I C data shift register. Use “STA,” “STX” or “STY” of the zero page
2
addressing instruction for writing.
(5) Writing to I C status register
➃Use “LDM” instruction for setting trigger of RESTART condition gen-
erating.
Do not execute an instruction to set the PIN bit to “1” from “0” and an
instruction to set the MST and TRX bits to “0” from “1” simultaneously.
It is because it may enter the state that the SCL pin is released and
the SDA pin is released after about one machine cycle. Do not ex-
ecute an instruction to set the MST and TRX bits to “0” from “1” si-
multaneously when the PIN bit is “1.” It is because it may become the
same as above.
➄Write the slave address value of above ➂ and set trigger of RE-
START condition generating of above ➃ continuously shown the
above procedure example.
➅Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating
(6) Process of after STOP condition generating
2
2
Do not write data in the I C data shift register S0 and the I C status
register S1 until the bus busy flag BB becomes “0” after generating
the STOP condition in the master mode. It is because the STOP
condition waveform might not be normally generated. Reading to the
above registers do not have the problem.
Rev. 1.3
41
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.7 PWM OUTPUT FUNCTION
This microcomputer is equipped with six 8-bit PWMs (PWM0–
PWM5). PWM0–PWM5 have the same circuit structure and an 8-bit
resolution with minimum resolution bit width of 4 µs (for f(XIN) = 8
MHz) and repeat period of 1024 µs (for f(XIN) = 8 MHz).
Figure 8.7.1 shows the PWM block diagram. The PWM timing gen-
erating circuit applies individual control signals to PWM0–PWM5 us-
ing f(XIN) divided by 2 as a reference signal.
8.7.1 Data Setting
When outputting PWM0–PWM5, set 8-bit output data to the PWMi
register (i means 0 to 5; addresses 020016 to 020516).
8.7.2 Transmitting Data from Register to PWM
circuit
Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is
executed at writing data to the register.
The signal output from the 8-bit PWM output pin corresponds to the
contents of this register.
8.7.3 Operating of 8-bit PWM
The following explains PWM operation.
First, set the bit 0 of PWM mode register 1 (address 020816) to “0”
(at reset, bit 0 is already set to “0” automatically), so that the PWM
count source is supplied.
PWM0–PWM5 are also used as pins P00–P05. Set the correspond-
ing bits of the port P0 direction register to “1” (output mode). And
select each output polarity by bit 3 of PWM mode register 1 (address
020816). Then, set bits 5 to 0 of PWM mode register 2 (address
020916) to “1” (PWM output).
The PWM waveform is output from the PWM output pins by setting
these registers.
Figure 17 shows the 8-bit PWM timing. One cycle (T) is composed
8
of 256 (2 ) segments. The 8 kinds of pulses relative to the weight of
each bit (bits 0 to 7), are output inside the circuit during 1 cycle.
Refer to Figure 17 (a). The 8-bit PWM outputs waveform which is
the logical sum (OR) of pulses corresponding to the contents of bits
0 to 7 of the 8-bit PWM register. Several examples are shown in
Figure 17 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are
selected by changing the contents of the PWM register. A length of
entirely HIGH cannot be output, i.e. 256/256.
8.7.4 Output after Reset
At reset, the output of ports P00–P05 is in the high-impedance state,
and the contents of the PWM register and the PWM circuit are unde-
fined. Note that after reset, the PWM output is undefined until setting
the PWM register.
Rev. 1.3
42
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data bus
PWM timing
generating
XIN
1/2
circuit
PM10
PWM0 register
(Address 020016
)
b7
b0
8
PWM0
PWM1
PM13
D0
D0
0
1
P0
0
8-bit PWM circuit
PM20
P0
1
PM21
P0
PM22
P0
PM23
P0
PM24
P0
PM25
PWM1 register (Address 020116
PWM2 register (Address 020216
PWM3 register (Address 020316
PWM4 register (Address 020416
PWM5 register (Address 020516
)
)
)
)
)
PWM2
PWM3
PWM4
PWM5
D0
D0
D0
D0
2
3
4
5
2
3
4
5
Selection gate:
Connected to
black side at
reset.
PM1 : PWM mode register 1 (address 0208 16
PM2 : PWM mode register 2 (address 0209 16
P0 : Port P0 register (address 00C016
D0 : Port P0 direction register (address 00C1 16
)
)
)
)
Inside of
is as same contents with the others.
Fig. 8.7.1 PWM Block Diagram
Rev. 1.3
43
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Fig. 8.7.2 PWM Timing
Rev. 1.3
44
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PWM Mode Register 1
b7b6 b5b4b3 b2b1b0
PWM mode register 1 (PM1) [Address 020816
]
After reset
0
B
0
Name
Functions
R W
PWM counts source
selection bit (PM10)
0 : Count source supply
1 : Count source stop
W
R
1, 2
3
—
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Indeterminate
0
R
PWM output polarity
selection bit (PM13)
0 : Positive polarity
1 : Negative polarity
R W
4
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
—
R
Indeterminate
Fig. 8.7.3 PWM Mode Register 1
PWM Mode Register 2
b7b6 b5b4b3 b2b1b0
0 0
PWM mode register 2 (PM2) [Address 0209 16]
B
0
Name
P00/PWM0 output
selection bit (PM20)
Functions
0 : P00 output
1 : PWM0 output
After reset R W
0
R W
1
2
3
4
0 : P01 output
1 : PWM1 output
P01/PWM1 output
selection bit (PM21)
0
0
0
R W
R W
R W
P02/PWM2 output
selection bit (PM22)
0 : P02 output
1 : PWM2 output
P03/PWM3 output
selection bit (PM23)
0 : P03 output
1 : PWM3 output
P04/PWM4 output
selection bit (PM24)
0
R W
0 : P04 output
1 : PWM4 output
P05/PWM5 output
selection bit (PW25)
5
0
0
R W
R W
0: P05 output
1: PWM5 output
Fix these bits to “0.”
6, 7
Fig. 8.7.4 PWM Mode Register 2
Rev. 1.3
45
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.8 A-D COMPARATOR
A-D comparator consists of 6-bit D-A converter and comparator. A-D
comparator block diagram is shown in Figure 8.8.1.
The reference voltage “Vref” for D-Aconversion is set by bits 0 to 5 of
A-D control register 2 (address 00ED16).
The comparison result of the analog input voltage and the reference
voltage “Vref” is stored in bit 4 of A-D control register 1 (address
00EC16).
For A-D comparison, set “0” to corresponding bits of the direction
register to use ports as analog input pins. Write the data for select of
analog input pins to bits 0 to 2 of A-D control register 1 and write the
digital value corresponding to Vref to be compared to the bits 0
to 5 of A-D control register 2. The voltage comparison starts by writ-
ing to A-D control register 2, and it is completed after 16 machine
cycles (NOP instruction ✕ 8).
Data bus
A-D control register 1
Bits 0 to 2
Comparator control
A-D control
register 1
A-D control
register 2
AD1
AD2
AD3
AD4
AD5
AD6
Analog
signal
switch
Compa-
rator
Bit 4
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Switch tree
Resistor ladder
Fig. 8.8.1 A-D Comparator Block Diagram
Rev. 1.3
46
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
A-D Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (AD1) [Address 00EC16
]
B
Name
Functions
After reset R W
0
to
2
Analog input pin selection
bits
(ADC10 to ADC12)
b2 b1 b0
0
R W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : AD1
1 : AD2
0 : AD3
1 : AD4
0 : AD5
1 : AD6
0 :
Do not set.
1 :
3
4
This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
—
R
0: Input voltage < reference voltage
1: Input voltage > reference voltage
Storage bit of comparison
result (ADC14)
Indeterminate R W
5
to
7
Nothing is assigned. This bits are write disable bits.
When these bits are read out, the values are “0.”
0
—
R
Fig. 8.8.2 A-D Control Register 1
A-D Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 2 (AD2) [Address 00ED16
]
B
Name
Functions
After reset
R
R
W
W
b5 b4 b3 b2 b1 b0
0
to
5
D-A converter set bits
(ADC20 to ADC25)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0 : 1/128Vcc
1 : 3/128Vcc
0 : 5/128Vcc
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1 : 123/128Vcc
0 : 125/128Vcc
1 : 127/128Vcc
Nothing is assigned. These bits are write disable bits.
When these bits are reed out, the values are “ 0.”
0
R
—
6, 7
Fig. 8.8.3 A-D Control Register 2
Rev. 1.3
47
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.9 ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses can be
corrected, a program for correction is stored in the ROM correction
vector in RAM as the top address. The ROM correction vectors are 2
vectors.
ROM correction address 1 (high-order) 020A16
ROM correction address 1 (low-order) 020B16
ROM correction address 2 (high-order) 020C16
Vector 1 : address 030016
Vector 2 : address 032016
Set the address of the ROM data to be corrected into the ROM cor-
rection address register. When the value of the counter matches the
ROM data address in the ROM correction vector as the top address,
the main program branches to the correction program stored in the
ROM memory for correction. To return from the correction program
to the main program, the op code and operand of the JMP instruction
(total of 3 bytes) are necessary at the end of the correction program.
The ROM correction function is controlled by the ROM correction
enable register.
ROM correction address 2 (low-order)
020D16
Fig. 8.9.1 ROM Correction Address Registers
Notes 1: Specify the first address (op code address) of each
instruction as the ROM correction address.
2: Use the JMP instruction (total of 3 bytes) to return from
the correction program to the main program.
3: Do not set the same ROM correction address to vectors 1
and 2.
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 020E 16
]
After reset
0
B
Name
Functions
R W
R W
0
Vector 1 enable bit (RC0)
0: Disabled
1: Enabled
1
Vector 2 enable bit (RC1)
0: Disabled
1: Enabled
0
0
R W
R —
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
2
to
7
Fig. 8.9.2 ROM Correction Enable Register
Rev. 1.3
48
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.10 DATA SLICER
When the data slicer function is not used, the data slicer circuit and
This microcomputer includes the data slicer function for the closed
caption decoder (referred to as the CCD). This function takes out the
caption data superimposed in the vertical blanking interval of a com-
posite video signal. A composite video signal which makes the sync
chip’s polarity negative is input to the CVIN pin.
the timing signal generating circuit can be cut off by setting bit 0 of
the data slicer control register 1 (address 00E016) to “0.” These set-
tings can realize the low-power dissipation.
0.1 µF
1 MΩ
Composite
video
signal
470 Ω
1 kΩ
Sync pulse counter
register
560 pF
1 µF
200 pF
(address 00E916
)
CVIN
H
SYNC
HLF
Synchronizing
signal counter
Data slicer control register 2
(address 00E116
Clamping
circuit
)
Synchronizing
separation
circuit
Low-pass
filter
Sync slice
circuit
Data slicer control register 1
(address 00E016
)
Timing signal
generating
circuit
Data slicer ON/OFF
VHOLD
Reference
voltage
generating
circuit
+
–
Clock run-in
determination
circuit
1000 pF
Comparator
Clock run-in defect register
(address 00E416
)
Data slice line
specification
circuit
Caption position register
(address 00E616
Start bit detecting
circuit
)
External circuit
Note : Make the length of wiring which is
Data clock
connected to VHOLD, HLF, and CVIN pin as
short as possible so that a leakage current
may not be generated when mounting a
resistor or a capacitor on each pin.
generating circuit
Data clock position register
(address 00E516
)
16-bit shift register
Data slicer
interrupt
request
Interrupt request
generating circuit
high-order
low-order
Caption data register 1
(address 00E216)
Caption data register 2
(address 00E316)
Caption data register 4
(address 00CF16)
Caption data register 3
(address 00CE16)
Data bus
Fig. 8.10.1 Data Slicer Block Diagram
Rev. 1.3
49
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.10.1 Notes When not Using Data Slicer
When bit 0 of data slicer control register 1 (address 00E016) is “0,”
terminate the pins as shown in Figure 8.10.2.
<When data slicer circuit and timing signal generating circuit is in OFF state>
Apply the same voltage as V CC to
AVCC pin.
AVCC
19
Leave HLF pin open.
Open
Open
HLF
20
21
22
Leave VHOLD pin open.
V
HOLD
CVIN
Pull-down CVIN pin to VSS through
a resistor of 5 kΩ or more.
5 kΩ or more
Fig. 8.10.2 Termination of Data Slicer Input/Output Pins when Data Slicer Circuit and Timing Generating Circuit Is in OFF State
When both bits 0 and 2 of data slicer control register 1 (address
00E016) are “1,” terminate the pins as shown in Figure 8.10.3.
<When using a reference clock generated in timing signal generating circuit as OSD clock>
Apply the same voltage as V CC to AVCC pin.
AVCC
19
1 kΩ
HLF
Connect the same external circuit as when
using data slicer to HLF pin.
20
21
1 µF
200pF
Open
VHOLD
Leave VHOLD pin open.
Pull-up CVIN to VCC through a resistor
of 5 kΩ or more.
5 kΩ or more
CVIN
22
Fig. 8.10.3 Termination of Data Slicer Input/Output Pins when Timing Signal Generating Circuit Is in ON State
Rev. 1.3
50
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Figures 8.10.4 and 8.10.5 the data slicer control registers.
Data Slicer Control Register 1
b7b6b5b4b3b2b1b0
0
1 1 0 0
Data slicer control register 1(DSC1) [Address 00E016
]
B
0
Name
Functions
0: Stopped
1: Operating
After reset
0
R
R
W
W
Data slicer and timing signal
generating circuit control bit (DSC10)
1
2
0: F2
1: F1
0
0
0
R
R
R
W
W
W
Selection bit of data slice reference
voltage generating field (DSC11)
0: Video signal
1: HSYNC signal
Reference clock source
selection bit (DSC12)
3, 4
Fix these bits to “0.”
5, 6
7
0
0
R
R
W
W
Fix these bits to “1.”
Fix this bit to “0.”
Definition of fields 1 (F1) and 2 (F2)
sep
H
F1:
F2:
sep
V
sep
H
sep
V
Fig. 8.10.4 Data Slicer Control Register 1
Data Slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Data slicer control register 2 (DSC2) [Address 00E116
]
0
1
After reset
R
R
W
—
B
0
Name
Functions
0: Data is not latched yet
and a clock-run-in is not
determined.
1: Data is latched and a
clock-run-in is determined.
Indeterminate
Caption data latch
completion flag 1
(DSC20)
Fix this bit to “1.”
Test bit
0
R
R
R
R
1
W
—
—
W
2
Read-only
Indeterminate
Indeterminate
0
3
4
0: F2
1: F1
Field determination
flag(DSC23)
0: Method (1)
1: Method (2)
Vertical synchronous signal
(Vsep) generating method
selection bit (DSC24)
5
6
0: Match
1: Mismatch
Indeterminate
R
—
V-pulse shape
determination flag (DSC25)
0
Fix this bit to “o.”
Test bit
R
R
W
—
Read-only
7
Indeterminate
Definition of fields 1 (F1) and 2 (F2)
sep
H
F1:
sep
V
sep
H
F2:
sep
V
Fig. 8.10.5 Data Slicer Control Register 2
Rev. 1.3
51
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.10.2 Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync chip part of the composite video
signal input from the CVIN pin. The low-pass filter attenuates the noise
of clamped composite video signal. The CVIN pin to which composite
video signal is input requires a capacitor (0.1 µF) coupling outside.
Pull down the CVIN pin with a resistor of hundreds of kiloohms to 1
MΩ. In addition, we recommend to install externally a simple low-
pass filter using a resistor and a capacitor at the CVIN pin (refer to
Figure 8.10.1).
Composite s
Measure LOW period
Timing
signal
Vsep signal
8.10.3 Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter.
A Vsep signal is generated at a rising of the timing signal
immediately after the LOW level width of the composite
sync signal exceeds a certain time.
8.10.4 Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
Fig. 8.10.6 Vsep Generating Timing (method 2)
(1)Horizontal Synchronous Signal (Hsep)
A one-shot horizontal synchronizing signal Hsep is generated at
the falling edge of the composite sync signal.
(2)Vertical Synchronous Signal (Vsep)
As a Vsep signal generating method, it is possible to select one of
the following 2 methods by using bit 4 of the data slicer control
register 2 (address 00E116).
•Method 1 The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, a Vsep
signal is generated in synchronization with the rising
of the timing signal immediately after this LOW level.
•Method 2 The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync sig-
nal exits or not in the LOW level period of the timing
signal immediately after this LOW level. If a falling
exists, a Vsep signal is generated in synchronization
with the rising of the timing signal (refer to Figure
8.10.6).
Figure 8.10.6 shows a Vsep generating timing. The timing signal shown
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 8.10.7, when the A level matches the B level, this bit
is “0.” In the case of a mismatch, the bit is “1.”
Rev. 1.3
52
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.10.5 Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large
as the horizontal synchronous signal frequency. It also generates
various timing signals on the basis of the reference clock, horizontal
synchronous signal and vertical synchronizing signal. The circuit
operates by setting bit 0 of data slicer control register 1 (address
00E016) to “1.”
Bit 5 of
DSC2
0
1
1
The reference clock can be used as a display clock for OSD function
in addition to the data slicer. The HSYNC signal can be used as a
count source instead of the composite sync signal. However, when
the HSYNC signal is selected, the data slicer cannot be used. A count
source of the reference clock can be selected by bit 2 of data slicer
control register 1 (address 00E016).
Composite
sync signal
A
B
For the pins HLF, connect a resistor and a capacitor as shown in
Figure 8.10.1. Make the length of wiring which is connected to these
pins as short as possible so that a leakage current may not be gener-
ated.
Note: It takes a few tens of milliseconds until the reference clock becomes
stable after the data slicer and the timing signal generating circuit are
started. In this period, various timing signals, Hsep signals and Vsep sig-
nals become unstable. For this reason, take stabilization time into con-
sideration when programming.
Fig. 8.10.7 Determination of V-pulse Waveform
Rev. 1.3
53
MITSUBISHI MICROCOMPUTERS
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and ON-SCREEN DISPLAY CONTROLLER
8.10.6 Data Slice Line Specification Circuit
(3) Field determination
(1) Specification of data slice line
The field determination flag can be read out by bit 3 of data slicer
This circuit decides a line on which caption data is superimposed.
The line 21 (fixed), 1 appropriate line for a period of 1 field (total 2
line for a period of 1 field), and both fields (F1 and F2) are sliced
their data. The caption position register (address 00E616) is used
for each setting (refer to Table 8.10.1).
control register 2. This flag charge at the falling edge of Vsep.
The counter is reset at the falling edge of Vsep and is incremented
by 1 every Hsep pulse. When the counter value matched the value
specified by bits 4 to 0 of the caption position register, this Hsep is
sliced.
The values of “0016” to “1F16” can be set in the caption position
register (at setting only 1 appropriate line). Figure 8.10.8 shows
the signals in the vertical blanking interval. Figure 8.10.9 shows
the structure of the caption position register.
(2) Specification of line to set slice voltage
The reference voltage for slicing (slice voltage) is generated for
the clock run-in pulse in the particular line (refer to Table 8.10.1).
The field to generate slice voltage is specified by bit 1 of data
slicer control register 1. The line to generate slice voltage 1 field is
specified by bits 6, 7 of the caption position register (refer to
Table 8.10.1).
Vertical blanking interval
Video signal
Composite
video signal
1 appropriate line is set by
the caption position register
(when setting line 19)
Vsep
Hsep
Line 21
Count value to be set in the caption position register (“0F 16” in this case)
Magnified
drawing
Hsep
Clock run-in
Start bit + 16-bit data
Start bit
Composite video
signal
Window for
deteminating
clock-run-in
Fig. 8.10.8 Signals in Vertical Blanking Interval
Rev. 1.3
54
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and ON-SCREEN DISPLAY CONTROLLER
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0
Caption Position Register (CPS) [Address 00E616]
R
R
W
W
B
Name
Functions
After reset
0
to
4
0
Caption position
bits(CPS0 to CPS4)
5
0: Data is not latched yet and a
clock-run-in is not determined.
1: Data is latched and a
R
—
Caption data latch
completion flag 2
(CPS5)
Indeterminate
clock-run-in is determined.
W
6, 7
Refer to the corresponding
Table (Table 8.10.1).
0
R
Slice line mode
specification bits
(in 1 field) (CPS6, CPS7)
Fig. 8.10.9 Caption Position Register
Table 8.10.1 Specification of Data Slice Line
CPS
Field and Line to Be Sliced Data
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
Field and Line to Generate Slice Voltage
• Field specified by bit 1 of DSC1
b7
0
b6
0
• Line 21 (total 1 line)
• Both fields of F1 and F2
• A line specified by bits 4 to 0 of CPS
(total 1 line) (See note 3)
• Field specified by bit 1 of DSC1
• A line specified by bits 4 to 0 of CPS
(total 1 line) (See note 3)
0
1
1
1
0
1
• Both fields of F1 and F2
• Line 21 (total 1 line)
• Field specified by bit 1 of DSC1
• Line 21 (total 1 line)
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
• Field specified by bit 1 of DSC1
• Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
Notes 1: DSC1 is data slicer control register 1.
CPS is caption position register.
2: Set “0016” to “1016” to bits 4 to 0 of CPS.
3: Set “0016” to “1F16” to bits 4 to 0 of CPS.
Rev. 1.3
55
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and ON-SCREEN DISPLAY CONTROLLER
8.10.7 Reference Voltage Generating Circuit
8.10.8 Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line
specification circuit.
and Comparator
The composite video signal clamped by the clamping circuit is input
to the reference voltage generating circuit and the comparator.
The detection of a start bit is described below.
➀ A sampling clock is generated by dividing the reference clock out-
put by the timing signal.
(1) Reference voltage generating circuit
This circuit generates a reference voltage (slice voltage) by us-
ing the amplitude of the clock run-in pulse in line specified by the
data slice line specification circuit. Connect a capacitor between
the VHOLD pin and the VSS pin, and make the length of wiring as
short as possible so that a leakage current may not be gener-
ated.
➁ A clock run-in pulse is detected by the sampling clock.
➂ After detection of the pulse, a start bit pattern is detected from the
comparator output.
8.10.9 Clock Run-in Determination Circuit
This circuit determinates clock run-in by counting the number of pulses
in a window of the composite video signal.
(2) Comparator
The reference clock count value in one pulse cycle is stored in bits 3
to 7 of the clock run-in detect register (address 00E416). Read out
these bits after the occurrence of a data slicer interrupt (refer to
“8.10.12 Interrupt Request Generating Circuit”).
The comparator compares the voltage of the composite video
signal with the voltage (reference voltage) generated in the refer-
ence voltage generating circuit, and converts the composite video
signal into a digital value.
Figure 8.10.10 shows the structure of clock run-in detect register.
Clock Run-in Detect Register
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register (CRD) [Address 00E416
]
R
R
W
—
B
Name
Functions
After reset
0
0
to
2
Read-only
Test bits
3
to
7
Number of reference clocks to
be counted in one clock run-in
pulse period.
0
R
—
Clock run-in detection bit
(CRD3 to CRD7)
Fig. 8.10.10 Clock Run-in Detect Register
Rev. 1.3
56
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.10.10 Data Clock Generating Circuit
This circuit generates a data clock synchronized with the start bit
detected in the start bit detecting circuit. The data clock stores cap-
tion data to the 16-bit shift register. When the 16-bit data has been
stored and the clock run-in determination circuit determines clock
run-in, the caption data latch completion flag is set. This flag is reset
at a falling of the vertical synchronous signal (Vsep).
Data Clock Position Register
b7 b6 b5 b4 b3 b2 b1 b0
0
1
0
Data clock position register (DPS) [Address 00E516]
R
R
W
W
B
0
Name
Functions
After reset
1
Fix this bit to “0.”
1
Fix this bit to “1.”
Fix this bit to “0.”
0
R
W
2
3
0
1
R
R
W
W
Data clock position set
bits (DPS3 to DPS7)
4
to
7
0
Fig. 8.10.11 Data Clock Position Register
Rev. 1.3
57
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.10.11 16-bit Shift Register
8.10.12 Interrupt Request Generating Circuit
The caption data converted into a digital value by the comparator is
stored into the 16-bit shift register in synchronization with the data
clock. The contents of the high-order 8 bits of the stored caption data
can be obtained by reading out data register 2 (address 00E316) and
data register 4 (address 00CF16). The contents of the low-order 8
bits can be obtained by reading out data register 1 (address 00E216)
and data register 3 (address 00CE16), respectively. These registers
are reset to “0” at a falling of Vsep. Read out data registers 1 and 2
after the occurrence of a data slicer interrupt (refer to “8.10.12 Inter-
rupt Request Generating Circuit”).
The interrupt requests as shown in Table 8.10.3 are generated by
combination of the following bits; bits 6 and 7 of the caption position
register (address 00E616). Read out the contents of data registers 1
to 4 and the contents of bits 3 to 7 of the clock run-in detect register
after the occurrence of a data slicer interrupt request.
Table 8.10.2 Contents of Caption Data Latch Completion Flag and 16-bit Shift Register
Slice Line Specification Mode
CPS
Contents of Caption Data Latch Completion Flag
Contents of 16-bit Shift Register
Completion Flag 1
(bit 0 of DSC2)
Completion Flag 2
(bit 5 of CPS)
Caption Data
Caption Data
Registers 3, 4
Registers 1, 2
bit 7
bit 6
A line specified by
bits 4 to 0 of CPS
16-bit data of line 21
16-bit data of a line specified by
bits 4 to 0 of CPS
0
0
Line 21
A line specified by
bits 4 to 0 of CPS
16-bit data of a line specified
by bits 4 to 0 of CPS
0
1
1
1
0
1
Invalid
Invalid
Invalid
Invalid
Line 21
Line 21
16-bit data of line 21
16-bit data of line 21
A line specified by
bits 4 to 0 of CPS
16-bit data of a line specified by
bits 4 to 0 of CPS
CPS: Caption position register
DSC2: Data slicer control register 2
Table 8.10.3 Occurence Sources of Interrupt Request
Caption position register
Occurence Souces of Interrupt Request at End of Data Slice Line
After slicing line 21
b7
b6
0
0
1
After a line specified by bits 4 to 0 of CPS
After slicing line 21
0
1
1
After slicing line 21
Rev. 1.3
58
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.10.13 Synchronous Signal Counter
The latch value can be obtained by reading out the sync pulse counter
register (address 00E916). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronous signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronous signal Vsep as a count source.
The synchronous signal counter is used when bit 0 of PWM mode
register 1 (address 020816).
13
The count value in a certain time (T time) generated by f(XIN)/2 or
13
f(XIN)/2 is stored into the 5-bit latch. Accordingly, the latch value
Figure 8.10.12 shows the structure of the sync pulse counter and
Figure 8.10.13 shows the synchronous signal counter block diagram.
changes in the cycle of T time. When the count value exceeds “1F16,”
“1F16” is stored into the latch.
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (HC) [Address 00E916
]
R
R
W
—
B
Name
Functions
After reset
0
Count value (HC0 to HC4)
0
to
4
5
Count source (HC5)
0: HSYNC signal
1: Composite sync signal
0
0
R
R
W
—
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
6, 7
Fig. 8.10.12 Sync Pulse Counter Register
f(XIN)/213
Composite
sync signal
Reset
Counter
5-bit counter
H
SYNC signal
Sync pulse
counter register
Latch (5 bits)
b5
Selection gate : connected to black
side when reset.
Data bus
Fig. 8.10.13 Synchronous Signal Counter Block Diagram
Rev. 1.3
59
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.11 OSD FUNCTIONS
Table 8.11.1 outlines the OSD functions.
This microcomputer incorporates an OSD circuit of 32 characters ✕
2 lines. And also, there are 2 display modes and they are selected by
a block unit. The display modes are selected by bits 0 and 1 of block
control register i (i = 1 and 2).
The features of each mode are described below.
Table 8.11.1 Features of Each Display Mode
Display mode
Parameter
CC mode
(Closed caption mode)
OSD mode (Border OFF)
(On-screen display mode)
Number of display characters
Dot structure
32 characters ✕ 2 lines
16 ✕ 26 dots (Character display area : 16 ✕ 20 dots)
254 kinds
16 ✕ 20 dots
Kinds of characters
Kinds of character sizes
1 kinds
8 kinds
Pre-divide ratio (See note)
Dot size
✕ 2 (fixed)
✕ 2, ✕ 3
1T
Smooth italic, under line, flash
1 screen : 8 kinds (per character unit)
1 screen : 8 kinds (per character unit)
C
✕ 1/2H
1T
C
✕ 1/2H, 1T
C ✕ 1H, 2TC ✕ 2H, 3TC ✕ 3H
Attribute
Border (black)
Character font coloring
Character background coloring
OSD output
R, G, B
Possible (per character unit)
Auto solid space function
Window function
Horizontal: 128 levels, Vertical: 512 levels
Possible
Raster coloring
Function
Display position
Display expansion (multiline display)
Notes 1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as “pre-divide ratio” hereafter.
2: The character size is specified with dot size and pre-divide ratio (refer to 8.11.2 Dot Size).
Rev. 1.3
60
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The OSD circuit has an extended display mode. This mode allows
multiple lines (3 lines or more) to be displayed on the screen by inter-
rupting the display each time one line is displayed and rewriting data
in the block for which display is terminated by software.
Figure 8.11.1 shows the configuration of OSD character. Figure 8.11.2
shows the block diagram of the OSD circuit. Figure 8.11.3 shows the
OSD control register. Figure 8.11.4 shows the block control register i.
CC mode
OSD mode
16 dots
16 dots
'Blank area✽
'Underline area✽
'Blank area✽
✽: Displayed only in CCD mode.
Fig. 8.11.1 Configuration of OSD Character Display Area
Rev. 1.3
61
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and ON-SCREEN DISPLAY CONTROLLER
Clock for OSD
OSC1 OSC2
HSYNC VSYNC
Display
oscillation
circuit
Data slicer clock
Control registers for OSD
(address 00D016
OSD Control circuit
)
)
OSD control register
(address 00D116
Horizontal position register
Block control register i
Vertical position register i
Window register i
(addresses 00D216, 00D316
(addresses 00D416, 00D516
(addresses 00D616, 00D716
(address 00D816
(address 00D916
)
)
)
)
)
I/O polarity control register
Raster color register
RAM for OSD
2 bytes ✕ 32 characters ✕ 2 lines
ROM for OSD
16 dots ✕ 20 dots ✕ 254 characters
Shift register
16-bit
Output circuit
R
G
B
OUT1
OUT2
Data bus
Fig. 8.11.2 Block Diagram of OSD Circuit
Rev. 1.3
62
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OSD Control Register
b7 b6 b5b4 b3 b2b1 b0
0
OSD control register (OC) [Address 00D0 16
Functions
]
After reset R
W
B
Name
0 : All-blocks display off
1 : All-blocks display on
0
0
0
0
R W
R W
R W
R W
0
1
2
OSD control bit
(OC0) (See note)
Automatic solid space
control bit (OC1)
0 : OFF
1 : ON
Window control bit
(OC2)
0 : OFF
1 : ON
CC mode clock
selection bit (OC3)
0 : Data slicer clock
1 : Clock from OSC1 pin
3
4
OSD mode clock
selection bit (OC4)
0
0
R W
R W
0 : Data slicer clock
1 : Clock from OSC1 pin
b6 b5
5, 6 OSC1 clock
selection bit
0 0: 32 kHz oscillating
0 1: Do not set.
1 0: LC oscillating,
Ceramic oscillating
1 1: Do not set.
(OC5, OC6)
0
R W
7
Fix this bit to “0.”
Note: Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next V SYNC
.
Fig. 8.11.3 OSD Control Register
Rev. 1.3
63
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Block Control register i
b7 b6 b5b4 b3 b2b1 b0
Block control register i (BCi) (i=1, 2) [Addresses 00D2 16 and 00D316
]
After reset
B
Name
Functions
R W
R W
b1 b0
Indeterminate
0, 1 Display mode
selection bits
(BCi0, BCi1)
0 0: Display OFF
0 1: CC mode
1 0: OSD mode (Border OFF)
1 1: OSD mode (Border ON)
(See note 1)
b4 b3 b2 Pre-divide Ratio Dot Size
Indeterminate
Indeterminate
2, 3 Dot size selection
bits (BCi2, BCi3)
R W
R W
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
0
1
✕ 2
4
Pre-divide ratio
selection bit (BCi4)
✕ 3
5
6
0: OUT1 output control
1: OUT2 output control
OUT1/OUT2 output control
bit (BCi5) (See note 1)
Indeterminate
Indeterminate
R W
R W
Vertical display start
position control bit
(BCi6)
BC16: Block 1
BC26: Block 1
BC17: Window top boundary
BC27: Window bottom boundary
Indeterminate
7
Window top/bottom
boundary control bit
(BCi7)
R W
Notes 1: Bit RA3 of OSD RAM controls OUT1 output when bit 5 is “0.”
Bit RA3 of OSD RAM controls OUT2 output when bit 5 is “1.”
2: Tc is OSD clock cycle divided in pre-divide circuit.
3: H is HSYNC
.
Fig. 8.11.4 Block Control Register i
Rev. 1.3
64
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8.11.1 Display Position
Blocks are displayed in conformance with the following rules:
The display positions of characters are specified in units called a
“block.” There are 2 blocks, blocks 1 and 2. Up to 32 characters can
be displayed in each block (refer to “8.11.5 Memory for OSD”).
The display position of each block can be set in both horizontal and
vertical directions by software.
• When the display position of block 1 is overlapped with that of block
2 (Figure 8.11.5 (b)), the block 1 is displayed on the front.
• When another block display position appears while one block is
displayed (Figure 8.11.5 (c)), the block with a larger set value as
the vertical display start position is displayed.
The display start position in the horizontal direction can be selected
for all blocks in common from 128-step display positions in units of
4TOSC (TOSC = OSD oscillation cycle).
The display start position in the vertical direction for each block can
be selected from 512-step display positions in units of 1 TH ( TH =
HSYNC cycle).
(HP)
VP1
Block 1
Block 2
VP2
(a) Example when each block is separated
(HP)
VP1 = VP2
Block 1
(Block 2 is not displayed)
(b) Example when block 2 overlaps with block 1
(HP)
VP1
VP2
Block 1
Block 2
(c) Example when block 2 overlaps in process of block 1
Note: VP1 or VP2 indicates the vertical display start position of display block 1 or 2.
Fig. 8.11.5 Display Position
Rev. 1.3
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M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The vertical display start position is determined by counting the hori-
zontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are
positive polarity (negative polarity), it starts to count the rising edge
(falling edge) of HSYNC signal from after fixed cycle of rising edge
(falling edge) of VSYNC signal. So interval from rising edge (falling
edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal
needs enough time (2 machine cycles or more) for avoiding jitter.
The polarity of HSYNC and VSYNC signals can select with the I/O po-
larity control register (address 00D816).
8 machine cycles
or more
VSYNC signal input
0.25 to 0.50 [µs]
( at f(XIN) = 8MHz)
VSYNC control
signal in
microcomputer
Period of counting
HSYNC signal
(See note 2)
HSYNC
signal input
8 machine cycles
or more
1
2
3
4
5
Not count
When bits 0 and 1 of the I/O polarity control register
(address 00D816) are set to “1” (negative polarity)
Notes 1 : The vertical position is determined by counting falling edge of HSYNC
signal after rising edge of VSYNC control signal in the microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge of
VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or
more.
Fig. 8.11.6 Supplement Explanation for Display Position
Rev. 1.3
66
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The vertical display start position for each block can be set in 512
steps (where each step is 1TH (TH: HSYNC cycle)) as values “0016” to
“FF16” in vertical position register i (i = 1 and 2) (addresses 00D416
and 00D516) and values “0” or “1” in bit 6 of block control register i (i
= 1 and 2) (addresses 00D216 and 00D316). The vertical position
registers is shown in Figure 8.11.7.
Vertical Position Register i
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D416, 00D516
]
After reset
Name
B
Functions
R
R
W
W
Vertical display start
position control bits
(VPi0 to VPi7)
Vertical display start position =
Inderterminate
0
to
7
TH
✕ (BCi6 ✕ 162 + n)
(n: setting value, TH: HSYNC cycle,
(See note)
BCi6: bit 6 of block control register i)
Note: Set values except “0016” to VPi when BCi6 is “0.”
Fig. 8.11.7 Vertical Position Register i (i = 1 and 2)
Rev. 1.3
67
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The horizontal display start position is common to all blocks, and can
be set in 128 steps (where 1 step is 4TOSC, TOSC being the OSD
oscillation cycle) as values “0016” to “FF16” in bits 0 to 6 of the hori-
zontal position register (address 00D116). The horizontal position reg-
ister is shown in Figure 8.11.8.
Horizontal Position Register
b7 b6 b5b4 b3 b2b1 b0
Horizontal position register (HP) [Address 00D1 16
]
B
0
Name
Functions
Horizontal display start positions
128 steps (0016 to 7F16
(1 step is 4TOSC
After reset R W
Horizontal display start
0
R W
)
to position control bits
6
(HP0 to HP6)
)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
7
0
R —
Note: The setting value synchronizes with the V SYNC
.
Fig. 8.11.8 Horizontal Position Register
Notes 1 : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs
between the horizontal display start position set by the horizontal
position register and the most left dot of the 1st block. Accordingly,
when 2 blocks have different pre-divide ratios, their horizontal dis-
play start position will not match.
2 : The horizontal start position is based on the OSD clock source cycle
selected for each block. Accordingly, when 2 blocks have different
OSD clock source cycles, their horizontal display start position will
not match.
3 : When setting “0016” to the horizontal position register, it needs ap-
proximately 62TOSC (= Tdef) interval from a rising edge (when nega-
tive polarity is selected) of HSYNC signal to the horizontal display start
position.
H
SYNC
1T
C
T
def
4TOSC ✕ N
Note 1
Block 2 (Pre-divide ratio = 2, clock source = data slicer clock)
Block 3 (Pre-divide ratio = 3, clock source = data slicer clock)
1T
C
1T
C
Tdef’
4TOSC’ ✕ N
Note 2
Block 4 (Pre-divide ratio = 3, clock source = OSC1)
N
1T
: Value of horizontal position register (decimal notation)
: OSD clock cycle divided in pre-divide circuit
C
T
T
OSC : OSD oscillation cycle
def : 62 TOSC
Fig. 8.11.9 Notes on Horizontal Display Start Position
Rev. 1.3
68
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.11.2 Dot Size
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing HSYNC in the vertical dot size con-
trol circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1) in
the pre-divide circuit. The clock cycle divided in the pre-divide circuit
is defined as 1TC.
The dot size of each block is specified by bits 2 to 4 of the block
control register i.
Refer to Figure 8.11.4 (the structure of the block control register).
The block diagram of dot size control circuit is shown in Figure 8.11.10.
“0”
OSC1
Clock cycle
= 1TC
Cycle ✕ 2
Synchronous
circuit
Horizontal dot size
control circuit
“1” BCi4
OC3 or OC4
Data slicer clock
Cycle ✕ 3
Pre-divide circuit
Vertical dot size
control circuit
HSYNC
OSD control circuit
Note: To use data slicer clock, set bit 0 of data slicer control register 1 to “1.”
Fig. 8.11.10 Block Diagram of Dot Size Control Circuit
1dot
1T
C
1T
C
2T
C
3TC
ScanninglineofF1(F2)
ScanninglineofF2(F1)
1/2H
1H
2H
3H
Fig. 8.11.11 Definition of Dot Sizes
Rev. 1.3
69
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.11.3 Clock for OSD
As a clock for display to be used for OSD, it is possible to select one
of the following 3 types.
• Data slicer clock output from the data slicer (approximately 26 MHz)
• OSC1 clock supplied from the pins OSC1 and OSC2
• Clock from the ceramic resonator or the LC oscillator from the pins
OSC1 and OSC2
This OSD clock for each block can be selected by the following bits
: bit 7 of the raster color register (address 00D916), bits 3 to 6 of the
clock source control register (addresses 00D016). A variety of char-
acter sizes can be obtained by combining dot sizes with OSD clocks.
When not using the pins OSC1 and OSC2 for the OSD clock I/O
pins, the pins can be used as sub-clock I/O pins or port P2.
Table 8.11.2 Setting for P26/OSC1/XCIN, P27/OSC2/XCOUT
OSD clock
I/O Pin
Sub-clock
I/O Pin
I/O
Port
Function
Register
b7 of raster color
register
0
0
1
b6
b5
OSD control
register
1
0
0
0
1
0
Data slicer clock
(See note)
“0”
Data slicer
circuit
CC mode block
OC3
OC4
“1”
“0”
OSD mode block
OSC1 clock
Ceramic · LC
“1”
“10”
OC6, OC5
Oscillating mode for OSD
Note : To use data slicer clock, set bit 0 of data slicer control register 1 to “1.”
Fig. 8.11.12 Block Diagram of OSD Selection Circuit
Rev. 1.3
70
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.11.4 Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even
field or an odd field is determined through differences in a synchro-
nizing signal waveform of interlacing system. The dot line 0 or 1 (re-
fer to Figure 8.11.14) corresponding to the field is displayed alter-
nately.
In the following, the field determination standard for the case where
both the horizontal sync signal and the vertical sync signal are nega-
tive-polarity inputs will be explained. A field determination is deter-
mined by detecting the time from a falling edge of the horizontal sync
signal until a falling edge of the VSYNC control signal (refer to Figure
8.11.6) in the microcomputer and then comparing this time with the
time of the previous field. When the time is longer than the compar-
ing time, it is regarded as even field. When the time is shorter, it is
regarded as odd field
The contents of this field can be read out by the field determination
flag (bit 6 of the I/O polarity control register at address 00D816). A dot
line is specified by bit 5 of the I/O polarity control register (refer to
Figure 8.11.14).
However, the field determination flag read out from the CPU is fixed
to “0” at even field or “1” at odd field, regardless of bit 5.
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
I/O polarity control register (PC) [Address 00D816
]
After reset
0
B
0
Name
Functions
R
R
W
W
H
SYNC input polarity
switch bit (PC0)
0 : Positive polarity input
1 : Negative polarity input
1
2
3
4
5
0 : Positive polarity input
1 : Negative polarity input
0
0
0
0
0
R
R
R
R
R
W
W
W
W
W
V
SYNC input polarity
switch bit (PC1)
0 : Positive polarity output
1 : Negative polarity output
R, G, B output polarity
switch bit (PC2)
OUT1 output polarity
switch bit (PC3)
0 : Positive polarity output
1 : Negative polarity output
OUT2 output polarity
switch bit (PC4)
0 : Positive polarity output
1 : Negative polarity output
Display dot line selection
bit (PC5) (See note)
0 : “
” at even field
” at odd field
” at even field
” at odd field
“
1 : “
“
6
7
Field determination flag
(PC6)
0 : Even field
1 : Odd field
1
0
R
R
—
W
Fix this bit to “0.”
Note: Refer to the corresponding figure (8.11.14).
Fig. 8.11.13 I/O Polarity Control Register
Rev. 1.3
71
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Both HSYNC signal and VSYNC signal are negative-polarity input
Field
determination
flag(Note)
Display dot line
selection bit
Display dot line
H
SYNC
Field
Odd
V
V
SYNC and
SYNC
(n |1) field
(Odd-numbered)
control
signal
in microcom-
puter
0.25 to 0.50[ ˚s] at
f(XIN) 8 MHz
T1
T2
T3
0
1
Dot line 1
Dot line 0
(n) field
(Even-numbered)
Even
Odd
0 (T2 > T1)
1 (T3 < T2)
Upper :
SYNC signal
V
Lower :
SYNC control
signal in
micro-
computer
V
0
1
Dot line 0
Dot line 1
(n {1) field
(Odd-numbered)
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 0208 16) to “0.”
3 4 7 8 9 10 11 12 13 1415 16 3 4 6 7 9 10 1112 13 14 15 16
1
2
5
6
1
2
5
8
1
2
1
2
3
3
4
4
5
6
5
6
7
7
8
9
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
10
11
12
13
14
15
16
17
18
19
20
OSD mode
When the display dot line selection bit is “0,”
24
25
the “ ” font is displayed at even field, the
” font is displayed at odd field. Bit 6 of the
“
I/O polarity control register can be read as the
field determination flag : “1” is read at odd field,
“0” is read at even field.
26
CC mode
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in
the microcomputer.
Fig. 8.11.14 Relation between Field Determination Flag and Display Font
Rev. 1.3
72
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.11.5 Memory for OSD
(1) OSD ROM (addresses 140016 to 3BFF16)
There are 2 types of memory for OSD : OSD ROM used to store
character dot data and OSD RAM used to specify the characters and
colors to be displayed.
The dot pattern data for OSD characters is stored in OSD ROM. To
specify the kinds of the character font, it is necessary to write the
character code into the OSD RAM.
<M37272M6/M8-XXXSP/FP, M37272E8SP/FP>
OSD ROM : addresses 140016 to 3BFF16
OSD RAM : addresses 080016 to 087F16
Data of the character font is specified shown in Figure 8.11.15.
<M37272MA-XXXSP, M37272EFSP>
OSD ROM : addresses 1140016 to 13BFF16
OSD RAM : addresses 080016 to 087F16
OSD ROM address of character font data
OSD ROM
AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
address bit
Font
bit
Line number/character
code/font bit
1
(Note)
0
0
Line number
Character code
“0A16” to “1D16”
“0016” to “FF16” (“7F16” and “8016” cannot be used)
0 : Left area
Line number
Character code
Font bit
1 : Right area
Note: Only M37272MA-XXXSP and M37272EFSP have AD16.
Data in
OSD
ROM
Line
number
Left
area
Right
area
b7
b0 b7
b0
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
000016
7FF016
7FF816
601C16
600C16
600C16
600C16
600C16
601C16
7FF816
7FF016
630016
638016
61C016
60E016
607016
603816
601C16
600C16
000016
Character font
Fig. 8.11.15 Character Font Data Storing Address
Rev. 1.3
73
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Notes 1 : The 80-byte addresses corresponding to the character code “7F16”
2 : The character code “0916” is used for “transparent space” when
displaying Closed Caption.
Therefore, set “0016” to the 40-byte addresses corresponding to the
character code “0916.”
and “8016” in OSD ROM are the test data storing area. Set data to
the area as follows.
<Test data storing area>
■M37272M6/M8-XXXSP/FP, M37272E8SP/FP
addresses 100016 + (4 + 2n) ✕ 10016 + FE16 to
100016 + (5 + 2n) ✕ 10016 + 0116
(n = 0 to 19)
■M37272MA-XXXSP, M37272EFSP
addresses 1100016 + (4 + 2n) ✕ 10016 + FE16 to
1100016 + (5 + 2n) ✕ 10016 + 0116
(n = 0 to 19)
<Transparent space font data storing area>
■M37272M6/M8-XXXSP/FP, M37272E8SP/FP
addresses 100016 + (4 + 2n) ✕ 10016 + 1216 to
100016 + (4 + 2n) ✕ 10016 + 1316
(n = 0 to 19)
addresses 141216 and 141316
addresses 161216 and 161316
addresses 381216 and 381316
addresses 3A1216 and 3A1316
(1)Mask version (M37272M6/M8-XXXSP/FP, M37272MA-XXXSP)
Set “FF16” to the area (We stores the test data to this area and the different
data from “FF16” is stored for the actual products.) When using our font
editor, the test data is written automatically.
(2)EPROM version (M37272E8SP/FP, M37272EFSP)
Set the test data to the area. When using our font editor, the test data
is written automatically.
■M37272MA-XXXSP, M37272EFSP
addresses 1100016 + (4 + 2n) ✕ 10016 + 1216 to
1100016 + (4 + 2n) ✕ 10016 + 1316
(n = 0 to 19)
addresses 1141216 and 1141316
addresses 1161216 and 1161316
■M37272E8SP/FP
<“FF16”> address (test data)
<“8016”> address (test data)
150016 (9016), 150116 (A116)
170016 (0016), 170116 (A216)
190016 (4816), 190116 (A316)
1B0016 (0016), 1B0116 (A416)
1D0016 (2416), 1D0116 (A516)
1F0016 (0016), 1F0116 (A616)
210016 (1216), 210116 (A716)
230016 (0016), 230116 (A816)
250016 (0916), 250116 (A916)
270016 (0016), 270116 (AA16)
290016 (8116), 290116 (AB16)
2B0016 (1816), 2B0116 (AC16)
2D0016 (0016), 2D0116 (AD16)
2F0016 (4216), 2F0116 (AE16)
310016 (2416), 310116 (AF16)
330016 (0016), 330116 (B016)
350016 (8116), 350116 (B116)
370016 (0C16), 370116 (B216)
390016 (0616), 390116 (B316)
3B0016 (0016), 3B0116 (B416)
14FE16 (0916), 14FF16 (5116)
16FE16 (0016), 16FF16 (5216)
18FE16 (1216), 18FF16 (5316)
1AFE16 (0016), 1AFF16 (5416)
1CFE16 (2416), 1CFF16 (5516)
1EFE16 (0016), 1EFF16 (5616)
20FE16 (8816), 20FF16 (5716)
22FE16 (0016), 22FF16 (5816)
24FE16 (9016), 24FF16 (5916)
26FE16 (4816), 26FF16 (5A16)
28FE16 (2416), 28FF16 (5B16)
2AFE16 (0016), 2AFF16 (5C16)
2CFE16 (2416), 2CFF16 (5D16)
2EFE16 (4816), 2EFF16 (5E16)
30FE16 (0016), 30FF16 (5F16)
32FE16 (4816), 32FF16 (5016)
34FE16 (9016), 34FF16 (5116)
36FE16 (0016), 36FF16 (5216)
38FE16 (0116), 38FF16 (5316)
3AFE16 (8016), 3AFF16 (5416)
addresses 1381216 and 1381316
addresses 13A1216 and 13A1316
■M37272EFSP
<“7F16”> address (test data)
<“8016”> address (test data)
1150016 (9016), 1150116 (A116)
1170016 (0016), 1170116 (A216)
1190016 (4816), 1190116 (A316)
11B0016 (0016), 11B0116 (A416)
11D0016 (2416), 11D0116 (A516)
11F0016 (0016), 11F0116 (A616)
1210016 (1216), 1210116 (A716)
1230016 (0016), 1230116 (A816)
1250016 (0916), 1250116 (A916)
1270016 (0016), 1270116 (AA16)
1290016 (8116), 1290116 (AB16)
12B0016 (1816), 12B0116 (AC16)
12D0016 (0016), 12D0116 (AD16)
12F0016 (4216), 12F0116 (AE16)
1310016 (2416), 1310116 (AF16)
1330016 (0016), 1330116 (B016)
1350016 (8116), 1350116 (B116)
1370016 (0C16), 1370116 (B216)
1390016 (0616), 1390116 (B316)
13B0016 (0016), 13B0116 (B416)
114FE16 (0916), 114FF16 (5116)
116FE16 (0016), 116FF16 (5216)
118FE16 (1216), 118FF16 (5316)
11AFE16 (0016), 11AFF16 (5416)
11CFE16 (2416), 11CFF16 (5516)
11EFE16 (0016), 11EFF16 (5616)
120FE16 (8816), 120FF16 (5716)
122FE16 (0016), 122FF16 (5816)
124FE16 (9016), 124FF16 (5916)
126FE16 (4816), 126FF16 (5A16)
128FE16 (2416), 128FF16 (5B16)
12AFE16 (0016), 12AFF16 (5C16)
12CFE16 (2416), 12CFF16 (5D16)
12EFE16 (4816), 12EFF16 (5E16)
130FE16 (0016), 130FF16 (5F16)
132FE16 (4816), 132FF16 (5016)
134FE16 (9016), 134FF16 (5116)
136FE16 (0016), 136FF16 (5216)
138FE16 (0116), 138FF16 (5316)
13AFE16 (8016), 13AFF16 (5416)
Rev. 1.3
74
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(2) OSD RAM
The RAM for OSD is allocated at addresses 080016 to 087F16, and
is divided into a display character code specification part, color code
1 specification part, and color code 2 specification part for each block.
Table 8.11.3 shows the contents of the OSD RAM.
For example, to display 1 character position (the left edge) in block
1, write the character code in address 080016, write the color code 1
at 082016.
The structure of the OSD RAM is shown in Figure 8.11.16.
Table 8.11.3 Contents of OSD RAM
Display Position (from left)
Color Code Specification
Block
Character Code Specification
080016
080116
082016
082116
1st character
2nd character
080216
:
081D16
082216
:
083D16
3rd character
Block 1
:
30th character
081E16
081F16
084016
084116
083E16
083F16
086016
086116
31st character
32nd character
1st character
2nd character
3rd character
084216
:
086216
:
:
Block 2
30th character
085D16
087D16
31st character
32nd character
085E16
085F16
087E16
087F16
Rev. 1.3
75
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Blocks 1, 2
b7
b0
b7
b0
RA6 RA5 RA4 RA3 RA2 RA1 RA0 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0
(See note 1)
Color code 1
CC mode
Character code (See note 3)
OSD mode
Bit name
Bit
Bit name
Function
Function
RF0
RF1
RF2
RF3
RF4
RF5
RF6
RF7
RA0
Character code
Character code in
OSD ROM
Character code
Character code in
OSD ROM
0: Color signal output OFF
1: Color signal output ON
Control of
character color R
Control of
0: Color signal output OFF
1: Color signal output ON
Control of
character color R
Control of
RA1
RA2
RA3
RA4
RA5
RA6
character color G
Control of
character color G
Control of
character color B
character color B
(See note 2)
OUT1/OUT2 control
(See note 2)
OUT1/OUT2 control
Flash control
0: Flash OFF
1: Flash ON
Control of
background color R
Control of
0: Color signal output OFF
1: Color signal output ON
0: Underline OFF
1: Underline ON
0: Italic OFF
Underline control
Italic control
background color G
Control of
1: Italic ON
background color B
Notes 1: Read value of bits 7 of the color code is “0.”
2: For OUT1/OUT2 control, refer to “8.11.8 OUT1/OUT2 signal.”
3: “7F16” and “8016” cannot be used as character code.
Fig. 8.11.16 Bit structure of OSD RAM
Rev. 1.3
76
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.11.6 Character color
8.11.7 Character background color
The color for each character is displayed by the color code.
The character background color can be displayed in the character
display area only in the OSD mode. The character background color
for each character is specified by the color code.
<7 kinds>
<7 kinds>
Specified by bits 0 (R), 1 (G), and 2 (B) of the color code
Specified by bits 4 (R), 5 (G), and 6 (B) of the color code
Note : The character background color is displayed in the following part :
(character display area)–(character font)–(border).
Accordingly, the character background color does not mix with these
color signal.
Rev. 1.3
77
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.11.8 OUT1, OUT2 signals
controlling OUT1, OUT2 and the corresponding output waveform is
The OUT1, OUT2 signals are used to control the luminance of the
video signal. The output waveform of the OUT1, OUT2 signals is
controlled by display mode, bit 5 of the block control register i (refer
to Figure 8.11.4) and RA3 of OSD RAM. The setting values for
shown in Figure 8.11.17.
Note : When OUT2 signal is output, set bit 7 of OSD port control register (refer
to Figure 8.11.28) to “1.”
A'
A
Block Control
Register i
OUT1/OUT2 Output
Control Bit (b5)
OUT1/OUT2
Control
RA3 of
Display
Mode
Output Waveform (A-A')
OSD RAM
OUT1 = FONT/BORDER
OUT2 = “L”
0
1
0
(OUT1 output
is controlled
by RA3)
OUT1 = AREA
OUT2 = “L”
OSD
OUT1 = FONT/BORDER
OUT2 = “L”
0
1
1
(OUT2 output
is controlled
by RA3)
OUT1 = FONT/BORDER
OUT2 = AREA
OUT1 = FONT
OUT2 = “L”
0
1
0
1
0
(OUT1 output
is controlled
by RA3)
OUT1 = AREA
OUT2 = “L”
CC
OUT1 = FONT
OUT2 = “L”
1
(OUT2 output
is controlled
by RA3)
OUT1 = FONT
OUT2 = AREA
Notes 1 : FONT/BORDER.....In the OSD mode (Border ON), OUT1 outputs to the area of font and border.
In the OSD mode (Border OFF), OUT1 outputs to only the font area.
AREA.....................OUT1/OUT2 outputs to entire display area of character.
FONT.....................In the CC mode, OUT1 outputs to font area.
2 : When the automatic solid space function is OFF in the CC mode, AREA outputs according to bit 3 of color code.
When it is ON, the solid space is automatically output by a character code regardless of RA3.
Fig. 8.11.17 Setting Value for Controlling OUT1, OUT2 and Corresponding Output Waveform
Rev. 1.3
78
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.11.9 Attribute
The attributes (border, flash, underline, italic) are controlled to the
character font. The attributes to be controlled are different depend-
ing on each mode.
CC mode ..................... Flash, underline, italic (per character unit)
OSD mode .................. Border (per character unit)
(1) Under line
The underline is output at the 23th and 24th dots in vertical direction
only in the CC mode. The underline is controlled by RA5 of OSD
RAM. The color of underline is the same color as that of the charac-
ter font.
(2) Flash
The character font and the underline are flashed only in the CC mode.
The flash is controlled by RA4 of OSD RAM. As for character font
part, the character output part is flashed, the character background
part is not flashed. The flash cycle bases on the VSYNC count.
• VSYNC cycle ✕ 48 ≈ 800 ms (at display ON)
• VSYNC cycle ✕ 16 ≈ 267 ms (at display OFF)
(3) Italic
The italic is made by slanting the font stored in OSD ROM to the right
only in the CC mode. The italic is controlled by RA6 of OSD RAM.
The display example of the italic and underline is shown in Figure
8.11.8. In this case, “R” is displayed.
Notes 1: When setting both the italic and the flash, the italic character flashes.
2: The boundary of character color is displayed in italic. However, the
boundary of character background color is not affected by the italic
(refer to Figure 8.11.19).
3: The adjacent character (one side or both side) to an italic character is
displayed in italic even when the character is not specified to display
in italic (refer to Figure 8.11.19).
Rev. 1.3
79
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Color code
Color code
Bit 6
Bit 5
Bit 6
Bit 5
(RA6)
(RA5)
(RA6)
(RA5)
0
0
1
0
(a) Ordinary
(b) Under line
Color code
Color code
Bit 6
Bit 5
Bit 6
Bit 5
(RA6)
0
(RA5)
(RA6)
(RA5)
1
0
1
(c) Italic (pre-divide ratio = 1)
(d) Italic (pre-divide ratio = 2)
Color code
Bit 6
Bit 5
Bit 4
(RA6)
(RA5)
(RA4)
flash
flash
flash
1
1
1
ON
ON
OFF
OFF
(e) Under line amd Italic and flash
Fig. 8.11.18 Example of Attribute Display (in CC Mode)
Rev. 1.4
80
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
26th chracter
(Refer to “8.11.9 Notes 2, 3”)
(Refer to “8.11.9 Notes 2, 3”)
RA6 of
OSD RAM
1
0
0
1
1
0
1
Notes 1 : The dotted line is the boundary of character color.
2 : When bit 1 of OSD control register is “0.”
Fig. 8.11.19 Example of Italic Display
Rev. 1.3
81
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Notes 1 : The border dot area is the shaded area as shown in Figure 8.11.20.
2 : When the border dot overlaps on the next character font, the charac-
(4) Border
The border is output around of character font (all bordered) in the
OSD mode. The border ON/OFF is controlled by bit 0 and 1 of the
block control register i (refer to Figure 8.11.4).
ter font has priority (refer to Figure 8.11.22 A).
When the border dot overlaps on the next character back ground, the
border has priority (refer to Figure 8.11.22 B).
3 : The border in vertical out of character area is not displayed (refer to
Figure 8.11.22).
The OUT1 signal is used for border output.
The horizontal size (x) of border is 1TC (OSD clock cycle divided in
pre-divide circuit) regardless of the character font dot size. The verti-
cal size (y) different depending on the screen scan mode and the
vertical dot size of character font.
OSD mode
16 dots
Character
font area
All bordered
1 dot width of border
1 dot width of border
Fig. 8.11.20 Example of Border Display
y
x
Vertical dot size of
character font
1/2H
1H, 2H, 3H
Border dot size
1Tc (OSD clock cycle divided
in pre-divide circuit)
Horizontal size (x)
1/2H
1H
Vertical size (y)
Fig. 8.11.21 Horizontal and Vertical Size of Border
Rev. 1.3
82
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Character boundary Character boundary Character boundary
B
A
B
Fig. 8.11.22 Border Priority
Rev. 1.3
83
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Notes 1: An OSD interrupt does not occur at the end of display when the block
8.11.10 Multiline Display
is not displayed. In other words, if a block is set to off display by the
This microcomputer can ordinarily display 2 lines on the CRT screen
by displaying 2 blocks at different vertical positions. In addition, it can
display up to 16 lines by using OSD interrupts.
display control bit of the block control register (addresses 00D216,
00D316), an OSD interrupt request does not occur (refer to Figure
8.11.23 (A)).
2: When another block display appeares while one block is displayed,
an OSD interrupt request occurs only once at the end of the another
block display (refer to Figure 8.11.23 (B)).
3: On the screen setting window, an OSD interrupt occurs even at the
end of the CC mode block (off display) out of window (refer to Figure
8.11.23 (C)).
An OSD interrupt request occurs at the point at which display of each
block has been completed. In other words, when a scanning line
reaches the point of the display position (specified by the vertical
position registers) of a certain block, the character display of that
block starts, and an interrupt occurs at the point at which the scan-
ning line exceeds the block.
Block 1 (on display)
Block 1 (on display)
“OSD interrupt request”
“OSD interrupt request”
“OSD interrupt request”
Block 2 (on display)
Block 1’ (on display)
Block 2’ (on display)
Block 2 (on display)
“OSD interrupt request”
Block 1’ (off display)
Block 2’ (off display)
No
“OSD interrupt request”
“OSD interrupt request”
“OSD interrupt request”
No
“OSD interrupt request”
On display (OSD interrupt request occurs
at the end of block display)
Off display (OSD interrupt request does
not occur at the end of block display)
(A)
Block 1
Block 2
“OSD interrupt request”
“OSD interrupt request”
Block 1
Block 2
No
“OSD interrupt request”
“OSD interrupt request”
Block 1’
“OSD interrupt request”
Window
In CC mode
(C)
(B)
Fig. 8.11.23 Note on Occurence of OSD Interrupt
Rev. 1.3
84
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Notes : The character code “0916” is used for “transparent space” when dis-
8.11.11 Automatic Solid Space Function
playing Closed Caption.
Therefore, set “0016” to the 40-byte addresses corresponding to the
character code “0916.”
This function generates automatically the solid space (OUT1 or OUT2
blank output) of the character area in the CC mode.
The solid space is output in the following area :
<Transparent space font data storing area>
■M37272M6/M8-XXXSP/FP, M37272E8SP/FP
addresses 100016 + (4 + 2n) ✕ 10016 + 1216 to
100016 + (4 + 2n) ✕ 10016 + 1316
(n = 0 to 19)
• Any character area except character code “0916 ”
• Character area on the left and right sides of the above character
This function is turned on and off by bit 1 of the OSD control register
(refer to Figure 8.11.3).
addresses 141216 and 141316
addresses 161216 and 161316
addresses 381216 and 381316
addresses 3A1216 and 3A1316
■M37272MA-XXXSP, M37272EFSP
addresses 1100016 + (4 + 2n) ✕ 10016 + 1216 to
1100016 + (4 + 2n) ✕ 10016 + 1316
(n = 0 to 19)
addresses 1141216 and 1141316
addresses 1161216 and 1161316
addresses 1381216 and 1381316
addresses 13A1216 and 13A1316
When setting the character code “0516” as the character A, “0616” as the character B.
(OSD RAM)
• • •
05 09 09 09 06 06
06 09 09 06
16
16
16
16
16
16
16
16
16
16
(Display screen)
• • •
1st
2nd
31st
character
32nd
character
No blank output
character character
The solid space is automatically output on the left side of the 1st character and on the right side
of the 32nd character by setting the 1st and 32nd of the character code.
Fig. 8.11.24 Display Screen Example of Automatic Solid Space
Rev. 1.3
85
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.11.12 Window Function
This function sets the top and bottom boundary of display limit on a
screen. The window function is valid only in the CC mode. The top
boundary is set by the window registers 1 and bit 7 of block control
register 1. The bottom boundary is set by window registers 1 and bit
7 of block control register 2. This function is turned on and off by bit
2 of the OSD control register (refer to Figure 8.11.3).
The window registers 1 and 2 is shown in Figures 8.11.26 and 8.11.27.
Top
boundary
of window
OSD mode
CC mode
A B C D E
F G H
I
J
CC mode
CC mode
K L M N O
Window
P Q R S T
U V W X Y
OSD mode
Bottom
boundary
of window
Screen
Fig. 8.11.25 Example of Window Function
Rev. 1.3
86
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Window Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Window register 1 (WN1) [Address 00D616
]
After reset
Name
B
Functions
R
R
W
W
Window top border position =
✕ (BC17 ✕ 162 + n)
(n: setting value, T : HSYNC cycle,
BC17: bit 7 of block control register 1)
Inderterminate
Window top boundary
control bits
(WN10 to WN17)
0
to
7
T
H
H
Notes 1: Set values except “0016” to WN1 when BC17 is “0.”
2: Set values fit for the following condition: WN1 < WN2.
Fig. 8.11.26 Window Register 1
Window Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Window register 2 (WN2) [Address 00D716]
After reset
Name
B
Functions
R
W
Window bottom border position =
TH ✕ (BC27 ✕ 162 + n)
(n: setting value, TH: HSYNC cycle,
Inderterminate
Window bottom boundary
control bits
(WN20 to WN27)
R W
0
to
7
BC27: bit 7 of block control register 2)
Note: Set values fit for the following condition: WN1 < WN2.
Fig. 8.11.27 Window Register 2
Rev. 1.3
87
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.11.13 OSD Output Pin Control
The OSD output pins R, G, B and OUT1 can also function as ports
P52–P55. Set corresponding bit of the OSD port control register (ad-
dress 00CB16) to “0” to specify these pins as OSD output pins, or set
it to “1” to specify it as a general-purpose port P5.
The OUT2 can also function as port P10. Set bit 0 of the port P1
direction register (address 00C316) to “1” (output mode). After that,
set bit 7 of the OSD port control register to “1” to specify the pin as
OSD output pin, or set it to “0” to specify as port P10.
The input polarity of the HSYNC, VSYNC and output polarity of signals
R, G, B, OUT1 and OUT2 can be specified with the I/O polarity con-
trol register (address 00D8) . Set a bit to “0” to specify positive polar-
ity; set it to “1” to specify negative polarity (refer to Figure 8.11.13).
The structure of the OSD port control register is shown in Figure
8.11.28.
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
OSD port control register (PF) [Address 00CB16
]
0 0
B
Name
Functions
R
R
W
—
After reset
0
0, 1
Fix these bits to “0.”
2
3
4
Port P5
selection bit (PF2)
2
output signal
0 : R signal output
1 : Port P52 output
0
0
0
R
R
R
W
W
W
Port P5
3
output signal
0 : G signal output
1 : Port P5 output
selection bit (PF3)
3
0 : B signal output
1 : Port P5 output
Port P54 output signal
4
selection bit (PF4)
Port P5 output signal
selection bit (PF5)
5
0 : OUT1 signal output
1 : Port P5 output
0
0
0
R
R
R
W
—
W
5
6
7
3
Nothing is assigned. This bit is write disable bit.
When this bit is read out, the value is “0.”
Port P1
0
output signal
0 : Port P10 output
selection bit (PF7)
1 : OUT2 signal output
Fig. 8.11.28 OSD Port Control Register
Rev. 1.3
88
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.11.14 Raster Coloring Function
An entire screen (raster) can be colored by setting the bits 4 to 0 of
the raster color register. Since each of the R, G, B, OUT1, and OUT2
pins can be switched to raster coloring output, 8 raster colors can be
obtained.
When the character color/the character background color overlaps
with the raster color, the color (R, G, B, OUT1, OUT2), specified for
the character color/the character background color, takes priority of
the raster color. This ensures that character color/character back-
ground color is not mixed with the raster color.
The raster color register is shown in Figure 8.11.29, the example of
raster coloring is shown in Figure 8.11.30.
Raster Color Register
b7 b6 b5b4 b3 b2b1 b0
0 0
Raster color register (RC) [Address 00D9 16
Functions
]
After reset
R
W
B
Name
0 : No output
1 : Output
0
R W
R W
R W
R W
0
1
2
3
Raster color R
control bit (RC0)
Raster color G
control bit (RC1)
0 : No output
1 : Output
0
0
0
Raster color B
control bit (RC2)
0 : No output
1 : Output
Raster color OUT1
control bit (RC3)
0 : No output
1 : Output
4
Raster color OUT2
control bit (RC4)
0 : No output
1 : Output
0
R W
5, 6
Fix these bits to “0.”
0
0
R W
R W
7
Port function
selection bit (RC7)
0 : OSC1/XCIN
,
OSC2/XCOUT
1 : P2 , P2
6
7
Note: Either OSD clock source or 32 kHz oscillating clock is
selected by bits 5 and 6 of the OSD control register.
Fig. 8.11.29 Raster Color Register
Rev. 1.3
89
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
: Character color “RED” (R + OUT1 + OUT2)
: Border color “BLACK” (OUT1 + OUT2)
: Background color “MAGENTA” (R + B + OUT1 + OUT2)
: Raster color “BLUE” (B + OUT1 + OUT2)
A'
A
H
SYNC
OUT1
OUT2
R
Signals
across
A-A'
G
B
Fig. 8.11.30 Example of Raster Coloring
Rev. 1.3
90
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.12 SOFTWARE RUNAWAYDETECT FUNCTION
This microcomputer has a function to decode undefined instructions
to detect a software runaway.
When an undefined op-code is input to the CPU as an instruction
code during operation, the following processing is done.
➀ The CPU generates an undefined instruction decoding signal.
➁The device is internally reset because of occurrence of the unde-
fined instruction decoding signal.
➂As a result of internal reset, the same reset processing as in the
case of ordinary reset operation is done, and the program restarts
from the reset vector.
Note, however, that the software runaway detecting function cannot
be invalid.
φ
SYNC
AD
AD
H
,
Address
Data
PC
?
01,S
01,S–1
01,S–2
FFFE16
FFFF16
L
?
PCH
PC
L
PS
AD
L
ADH
Reset sequence
Undefined instruction decoding signal
occurs.Internal reset signal occurs.
: Undefined instruction decode
?
PC
S
: Invalid
: Program counter
: Stack pointer
ADL, ADH : Jump destination address of reset
Fig.8.12.1 Sequence at Detecting Software Runaway Detection
Rev. 1.3
91
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.13. RESET CIRCUIT
When the oscillation of a quartz-crystal oscillator or a ceramic reso-
nator is stable and the power source voltage is 5 V ± 10 %, hold the
RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as
shown in Figure 8.13.2, reset is released and the program starts form
the address formed by using the content of address FFFF16 as the
high-order address and the content of the address FFFE16 as the
low-order address. The internal state of microcomputer at reset are
shown in Figures 8.2.3 to 8.2.6.
Poweron
4.5 V
0.9 V
Power source voltage 0 V
Reset input voltage 0 V
An example of the reset circuit is shown in Figure 8.13.1.
The reset input voltage must be kept 0.9 V or less until the power
source voltage surpasses 4.5 V.
Vcc
1
5
4
RESET
M51953AL
0.1 µF
3
Vss
Microcomputer
Fig.8.13.1 Example of Reset Circuit
X
IN
φ
RESET
Internal RESET
SYNC
AD
AD
H
L
,
Address
Data
01, S-1
01, S-2
FFFE FFFF
?
?
01, S
Reset address from the vector table
AD
L
ADH
?
?
?
?
?
Notes 1 : f(XIN) and f(φ) are in the relation : f(XIN) = 2·f (φ).
2 : A question mark (?) indicates an undefined state that
depends on the previous state.
32768 count of XIN
clock cycle (See note 3)
3 : Immediately after a reset, timer 3 and timer 4 are
connected by hardware. At this time, “FF16” is set
in timer 3 and “0716” is set to timer 4. Timer 3 counts down
with f(XIN)/16, and reset state is released by the timer 4
overflow signal.
Fig.8.13.2 Reset Sequence
Rev. 1.3
92
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and ON-SCREEN DISPLAY CONTROLLER
(3) Low-speed Mode
8.14 CLOCK GENERATING CIRCUIT
If the internal clock is generated from the sub-clock (XCIN), a low
power consumption operation can be realized by stopping only the
main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU
mode register (00FB16) to “1.” When the main clock XIN is restarted,
the program must allow enough time to for oscillation to stabilize.
Note that in low-power-consumption mode the XCIN-XCOUT drivability
can be reduced, allowing even lower power consumption. To reduce
the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU mode regis-
ter (00FB16) to “0.” At reset, this bit is set to “1” and strong drivability
is selected to help the oscillation to start. When an STP instruction is
executed, set this bit to “1” by software before executing.
This microcomputer has 2 built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer’s recommended values. No external re-
sistor is needed between XIN and XOUT since a feed-back resistor
exists on-chip. However, an external feed-back resistor is needed
between XCIN and XCOUT. When using XCIN-XCOUT as sub-clock,
clear bits 5 and 6 of the OSD control register to “0.” To supply a clock
signal externally, input it to the XIN (XCIN) pin and make the XOUT
(XCOUT) pin open. When not using XCIN clock, connect the XCIN to
VSS and make the XCOUT pin open.
After reset has completed, the internal clock φ is half the frequency of
XIN. Immediately after poweron, both the XIN and XCIN clock start
oscillating. To set the internal clock φ to low-speed operation mode,
set bit 7 of the CPU mode register to “1.”
Microcomputer
8.14.1 OSCILLATION CONTROL
(1) Stop Mode
X
CIN
X
COUT
X
IN
XOUT
The built-in clock generating circuit is shown in Figure 120. When the
STP instruction is executed, the internal clock φ stops at HIGH. At
the same time, timers 3 and 4 are connected by hardware and “FF16”
is set in timer 3 and “0716” is set in timer 4. Select f(XIN)/16 or f(XCIN)/
16 as the timer 3 count source (set both bit 0 of the timer mode
register 2 and bit 6 at address 00C716 to “0” before the execution of
the STP instruction). Moreover, set the timer 3 and timer 4 interrupt
enable bits to disabled (“0”) before execution of the STP instruction.
The oscillator restarts when external interrupt is accepted. However,
the internal clock φ keeps its HIGH level until timer 4 overflows, al-
lowing time for oscillation stabilization when a ceramic resonator or a
quartz-crystal oscillator is used.
R
f
R
d
CCIN
C
COUT
CIN
COUT
Fig.8.14.1 Ceramic Resonator Circuit Example
Microcomputer
(2) Wait Mode
X
CIN
X
COUT
X
IN
XOUT
When the WIT instruction is executed, the internal clock φ stops in
the HIGH level but the oscillator continues running. This wait state is
released at reset or when an interrupt is accepted (See note). Since
the oscillator does not stop, the next instruction can be executed at
once.
Open
Open
External oscillation
circuit or external
pulse
External oscillation
circuit
Note: In the wait mode, the following interrupts are invalid.
• VSYNC interrupt
Vcc
Vss
Vcc
Vss
• OSD interrupt
• All timer interrupts using external clock input from port pin as count
source
• All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source
• All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source
• f(XIN)/4096 interrupt
• Multi-master I2C-BUS interface interrupt
• Data slicer interrupt
Fig.8.14.2 External Clock Input Circuit Example
• A-D conversion interrupt
Rev. 1.3
93
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
XCIN
XCOUT
OSC1 clock selection
bits (See notes 1, 4)
Timer 3 count
stop bit (See notes 1, 2)
Timer 4 count
stop bit (See notes 1, 2)
XIN
XOUT
“1”
“1”
“0”
Timer 3
Timer 4
1/8
1/2
“0”
Internal system clock
selection bit (See notes 1, 3)
Timer 3
count source selection bit (See notes 1, 2)
Timing φ
(Internal clock)
Main clock (XIN–XOUT) stop bit (See notes 1, 3)
Internal system clock selection bit
(See notes 1, 3)
Q
S
R
S
Q
Q
S
R
Reset
WIT
instruction
R
STP instruction
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Notes 1 : The value at reset is “0.”
2 : Refer to timer mode register 2.
3 : Refer to the CPU mode register.
4 : Refer to the OSD control register.
Fig.8.14.3 Clock Generating Circuit Block Diagram
Rev. 1.3
94
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
High-speed operation start
Reset
mode
WIT instruction
Interrupt
STP instruction
8 MHz oscillating
32 kHz oscillating
φ is stopped (“H”)
Timer operating
8 MHz oscillating
32 kHz oscillating
f(φ) = 4 MHz
8 MHz stopped
32 kHz stopped
φ is stopped (“H”)
Interrupt (See note 1)
External INT
External INT,
timer interrupt,
or SI/O interrupt
CM7 = 0
CM7 = 1
WIT instruction
Interrupt
STP instruction
8 MHz oscillating
32 kHz oscillating
φ is stopped (“H”)
Timer operating
(See note 3)
8 MHz oscillating
32 kHz oscillating
f(φ) = 16kHz
8 MHz stopped
32 kHz stopped
φ is stopped (“H”)
Interrupt (See note 2)
CM6 = 0
The program must
allow time for 8 MHz
oscillation to stabilize
CM6 = 1
STP instruction
WIT instruction
Interrupt
8 MHz stopped
32 kHz oscillating
φ is stopped (“H”)
Timer operating
(See note 3)
8 MHz stopped
32 kHz stopped
φ = stopped (“H”)
8 MHz stopped
32 kHz oscillating
f(φ) = 16 kHz
Interrupt (See note 2)
CPU mode register
(Address : 00FB16
)
CM6 : Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
CM7 : Internal system clock selection bit
0 : XIN-XOUT selected (high-speed mode)
1 : XCIN-XCOUT selected (low-speed mode)
The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. The φ indicates the internal clock.
Notes 1: When the STP state is ended, a delay of approximately 8 ms is automatically generated by timer 3 and timer 4.
2: The delay after the STP state ends is approximately 2s.
3: When the internal clock φ divided by 8 is used as the timer count source, the frequency of the count source is 2 kHz.
Fig.8.14.4 State Transitions of System Clock
Rev. 1.3
95
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.15 DISPLAY OSCILLATION CIRCUIT
8.17 ADDRESSING MODE
The OSD oscillation circuit has a built-in clock oscillation circuits, so
that a clock for OSD can be obtained simply by connecting an LC, a
ceramic resonator, or a quartz-crystal oscillator across the pins OSC1
and OSC2. Which of the sub-clock or the OSD oscillation circuit is
selected by setting bits 5 and 6 of the OSD control register (address
00D016).
The memory access is reinforced with 17 kinds of addressing modes.
Refer to SERIES 740 <Software> User’s Manual for details.
8.18 MACHINE INSTRUCTIONS
There are 71 machine instructions. Refer to SERIES 740 <Soft- ware>
User’s Manual for details.
9. PROGRAMMING NOTES
• The divide ratio of the timer is 1/(n+1).
•
Even though the BBC and BBS instructions are executed imme-
diately after the interrupt request bits are modified (by the pro-
gram), those instructions are only valid for the contents before
the modification. At least one instruction cycle is needed (such as
an NOP) between the modification of the interrupt request bits
and the execution of the BBC and BBS instructions.
OSC1
OSC2
L
C1
C2
•
After the ADC and SBC instructions are executed (in the decimal
mode), one instruction cycle (such as an NOP) is needed before
the SEC, CLC, or CLD instruction is executed.
•
•
An NOP instruction is needed immediately after the execution of
a PLP instruction.
Fig.8.15.1 Display Oscillation Circuit
In order to avoid noise and latch-up, connect a bypass capacitor
(≈ 0.1µF) directly between the VCC pin–VSS pin, AVCC pin–VSS
pin, and the VCC pin–CNVSS pin, using a thick wire.
8.16 AUTO-CLEAR CIRCUIT
When a power source is supplied, the auto-clear function will oper-
ate by connecting the following circuit to the RESET pin.
Circuit example 1
Vcc
RESET
Vss
Circuit example 2
Vcc
RESET
Vss
Note : Make the level change from “L” to “H” at the point at
which the power source voltage exceeds the specified
voltage.
Fig.8.16.1 Auto-clear Circuit Example
Rev. 1.3
96
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
10. ABSOLUTE MAXIMUM RATINGS
Symbol
Parametear
Conditions
Ratings
–0.3 to 6
–0.3 to 6
Unit
V
VCC, AVCC
Power source voltage VCC, AVCC
VI
VI
Input voltage
Input voltage
CNVSS
P00–P07, P10–P17, P20–P27, P3
P3 , P5 , P5 , XIN, RESET, CVIN
V
All voltages are based
on VSS.
Output transistors are
cut off.
0,
–0.3–VCC + 0.3
–0.3–VCC + 0.3
V
V
1
0
1
VO
Output voltage P06, P07, P10–P17, P20–P27,
P30, P31, P52–P55, XOUT
Output voltage P00–P05
–0.3 to 13
V
VO
Circuit current P10–P17, P20–P27, P30, P31
P52–P55
0 to 1 (See note 1)
mA
IOH
Circuit current P06, P07, P10, P15–P17, P20–P23,
P26, P27, P52–P55
0 to 2 (See note 2)
mA
IOL1
Circuit current P11–P14
Circuit current P00–P05
Circuit current P24, P25, P30, P31
Power dissipation
0 to 6 (See note 2)
0 to 1 (See note 2)
0 to 10 (See note 3)
550
mA
mA
mA
mW
IOL2
IOL3
IOL4
Pd
Ta = 25 °C
Operating temperature
Storage temperature
–10 to 70
Topr
Tstg
°C
°C
–40 to 125
11. RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Limits
Symbol
Unit
Parametear
Min.
4.5
Typ.
5.0
Max.
5.5
VCC, AVCC
VSS
Power source voltage (See note 4)
V
V
Power source voltage
HIGH Input voltage
0
0
0
VIH1
P00–P07, P10–P17, P20–P27, P30, P31, P50, P51,
RESET, XIN
0.8 VCC
VCC
V
2
VIH2
VIL1
VIL2
VIL3
HIGH Input voltage
LOW Input voltage
LOW Input voltage
SCL1, SCL2, SDA1, SDA2 (When using I C-BUS)
0.7 VCC
VCC
0.4 VCC
0.3 VCC
V
V
V
P00–P07, P10–P17, P20–P27, P30, P31
0
0
2
SCL1, SCL2, SDA1, SDA2 (When using I C-BUS)
LOW Input voltage (See note 6)
P50, P51, RESET, XIN, OSC1, TIM2,
TIM3, INT1, INT2, INT3, SIN, SCLK
0
0.2 VCC
V
IOH
HIGH average output current (See note1) P10–P17, P20–P27, P30, P31, P52–P55
1
2
mA
mA
IOL1
LOW average output current (See note 2) P06, P07, P10, P15–P17, P20–P23,
P26, P27, P52–P55
IOL2
IOL3
IOL4
f(XIN)
f(XCIN)
fOSC
fhs1
LOW average output current (See note 2) P11–P14
6
1
mA
mA
LOW average output current (See note 2) P00–P05
LOW average output current (See note 3) P24, P25, P30, P31
Oscillation frequency (for CPU operation) (See note 5) XIN
10
mA
8.1
MHz
kHz
MHz
kHz
MHz
kHz
kHz
V
7.9
29
8.0
32
Oscillation frequency (for sub-clock operation)
Oscillation frequency (for OSD)
XCIN
35
OSC1
27.0
100
1
26.5
27.0
Input frequency
TIM2, TIM3, INT1, INT2, INT3
fhs2
Input frequency
SCLK
fhs3
Input frequency
SCL1, SCL2
400
16.206
2.5
fhs4
Input frequency
Horizontal sync. signal of video signal
CVIN
15.262
1.5
15.734
2.0
VI
Input amplitude video signal
Rev. 1.4
97
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12. ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted)
Limits
Test
Symbol
Parametear
Unit
Test conditions
Min.
Typ.
Max.
30
circuit
OSD OFF
15
30
60
Data slicer OFF
VCC = 5.5V,
mA
f(XIN) = 8MHz
OSD ON
45
Data slicer ON
VCC = 5.5V, f(XIN) = 0,
f(XCIN) = 32kHz,
OSD OFF, Data slicer OFF,
Low-power dissipation mode set
200
µA
System operation
Wait mode
1
2
3
Power source current
ICC
(CM5 = “0”, CM6 = “1”)
VCC = 5.5 V, f(XIN) = 8 MHz
mA
2
25
4
100
µA
VCC = 5.5 V, f(XIN) = 0,
f(XCIN) = 32 kHz,
Low-power dissipation mode set
(CM5 = “0”, CM6 = “1”)
Stop mode
VCC = 5.5V, f(XIN) = 0,
f(XCIN) = 0
1
10
2.4
HIGH output voltage P10–P17, P20–P27,
P30, P31, P52–P55,
VCC = 4.5 V
IOH = –0.5 mA
VOH
VOL
V
V
LOW output voltage P00–P07, P10,
P15–P17, P20–P23,
VCC = 4.5 V
IOL = 0.5 mA
0.4
3.0
P26, P27, P52–P55
LOW output voltage P24, P25, P30, P31
VCC = 4.5 V
IOL = 10.0 mA
LOW output voltage P11–P14
VCC = 4.5 V
VCC = 5.0 V
IOL = 3 mA
IOL = 6 mA
0.4
0.6
1.3
Hysteresis (See note 6)
0.5
VT+ –VT–
V
RESET, P50, P51, INT1, INT2,
INT3, TIM2, TIM3, SIN, SCLK, SCL1,
SCL2, SDA1, SDA2
4
4
HIGH input leak current
P06, P07, P10–P17, P20–P27,
P30, P31, RESET, P50, P51,
VCC = 5.5 V
VI = 5.5 V
5
5
µA
µA
IIZH
IIZL
HIGH input leak current
P00–P07, P10–P17, P20–P27, P30,
P31, P50, P51, RESET
VCC = 5.5 V
VI = 0 V
IOZH
RBS
HIGH output leak current
P00–P05
5
6
10
µA
VCC = 5.5 V
VI = 12 V
2
I C-BUS • BUS switch connection resistor
130
Ω
VCC = 4.5 V
(between SCL1 and SCL2, SDA1 and SDA2)
Notes 1: The total current that flows out of the IC must be 20 mA or less.
2: The total input current to IC (IOL1 + IOL2 + IOL3) must be 30 mA or less.
3: The total average input current for ports P30, P31, P24 and P25 and AVCC–VSS to IC must be 20 mA or less.
4: Connect 0.1 µF or more capacitor externally between the power source pins VCC–VSS and AVCC–VSS so as to reduce power source noise.
Also connect 0.1 µF or more capacitor externally between the pins VCC–CNVSS.
5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz.
6: P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11–P14 have the hysteresis when these
pins are used as multi-master I2C-BUS interface ports. P20–P22 have the hysteresis when these pins are used as serial I/O pins.
7: Pin names in each parameter is described as below.
(1) Dedicated pins: dedicated pin names.
(2) Duble-/triple-function ports
• When the same limits: I/O port name.
• When the limits of functins except ports are different from I/O port limits: function pin name.
Rev. 1.4
98
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
+ Power source voltage
4.5 V
Vcc
1
2
A
Icc
Vcc
X
X
IN
8.00 MHz
OSC1
OUT
Each output pin
OSC2
OH
V
OH
I
V
or
or
Vss
OL
OL
Vss
V
I
Pin VCC is made the operation state and is
measured the current, with a ceramic
resonator.
OH
After setting each output pin to HIGH level when measuring V
OL
and to LOW level when measuring V , each pin is measured.
5.5 V
5.0 V
Vcc
3
4
IZH
Vcc
I
or
IZL
I
A
Each input pin
Each input pin
Vss
Vss
5.5 V
Vcc
4.5V
5
6
12 V
Vcc
BS
I
SCL1 or SDA1
OZH
I
A
Each output pin
A
BS
R
SCL2 or SDA2
Vss
BS
V
Vss
After setting each output pin OFF state, each
pin is measured
BS
R
BS BS
= V /I
Fig.12.1 Measure Circuits
Rev. 1.3
99
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
13. A-D CONVERTER CHARACTERISTICS
(VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
6
—
—
—
Resolution
bits
LSB
LSB
LSB
LSB
Non-linearity error
±1
±0.9
2
Differencial non-linearity error
Zero transition error
V0T
VFST
IOL (SUM) = 0 mA
Full-scale transition error
–2
14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS
Standard clock mode High-speed clock mode
Symbol
Parameter
Unit
Min.
4.7
4.0
4.7
Max.
Min.
1.3
Max.
tBUF
Bus free time
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
tHD; STA
tLOW
Hold time for START condition
LOW period of SCL clock
0.6
1.3
tR
Rising time of both SCL and SDA signals
Data hold time
1000
300
20+0.1Cb
0
300
0.9
tHD; DAT
tHIGH
0
HIGH period of SCL clock
4.0
0.6
tF
Falling time of both SCL and SDA signals
Data set-up time
20+0.1Cb
100
300
tSU; DAT
tSU; STA
tSU; STO
250
4.7
4.0
Set-up time for repeated START condition
Set-up time for STOP condition
0.6
0.6
Note: Cb = total capacitance of 1 bus line
SDA
t
SU;STO
t
HD;STA
t
BUF
t
LOW
t
R
tF
Sr
P
P
S
SCL
S : Start condition
Sr : Restart condition
P : Stop condition
t
HD
;
STA
t
HD
;
DAT
t
HIGH
t
SU;DAT
tSU;STA
2
Fig.14.1 Definition Diagram of Timing on Multi-master I C-BUS
Rev. 1.3
100
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
15. PROM PROGRAMMING METHOD
The built-in PROM of the One Time PROM version (blank) and the
built-in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming adapter.
Product
Name of Programming Adapter
PCA7429G02
M37272EFSP
M37272E8SP
M37272E8FP
PCA7429G02
PCA7427
The PROM of the One Time PROM version (blank) is not tested or
screened in the assembly process nor any following processes. To
ensure proper operation after programming, the procedure shown in
Figure 15.1 is recommended to verify programming.
Programming with
PROM programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150°C exceeding 100 hours.
Fig. 15.1 Programming and Testing of One Time PROM Version
Rev. 1.3
101
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
16. DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
• Mask ROM Order Confirmation Form
• Mark Specification Form
• Data to be written to ROM, in EPROM form (three identical copies)
or FDK
When using EPROM:
<M37272M6/M8-XXXSP/FP, M37272E8SP/FP>
28-pin DIP Type 27512
<M37272MA-XXXSP, M37272EFSP>
32-pin DIP Type 27C101
Rev. 1.4
102
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
17. MASK CONFIRMATION FORM
GZZ–SH55–37B < 91A0 >
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
Section head Supervisor
signature signature
SINGLE-CHIP MICROCOMPUTER M37272M6-XXXSP/FP
MITSUBISHI ELECTRIC
Note : Please fill in all items marked ✽.
Submitted by Supervisor
)
TEL
Company
name
(
✽
Customer
Date
issued
Date :
✽1. Confirmation
Specify the name of the product being ordered.
Three EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by a floppy disk.
Microcomputer name :
M37272M6-XXXSP
M37272M6-XXXFP
Ordering by EPROMs
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
EPROM type (indicate the type used)
(hexadecimal notation)
2 7 5 1 2
EPROM address
000016
Product nameASCII code:
'M37272M6-'
000F16
140016
OSDROM
3BFF16
A00016
Data ROM
(24K)
FFFF16
(1)
Set “FF16” in the shaded area.
1/3
Rev. 1.3
103
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
GZZ–SH55–37B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272M6-XXXSP/FP
MITSUBISHI ELECTRIC
(2)
Write the ASCII codes that indicate the product name of “M37272M6–” to addresses 000016 to 000F16.
Addresses 000016 to 000F16 store the product
name.
Address
Address
000816
ASCII codes ‘M37272M6-’ are listed on the right.
The addresses and data are in hexadecimal nota-
tion.
000016
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘2’ = 3216
‘7’ = 3716
‘2’ = 3216
‘M’ = 4D16
‘6’ = 3616
‘–’ = 2D16
FF16
000116
000216
000316
000416
000516
000616
000716
000916
000A16
000B16
000C16
000D16
000E16
000F16
FF16
Note: If the name of the product contained in the
EPROMs does not match the name on the mask
ROM confirmation form, the ROM processing is
disabled. Please make sure the data is written
correctly.
FF16
FF16
FF16
FF16
FF16
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. We shall assume
the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file.
Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files
must be 1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
✽2. Mark specification
Mark specification must be submitted using the correct form for the type of package being ordered. Fill the
appropriate mark specification form (42P4B for M37272M6-XXXSP , 42P2R for M37272M6-XXXFP) and attach
to the mask ROM confirmation form.
✽3. Comments
2/3
Rev. 1.3
104
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
GZZ–SH55–37B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272M6-XXXSP/FP
MITSUBISHI ELECTRIC
Font data must be stored in the proper OSD ROM address according to the following table.
OSD ROM address of character font data
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Font
OSD ROM address bit
Line number / Character code /
Font bit
0
0
Line number
Character code
bit
Line number = 0A16 to 1D16
Character code = 0016 to FF16 (Do not set 7F16 and 8016.)
Font bit = 0: Left font
1: Right font
Example) The font data “60” (shaded area
) of the character code “AA 16” is stored in address
0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 2 =255416.
Left font
Right font
DB7 DB6 DB5DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Line number 0A16
0B16
0C16
0D16
0E16
0F16
1016
1116
1216
1316
1416
1516
1616
1716
1816
1916
1A16
1B16
1C16
1D16
Character code “AA16”
Notes 1 : The 80-byte addresses corresponding to the character code “7F 16” and “8016” in OSD ROM are the test
data storning area. Set “FF16” to the area (We stores the test data to this area and the different data
from “FF16” is stored for the actual products.)
The test data storing area :
addresses 100016 + (4 + 2n) ✕ 10016 + FE16 to 100016 + (5 + 2n) ✕ 10016 + 0116 (n = 0 to 19)
addresses 14FE16 to 150116
addresses 16FE16 to 170116
•
•
addresses 38•FE16 to 390116
addresses 3AFE16 to 3B0116
2 : The character code “0916” is used for “transparent space” when displaying Closed Caption.
Therefore, set “0016” to the 40-byte addresses corresponding to the character code “09 16.”
The transparent space font data storing area :
addresses 100016 + (4 + 2n) ✕ 10016 + 1216 to 100016 + (4 + 2n) ✕ 10016 + 1316 (n = 0 to 19)
addresses 141216 and 141316
addresses 161216 and 161316
•
•
•
addresses 381216 and 381316
addresses 3A1216 and 3A1316
3/3
Rev. 1.3
105
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
GZZ–SH55–38B < 91A0 >
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
Section head Supervisor
signature signature
SINGLE-CHIP MICROCOMPUTER M37272M8-XXXSP/FP
MITSUBISHI ELECTRIC
Note : Please fill in all items marked ✽.
Submitted by Supervisor
)
TEL
Company
name
(
✽
Customer
Date
issued
Date :
✽1. Confirmation
Specify the name of the product being ordered.
Three EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by a floppy disk.
Microcomputer name :
M37272M8-XXXSP
M37272M8-XXXFP
Ordering by EPROMs
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
EPROM type (indicate the type used)
(hexadecimal notation)
2 7 5 1 2
EPROM address
000016
Product nameASCII code:
'M37272M8-'
000F16
140016
OSDROM
3BFF16
800016
Data ROM
(32K)
FFFF16
(1)
Set “FF16” in the shaded area.
1/3
Rev. 1.3
106
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
GZZ–SH55–38B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272M8-XXXSP/FP
MITSUBISHI ELECTRIC
(2)
Write the ASCII codes that indicate the product name of “M37272M8–” to addresses 000016 to 000F16.
Addresses 000016 to 000F16 store the product
Address
000016
Address
000816
name.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘2’ = 3216
‘7’ = 3716
‘2’ = 3216
‘M’ = 4D16
‘8’ = 3816
‘–’ = 2D16
FF16
ASCII codes ‘M37272M8-’ are listed on the right.
The addresses and data are in hexadecimal nota-
tion.
000116
000216
000316
000416
000516
000616
000716
000916
000A16
000B16
000C16
000D16
000E16
000F16
FF16
FF16
Note: If the name of the product contained in the
EPROMs does not match the name on the mask
ROM confirmation form, the ROM processing is
disabled. Please make sure the data is written
correctly.
FF16
FF16
FF16
FF16
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. We shall assume
the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file.
Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must
be 1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
✽2. Mark specification
Mark specification must be submitted using the correct form for the type of package being ordered. Fill the
appropriate mark specification form (42P4B for M37272M8-XXXSP , 42P2R for M37272M8-XXXFP) and attach
to the mask ROM confirmation form.
✽3. Comments
2/3
Rev. 1.3
107
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
GZZ–SH55–38B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272M8-XXXSP/FP
MITSUBISHI ELECTRIC
Font data must be stored in the proper OSD ROM address according to the following table.
OSD ROM address of character font data
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Font
OSD ROM address bit
Line number / Character code /
Font bit
Line number
Character code
0
0
bit
Line number = 0A16 to 1D16
Character code = 0016 to FF16 (Do not set 7F16 and 8016.)
Font bit = 0: Left font
1: Right font
Example) The font data “60” (shaded area
) of the character code “AA 16” is stored in address
=255416
0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0
2
.
Left font
Right font
DB7 DB6 DB5DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0A16
0B16
0C16
0D16
0E16
0F16
1016
1116
1216
1316
1416
1516
1616
1716
1816
1916
1A16
1B16
1C16
1D16
Line number
Character code “AA16
”
Notes 1 : The 80-byte addresses corresponding to the character code “7F 16” and “8016” in OSD ROM are the test
data storning area. Set “FF16” to the area (We stores the test data to this area and the different data
from “FF16” is stored for the actual products.)
The test data storing area :
addresses 100016 + (4 + 2n) ✕ 10016 + FE16 to 100016 + (5 + 2n) ✕ 10016 + 0116 (n = 0 to 19)
addresses 14FE16 to 150116
addresses 16FE16 to 170116
•
•
•
addresses 38FE16 to 390116
addresses 3AFE16 to 3B0116
2 : The character code “0916” is used for “transparent space” when displaying Closed Caption.
Therefore, set “0016” to the 40-byte addresses corresponding to the character code “09 16.”
The transparent space font data storing area :
addresses 100016 + (4 + 2n) ✕ 10016 + 1216 to 100016 + (4 + 2n) ✕ 10016 + 1316 (n = 0 to 19)
addresses 141216 and 141316
addresses 161216 and 161316
•
•
•
addresses 381216 and 381316
addresses 3A1216 and 3A1316
3/3
Rev. 1.3
108
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
GZZ–SH56–32B < 91A0 >
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272MA-XXXSP
Section head Supervisor
signature signature
MITSUBISHI ELECTRIC
Note : Please fill in all items marked ✽.
Submitted by Supervisor
)
TEL
(
Company
name
✽
Customer
Date
issued
Date :
✽1. Confirmation
Three EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by a floppy disk.
Ordering by EPROMs
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
EPROM type (indicate the type used)
(hexadecimal notation)
2 7 C 1 0 1
EPROM address
000016
Product nameASCII code:
'M37272MA-'
000F16
600016
Data ROM
(40K)
FFFF16
1140016
OSDROM
13BFF16
1FFFF16
(1)
Set “FF16” in the shaded area.
1/3
Rev. 1.3
109
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
GZZ–SH56–32B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272MA-XXXSP
(2)
Write the ASCII codes that indicate the product name of “M37272MA–” to addresses 000016 to 000F16.
Addresses 000016 to 000F16 store the product
Address
000016
Address
000816
name.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘2’ = 3216
‘7’ = 3716
‘2’ = 3216
‘M’ = 4D16
‘A’ = 4116
‘–’ = 2D16
FF16
ASCII codes ‘M37272MA-’ are listed on the right.
The addresses and data are in hexadecimal nota-
tion.
000116
000216
000316
000416
000516
000616
000716
000916
000A16
000B16
000C16
000D16
000E16
000F16
FF16
FF16
Note: If the name of the product contained in the
EPROMs does not match the name on the mask
ROM confirmation form, the ROM processing is
disabled. Please make sure the data is written
correctly.
FF16
FF16
FF16
FF16
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. We shall assume
the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file.
Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must
be 1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
✽2. Mark specification
Mark specification must be submitted using the correct form for the type of package being ordered. Fill the
appropriate mark specification form (42P4B for M37272MA-XXXSP) and attach to the mask ROM confirmation
form.
✽3. Comments
2/3
Rev. 1.3
110
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
GZZ–SH56–32B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272MA-XXXSP
MITSUBISHI ELECTRIC
Font data must be stored in the proper OSD ROM address according to the following table.
OSD ROM address of character font data
AD16AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Font
OSD ROM address bit
Line number / Character
code / Font bit
Line number
Character code
1
0
0
bit
Line number = 0A16 to 1D16
Character code = 0016 to FF16 (Do not set 7F16 and 8016.)
Font bit = 0: Left font
1: Right font
Example) The font data “60” (shaded area
) of the character code “AA 16” is stored in address
1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 2 =1255416.
Left font
Right font
DB7 DB6 DB5DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Line number
0A16
0B16
0C16
0D16
0E16
0F16
1016
1116
1216
1316
1416
1516
1616
1716
1816
1916
1A16
1B16
1C16
1D16
Character code “AA16”
Notes 1 : The 80-byte addresses corresponding to the character code “7F 16” and “8016” in OSD ROM are the test
data storning area. Set “FF16” to the area (We stores the test data to this area and the different data
from “FF16” is stored for the actual products.)
The test data storing area :
addresses 1100016 + (4 + 2n) ✕ 10016 + FE16 to 1100016 + (5 + 2n) ✕ 10016 + 0116 (n = 0 to 19)
addresses 114FE16 to 1150116
addresses 116FE16 to 1170116
•
•
•
addresses 138FE16 to 1390116
addresses 13AFE16 to 13B0116
2 : The character code “0916” is used for “transparent space” when displaying Closed Caption.
Therefore, set “0016” to the 40-byte addresses corresponding to the character code “09 16.”
The transparent space font data storing area :
addresses 1100016 + (4 + 2n) ✕ 10016 + 1216 to 1100016 + (4 + 2n) ✕ 10016 + 1316 (n = 0 to 19)
addresses 1141216 and 1141316
addresses 1161216 and 1161316
•
•
•
addresses 1381216 and 1381316
addresses 13A1216 and 13A1316
3/3
Rev. 1.3
111
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
18. MARK SPECIFICATION FORM
Rev. 1.3
112
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Rev. 1.3
113
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
19. ONE TIME PROM VERSION M37272E8SP/FP, M37272EFSP MARKING
M37272E8SP
XXXXXXX
XXXXXXX is mitsubishi lot number
XXXXXXX is mitsubishi lot number
XXXXXXX is mitsubishi lot number
M37272E8FP
XXXXXXX
M37272EFSP
XXXXXXX
Rev. 1.3
114
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
20. APPENDIX
Pin Configuration (TOP VIEW)
1
2
42
41
40
39
P5
0
/HSYNC
P5
P5
P5
P5
2
/R
P5
1
/VSYNC
/PWM0
/PWM1
/PWM2
/PWM3
/PWM4
/PWM5
3
4
5
/G
3
4
5
P0
P0
P0
P0
P0
P0
0
/B
1
2
3
4
5
/OUT1
38
37
36
P2
P2
0
/SCLK
/SOUT
6
7
1
P2
2/SIN
8
9
35
34
P1
P1
0
/OUT2
/SCL1
1
P0
6
/INT2/AD4
P0 /INT1
10
33
32
31
7
P1
P1
P1
P1
P1
P1
P3
2
3
4
5
6
7
0
/SCL2
/SDA1
/SDA2
/AD1/INT3
/AD2
11
12
P2
P2
3
/TIM3
/TIM2
4
P2
5
13
14
15
30
29
28
AVCC
HLF
/AD3
16
17
27
26
/AD5
VHOLD
CVIN
P3
1/AD6
18
19
25
24
RESET
CNVSS
P2
P2
6
/OSC1/XCIN
XIN
20
21
23
22
7/OSC2/XCOUT
XOUT
V
CC
V
SS
Outline 42P4B
1
2
42
P5
0
/HSYNC
P5
2
/R
41
40
39
P5
1
/VSYNC
/PWM0
/PWM1
/PWM2
/PWM3
/PWM4
/PWM5
P5
P5
P5
3
4
5
/G
3
4
5
6
7
/B
P0
P0
0
1
2
3
4
5
/OUT1
38
37
36
P0
P0
P0
P0
P2
0/SCLK
P2
P2
1
/SOUT
/SIN
2
8
9
35
34
P1
P1
P1
0
/OUT2
/SCL1
/SCL2
1
P0
6
/INT2/AD4
P0 /INT1
10
11
33
32
2
3
4
7
P2
P2
3
/TIM3
P1
P1
/SDA1
/SDA2
12
31
30
29
4
/TIM2
P2
5
13
14
P1
P1
P1
5
6
7
/AD1/INT3
/AD2
AVCC
15
16
28
27
/AD3
HLF
V
HOLD
P3
P3
0
/AD5
/AD6
17
18
19
26
25
24
CVIN
1
RESET
CNVSS
IN
OUT
X
P2
P2
6/OSC1/XCIN
20
21
23
22
X
7/OSC2/XCOUT
V
SS
VCC
Outline 42P2R-A/E
Rev. 1.4
115
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Memory Map
■M37272M6/M8-XXXSP/FP, M37272E8SP/FP
000016
1000016
Zero page
00BF16
00C016
00FF16
010016
SFR1 area
M37272M8-
XXXSP/FP,
M37272E8SP/FP
RAM
M37272M6-
XXXSP/FP
RAM
01FF
02001166
(1024 bytes)
(1152 bytes)
SFR2 area
Not used
020F16
030016
032016
ROM correction function
053F16
05BF16
Vector 1: address 030016
Vector 2: address 032016
Not used
Not used
OSD RAM
(128 bytes)
(See note)
080016
087F16
Not used
OSD ROM
(10K bytes)
140016
3BFF16
Not used
M37272M8-
XXXSP/FP,
M37272E8SP/FP
ROM
(32K bytes)
800016
A00016
M37272M6-
XXXSP/FP
ROM
FF0016
FFDE16
Special page
(24K bytes)
Interrupt vector area
FFFF16
1FFFF16
Note: Refer to Table 8.11.3 OSD RAM.
Rev. 1.4
116
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■M37272MA-XXXSP, M37272EFSP
1000016
000016
Zero page
00BF16
00C016
00FF16
010016
SFR1 area
02001166
01FF
RAM
(1472 bytes)
SFR2 area
Not used
020F16
030016
032016
Not used
ROM correction functrion
Vector 1: address 030016
Vector 2: address 032016
06FF16
Not used
Not used
OSD RAM
(128 bytes)
(See note)
080016
087F16
100016
1140016
13BFF16
OSD ROM
(10K bytes)
M37272EFSP
ROM
(60K bytes)
600016
Not used
M37272MA-XXXSP
ROM
(40K bytes)
FF0016
FFDE16
Special page
Interrupt vector area
FFFF16
1FFFF16
Note: Refer to Table 8.11.3 OSD RAM.
Rev. 1.3
117
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Memory Map of Special Function Register
(SFR)
■SFR1 Area (addresses C016 to DF16
)
<Bit allocation>
<State immediately after reset>
:
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
Name
:
: No function bit
: Indeterminate immediately
after reset
: Fix this bit to “0”
(do not write “1”)
0
1
: Fix this bit to “1”
(do not write “0”)
Register
Bit allocation
State immediately after reset
Address
b7
b0 b7
b0
?
0016
Port P0 (P0)
C016
C116
Port P0 direction register (D0)
?
C216 Port P1 (P1)
0016
?
0016
C316
Port P1 direction register (D1)
Port P2 (P2)
C416
C516
Port P2 direction register (D2)
P31 P30
P31CP30CP31DP30D
0
0
0
0
0016
0
0
?
?
C616 Port P3 (P3)
T3SC
Port P3 direction register (D3)
C716
C816
C916
CA16
CB16
CC16
?
?
?
Port P5 (P5)
PF7
PF5 PF4 PF3 PF2
0016
0016
0016
?
0
0
OSD port control register (PF)
CD16
CE16
CF16
D016
CDL27CDL26CDL25CDL24CDL23CDL22CDL21CDL20
CDH27CDH26CDH25CDH24CDH23CDH22CDH21CDH20
?
?
Caption data register 3 (CD3)
Caption data register 4 (CD4)
OSD control register (OC)
OC6
HP6
OC5 OC4 OC3 OC2 OC1 OC0
HP5 HP4 HP3 HP2 HP1 HP0
0
0016
0016
Horizontal position register (HP)
Block control register 1 (BC1)
Block control register 2 (BC2)
Vertical position register 1 (VP1)
Vertical position register 2 (VP2)
Window register 1 (WN1)
D116
D216
D316
D416
D516
D616
D716
BC11BC10
BC17BC16BC15BC14BC13BC12
?
?
?
?
?
BC27BC26BC25BC24BC23BC22BC21BC20
VP17VP16VP15VP14VP13VP12VP11VP10
VP27VP26VP25VP24VP23VP22VP21VP20
WN17WN16WN15WN14WN13WN12WN11WN10
WN27WN26WN25WN24WN23WN22WN21WN20
?
Window register 2 (WN2)
PC6
PC5 PC4 PC3 PC2 PC1 PC0
4016
0016
?
0
RC7
D816 I/O polarity control register (PC)
RC4 RC3 RC2 RC1 RC0
0
0
Raster color register (RC)
D916
DA16
DB16
DC16
DD16
DE16
DF16
?
INT3 INT2 INT1
0016
0016
0016
Interrupt input polarity control register (RE)
0016
0016
0016 (See note 1)
0016 (See note 2)
Notes 1: This is only M37272MA-XXXSP and M37272EFSP.
2: As for M37272M6/M8-XXXSP/FP and M37272E8SP/FP, the reset value is ? (indeterminate).
Rev. 1.4
118
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■SFR1 Area (addresses E016 to FF16
)
<Bit allocation>
:
<State immediately after reset>
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
Name
:
: No function bit
: Indeterminate immediately
after reset
: Fix this bit to “0”
(do not write “1”)
0
1
: Fix this bit to “1”
(do not write “0”)
Bit allocation
State immediately after reset
Address
Register
b7
0
b0 b7
b0
Data slicer control register 1 (DSC1)
Data slicer control register 2 (DSC2)
Caption data register 1 (CD1)
Caption data register 2 (CD2)
Clock run-in detect register (CRD)
Data clock position register (DPS)
Caption position register (CPS)
Data slicer test register 2
DSC12DSC11DSC10
0016
E016
E116
E216
E316
1
0
1
0
0
DSC25DSC24DSC23
DSC20
1
?
0
?
0
?
?
0
?
CDL17CDL16CDL15CDL14CDL13CDL12CDL11CDL10
CDH17CDH16CDH15CDH14CDH13CDH12CDH11CDH10
CRD7CRD6CRD5CRD4CRD3
0016
0016
0016
0916
E416
E516
E616
DPS7 DPS6 DPS5 DPS4 DPS3
1
0
0
CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
0
0
?
0
0
0
0
0
0
0016
0016
0016
E716
E816
E916
EA16
EB16
EC16
Data slicer test register 1
HC5 HC4 HC3 HC2 HC1 HC0
Synchronous signal counter register (
Serial I/O register (SIO)
?
Serial I/O mode register (SM)
0
SM6 SM5
SM3 SM2 SM1 SM0
0016
?
0
ADC14
ADC12 ADC11ADC10
A-D control register 1 (AD1)
A-D control register 2 (AD2)
Timer 5 (T5)
0
0
0
0
0
0
ADC25 ADC24ADC23 ADC22ADC21 ADC20
0016
0716
ED16
EE16
EF16
F016
Timer 6 (T6)
FF16
FF16
0716
FF16
0716
Timer 1 (T1)
Timer 2 (T2)
F116
F216
F316
F416
F516
Timer 3 (T3)
Timer 4 (T4)
TM17 TM16 TM15TM14 TM13 TM12 TM11 TM10
TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20
Timer mode register 1 (TM1)
0016
Timer mode register 2 (TM2)
2
0016
?
0016
D7 D6 D5 D4 D3 D2 D1 D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0RBW
F616 I C data shift register (S0)
2
F716
F816
I C address register (S0D)
MST TRX BB PIN AL AAS AD0 LRB
10BIT
2
0
0
0
1
0
0
0
?
I C status register (S1)
BSEL1BSEL0
ALS ESO BC2 BC1 BC0
CCR4CCR3CCR2 CCR1CCR0
CM2
2
0016
I C control register (S1D)
SAD
FAST
MODE
F916
FA16
FB16
FC16
FD16
FE16
FF16
ACK
ACK
2
0016
3C16
0016
0016
0016
0016
I C clock control register (S2)
BIT
CM7 CM6 CM5
1
1
0
0
CPU mode register (CPUM)
VSCR OSDRTM4RTM3RTM2RTM1R
IN3R
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
TM56R
DSR
IICR IN2R CKR S1R
IN1R
0
VSCEOSDE TM4ETM3ETM2ETM1E
IICE IN2E CKE S1E DSE IN1E
IN3E
Interrupt control register 2 (ICON2) TM56CTM56E
Rev. 1.3
119
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■SFR2 Area (addresses 20016 to 20F16
)
<Bit allocation>
:
<State immediately after reset>
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
Name
:
: No function bit
: Indeterminate immediately
after reset
: Fix this bit to “0”
(do not write “1”)
0
1
: Fix this bit to “1”
(do not write “0”)
Register
Bit allocation
State immediately after reset
Address
b7
b0 b7
b0
PWM0 register (PWM0)
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM4 register (PWM4)
PWM5 register (PWM5)
20016
20116
20216
20316
?
?
?
?
?
?
?
?
20416
20516
20616
0016
0016
20716
20816
20916
20A16
PM13
PM10
PWM mode register 1 (PM1)
PWM mode register 2 (PM2)
ROM correction address 1 (high-order)
?
?
?
?
0
?
?
0
PM25 PM24 PM23 PM22 PM21 PM20
0
0
0016
0016
0016
0016
0016
0016
?
20B16 ROM correction address 1 (low-order)
20C16
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
20D16
20E16
20F16
RC1 RC0
Rev. 1.3
120
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Internal State of Processor Status Register and
Program Counter at Reset
<State immediately after reset>
<Bit allocation
>
:
: “0” immediately after reset
: “1” immediately after reset
0
1
?
Function bit
:
:
Name
No function bit
: Indeterminate immediately
after reset
: Fix to this bit to “0”
(do not write to “1”)
0
1
: Fix to this bit to “1”
(do not write to “0”)
Register
Bit allocation
State immediately after reset
b0
b0
b7
N
b7
Processor status register (PS)
V
T
B
D
I
Z
C
?
?
?
?
?
1
?
?
Program counter (PC
H)
Contents of address FFFF16
Contents of address FFFE16
Program counter (PC
L
)
Rev. 1.3
121
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Structure of Register
The figure of each register structure describes its functions, contents
at reset, and attributes as follows:
<Example>
Bit position
Bit attributes(Note 2)
CPU Mode Register
(Note 1)
Values immediately after reset release
b7b6 b5b4b3 b2b1b0
1 1 0 0
CPU mode register (CPUM) (CM) [Address 00FB16]
B
Name
Functions
R W
R W
After re
0
Processor mode bits b1 b0
(CM0, CM1)
0, 1
0 0: Single-chip mode
0 1:
1 0:
1 1:
Not available
0: 0 page
1: 1 page
Stack page selection
bit (See note) (CM2)
2
1
R W
3, 4 Fix these bits to “1.”
1
1
R W
R W
5
Nothing is assigned. This bit is write disable bit.
When this bit is read out, the value is “1.”
Clock switch bits
(CM6, CM7)
b7 b6
6, 7
0
R W
0 0: f(XIN) = 8 MHz
0 1: f(XIN) = 12 MHz
1 0: f(XIN) = 16 MHz
1 1: Do not set
: Bit in which nothing is assigned
Notes 1: Values immediately after reset release
0 ••••••••••••••••••“0” after reset release
1 ••••••••••••••••••“1” after reset release
Indeterminate•••Indeterminate after reset
release
2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
W••••••Write
W
R
–
••••••Read enabled
••••••Read disabled
••••••Write enabled
–
••••••Write disabled
✽ ••••••“0” can be set by software, but “1”
cannot be set.
Rev. 1.3
122
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00C116, 00C316, 00C516
Port Pi Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i=0,1,2) [Addresses 00C116, 00C316, 00C516
]
B
0
Name
Functions
After reset
R
R
W
W
0 : Port Pi
1 : Port Pi
0
0
input mode
output mode
0
Port Pi direction register
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0 : Port Pi
1 : Port Pi
1
1
input mode
output mode
R
R
R
R
R
R
R
W
W
W
W
W
W
W
0 : Port Pi
1 : Port Pi
2
2
input mode
output mode
0 : Port Pi
1 : Port Pi
3
3
input mode
output mode
0 : Port Pi
1 : Port Pi
4
4
input mode
output mode
0 : Port Pi
1 : Port Pi
5
5
input mode
output mode
0 : Port Pi
1 : Port Pi
6
6
input mode
output mode
0 : Port Pi
1 : Port Pi
7
7
input mode
output mode
Address 00C716
Port P3 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
Port P3 direction register (P3D) [Address 00C716
]
B
0
Name
Functions
R
W
W
After reset
Port P3 direction register
0 : Port P3
1 : Port P3
0
0
input mode
output mode
0
R
R
R
R
1
2
3
0
0
0
W
W
W
0 : Port P3
1 : Port P3
1
1
input mode
output mode
Port P3
0
output structure
selection bit (P30C)
0 : CMOS output
1 : N-channel open-drain output
Port P3
1
output structure
0 : CMOS output
selection bit (P30C)
1 : N-channel open-drain output
4, 5,
7
0
0
R
R
—
W
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Timer 3 count source
selection bit (T3SC)
Refer to Timer section.
6
Rev. 1.3
123
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00CB16
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
OSD port control register (PF) [Address 00CB16
]
0 0
B
Name
Functions
R
R
W
—
After reset
0
0, 1
Fix these bits to “0.”
2
3
4
Port P5
selection bit (PF2)
2
output signal
0 : R signal output
1 : Port P52 output
0
0
0
R
R
R
W
W
W
Port P5
3
output signal
0 : G signal output
1 : Port P5 output
selection bit (PF3)
3
0 : B signal output
1 : Port P5 output
Port P54 output signal
4
selection bit (PF4)
Port P5 output signal
selection bit (PF5)
5
0 : OUT1 signal output
1 : Port P5 output
0
0
0
R
R
R
W
—
W
5
6
7
3
Nothing is assigned. This bit is write disable bit.
When this bit is read out, the value is “0.”
Port P1
0
output signal
0 : Port P10 output
selection bit (PF7)
1 : OUT2 signal output
Address 00D016
OSD Control Register
b7 b6 b5b4 b3 b2b1 b0
0
OSD control register (OC) [Address 00D0 16]
Functions
Name
After reset R
W
B
0
0 : All-blocks display off
1 : All-blocks display on
0
0
0
0
R W
OSD control bit
(OC0) (See note)
Automatic solid space
control bit (OC1)
0 : OFF
1 : ON
R W
R W
R W
1
2
3
Window control bit
(OC2)
0 : OFF
1 : ON
CC mode clock
0 : Data slicer clock
selection bit (OC3)
1 : Clock from OSC1 pin
4
OSD mode clock
selection bit (OC4)
0
0
R W
R W
0 : Data slicer clock
1 : Clock from OSC1 pin
b6 b5
5, 6 OSC1 clock
0 0: 32 kHz oscillating
selection bit
(OC5, OC6)
0 1: Do not set.
1 0: LC oscillating,
Ceramic oscillating
1 1: Do not set.
0
R W
7
Fix this bit to “0.”
Note: Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next V SYNC.
Rev. 1.3
124
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00D116
Horizontal Position Register
b7 b6 b5b4 b3 b2b1 b0
Horizontal position register (HP) [Address 00D1 16
]
B
0
Name
Functions
Horizontal display start positions
128 steps (0016 to 7F16
(1 step is 4TOSC
After reset R W
Horizontal display start
0
R W
)
to position control bits
6
(HP0 to HP6)
)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
7
0
R —
Note: The setting value synchronizes with the V SYNC
.
Address 00D216, 00D316
Block Control register i
b7 b6 b5b4 b3 b2b1 b0
Block control register i (BCi) (i=1, 2) [Addresses 00D2 16 and 00D316
]
After reset
B
Name
Functions
R W
R W
b1 b0
Indeterminate
0, 1 Display mode
selection bits
(BCi0, BCi1)
0 0: Display OFF
0 1: CC mode
1 0: OSD mode (Border OFF)
1 1: OSD mode (Border ON)
(See note 1)
b4 b3 b2 Pre-divide Ratio Dot Size
Indeterminate
Indeterminate
2, 3 Dot size selection
bits (BCi2, BCi3)
R W
R W
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
0
1
✕ 2
4
Pre-divide ratio
selection bit (BCi4)
✕ 3
5
6
0: OUT1 output control
1: OUT2 output control
OUT1/OUT2 output control
bit (BCi5) (See note 1)
Indeterminate
Indeterminate
R W
R W
Vertical display start
position control bit
(BCi6)
BC16: Block 1
BC26: Block 1
BC17: Window top boundary
BC27: Window bottom boundary
Indeterminate
7
Window top/bottom
boundary control bit
(BCi7)
R W
Notes 1: Bit RA3 of OSD RAM controls OUT1 output when bit 5 is “0.”
Bit RA3 of OSD RAM controls OUT2 output when bit 5 is “1.”
2: Tc is OSD clock cycle divided in pre-divide circuit.
3: H is HSYNC
.
Rev. 1.3
125
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00D416, 00D516
Vertical Position Register i
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D416, 00D516
]
After reset
Name
B
Functions
R
R
W
W
Vertical display start
position control bits
(VPi0 to VPi7)
Vertical display start position =
Inderterminate
0
to
7
TH
✕ (BCi6 ✕ 162 + n)
(n: setting value, T
H: HSYNC cycle,
(See note)
BCi6: bit 6 of block control register i)
Note: Set values except “0016” to VPi when BCi6 is “0.”
Address 00D616
Window Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Window register 1 (WN1) [Address 00D616
]
After reset
Name
B
Functions
R
R
W
W
Window top border position =
✕ (BC17 ✕ 162 + n)
(n: setting value, T : HSYNC cycle,
BC17: bit 7 of block control register 1)
Inderterminate
Window top boundary
control bits
(WN10 to WN17)
0
to
7
T
H
H
Notes 1: Set values except “0016” to WN1 when BC17 is “0.”
2: Set values fit for the following condition: WN1 < WN2.
Address 00D716
Window Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Window register 2 (WN2) [Address 00D716
]
After reset
Name
B
Functions
R
R
W
W
Window bottom border position =
✕ (BC27 ✕ 162 + n)
(n: setting value, T : HSYNC cycle,
BC27: bit 7 of block control register 2)
Inderterminate
Window bottom boundary
control bits
(WN20 to WN27)
0
to
7
T
H
H
Note: Set values fit for the following condition: WN1 < WN2.
Rev. 1.3
126
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00D816
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
I/O polarity control register (PC) [Address 00D816
]
After reset
0
B
0
Name
Functions
R
R
W
W
H
SYNC input polarity
switch bit (PC0)
0 : Positive polarity input
1 : Negative polarity input
1
2
3
4
5
0 : Positive polarity input
1 : Negative polarity input
0
0
0
0
0
R
R
R
R
R
W
W
W
W
W
V
SYNC input polarity
switch bit (PC1)
0 : Positive polarity output
1 : Negative polarity output
R, G, B output polarity
switch bit (PC2)
OUT1 output polarity
switch bit (PC3)
0 : Positive polarity output
1 : Negative polarity output
OUT2 output polarity
switch bit (PC4)
0 : Positive polarity output
1 : Negative polarity output
Display dot line selection
bit (PC5) (See note)
0 : “
” at even field
” at odd field
” at even field
” at odd field
“
1 : “
“
6
7
Field determination flag
(PC6)
0 : Even field
1 : Odd field
1
0
R
R
—
W
Fix this bit to “0.”
Note: Refer to the corresponding figure (8.11.14).
Address 00D916
Raster Color Register
b7 b6 b5b4 b3 b2b1 b0
0 0
Raster color register (RC) [Address 00D9 16
]
After reset
Functions
Name
R
W
B
0
0 : No output
1 : Output
0
R W
R W
R W
R W
Raster color R
control bit (RC0)
Raster color G
control bit (RC1)
0 : No output
1 : Output
0
0
0
1
2
3
Raster color B
control bit (RC2)
0 : No output
1 : Output
Raster color OUT1
control bit (RC3)
0 : No output
1 : Output
4
Raster color OUT2
control bit (RC4)
0 : No output
1 : Output
0
R W
5, 6
Fix these bits to “0.”
0
0
R W
R W
7
Port function
selection bit (RC7)
0 : OSC1/XCIN
,
OSC2/XCOUT
1 : P2 , P2
6
7
Note: Either OSD clock source or 32 kHz oscillating clock is
selected by bits 5 and 6 of the OSD control register.
Rev. 1.3
127
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00DC16
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt input polarity register (RE) [Address 00DC16]
B
0
Name
Functions
After reset
0
R
R
W
W
INT1 polarity switch bit
(INT1)
0 : Positive polarity
1 : Negative polarity
0
0
0
R
R
R
W
W
—
4
5
INT2 polarity switch bit
(INT2)
0 : Positive polarity
1 : Negative polarity
INT3 polarity switch bit
(INT3)
0 : Positive polarity
1 : Negative polarity
4
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Address 00E016
Data Slicer Control Register 1
b7b6b5b4b3b2b1b0
0 1 1 0 0
Data slicer control register 1(DSC1) [Address 00E016
]
B
0
Name
Functions
0: Stopped
1: Operating
After reset
R
W
0
R
W
W
W
W
Data slicer and timing signal
generating circuit control bit (DSC10)
1
2
0: F2
1: F1
0
0
0
R
R
R
Selection bit of data slice reference
voltage generating field (DSC11)
0: Video signal
1: HSYNC signal
Reference clock source
selection bit (DSC12)
3, 4
Fix these bits to “0.”
5, 6
7
0
0
R
R
W
W
Fix these bits to “1.”
Fix this bit to “0.”
Definition of fields 1 (F1) and 2 (F2)
sep
H
F1:
F2:
sep
V
sep
H
sep
V
Rev. 1.3
128
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00E116
Data Slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Data slicer control register 2 (DSC2) [Address 00E116]
0
1
After reset
R
R
W
—
B
0
Name
Functions
0: Data is not latched yet
and a clock-run-in is not
determined.
1: Data is latched and a
clock-run-in is determined.
Indeterminate
Caption data latch
completion flag 1
(DSC20)
Fix this bit to “1.”
Test bit
0
R
1
W
—
—
W
2
Read-only
Indeterminate R
Indeterminate R
3
4
0: F2
1: F1
Field determination
flag(DSC23)
0: Method (1)
1: Method (2)
0
R
R
Vertical synchronous signal
(Vsep) generating method
selection bit (DSC24)
5
6
0: Match
1: Mismatch
Indeterminate
—
V-pulse shape
determination flag (DSC25)
0
Fix this bit to “o.”
Test bit
R
R
W
—
Read-only
7
Indeterminate
Definition of fields 1 (F1) and 2 (F2)
sep
H
F1:
sep
V
sep
H
F2:
sep
V
Address 00E416
Clock Run-in Detect Register
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register (CRD) [Address 00E416
]
R
R
W
—
B
Name
Functions
After reset
0
0
to
2
Read-only
Test bits
3
to
7
Number of reference clocks to
be counted in one clock run-in
pulse period.
0
R
—
Clock run-in detection bit
(CRD3 to CRD7)
Rev. 1.3
129
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00E516
Data Clock Position Register
b7 b6 b5 b4 b3 b2 b1 b0
0
1
0
Data clock position register (DPS) [Address 00E516
]
R
R
W
W
B
0
Name
Functions
After reset
1
Fix this bit to “0.”
1
Fix this bit to “1.”
Fix this bit to “0.”
0
R
W
2
3
0
1
R
R
W
W
Data clock position set
bits (DPS3 to DPS7)
4
to
7
0
Address 00E616
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0
Caption Position Register (CPS) [Address 00E616
]
R
R
W
W
B
Name
Functions
After reset
0
to
4
0
Caption position
bits(CPS0 to CPS4)
5
0: Data is not latched yet and a
clock-run-in is not determined.
1: Data is latched and a
R
—
Caption data latch
completion flag 2
(CPS5)
Indeterminate
clock-run-in is determined.
W
6, 7
Refer to the corresponding
Table (Table 8.10.1).
0
R
Slice line mode
specification bits
(in 1 field) (CPS6, CPS7)
Address 00E916
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (HC) [Address 00E916
]
R
W
—
B
Name
Functions
After reset
0
to
4
Count value (HC0 to HC4)
0
R
5
Count source (HC5)
0: HSYNC signal
1: Composite sync signal
0
0
R
W
—
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
6, 7
R
Rev. 1.3
130
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00EB16
Serial I/O Mode Register
b7b6 b5b4b3 b2b1b0
0
0
Serial I/O mode register (SM) [Address 00EB16]
After reset
B
Name
Functions
R W
R W
0
b1 b0
0, 1
Internal synchronous
clock selection bits
(SM0, SM1)
0 0: f(XIN)/4 or f(XCIN)/4
0 1: f(XIN)/16 or f(XCIN)/16
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/64
0
0
R W
R W
2
3
0: External clock
1: Internal clock
Synchronous clock
selection bit (SM2)
0: P20, P21
1: SCLK, SOUT
Port function
selection bit (SM3)
0
0
R W
R W
Fix this bit to “0.”
4
5
6
7
0: LSB first
1: MSB first
Transfer direction
selection bit (SM5)
Transfer clock input
pin selection bit (SM6)
0: Input signal from SIN pin
1: Input signal from SOUT pin
0
0
R W
R W
Fix this bit to “0.”
Address 00EC16
A-D Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (AD1) [Address 00EC16
]
B
Name
Functions
After reset R W
0
to
2
Analog input pin selection
bits
(ADC10 to ADC12)
b2 b1 b0
0
R W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : AD1
1 : AD2
0 : AD3
1 : AD4
0 : AD5
1 : AD6
0 :
Do not set.
1 :
3
4
This bit is a write disable bit.
When this bit is read out, the value is “0.”
0
—
R
0: Input voltage < reference voltage
1: Input voltage > reference voltage
Storage bit of comparison
result (ADC14)
Indeterminate R W
5
to
7
Nothing is assigned. This bits are write disable bits.
When these bits are read out, the values are “0.”
0
—
R
Rev. 1.3
131
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00ED16
A-D Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 2 (AD2) [Address 00ED16
]
B
Name
Functions
After reset
R
R
W
W
b5 b4 b3 b2 b1 b0
0
to
5
D-A converter set bits
(ADC20 to ADC25)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0 : 1/128Vcc
1 : 3/128Vcc
0 : 5/128Vcc
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1 : 123/128Vcc
0 : 125/128Vcc
1 : 127/128Vcc
Nothing is assigned. These bits are write disable bits.
When these bits are reed out, the values are “ 0.”
0
R
—
6, 7
Address 00F416
Timer Mode Register 1
b7b6 b5b4b3 b2b1b0
Timer mode register 1 (TM1) [Address 00F4 16
]
After reset
0
B
0
Name
Functions
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Count source selected by bit 5 of TM1
R W
R W
Timer 1 count source
selection bit 1 (TM10)
0: Count source selected by bit 4 of TM1
1: External clock from TIM2 pin
0
R W
1
Timer 2 count source
selection bit 1 (TM11)
Timer 1 count
stop bit (TM12)
2
3
4
0: Count start
1: Count stop
0
0
0
R W
R W
R W
Timer 2 count stop
bit (TM13)
0: Count start
1: Count stop
Timer 2 count source
selection bit 2
(TM14)
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Timer 1 overflow
5
Timer 1 count source
selection bit 2 (TM15)
0: f(XIN)/4096 or f(XCIN)/4096 (See note)
1: External clock from TIM2 pin
0
R W
6
7
Timer 5 count source
selection bit 2 (TM16)
0: Timer 2 overflow
1: Timer 4 overflow
0
0
R W
R W
Timer 6 internal count 0: f(XIN)/16 or f(XCIN)/16 (See note)
source selection bit
(TM17)
1: Timer 5 overflow
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Rev. 1.3
132
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00F516
Timer Mode Register 2
b7b6 b5b4b3 b2b1b0
Timer mode register 2 (TM2) [Address 00F5 16
]
After reset
0
B
0
Name
Functions
R W
R W
Timer 3 count source
selection bit (TM20)
(b6 at address 00C716
)
b0
0
0
1
1
0 : f(XIN)/16 or f(XCIN)/16 (See note)
1 : f(XCIN
)
0 :
1 :
External clock from TIM3 pin
b4 b1
1, 4
Timer 4 count source
selection bits
(TM21, TM24)
0
R W
0
0
1
1
0 : Timer 3 overflow signal
1 : f(XIN)/16 or f(XCIN)/16 (See note)
0 : f(XIN)/2 or f(XCIN)/2 (See note)
1 : f(XCIN
)
Timer 3 count
stop bit (TM22)
2
3
0: Count start
1: Count stop
0
0
R W
R W
Timer 4 count stop bit
(TM23)
0: Count start
1: Count stop
Timer 5 count stop bit
(TM25)
5
6
0: Count start
1: Count stop
0
0
R W
R W
Timer 6 count stop bit
(TM26)
0: Count start
1: Count stop
Timer 5 count source
selection bit 1
(TM27)
7
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Count source selected by bit 6
of TM1
0
R W
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Address 00F616
2
I C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C data shift register1(S0) [Address 00F616
]
B
Name
Functions
After reset
R
W
W
0
to
7
D0 to D7 This is an 8-bit shift register to store
receive data and write transmit data.
Indeterminate R
2
Note:
To write data into the I C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Rev. 1.3
133
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00F716
2
I C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716
]
B
Name
Functions
After reset R W
<Only in 10-bit addressing (in slave) mode>
The last significant bit of address data is
compared.
0
Read/write bit
(RBW)
0
R —
0: Wait the first byte of slave address after
START condition
(read state)
1: Wait the first byte of slave address after
RESTART condition
(write state)
Slave address
(SAD0 to SAD6)
<In both modes>
The address data is compared.
1
to
7
0
R W
Address 00F816
2
I C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816
]
B
Name
Functions
After reset R W
0
Last receive bit (LRB)
(See note)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
Indeterminate
R —
R —
R —
(See note)
1
2
General call detecting flag
(AD0) (See note)
0 : No general call detected
1 : General call detected
0
0
(See note)
Slave address comparison
flag (AAS) (See note)
0 : Address mismatch
1 : Address match
(See note)
(See note)
3
4
5
Arbitration lost detecting flag 0 : Not detected
(AL) (See note)
0
1
0
R —
R W
R W
R W
1 : Detected
I2C-BUS interface interrupt
request bit (PIN)
0 : Interrupt request issued
1 : No interrupt request issued
Bus busy flag (BB)
0 : Bus free
1 : Bus busy
0
6, 7
Communication mode
specification bits
(TRX, MST)
b7 b6
0
0
1
1
0 : Slave recieve mode
1 : Slave transmit mode
0 : Master recieve mode
1 : Master transmit mode
Note : These bits and flags can be read out, but cannnot be written.
Rev. 1.3
134
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00F916
2
I C Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register (S1D address 00F916
)
B
Name
Functions
After reset R W
Bit counter
(Number of transmit/recieve
bits)
(BC0 to BC2)
b2 b1 b0
0
0
to
2
R W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 :8
1 :7
0 :6
1 :5
0 :4
1 :3
0 :2
1 :1
I2C-BUS interface use
enable bit (ESO)
0 :Disabled
1 :Enabled
3
4
5
0
R W
Data format selection
bit(ALS)
0
0 :Addressing mode
1 :Free data format
R W
Addressing format selection
bit (10BIT SAD)
0
0 :7-bit addressing format
1 :10-bit addressing format
R W
b7 b6 Connection port (See note)
0
6, 7 Connection control bits
between I2C-BUS interface
and ports
R W
0
0
1
1
0 :None
1 :SCL1, SDA1
0 :SCL2, SDA2
1 :SCL1, SDA1
SCL2, SDA2
Note: When using ports P1
automatically from CMOS output to N-channel open-drain output.
1-P14
as I2C-BUS interface, the output structure changes
Address 00FA16
2
I C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C clock control register (S2 : address 00FA16
)
After reset
0
B
Name
Functions
R W
R W
0
to
4
Setup value Standard clock High speed
SCL frequency control
bits
(CCR0 to CCR4)
of CCR4–
CCR0
00 to 02
mode
clock mode
Setup disabled Setup disabled
Setup disabled
333
03
04
05
06
Setup disabled
250
400 (See note)
100
83.3
166
500/CCR value 1000/CCR value
17.2
16.6
16.1
34.5
33.3
32.3
1D
1E
1F
(at φ = 4 MHz, unit : kHz)
5
SCL mode
specification bit
(FAST MODE)
0: Standard clock mode
1: High-speed clock mode
0
R W
6
7
ACK bit
(ACK BIT)
0: ACK is returned.
1: ACK is not returned.
0
0
R W
R W
ACK clock bit
(ACK)
0: No ACK clock
1: ACK clock
Note: At 4000kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Rev. 1.3
135
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00FB16
CPU Mode Register
b7b6 b5b4b3 b2b1b0
1 1
0 0
CPU mode register (CM) [Address 00FB16
]
B
Name
Functions
After reset R W
Processor mode bits
(CM0, CM1)
b1 b0
0, 1
0
R W
0 0: Single-chip mode
0 1:
1 0:
1 1:
Not available
0: 0 page
1: 1 page
Stack page selection
bit (CM2) (See note)
2
1
R W
3, 4 Fix these bits to “1.”
1
1
R W
R W
0: LOW drive
1: HIGH drive
X
COUT drivability
5
6
selection bit (CM5)
Main Clock (XIN–XOUT
stop bit
)
0
0
R W
R W
0: Oscillating
1: Stopped
(CM6)
Internal system clock
selection bit
(CM7)
7
0: XIN–XOUT selected
(high-speed mode)
1: XCIN–XCOUT selected
(high-speed mode)
Note: This bit is set to “1” after the reset release.
Address 00FC16
Interrupt Request Register 1
b7b6 b5b4b3 b2b1b0
Interrupt request register 1 (IREQ1) [Address 00FC16
]
After reset
0
B
0
Name
Functions
R W
R
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt
request bit (TM1R)
✽
1
2
3
4
5
6
7
Timer 2 interrupt
0 : No interrupt request issued
0
0
0
0
0
0
0
R
R
R
R
R
R
✽
✽
✽
✽
✽
✽
request bit (TM2R) 1 : Interrupt request issued
Timer 3 interrupt 0 : No interrupt request issued
request bit (TM3R) 1 : Interrupt request issued
Timer 4 interrupt 0 : No interrupt request issued
request bit (TM4R) 1 : Interrupt request issued
OSD interrupt request 0 : No interrupt request issued
bit (OSDR)
SYNC interrupt
1 : Interrupt request issued
V
0 : No interrupt request issued
request bit (VSCR) 1 : Interrupt request issued
INT3 external interrupt
request bit (VSCR)
0 : No interrupt request issued
1 : Interrupt request issued
R —
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
✽: “0” can be set by software, but “1” cannot be set.
Rev. 1.3
136
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00FD16
Interrupt Request Register 2
b7 b6b5b4b3 b2b1b0
0
Interrupt request register 2 (IREQ2) [Address 00FD16
]
After reset
0
B
0
Name
Functions
R W
INT1 external interrupt
request bit (INIR)
0 : No interrupt request issued
1 : Interrupt request issued
R
R
R
R
R
R
✽
✽
✽
✽
✽
✽
Data slicer interrupt
request bit (DSR)
1
2
3
4
5
6
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
0
0
0
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O interrupt
request bit (S1R)
f(XIN)/4096 interrupt
request bit (CKR)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
INT2 external interrupt
request bit (IN2R)
Multi-master I2C-BUS
interrupt request bit (IICR)
Timer 5 • 6 interrupt
request bit (TM56R)
0 : No interrupt request issued
1 : Interrupt request issued
R
✽
7
Fix this bit to “0.”
0
R W
✽: “0” can be set by software, but “1” cannot be set.
Address 00FE16
Interrupt Control Register 1
b7b6 b5b4b3 b2b1b0
Interrupt control register 1 (ICON1) [Address 00FE16
]
After reset
0
B
0
Name
Functions
R W
R W
Timer 1 interrupt
enable bit (TM1E)
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
enable bit (TM2E)
1
2
3
4
5
6
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
R W
R W
R W
R W
R W
R W
Timer 3 interrupt
enable bit (TM3E)
0 : Interrupt disabled
1 : Interrupt enabled
Timer 4 interrupt
enable bit (TM4E)
OSD interrupt enable bit
(OSDE)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
VSYNC interrupt enable
0 : Interrupt disabled
1 : Interrupt enabled
bit (VSCE)
INT3 external interrupt
enable bit (IN3E)
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
7
0
R —
Rev. 1.3
137
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 00FF16
Interrupt Control Register 2
b7b6 b5b4b3 b2b1b0
Interrupt control register 2 (ICON2) [Address 00FF16
]
After reset
0
B
0
Name
Functions
R W
R W
INT1 external interrupt
enable bit (IN1E)
0 : Interrupt disabled
1 : Interrupt enabled
Data slicer interrupt
enable bit (DSE)
1
2
3
4
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
R W
R W
R W
R W
Serial I/O interrupt
enable bit (S1E)
f(XIN)/4096 interrupt
enable bit (CKE)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
INT2 external interrupt
enable bit (IN2E)
0 : Interrupt disabled
1 : Interrupt enabled
Multi-master I2C-BUS
interface interrupt enable
bit (IICE)
0
R W
5
0 : Interrupt disabled
1 : Interrupt enabled
Timer 5 • 6 interrupt
enable bit (TM56E)
6
7
0 : Interrupt disabled
1 : Interrupt enabled
0
0
R W
R W
Timer 5 • 6 interrupt
switch bit (TM56C)
0 : Timer 5
1 : Timer 6
Address 020816
PWM Mode Register 1
b7b6 b5b4b3 b2b1b0
PWM mode register 1 (PM1) [Address 020816
]
After reset
R W
B
0
Name
Functions
PWM counts source
selection bit (PM10)
0 : Count source supply
1 : Count source stop
W
0
R
1, 2
3
—
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Indeterminate
0
R
PWM output polarity
selection bit (PM13)
0 : Positive polarity
1 : Negative polarity
R W
4
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
—
R
Indeterminate
Rev. 1.3
138
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Address 020916
PWM Mode Register 2
b7b6 b5b4b3 b2b1b0
0 0
PWM mode register 2 (PM2) [Address 0209 16]
B
0
Name
P00/PWM0 output
selection bit (PM20)
Functions
0 : P00 output
1 : PWM0 output
After reset R W
0
R W
1
2
3
4
0 : P01 output
1 : PWM1 output
P01/PWM1 output
selection bit (PM21)
0
0
0
R W
R W
R W
P02/PWM2 output
selection bit (PM22)
0 : P02 output
1 : PWM2 output
P03/PWM3 output
selection bit (PM23)
0 : P03 output
1 : PWM3 output
P04/PWM4 output
selection bit (PM24)
0
R W
0 : P04 output
1 : PWM4 output
P05/PWM5 output
selection bit (PW25)
5
0
0
R W
R W
0: P05 output
1: PWM5 output
Fix these bits to “0.”
6, 7
Address 020E16
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 020E 16
]
After reset
0
B
Name
Functions
R W
R W
0
Vector 1 enable bit (RC0)
0: Disabled
1: Enabled
1
Vector 2 enable bit (RC1)
0: Disabled
1: Enabled
0
0
R W
R —
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
2
to
7
Rev. 1.3
139
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
21. PACKAGE OUTLINE
42P4B
Plastic 42pin 600mil SDIP
EIAJ Package Code
SDIP42-P-600-1.78
JEDEC Code
–
Weight(g)
4.1
Lead Material
Alloy 42/Cu Alloy
42
22
1
21
Dimension in Millimeters
Symbol
A
Min
–
0.51
–
Nom
–
–
Max
5.5
–
D
A1
A
2
3.8
–
b
0.35
0.9
0.63
0.22
36.5
12.85
–
–
3.0
0°
0.45
1.0
0.55
1.3
1.03
0.34
36.9
13.15
–
–
–
15°
b1
b2
0.73
0.27
36.7
13.0
1.778
15.24
–
c
D
E
e
e
b1
b
b2
e1
L
SEATING PLANE
–
42P2R-A/E
Plastic 42pin 450mil SSOP
EIAJ Package Code
SSOP42-P-450-0.80
JEDEC Code
–
Weight(g)
0.63
Lead Material
Alloy 42
e
b2
42
22
Recommended Mount Pad
Dimension in Millimeters
F
Symbol
Min
–
0.05
–
0.25
0.13
17.3
8.2
–
11.63
0.3
–
–
–
–
0°
–
–
1.27
Nom
–
–
Max
2.4
–
A
A
A
1
21
1
2
A
2.0
0.3
0.15
17.5
8.4
0.8
11.93
0.5
1.765
0.75
–
–
D
G
b
0.4
0.2
17.7
8.6
–
12.23
0.7
–
c
D
E
e
H
L
A2
A1
e
b
E
y
L1
z
Z
y
–
1
0.9
0.15
10°
–
–
–
–
–
c
z
b2
0.5
11.43
–
Z
1
Detail G
Detail F
e1
I
2
Rev. 1.4
140
MITSUBISHI MICROCOMPUTERS
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
•
•
•
•
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved
destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1999 MITSUBISHI ELECTRIC CORP.
New publication, effective Dec. 1999.
Specifications subject to change without notice.
M37272M6/M8-XXXSP/FP, M37272MA-XXXSP,
REVISION DESCRIPTION LIST
M37272E8SP/FP, M37272EFSP
DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition of PDF File
990201
9907
1.1 • Delete “PRELIMINALY”
• Correct product name (head of P141).
1.3 Updated to Rev.1.3 (all pages)
9912
ROM correction memory is included to RAM (P1, 5, 12, 13)
ROM correction memory “Block” changed to “Vector” (P5, 12, 13, 48)
P42/TIM2 pin changed to TIM2 pin (P23)
Clock Run-in Detect Register (address 00EA16) changed to (address 00E416) (P56)
OSD Control Register (OC) “f(XIN)” changed to “Do not set.” at OC5, OC6 = “1”, “1” (P63)
Changed and added of Notes of OSD memory (P74)
OSC1/XIN, OSC2/XOUT changed to OSC1/XCIN, OSC2/XCOUT at RC7 = “0” (P89)
1.4 Updated to Rev.1.4 (Top page and version up pages)
PIN DESCRIPTION Outline 42P2R-A changed to 42P2R-A/E(P3, 115)
PIN DESCRIPTION RESET RESET changed to RESET (P7)
P52/R Functions “Ports P52-P57 are a 6-bit” changed to “Ports
P52-P55 are a 4-bit” (P8)
0003
Figure 7.2 I/O Pin Block Diagram P52-P57, P6 changed to P52-P55 (P10)
Figure 8.2.3 SFR1 Area CC16 Port P6 is delated. Add Note 1 (P14, 118)
Figure 8.11.18 Color code is changed (P80)
10.ABSOLUTE MAXIMUM RATINGS VI RESET changed to RESET (P97)
11.RECOMMENDED OPERATING CONDITIONS VIL3 RESET changed to RESET (P97)
12.ELECTRIC CHARACTERISTICS VT+-VT- RESET changed to RESET (P98)
IIZL RESET changed to RESET (P98)
16.DATA REQUIRED FOR MASK ORDERS “M37272M6/M8-XXXSP, ” changed to
“M37272M6/M8-XXXSP/FP, ” (P102)
21.PACKAGE OUTLINE 42P2R-A changed to 42P2R-A/E(P140)
(1/1)
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