M30612M4-155FP [MITSUBISHI]
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER; 单芯片16位CMOS微机
| 型号： | M30612M4-155FP |
| 厂家： | 
Mitsubishi Group |
| 描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 文件： | 总197页 (文件大小：2650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Mitsubishi microcomputers
M16C / 61 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M16C/61 group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of in-
struction efficiency. With 1M bytes of address space, they are capable of executing instructions at high
speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communi-
cations, industrial equipment, and other high-speed processing applications.
The M16C/61 group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Memory capacity............................................ ROM (See Figure 1.1.4. ROM Expansion)
RAM 4K to 10K bytes
• Shortest instruction execution time ................ 100ns (f(XIN)=10MHZ)
• Supply voltage ............................................... 4.0 to 5.5V (f(XIN)=10MHZ)
2.7 to 5.5V (f(XIN)=7MHZ with software one-wait)
• Low power consumption ................................ 18mW ( f(XIN)=7MHZ, with software one-wait, VCC = 3V)
• Interrupts........................................................ 20 internal and 5 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer................................ 5 output timers + 3 input timers
• Serial I/O (UART or clock synchronous)........ 3 channels
• DMAC ............................................................ 2 channels (trigger: 16 sources)
• A-D converter................................................. 10 bits X 8 channels
(Expandable up to 10 channels)
• D-A converter................................................. 8 bits X 2 channels
• CRC calculation circuit................................... 1 circuit
• Watchdog timer.............................................. 1 line
• Programmable I/O ......................................... 87 lines
_______
• Input port........................................................ 1 line (P85 shared with NMI pin)
• Memory expansion ........................................ Available (to a maximum of 1M bytes)
• Chip select output .......................................... 4 lines
• Clock generating circuit ................................. 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
------Table of Contents------
Timer ............................................................. 70
Serial I/O ....................................................... 87
A-D Converter ............................................. 114
D-A Converter ............................................. 124
CRC Calculation Circuit .............................. 126
Programmable I/O Ports ............................. 128
Electrical Characteristics............................. 142
Central Processing Unit (CPU) ..................... 11
Reset............................................................. 14
Processor Mode ............................................ 19
Clock Generating Circuit ............................... 30
Protection ...................................................... 39
Interrupts ....................................................... 40
Watchdog Timer............................................ 59
DMAC ........................................................... 61
1
Mitsubishi microcomputers
M16C / 61 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Configuration
Figures 1.1.1 and 1.1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
P07/D7
81
P44/CS0
P45/CS1
P46/CS2
P47/CS3
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P06/D6
82
P05/D5
83
P04/D4
84
P03/D3
P02/D2
P01/D1
85
86
87
88
89
P50/WRL/WR
P51/WRH/BHE
P52/RD
P53/BCLK
P54/HLDA
P55/HOLD
P56/ALE
P57/RDY/CLKOUT
P60/CTS0/RTS0
P61/CLK0
P62/RxD0
P63/TXD0
P64/CTS1/RTS1/CTS0/CLKS1
P65/CLK1
P66/RxD1
P67/TXD1
P00/D0
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P103/AN3
P102/AN2
P101/AN1
AVSS
P100/AN0
VREF
AVcc
P97/ADTRG
90
91
92
M16C/61 Group
93
94
95
96
97
98
99
100
Package: 100P6S-A
Note: P70 and P71 are N channel open-drain output pin.
Figure 1.1.1. Pin configuration (top view)
2
Mitsubishi microcomputers
M16C / 61 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (top view)
P1
P1
P1
P0
P0
P0
2/D10
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P4
P4
P4
P4
P4
P4
P5
P5
2
3
4
5
6
7
0
1
/A18
/A19
1
/D
/D
/D
9
0
8
/CS0
/CS1
/CS2
/CS3
/WRL/WR
/WRH/BHE
/RD
7
7
6
5
/D
/D
6
5
P0
P0
4
3
/D
/D
4
3
P0
P0
2
1
/D
/D
2
1
P5
2
P53
P54
P55
P56
/BCLK
P0
/AN
/AN
/AN
/AN4/KI
0
/D
/KI
/KI
/KI
0
/HLDA
/HOLD
/ALE
P10
P10
P10
7
7
3
6
6
2
M16C/61 Group
5
5
1
P57/RDY/CLKOUT
P6
P6
P6
P6
0
/CTS
/CLK
/RxD
0
0
0
/RTS0
P10
4
0
1
2
3
P10
3
/AN
3
2
1
P10
2
/AN
/AN
/TXD0
P10
1
P64/CTS1/RTS1/CTS0/CLKS1
AVSS
/AN
P6
P6
P6
P7
P7
P7
5
6
7
0
/CLK
/RxD
1
P10
0
0
1
V
AVcc
7/ADTRG
/ANEX1
REF
/T
X
D
1
/TxD
/RxD
/CLK
2
/TA0OUT(Note)
P9
P9
P9
1
2
2
/TA0IN(Note)
/TA1OUT
6
2
5
/ANEX0
Package: 100P6Q-A
Note: P70 and P71 are N channel open-drain output pin.
Figure 1.1.2. Pin configuration (top view)
3
Mitsubishi microcomputers
M16C / 61 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block Diagram
Figure 1.1.3 is a block diagram of the M16C/61 group.
Block diagram of the M16C/61 group
8
8
Port P2
8
8
8
8
8
I/O ports
Port P0
Port P1
Port P3
Port P4
Port P5
Port P6
Internal peripheral functions
Timer
System clock generator
IN-XOUT
CIN-XCOUT
A-D converter
(10 bits
X 8 channels
X
X
Expandable up to 10 channels)
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
UART/clock synchronous SI/O
(8 bits X 3channels) (Note 3)
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
M16C/60 series16-bit CPU core
Memory
ROM
(Note 1)
Registers
Program counter
Watchdog timer
(15 bits)
R0H
R0H
R1H
R2
R3
A0
A1
FB
R0L
R0L
R1L
PC
RAM
(Note 2)
Vector table
INTB
DMAC
(2 channels)
Stack pointer
ISP
D-A converter
(8 bits X 2 channels)
USP
Multiplier
SB
FLG
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Note 3: One of serial I/O can use for SIM interface.
Figure 1.1.3. Block diagram of M16C/61 group
4
Mitsubishi microcomputers
M16C / 61 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Performance Outline
Table 1.1.1 is a performance outline of M16C/61 group.
Table 1.1.1. Performance outline of M16C/61 group
Item
Performance
Number of basic instructions
91 instructions
100ns(f(XIN)=10MHZ)
Shortest instruction execution time
Memory
ROM
(See the Figure 4. ROM Expansion)
4K to 10K bytes
capacity
RAM
I/O port
P0 to P10 (except P85)
P85
8 bits x 10, 7 bits x 1
Input port
Multifunction
timer
1 bit x 1
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2
UART0, UART1, UART2
16 bits x 5
16 bits x 3
Serial I/O
A-D converter
D-A converter
DMAC
(UART or clock synchronous) x 3
10 bits x (8 + 2) channels
8 bits x 2
2 channels (trigger: 16 sources)
CRC - CCITT
CRC calculation circuit
Watchdog timer
15 bits x 1 (with prescaler)
20 internal and 5 external sources, 4 software sources, 7 levels
2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
4.0 to 5.5V (f(XIN ) = 10MHZ)
2.7 to 5.5V(f(XIN)=7MHZ with software one-wait)
18mW (f(XIN) = 7MHZ with software one-wait,VCC = 3V)
5V
Interrupt
Clock generating circuit
Supply voltage
Power consumption
I/O
I/O withstand voltage
Output current
characteristics
Memory expansion
Device configuration
Package
5mA
Available (to a maximum of 1M bytes)
CMOS silicon gate
100-pin plastic mold QFP
5
Mitsubishi microcomputers
M16C / 61 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi plans to release the following products in the M16C/61 group:
(1) Support for mask ROM version, external ROM version, one-time PROM version, and EPROM version
(2) ROM capacity
(3) Package
100P6S-A : Plastic molded QFP (mask ROM version and one-time PROM version)
100P6Q-A : Plastic molded QFP (mask ROM version and one-time PROM version)
100D0
: Ceramic LCC (EPROM version)
ROM
Size(Byte)
External
ROM
M30612SAFP/GP
M30610SAFP/GP
M30610MCA-XXXFP/GP
M30610ECFP/GP
M30610ECFS
128 K
96 K
M30612MCA-XXXFP/GP
M30610MAA-XXXFP/GP
M30612MAA-XXXFP/GP
M30610M8A-XXXFP/GP
M30612M8A-XXXFP/GP
64 K
32 K
M30612M4A-XXXFP/GP
M30612E4FP/GP
Mask ROM version
One-time PROM version
EPROM version
External ROM version
Figure 1.1.4. ROM expansion
The M16C/61 group products currently supported are listed in Table 2.
Table 1.1.2. M16C/61 group
Apr. 1999
Type No
ROM capacity
RAM capacity
4K byte
Package type
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100D0
Remarks
M30612M4A-XXXFP
M30612M4A-XXXGP
M30610M8A-XXXFP
32K byte
10K byte
4K byte
M30610M8A-XXXGP
M30612M8A-XXXFP
M30612M8A-XXXGP
M30610MAA-XXXFP
M30610MAA-XXXGP
M30612MAA-XXXFP
M30612MAA-XXXGP
M30610MCA-XXXFP
M30610MCA-XXXGP
M30612MCA-XXXFP
M30612MCA-XXXGP
M30612E4FP
64K byte
96K byte
10K byte
Mask ROM version
4K byte
10K byte
128K byte
32K byte
5K byte
4K byte
M30612E4GP
One-time PROM version
EPROM version (Note)
M30610ECFP
128K byte
128K byte
10K byte
10K byte
10K byte
M30610ECGP
M30610ECFS
M30610SAFP
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
M30610SAGP
External ROM version
M30612SAFP
4K byte
M30612SAGP
Note: Do not use the EPROM version for mass production, because it is a tool for program development
(for evaluation).
6
Mitsubishi microcomputers
M16C / 61 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Type No.
M 3 0 6 1 2 M 4 – X X X F P
Package type:
FP : Package 100P6S-A
GP :
FS
100P6Q-A
100D0
:
ROM No.
Omitted for blank one-time PROM version
and EPROM version
ROM capacity:
4 : 32K bytes
8 : 64K bytes
A : 96K bytes
C : 128K bytes
Memory type:
M : Mask ROM version
E : EPROM or one-time PROM version
S : External ROM version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/61 Group
M16C Family
Figure 1.1.5. Type No., memory size, and package
7
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name
VCC, VSS
Signal name
I/O type
Function
Power supply
input
Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
CNVSS
RESET
CNVSS
Input
This pin switches between processor modes. Connect it to the
VSS pin when operating in single-chip or memory expansion mode.
Connect it to the VCC pin when in microprocessor mode.
Reset input
Input
A “L” on this input resets the microcomputer.
XIN
Clock input
Input
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the XIN and the XOUT pins. To
use an externally derived clock, input it to the XIN pin and leave the
XOUT pin open.
XOUT
Clock output
Output
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”. When
operating in single-chip mode,connect this pin to VSS.
BYTE
External data Input
bus width
select input
AVCC
AVSS
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VCC.
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VSS.
VREF
Input
Reference
voltage input
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When used for input in single-chip mode, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. In memory expansion and microprocessor modes, selection
of the internal pull-resistor is not available.
P00 to P07
I/O port P0
Input/output
D0 to D7
Input/output When set as a separate bus, these pins input and output data (D0–D7).
Input/output This is an 8-bit I/O port equivalent to P0.
P10 to P17
I/O port P1
I/O port P2
D8 to D15
Input/output When set as a separate bus, these pins input and output data (D
8–D15).
P20 to P27
A0 to A7
Input/output This is an 8-bit I/O port equivalent to P0.
Output
These pins output 8 low-order address bits (A0–A7).
Input/output If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D0–D7) and output 8 low-order address bits
(A0–A7) separated in time by multiplexing.
A0/D0 to
A7/D7
Output
Input/output
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D0–D6) and output address (A1–A7) separated
in time by multiplexing. They also output address (A0).
A0, A1/D0
to A7/D6
P30 to P37
A8 to A15
I/O port P3
I/O port P4
Input/output This is an 8-bit I/O port equivalent to P0.
Output
These pins output 8 middle-order address bits (A8–A15).
Input/output If the external bus is set as a 16-bit wide multiplexed bus, these pins
A8/D7,
A9 to A15
Output
input and output data (D7) and output address (A8) separated in time
by multiplexing. They also output address (A9–A15).
P40 to P47
Input/output This is an 8-bit I/O port equivalent to P0.
Output
Output
These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip
select signals used to specify an access space. A16–A19 are 4 high-
order address bits.
CS0 to CS3,
A16 to A19
8
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name
Signal name
I/O port P5
I/O type
Function
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as XCIN as selected by software.
P50 to P57
Input/output
Output
Output
Output
Output
Output
Input
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
HOLD,
ALE,
RDY
Output
Input
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the ready state.
This is an 8-bit I/O port equivalent to P0. When used for input in single-
chip, memory expansion, and microprocessor modes, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. Pins in this port also function as UART0 and UART1 I/O pins
as selected by software.
P60 to P67
P70 to P77
I/O port P6
Input/output
Input/output
This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel
open-drain output). Pins in this port also function as timer A0–A3 or
UART2 I/O pins as selected by software.
I/O port P7
I/O port P8
I/O port P85
P80 to P84, P86, and P87 are I/O ports with the same functions as P6.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P86 and P87 can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P86 (XCOUT
pin) and P87 (XCIN pin). P85 is an input-only port that also functions
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be cancelled using
software. The pull-up cannot be set for this pin.
P80 to P84,
P86,
Input/output
Input/output
P87,
P85
Input/output
Input
P90 to P97
I/O port P9
Input/output
Input/output
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as Timer B0–B2 input pins, D-A converter output pins, A-D converter
extended input pins, or A-D trigger input pins as selected by software.
P100 to P107 I/O port P10
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins. Furthermore, P104–P107 also function as
input pins for the key input interrupt function.
9
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Operation of Functional Blocks
The M16C/61 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit,
A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.4.1 is a memory map of the M16C/61 group. The address space extends the 1M bytes from
address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30612M4A-XXXFP,
there is 32K bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as
_______
the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is
stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the
internal register (INTB). See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30612M4A-XXXFP, 4K bytes of internal RAM is mapped
to the space from 0040016 to 013FF16. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used. For example, in the M30612M4A-XXXFP, the following spaces cannot be used.
• The space between 0140016 and 03FFF16
• The space between D000016 and F7FFF16 (When external area do not expand in memory expansion
mode)
Do not expand the external area in single chip mode. A part of internal memory cannot be used depending
on MCU.
0000016
SFR area
For details, see Figure
1.7.1 and Figure 1.7.2
FFE0016
0040016
Internal RAM area
Special page
vector table
XXXXX16
Internal reserved
area (Note 1)
0400016
FFFDC16
Undefined instruction
External area
Overflow
Type No.
Address XXXXX16 Address YYYYY16
BRK instruction
Address match
Single step
M30610M8A
M30610MAA
M30610MCA/EC
M30612M4A/E4
M30612M8A
M30612MAA
M30612MCA
02BFF16
02BFF16
02BFF16
013FF16
013FF16
013FF16
017FF16
F000016
E800016
E000016
F800016
F000016
E800016
E000016
Internal reserved
area (Note 2)
D000016
Watchdog timer
YYYYY16
DBC
NMI
Reset
Internal ROM area
FFFFF16
FFFFF16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: When external area do not expand in memory expansion mode.
Figure 1.4.1. Memory map
10
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
b15
b15
b15
b15
b15
b15
b15
b8 b7
b8 b7
b0
b0
b0
b0
b0
b0
b0
R0(Note)
R1(Note)
R2(Note)
R3(Note)
A0(Note)
A1(Note)
FB(Note)
L
L
H
H
b19
b19
b0
PC
Program counter
Data
registers
b0
b0
Interrupt table
register
INTB
H
L
b15
b15
b15
b15
User stack pointer
USP
ISP
SB
b0
b0
b0
Interrupt stack
pointer
Address
registers
Static base
register
FLG
Frame base
registers
Flag register
IPL
U
I O B S Z D C
Note: These registers consist of two register banks.
Figure 1.5.1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
11
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”
.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
12
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
b15
b0
IPL
Flag register (FLG)
U
I
O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.5.2. Flag register (FLG)
13
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 1.6.1 shows the example reset circuit. Figure 1.6.2 shows the reset sequence.
5V
4.0V
V
CC
0V
5V
VCC
RESET
RESET
0V
0.8V
Example when VCC = 5V
.
Figure 1.6.1. Example reset circuit
X
IN
More than 20 cycles are needed
BCLK 24cycles
Microprocessor
mode BYTE = “H”
RESET
BCLK
Address
RD
Content of reset vector
FFFFC16
FFFFD16
FFFFE16
WR
CS0
Microprocessor
mode BYTE = “L”
Content of reset vector
FFFFC16
FFFFE16
Address
RD
WR
CS0
Single chip
mode
FFFFC16
Content of reset vector
Address
FFFFE16
Figure 1.6.2. Reset sequence
14
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
____________
Table 1.6.1 shows the statuses of the other pins while the RESET pin level is “L”. Figure 1.6.3 shows the
internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 1.6.1. Pin status when RESET pin level is “L”
Status
CNVSS = VCC
Pin name
CNVSS = VSS
BYTE = VSS
Data input (floating)
BYTE = VCC
Data input (floating)
P0
P1
Input port (floating)
Input port (floating)
Data input (floating)
Input port (floating)
P2, P3, P40 to P43 Input port (floating)
Address output (undefined)
Address output (undefined)
P44
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
CS0 output (“H” level is output) CS0 output (“H” level is output)
Input port (floating) Input port (floating)
WR output (“H” level is output) WR output (“H” level is output)
BHE output (undefined) BHE output (undefined)
RD output (“H” level is output) RD output (“H” level is output)
BCLK output BCLK output
P45 to P47
P50
P51
P52
P53
HLDA output (The output value HLDA output (The output value
P54
Input port (floating)
depends on the input to the
HOLD pin)
depends on the input to the
HOLD pin)
P55
P56
P57
Input port (floating)
Input port (floating)
Input port (floating)
HOLD input (floating)
HOLD input (floating)
ALE output (“L” level is output) ALE output (“L” level is output)
RDY input (floating)
Input port (floating)
RDY input (floating)
Input port (floating)
P6, P7, P80 to P84,
P86, P87, P9, P10
Input port (floating)
15
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(1) Processor mode register 0 (Note)
(2) Processor mode register 1
(000416)···
(000516)···
(000616)···
(000716)···
(000816)···
(000916)···
(000A16)···
(000F16)···
(001016)···
(001116)···
(001216)···
(001416)···
(001516)···
(001616)···
(002C16)···
(003C16)···
(004A16)···
(004B16)···
(004C16)···
(004D16)···
(004E16)···
(004F16)···
(005016)···
(005116)···
(005216)···
(005316)···
(005416)···
(005516)···
(005616)···
(005716)···
(005816)···
(005916)···
(005A16)···
(005B16)···
(005C16)···
(005D16)···
(005E16)···
(005F16)···
(037816)···
(037C16)···
(037D16)···
(038016)···
(038116)···
(038216)···
(038316)···
(038416)···
(43)Timer A0 mode register
(44)Timer A1 mode register
(45)Timer A2 mode register
(46)Timer A3 mode register
(47)Timer A4 mode register
(48)Timer B0 mode register
(49)Timer B1 mode register
(50)Timer B2 mode register
(51)UART0 transmit/receive mode register
(039616)···
(039716)···
(039816)···
(039916)···
(039A16)···
(039B16)···
(039C16)···
(039D16)···
(03A016)···
0016
0016
0016
0016
0016
0016
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
?
(3) System clock control register 0
(4) System clock control register 1
(5) Chip select control register
(6) Address match interrupt enable register
(7) Protect register
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
?
0
0
0
0
0
0
?
?
?
0
0
0
0
0
0
0
0
0
0
0
?
(8) Watchdog timer control register
(9) Address match interrupt register 0
0
0
0
?
?
0
0016
0016
0
0016
(52)UART0 transmit/receive control register 0 (03A416)···
(53)UART0 transmit/receive control register 1 (03A516)···
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
(10)Address match interrupt register 1
0016
0016
0
(54)UART1 transmit/receive mode register
(03A816)···
0016
(55)UART1 transmit/receive control register 0 (03AC16)···
(56)UART1 transmit/receive control register 1 (03AD16)···
(57)UART transmit/receive control register 2 (03B016)···
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
?
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(11)DMA0 control register
(12)DMA1 control register
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
(58)DMA0 cause select register
(59)DMA1 cause select register
(60) A-D control register 2
(03B816)···
(03BA16)···
(03D416)···
(03D616)···
(03D716)···
(03DC16)···
(03E216)···
(03E316)···
(03E616)···
(03E716)···
(03EA16)···
(03EB16)···
(03EE16)···
(03EF16)···
(03F216)···
(03F316)···
(03F616)···
(03FC16)···
(03FD16)···
(03FE16)···
0016
0016
0
Bus collision detection interrupt control
register
(13)
(14)DMA0 interrupt control register
(15)DMA1 interrupt control register
(16)Key input interrupt control register
(17)A-D conversion interrupt control register
(18)UART2 transmit interrupt control register
(19)UART2 receive interrupt control register
(20)UART0 transmit interrupt control register
(21)UART0 receive interrupt control register
(22)UART1 transmit interrupt control register
(23)UART1 receive interrupt control register
(24)Timer A0 interrupt control register
(25)Timer A1 interrupt control register
(26)Timer A2 interrupt control register
(27)Timer A3 interrupt control register
(28)Timer A4 interrupt control register
(29)Timer B0 interrupt control register
(30)Timer B1 interrupt control register
(31)Timer B2 interrupt control register
(32)INT0 interrupt control register
(33)INT1 interrupt control register
(34)INT2 interrupt control register
(35)UART2 transmit/receive mode register
(36)UART2 transmit/receive control register 0
(37)UART2 transmit/receive control register 1
(38)Count start flag
0
0
0
0
0
0
0
?
(61) A-D control register 0
0
0 ? ?
(62) A-D control register 1
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
(63)D-A control register
(64)Port P0 direction register
(65)Port P1 direction register
(66)Port P2 direction register
(67)Port P3 direction register
(68)Port P4 direction register
(69)Port P5 direction register
(70)Port P6 direction register
(71)Port P7 direction register
(72)Port P8 direction register
(73)Port P9 direction register
(74)Port P10 direction register
(75)Pull-up control register 0
(76)Pull-up control register 1
(77)Pull-up control register 2
(78)Data registers (R0/R1/R2/R3)
(79)Address registers (A0/A1)
(80)Frame base register (FB)
(81)Interrupt table register (INTB)
(82)User stack pointer (USP)
(83)Interrupt stack pointer (ISP)
(84)Static base register (SB)
(85)Flag register (FLG)
0
0
0
0
0
0
0
0016
0016
0016
0016
0016
0
0
0
0
0
0
000016
000016
000016
0000016
000016
000016
000016
000016
0016
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0016
(39)Clock prescaler reset flag
0
0
(40)One-shot start flag
0
0
0
0
0
0
x : Nothing is mapped to this bit
? : Undefined
(41)Trigger select flag
0016
0016
(42)Up-down flag
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset.
Figure 1.6.3. Device's internal status after a reset is cleared
16
Mitsubishi microcomputers
M16C / 61 Group
SFR
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Chip select control register (CSR)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Bus collision detection interrupt control register (BCNIC)
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
DMA0 source pointer (SAR0)
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
DMA0 destination pointer (DAR0)
DMA0 transfer counter (TCR0)
DMA0 control register (DM0CON)
DMA1 source pointer (SAR1)
DMA1 destination pointer (DAR1)
UART2 transmit/receive mode register (U2MR)
UART2 bit rate generator (U2BRG)
DMA1 transfer counter (TCR1)
DMA1 control register (DM1CON)
UART2 transmit buffer register (U2TB)
UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive control register 1 (U2C1)
UART2 receive buffer register (U2RB)
Figure 1.7.1. Location of peripheral unit control registers
17
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
038016
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Count start flag (TABSR)
A-D register 0 (AD0)
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
Timer A0 (TA0)
Timer A1 (TA1)
Timer A2 (TA2)
Timer A3 (TA3)
Timer A4 (TA4)
Timer B0 (TB0)
Timer B1 (TB1)
Timer B2 (TB2)
A-D register 6 (AD6)
A-D register 7 (AD7)
A-D control register 2 (ADCON2)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
D-A register 1 (DA1)
D-A control register (DACON)
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2)
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
Port P3 (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 (P4)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
Port P5 (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 (P6)
UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
Port P7 (P7)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 (P8)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Port P9 (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 (P10)
Port P10 direction register (PD10)
DMA0 cause select register (DM0SL)
DMA1 cause select register (DM1SL)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
CRC data register (CRCD)
CRC input register (CRCIN)
Figure 1.7.2. Location of peripheral unit control registers
18
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
Processor Mode
(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro-
processor mode. The functions of some pins, the memory map, and the access space differ according to
the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal
peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM).
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Also do not attempt to
shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 1.8.1 shows the processor mode register 0 and 1. Figure 1.9.1 shows the memory maps appli-
cable for each of the modes.
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Processor mode register 0 (Note 1)
Symbol
PM0
Address
000416
When reset
0016 (Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
Bit name
Function
b1 b0
PM00
Processor mode bit
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Inhibited
1 1: Microprocessor mode
PM01
PM02
0 : RD,BHE,WR
1 : RD,WRH,WRL
R/W mode select bit
Software reset bit
PM03
PM04
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
b5 b4
Multiplexed bus space
select bit
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
PM05
PM06
0 : Address output
1 : Port function
(Address is not output)
Port P40 to P43 function
select bit (Note 3)
0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
PM07
BCLK output disable bit
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when
reset is 0316. (PM00 and PM01 both are set to “1”.)
Note 3: Valid in microprocessor and memory expansion modes.
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose
an 8-bit width.The processor operates using the separate bus after reset is
revoked, so the entire space multiplexed bus cannot be chosen in microprocessor
mode.
The higher-order address becomes a port if the entire space multiplexed
bus is chosen, so only 256 bytes can be used in each chip select.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
Address
000516
When reset
00XXXXX0
2
0
0
0
0
R W
Bit symbol
Reserved bit
Bit name
Function
Must always be set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Must always be set to “0”
Reserved bit
PM16
External memory area
expansion bit (Note 2)
0 : Do not expand
1 : Expand
PM17
0 : No wait state
1 : Wait state inserted
Wait bit
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing
new values to this register.
Note 2: When this bit is set to “1” in memory expansion mode, M30612M4A/E4
provides the means of using part of internal reserved area as an external
area. Set this bit to “0” except M30612M4A/E4. Set this bit to “0” in single
chip mode.
Figure 1.8.1. Processor mode register 0 and 1
20
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Single-chip mode
SFR area
Memory expansion mode
SFR area
Microprocessor mode
SFR area
0000016
0040016
Internal RAM
area
Internal RAM
area
Internal RAM
area
XXXXX16
0400016
Internally
reserved area
Internally
reserved area
Inhibited
External area
D000016
External area
Internally reserved
area (Note 1)
YYYYY16
Internal ROM
area (Note 2)
Internal ROM
area
FFFFF16
Type No.
Address
XXXXX16
Address
YYYYY16
External area : Accessing this area allows the user to
access a device connected externally
to the microcomputer.
M30610M8A
M30610MAA
02BFF16
02BFF16
F000016
E800016
E000016
F800016
F000016
E800016
E000016
M30610MCA/EC
M30612M4A/E4
M30612M8A
02BFF16
013FF16
013FF16
013FF16
017FF16
Note 1: This area becomes external area when PM16 (external
memory area expansion bit ) = “1” in M30612M4A/E4.
Set “0” except M30612M4A/E4.
Note 2: Set “0” to PM16 (external memory area expansion bit)
in single chip mode.
M30612MAA
M30612MCA
Figure 1.9.1. Memory maps in each processor mode
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus
settings.
Table 1.10.1 shows the factors used to change the bus settings.
Table 1.10.1. Factors for switching bus settings
Bus setting
Switching factor
Bit 6 of processor mode register 0
BYTE pin
Switching external address bus width
Switching external data bus width
Switching between separate and multiplex bus
Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K
bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0
is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address
bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set
to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the
address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be
set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus
width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16
bits and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin =
“H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7.
With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8.
D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are
mapped to the microcomputer’s even addresses (every 2nd address). To access these external de-
vices, access the even addresses as bytes.
The ALE signal latches the address. It is output from P56.
Before using the multiplex bus for access, be sure to insert a software wait.
If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed
bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256
bytes can be used in each chip select.
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
Table 1.10.2. Pin functions for each processor mode
Single-chip
Memory
expansion mode
Processor mode
Memory expansion mode/microprocessor modes
mode
“01”, “10”
“00”
“11” (Note 1)
multiplexed
bus for the
entire
Multiplexed bus
space select bit
Either CS1 or CS2 is for
multiplexed bus and others
are for separate bus
(separate bus)
space
8 bits
“H”
Data bus width
BYTE pin level
16 bits
“L”
8 bits
“H”
16 bits
“L”
8 bit
“H”
P0
0
to P0
7
I/O port
Data bus
Data bus
Data bus
Data bus
I/O port
P1
0
to P1
7
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
Data bus
I/O port
Data bus
I/O port
P2
0
Address bus
/data bus(Note 2)
Address bus
Address bus
Address bus
Address bus
Address bus
/O port
Address bus
Address bus
Address bus
Address bus
I/O port
Address bus
/data bus
P2
1
0
to P2
7
Address bus
/data bus(Note 2) /data bus(Note 2)
Address bus
Address bus
/data bus
P3
Address bus
/data bus(Note 2)
Address bus
Address bus
I/O port
A8/D7
P3
1
to P3
to P4
7
Address bus
I/O port
I/O port
I/O port
P4
Port P4
0
3
0
to P43
function select bit = 1
P4
Port P4
0
to P4
3
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
0
to P43
function select bit = 0
CS (chip select) or programmable I/O port
(For details, refer to “Bus control”)
P4
P5
P5
P5
4
0
4
5
to P4
7
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”)
to P5
3
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
P5
6
7
P5
RDY
RDY
RDY
RDY
RDY
Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be
chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used
in each chip select.
Note 2: Address bus when in separate bus mode.
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function as
the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
Both the address and data bus retain their previous states when internal ROM or RAM is accessed. Also,
when a change is made from single-chip mode to memory expansion mode, the value of the address bus
is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register.
_______
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been cancelled.
_______
_______
_______
_______
CS1 to CS3 function as input ports. Therefore, when using CS1 to CS3, external pull-up resistors are
required. Figure 1.11.1 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Table 1.11.1
shows the external memory areas specified using the chip select signal.
Table 1.11.1. External areas specified by the chip select signals
Specified address range
Chip select
Memory expansion mode
Microprocessor mode
3000016 to CFFFF16 (640K)
3000016 to FFFFF16 (832K)
CS0
3000016 to F7FFF16
2800016 to 2FFFF16
(Note)
(800K)
(32K)
2800016 to 2FFFF16 (32K)
0800016 to 27FFF16 (128K)
0400016 to 07FFF16 (16K)
CS1
CS2
CS3
0800016 to 27FFF16 (128K)
0400016 to 07FFF16 (16K)
Note: When PM16 (External memory area expansion bit) = “1”. (Only M30612M4A/E4 is valid.)
Chip select control register
Symbol
CSR
Address
000816
When reset
0116
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
Bit name
Function
CS0
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
CS1
CS2
CS3
CS0W
CS1W
CS2W
CS3W
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
0 : Wait state inserted
1 : No wait state
Figure 1.11.1. Chip select control register
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the
_____ ________
______
_____ ________
_________
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE
_____ ______
_______
pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 000416) to “0”.) Tables 1.11.2 and 1.11.3 show the operation of these signals.
_____ ______
________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
_____ _________
_________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
_____ ________
_________
Table 1.11.2. Operation of RD, WRL, and WRH signals
Data bus width
Status of external data bus
RD
L
WRL
H
L
WRH
H
H
L
Read data
H
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
16-bit
(BYTE = “L”)
H
H
L
H
L
_____ ______
________
Table 1.11.3. Operation of RD, WR, and BHE signals
Data bus width
A0
H
Status of external data bus
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
RD
H
L
WR
L
BHE
L
H
L
L
H
16-bit
(BYTE = “L”)
H
L
H
L
H
L
H
L
H
L
L
L
H
L
L
L
H
L
Not used
Not used
H / L
H / L
8-bit
(BYTE = “H”)
H
Read 1 byte of data
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = “L”
ALE
When BYTE pin = “H”
ALE
A
0
Address
Data (Note 1)
Address
Data (Note 1)
D0/A0 to D7/A7
D0/A1 to D7/A8
Address
A8 to A19
Address (Note 2)
A9 to A19
Address
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.11.2. ALE signal and address/data bus
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(5) The _R__D___Y__ signal
________
RDY is a signal that facilitates access to an external device that requires long access time. As shown in
________
Figure 1.11.3, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state.
________
If an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table
1.11.4 shows the state of the microcomputer with the bus in the wait state, and Figure 1.11.3 shows an
____
________
example in which the RD signal is prolonged by the RDY signal.
________
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the
________
chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to all
________
bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as
properly as in non-using.
Table 1.11.4. Microcomputer status in ready state (Note)
Item
Status
Oscillation
On
___
_____
________
R/W signal, address bus, data bus, CS
Maintain status when RDY signal received
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
On
________
Note: The RDY signal cannot be received immediately prior to a software wait.
In an instance of separate bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
_____
________
Figure 1.11.3. Example of RD signal extended by RDY signal
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
__________
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
__________
__________
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.11.5
shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
__________
HOLD > DMAC > CPU
Figure 1.11.4. Bus-using priorities
Table 1.11.5. Microcomputer status in hold state
Item
Status
Oscillation
ON
___
_____ _______
R/W signal, address bus, data bus, CS, BHE
Floating
Floating
Programmable I/O ports
P0, P1, P2, P3, P4, P5
P6, P7, P8, P9, P10
Maintains status when hold signal is received
Output “L”
__________
HLDA
Internal peripheral circuits
ALE signal
ON (but watchdog timer stops)
Undefined
(7) External bus status when the internal area is accessed
Table 1.11.6 shows the external bus status when the internal area is accessed.
Table 1.11.6. External bus status when the internal area is accessed
Item
SFR accessed
Address output
Internal ROM/RAM accessed
Maintain status before accessed
address of external area
Floating
Address bus
Data bus
When read
When write
Floating
Output data
Undefined
RD, WR, WRL, WRH
BHE
RD, WR, WRL, WRH output
BHE output
Output "H"
Maintain status before accessed
status of external area
Output "H"
CS
Output "H"
Output "L"
ALE
Output "L"
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(8) BCLK output
The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note).
When set to “1”, the output floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLK
cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring
to the recommended operating conditions (main clock input oscillation frequency) of the electric character-
________
istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register’s
bits 4 to 7 must be set to “0”.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______
_______
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in
one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
insert a software wait if using the multiplex bus to access the external memory area.
Table 1.11.7 shows the software wait and bus cycles. Figure 1.11.5 shows example bus timing when
using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 1.11.7. Software waits and bus cycles
Bits 4 to 7 of chip select
Bus cycle
2 BCLK cycles
Area
SFR
Bus status
Wait bit
control register
Invalid
0
Invalid
Invalid
1 BCLK cycle
Internal
ROM/RAM
1
0
0
Invalid
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
Separate bus
Separate bus
Separate bus
1
0
External
memory
area
1
0
1
0 (Note)
0
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
Multiplex bus
Multiplex bus
0 (Note)
Note: When using the RDY signal, always set to “0”.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
< Separate bus (no wait) >
Bus cycle
BCLK
Write signal
Read signal
Data bus
Output
Input
Address bus
Chip select
Address
Address
< Separate bus (with wait) >
Bus cycle
BCLK
Write signal
Read signal
Input
Output
Data bus
Address
Address bus
Address
Chip select
< Multiplexed bus >
Bus cycle
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Address
Address
Address
Input
Data output
Address
Data bus
Chip select
Figure 1.11.5. Typical bus timings using software wait
29
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 1.12.1. Main clock and sub-clock generating circuits
Main clock generating circuit
• CPU’s operating clock source
• Internal peripheral units’
operating clock source
Ceramic or crystal oscillator
XIN, XOUT
Sub-clock generating circuit
• CPU’s operating clock source
• Timer A/B’s count clock
source
Use of clock
Usable oscillator
Crystal oscillator
XCIN, XCOUT
Pins to connect oscillator
Oscillation stop/restart function
Oscillator status immediately after reset
Other
Available
Available
Oscillating
Stopped
Externally derived clock can be input
Example of oscillator circuit
Figure 1.12.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 1.12.2 shows some examples
of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 1.12.1 and 1.12.2 vary with each oscillator used. Use
the values recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
XIN
XOUT
XIN
XOUT
Open
(Note)
Rd
Externally derived clock
Vcc
Vss
CIN
C
OUT
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 1.12.1. Examples of main clock
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
CIN
XCOUT
X
CIN
XCOUT
Open
(Note)
RCd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.
Figure 1.12.2. Examples of sub-clock
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Control
Figure 1.12.3 shows the block diagram of the clock generating circuit.
XCIN
X
COUT
fC32
1/32
f1
CM04
f1SIO2
fAD
fC
f8SIO2
f8
Sub clock
f
32SIO2
CM10 “1”
Write signal
f
32
S
R
Q
X
IN
X
OUT
b
c
CM07=0
a
d
Divider
RESET
Software reset
NMI
BCLK
f
C
Main clock
CM02
CM07=1
CM05
Interrupt request
level judgment
output
S Q
R
WAIT instruction
c
b
1/2
1/2
1/2
1/2
1/2
a
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
d
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
Details of divider
Figure 1.12.3. Clock generating circuit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re-
tained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can
be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expan-
sion and the microprocessor modes.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-
speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 1.12.4 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
When reset
4816
Bit symbol
CM00
Bit name
Function
R W
b1 b0
Clock output function
select bit
(Valid only in single-chip
mode)
0 0 : I/O port P5
0 1 : f
1 0 : f
1 1 : f32 output
7
C
output
output
8
CM01
CM02
CM03
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
Port X
C
select bit
0 : I/O port
1 : XCIN-XCOUT generation
CM04
CM05
Main clock (XIN-XOUT
stop bit (Note 3, 4, 5)
)
0 : On
1 : Off
Main clock division select 0 : CM16 and CM17 valid
CM06
CM07
bit 0 (Note 7)
1 : Division by 8 mode
System clock select bit
(Note 6)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shiffing to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and
operating with XIN, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select
bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns
pulled up to XOUT (“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the
main clock oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: fC32 is not included.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
000716
When reset
2016
0
0
0
0
Bit symbol
CM10
Bit name
Function
R W
All clock stop control bit
(Note4)
0 : Clock on
1 : All clocks off (stop mode)
Reserved bit
Always set to “0”
Reserved bit
Reserved bit
Reserved bit
Always set to “0”
Always set to “0”
Always set to “0”
X
IN-XOUT drive capacity
0 : LOW
1 : HIGH
CM15
select bit (Note 2)
b7 b6
Main clock division
select bit 1 (Note 3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
CM16
CM17
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is
fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-
impedance state.
Figure 1.12.4. Clock control registers 0 and 1
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or
fC to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address
000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation, BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions
provided an external clock is selected. Table 1.12.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
Table 1.12.2. Port status during stop mode
Pin
Memory expansion mode
Microprocessor mode
Single-chip mode
_______
_______
Address bus, data bus, CS0 to CS3
_____ ______ ________ ________ _________
RD, WR, BHE, WRL, WRH
__________
Retains status before stop mode
“H”
HLDA, BCLK
“H”
“H”
ALE
Port
Retains status before stop mode Retains status before stop mode
Valid only in single-chip mode “H”
CLKOUT
When fC selected
When f8, f32 selected
Valid only in single-chip mode Retains status before stop mode
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Wait Mode
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function
clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral
functions, allowing power dissipation to be reduced. Table 1.12.3 shows the status of the ports in wait
mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Table 1.12.3. Port status during wait mode
Pin
Memory expansion mode
Microprocessor mode
Single-chip mode
_______
_______
Address bus, data bus, CS0 to CS3
_____ ______ ________ ________ _________
RD, WR, BHE, WRL, WRH
__________
Retains status before wait mode
“H”
HLDA,BCLK
“H”
ALE
Port
“H”
Retains status before wait mode
Retains status before wait mode
CLKOUT
When fC selected
Valid only in single-chip mode Does not stop
When f8, f32 selected Valid only in single-chip mode Does not stop when the WAIT
peripheral function clock stop
bit is “0”.
When the WAIT peripheral
function clock stop bit is “1”,
the status immediately prior
to entering wait mode is main-
tained.
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Status Transition Of BCLK
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.13.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
Table 1.12.4. Operating modes dictated by settings of system clock control registers 0 and 1
CM17
CM16
CM07
CM06
CM05
CM04
Invalid
Invalid
Invalid
Invalid
Invalid
1
Operating mode of BCLK
Division by 2 mode
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
Division by 4 mode
Invalid
1
Invalid
1
1
0
Division by 8 mode
Division by 16 mode
No-division mode
0
0
0
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Low-speed mode
1
Low power dissipation mode
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power control
Power control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal
clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the internal clock selected. Each peripheral function oper-
ates according to its assigned clock.
• Low-speed mode
fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the
secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fC
clock. The fC clock is supplied by the secondary clock. The only peripheral functions that operate
are those with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 1.12.5 is the state transition diagram of the above modes.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power control
Transition of stop mode, wait mode
Reset
All oscillators stopped
CPU operation stopped
WAIT
instruction
CM10 = “1”
Interrupt
Medium-speed mode
(divided-by-8 mode)
Stop mode
Wait mode
Interrupt
Interrupt
WAIT
instruction
All oscillators stopped
CPU operation stopped
High-speed/medium-
speed mode
CM10 = “1”
Stop mode
Wait mode
Interrupt
WAIT
instruction
All oscillators stopped
CPU operation stopped
CM10 = “1”
Interrupt
Low-speed/low power
dissipation mode
Stop mode
Wait mode
Interrupt
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
CM06 = “1”
BCLK : f(XIN)/8
CM07 = “0” CM06 = “1”
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM04 = “1”
(Notes 1, 3)
Main clock is oscillating
Sub clock is oscillating
CM04 = “0”
Medium-speed mode
(divided-by-2 mode)
High-speed mode
Main clock is oscillating
Sub clock is oscillating
BCLK : f(XIN
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
)
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-8 mode)
Low-speed mode
CM07 = “0”
(Note 1, 3)
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
BCLK : f(XCIN
CM07 = “1”
)
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
CM07 = “1”
(Note 2)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
CM05 = “0”
CM05 = “1”
CM04 = “0”
CM04 = “1”
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
Medium-speed mode
(divided-by-2 mode)
High-speed mode
CM07 = “1” (Note 2)
CM05 = “1”
BCLK : f(XIN
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
)
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
BCLK : f(XCIN
CM07 = “1”
)
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
CM06 = “0”
(Notes 1,3)
BCLK : f(XIN)/4
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
Figure 1.12.5. State transition diagram of Power control mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.12.6 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-
ister 0 (address 000616), system clock control register 1 (address 000716) and port P9 direction register
(address 03F316) can only be changed when the respective bit in the protect register is set to “1”. There-
fore, important outputs can be allocated to port P9.
If, after “1” (write-enabled) has been written to the port P9 direction register write-enable bit (bit 2 at address
000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the
system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and
1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000A16
When reset
XXXXX0002
Bit symbol
PRC0
Bit name
Function
0 : Write-inhibited
R W
Enables writing to system clock
control registers 0 and 1 (addresses
1 : Write-enabled
000616 and 000716
)
Enables writing to processor mode
registers 0 and 1 (addresses 000416
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC2
and 000516
)
Enables writing to port P9 direction
register (address 03F316) (Note)
0 : Write-inhibited
1 : Write-enabled
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Figure 1.12.6. Protect register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Overview of Interrupt
Type of Interrupts
Figure 1.13.1 lists the types of interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
Software
INT instruction
Interrupt
Reset
_______
NMI
________
DBC
Special
Watchdog timer
Single step
Hardware
Address matched
Peripheral I/O (Note)
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 1.13.1. Classification of interrupts
• Maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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Interrupt
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing
the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts,
so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O
interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re-
quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
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Interrupt
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset occurs if an “L” is input to the RESET pin.
_______
• NMI interrupt
_______
_______
An NMI interrupt occurs if an “L” is input to the NMI pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs. For address match interrupt, see 2.11 Address match Interrupt.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt
These are interrupts that DMA generates.
• Key-input interrupt
___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1 and UART2 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1 and UART2 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B2 interrupt
These are interrupts that timer B generates.
________
________
• INT0 interrupt through INT2 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
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Interrupt
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.13.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
MSB
LSB
Low address
Mid address
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
0 0 0 0
0 0 0 0
High address
0 0 0 0
Figure 1.13.2. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.13.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 1.13.1. Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
FFFE416 to FFFE716
Remarks
Undefined instruction
Overflow
Interrupt on UND instruction
Interrupt on INTO instruction
BRK instruction
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Address match
FFFE816 to FFFEB16
FFFEC16 to FFFEF16
FFFF016 to FFFF316
FFFF416 to FFFF716
FFFF816 to FFFFB16
FFFFC16 to FFFFF16
Single step (Note)
Watchdog timer
________
DBC (Note)
NMI
Do not use
_______
External interrupt by input to NMI pin
Reset
Note: Interrupts used for debugging purposes only.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-
dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 1.13.2 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
Table 1.13.2. Interrupts assigned to the variable vector tables and addresses of vector tables
Vector table address
Software interrupt number
Software interrupt number 0
Interrupt source
BRK instruction
Remarks
Address (L) to address (H)
+0 to +3 (Note)
Cannot be masked I flag
Software interrupt number 10
Software interrupt number 11
+40 to +43 (Note)
+44 to +47 (Note)
Bus collision detection
DMA0
Software interrupt number 12
Software interrupt number 13
Software interrupt number 14
Software interrupt number 15
Software interrupt number 16
Software interrupt number 17
Software interrupt number 18
Software interrupt number 19
Software interrupt number 20
Software interrupt number 21
Software interrupt number 22
Software interrupt number 23
Software interrupt number 24
Software interrupt number 25
Software interrupt number 26
Software interrupt number 27
Software interrupt number 28
Software interrupt number 29
Software interrupt number 30
Software interrupt number 31
+48 to +51 (Note)
+52 to +55 (Note)
+56 to +59 (Note)
+60 to +63 (Note)
+64 to +67 (Note)
+68 to +71 (Note)
+72 to +75 (Note)
+76 to +79 (Note)
+80 to +83 (Note)
+84 to +87 (Note)
+88 to +91 (Note)
+92 to +95 (Note)
+96 to +99 (Note)
+100 to +103 (Note)
+104 to +107 (Note)
+108 to +111 (Note)
+112 to +115 (Note)
+116 to +119 (Note)
+120 to +123 (Note)
+124 to +127 (Note)
DMA1
Key input interrupt
A-D
UART2 transmit
UART2 receive
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
INT0
INT1
INT2
Software interrupt number 32
to
+128 to +131 (Note)
to
Software interrupt
Cannot be masked I flag
Software interrupt number 63
+252 to +255 (Note)
Note: Address relative to address in interrupt table register (INTB)
44
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 1.13.3 shows the memory map of the interrupt control registers.
45
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt control register
Symbol
BCNIC
DMiIC(i=0, 1)
KUPIC
ADIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
Address
When reset
004A16
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
004B16, 004C16
004D16
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005916
005A16 to 005C16
b7 b6 b5 b4 b3 b2 b1 b0
R
W
Bit symbol
Bit name
Function
Interrupt priority level
select bit
ILVL0
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Symbol
Address
When reset
XX00X000
b7 b6 b5 b4 b3 b2 b1 b0
INTiIC(i=0 to 2) 005D16 to 005F16
2
0
R
W
Bit symbol
Bit name
Function
Interrupt priority level
select bit
ILVL0
ILVL1
ILVL2
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt request bit
Polarity select bit
IR
0: Interrupt not requested
1: Interrupt requested
(Note 1)
POL
0 : Selects falling edge
1 : Selects rising edge
Reserved bit
Always set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Figure 1.13.3. Interrupt control registers
46
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.13.3 shows the settings of interrupt priority levels and Table 1.13.4 shows the interrupt levels
enabled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 1.13.4. Interrupt levels enabled according
to the contents of the IPL
Table 1.13.3. Settings of interrupt priority levels
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
IPL
Enabled interrupt priority levels
b2 b1 b0
IPL2
IPL1
IPL0
Level 0 (interrupt disabled)
0
0
0
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0
0
0
1
1
0
Low
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
High
47
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP
NOP
FSET
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
I
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0
; Dummy read.
; Enable interrupts.
FSET
I
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
; Disable interrupts.
FCLR
I
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
48
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-
dress 0000016.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.13.4 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction in
interrupt routine
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
Figure 1.13.4. Interrupt response time
49
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.13.5.
Table 1.13.5. Time required for executing the interrupt sequence
Interrupt vector address Stack pointer (SP) value
16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address
0000
Address bus
Data bus
Indeterminate
Indeterminate
SP-2
SP-4
vec
vec+2
PC
Interrupt
information
SP-2
SP-4
vec
vec+2
contents contents contents contents
R
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 1.13.5. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.13.6 is set in the IPL.
Table 1.13.6. Relationship between interrupts without interrupt priority levels and IPL
Value set in the IPL
Interrupt sources without priority levels
_______
Watchdog timer, NMI
7
0
Reset
Other
Not changed
50
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 1.13.6 shows the state of the stack as it was before the acceptance of the
interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Stack area
Stack area
Address
MSB
Address
MSB
LSB
LSB
[SP]
New stack
pointer value
m – 4
m – 3
m – 2
m – 1
m
m – 4
m – 3
m – 2
m – 1
m
Program counter (PC
Program counter (PC
L
)
M
)
Flag register (FLG )
L
Flag register
(FLG
Program
counter (PC )
H
)
H
[SP]
Stack pointer
value before
interrupt occurs
Content of previous stack
Content of previous stack
Content of previous stack
Content of previous stack
m + 1
m + 1
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 1.13.6. State of stack before and after acceptance of interrupt request
51
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.13.7 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
(1) Stack pointer (SP) contains even number
Sequence in which order
registers are saved
Address
Stack area
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
Program counter (PC )
L
(2) Saved simultaneously,
all 16 bits
Program counter (PC
Flag register (FLG
M
)
L
)
(1) Saved simultaneously,
all 16 bits
Flag register
(FLG
Program
counter (PC )
H
)
H
[SP]
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
Program counter (PC )
L
(3)
(4)
Program counter (PC
Flag register (FLG
M
)
Saved simultaneously,
all 8 bits
L
)
(1)
(2)
Program
counter (PC )
Flag register
(FLG
H
H
)
[SP]
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 1.13.7. Operation of saving registers
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruc-
tion before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware
priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.13.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset > _N__M___I_ > _D__B___C__ > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 1.13.8. Hardware interrupts priorities
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level. Figure 1.13.9 shows the circuit that judges the interrupt priority level.
53
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Priority level of each interrupt
INT1
Level 0 (initial value)
High
Timer B2
Timer B0
Timer A3
Timer A1
INT2
INT0
Timer B1
Timer A4
Timer A2
UART1 reception
UART0 reception
Priority of peripheral I/O interrupts
(if priority levels are same)
UART2 reception
A-D conversion
DMA1
Bus collision detection
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission
Key input interrupt
DMA0
Low
Processor interrupt priority level (IPL)
Interrupt
request
Interrupt enable flag (I flag)
accepted
Address match
Watchdog timer
DBC
NMI
Reset
Figure 1.13.9. Maskable interrupts priorities (peripheral I/O interrupts)
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Mitsubishi microcomputers
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_N___M___I_ Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
______
INT Interrupt
________
________
INT0 to INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity
select bit.
______
NMI Interrupt
______
______
______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03F016).
This pin cannot be used as a normal port input.
Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 1.13.10 shows the block diagram of the key input interrupt. Note that if an
“L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as
an interrupt.
Port P10
4-P107 pull-up
select bit
Pull-up
Key input interrupt control register
(address 004D16
)
transistor
Port P10
register
7 direction
Port P10
7
direction register
P10
7
/KI
3
2
Port P10
register
6 direction
Pull-up
transistor
Key input interrupt
request
Interrupt control circuit
P10
6
/KI
Pull-up
transistor
Port P10
register
5
direction
direction
P105/KI1
Port P10
register
4
Pull-up
transistor
P104/KI0
Figure 1.13.10. Block diagram of key input interrupt
55
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC)
for an address match interrupt varies depending on the instruction being executed.
Figure 1.13.11 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXXXX002
Bit symbol
AIER0
Bit name
Function
R W
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Address match interrupt 1
enable bit
AIER1
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Address match interrupt register i (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
When reset
X0000016
X0000016
b0
Function
Values that can be set
R W
Address setting register for address match interrupt
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Figure 1.13.11. Address match interrupt-related registers
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
_______
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point
at the beginning of a program. Concerning the first instruction immediately after reset, generating any
_______
interrupts including the NMI interrupt is prohibited.
(3) The _N__M___I_ interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a resistor
(pull-up) if unused. Be sure to work on it.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
_______
when the NMI interrupt is input.
_______
• Do not reset the CPU with the input to the NMI pin being in the “L” state.
_______
• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to
_______
the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned
down.
_______
• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to
_______
the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved.
In this instance, the CPU is returned to the normal state by a later interrupt.
_______
• Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.
(4) External interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
________
through INT2 regardless of the CPU operation clock.
________
________
• When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 1.13.12 shows the procedure for
______
changing the INT interrupt generate factor.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
______
Figure 1.13.12. Switching condition of INT interrupt request
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP
NOP
FSET
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
I
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0
; Dummy read.
; Enable interrupts.
FSET
I
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
; Disable interrupts.
FCLR
I
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
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Mitsubishi microcomputers
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Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by
16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7
of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calcu-
lated as given below. The watchdog timer's period is, however, subject to an error due to the pre-scaler.
With XIN chosen for BCLK
pre-scaler dividing ratio (16 or 128) X watchdog timer count (32768)
Watchdog timer period =
BCLK
With XCIN chosen for BCLK
pre-scaler dividing ratio (2) X watchdog timer count (32768)
Watchdog timer period =
BCLK
For example, suppose that BCLK runs at 10 MHZ and that 16 has been chosen for the dividing ratio of the
pre-scaler, then the watchdog timer's period becomes approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 1.14.1 shows the block diagram of the watchdog timer. Figure 1.14.2 shows the watchdog timer-
related registers.
Prescaler
“CM07 = 0”
“WDC7 = 0”
1/16
“CM07 = 0”
“WDC7 = 1”
BCLK
HOLD
Watchdog timer
interrupt request
1/128
1/2
Watchdog timer
“CM07 = 1”
Write to the watchdog timer
start register
Set to
“7FFF16
(address 000E16
)
”
RESET
Figure 1.14.1. Block diagram of watchdog timer
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16
When reset
000XXXXX
0
0
2
Bit symbol
Bit name
Function
R W
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
Must always be set to “0”
Reserved bit
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
R W
this register. The watchdog timer value is always initialized to “7FFF16
regardless of whatever value is written.
”
Figure 1.14.2. Watchdog timer control and start registers
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Mitsubishi microcomputers
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-
bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.15.1 shows the block diagram
of the DMAC. Table 1.15.1 shows the DMAC specifications. Figure 1.15.2 to Figure 1.15.3 show the regis-
ters used by the DMAC.
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016
DMA0 destination pointer DAR0 (20)
)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016
DMA1 destination pointer DAR1 (20)
(addresses 002916, 002816
)
)
DMA0 transfer counter TCR0 (16)
(addresses 003616 to 003416)
DMA1 forward address pointer (20) (Note)
DMA1 transfer counter reload register TCR1 (16)
(addresses 003916, 003816
)
DMA latch high-order bits DMA latch low-order bits
DMA1 transfer counter TCR1 (16)
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 1.15.1. Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.15.1. DMAC specifications
Item
No. of channels
Transfer memory space
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
________ ________
________
DMA request factors (Note)
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transmission and reception interrupt requests
UART1 transmission and reception interrupt requests (UART1 trans-
mission can be selected by DMA0, UART1 reception by DMA1)
UART2 transmission and reception interrupt requests
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
8 bits or 16 bits
Transfer unit
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
• Single transfer mode
After the transfer counter underflows, the DMA enable bit turns to
“0”, and the DMAC turns inactive
• Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.
The DMAC remains active unless a “0” is written to the DMA enable bit.
DMA interrupt request generation timing When an underflow occurs in the transfer counter
Active
When the DMA enable bit is set to “1”, the DMAC is active.
When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.
Inactive
• When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode
At the time of starting data transfer immediately after turning the DMAC active, re
the value of one of source pointer and destination pointer - the one specified for the
forward direction - is reloaded to the forward direction address pointer,and the value
of the transfer counter reload register is reloaded to the transfer counter.
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Forward address pointer and
load timing for transfer
counter
Writing to register
Reading the register
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
flag (I flag) nor by the interrupt priority level.
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi request cause select register
Symbol
DMiSL(i=0,1)
Address
03B816,03BA16
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Function
Bit symbol
DSEL0
Bit name
R
W
b3 b2 b1 b0
DMA request cause
select bit
0 0 0 0 : Falling edge of INT0 / INT1
pin (Note 1)
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4
0 1 1 1 : Timer B0
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
DSEL1
DSEL2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit / UART1
receive (Note 2)
DSEL3
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Software DMA request bit
DSR
Note 1: Address 03B816 is for INT0 ; address 03BA16 is for INT1.
Note 2: Address 03B816 is for UART1 transmit ; address 03BA16 is for UART1 receive.
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DMiCON(i=0,1)
Address
002C16, 003C16
When reset
00000X00
2
Bit symbol
DMBIT
Bit name
Function
R
W
Transfer unit bit select bit 0 : 16 bits
1 : 8 bits
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMASL
DMAS
DMAE
0 : DMA not requested
1 : DMA requested
DMA request bit (Note 1)
DMA enable bit
(Note 2)
0 : Disabled
1 : Enabled
Source address direction
select bit (Note 3)
0 : Fixed
1 : Forward
DSD
DAD
Destination address
direction select bit (Note 3)
0 : Fixed
1 : Forward
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
Figure 1.15.2. DMAC register (1)
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Mitsubishi microcomputers
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi source pointer (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
R W
• Source pointer
Stores the source address
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi destination pointer (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
R W
• Destination pointer
Stores the destination address
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
R W
• Transfer counter
Set a value one less than the transfer count
000016 to FFFF16
Figure 1.15.3. DMAC register (2)
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Mitsubishi microcomputers
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of BYTE pin level
When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and
microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are
required for reading the data and two are required for writing the data. Also, in contrast to when the
CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal
RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.15.4 shows the example of the transfer cycles for a source read. For convenience, the destina-
tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown.
In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec-
tive conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 36,
if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source
read cycle and the destination write cycle.
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) 8-bit transfers
16-bit transfers from even address and the source address is even.
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1 Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source + 1
Source
CPU use
Destination
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.15.4. Example of the transfer cycles for a source read
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Mitsubishi microcomputers
M16C / 61 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.15.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.15.2. No. of DMAC transfer cycles
Single-chip mode
Memory expansion mode
Microprocessor mode
Transfer unit
Bus width
Access address
No. of read No. of write No. of read No. of write
cycles
cycles
cycles
cycles
16-bit
(BYTE= “L”)
8-bit
Even
Odd
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
2
2
2
8-bit transfers
(DMBIT= “1”)
Even
Odd
—
—
1
—
—
1
(BYTE = “H”)
16-bit
Even
Odd
16-bit transfers
(DMBIT= “0”)
(BYTE = “L”)
8-bit
2
2
Even
Odd
—
—
—
—
(BYTE = “H”)
Coefficient j, k
Internal memory
External memory
Internal ROM/RAM Internal ROM/RAM SFR area Separate bus Separate bus
Multiplex
No wait
1
With wait
2
No wait
1
With wait
2
bus
3
2
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Mitsubishi microcomputers
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA enable bit
Setting the DMA enable bit to 1 makes the DMAC active. The DMAC carries out the following operations at
the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the
forward direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting 1 to the DMA enable bit with the DMAC being active carries out the operations given
above, so the DMAC operates again from the initial state at the instant 1 is overwritten to the DMA enable
bit.
DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA
request factors for each channel.
DMA request factors include the following.
* Factors effected by using the interrupt request signals from the built-in peripheral functions and software
DMA factors (internal factors) effected by a program.
* External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMAi factor selection register.
The DMA request bit turns to 1 if the DMA transfer request signal occurs regardless of the DMAC's state
(regardless of whether the DMA enable bit is set 1 or to 0). It turns to 0 immediately before data transfer
starts.
In addition, it can be set to 0 by use of a program, but cannot be set to 1.
There can be instances in which a change in DMA request factor selection bit causes the DMA request bit
to turn to 1. So be sure to set the DMA request bit to 0 after the DMA request factor selection bit is changed.
The DMA request bit turns to 1 if a DMA transfer request signal occurs, and turns to 0 immediately before
data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request
bit, if read by use of a program, turns out to be 0 in most cases. To examine whether the DMAC is active,
read the DMA enable bit.
Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to 1 due
to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to
turn to 1 due to several factors.
Turning the DMA request bit to 1 due to an internal factor is timed to be effected immediately before the
transfer starts.
(2) External factors
An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on
which DMAC channel is used).
Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from
these pins to become the DMA transfer request signals.
The timing for the DMA request bit to turn to 1 when an external factor is selected synchronizes with the
signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes
with the trailing edge of the input signal to each INTi pin, for example).
With an external factor selected, the DMA request bit is timed to turn to 0 immediately before data transfer
starts similarly to the state in which an internal factor is selected.
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from
the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently
turn to 1. If the channels are active at that moment, DMA0 is given a high priority to start data transfer.
When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus
access, then DMA1 starts data transfer and gives the bus right to the CPU.
An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer
request signals due to external factors concurrently occur.
Figure 1.15.5 An example of DMA transfer effected by external factors.
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
BCLK
DMA0
Obtainm
ent of the
bus right
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 1.15.5. An example of DMA transfer effected by external factors
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
Timer
There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(three). All these timers function independently. Figure 1.16.1 shows the block diagram of timers.
Clock prescaler
f
1
8
fC32
XIN
1/32
Reset
X
CIN
f
1/8
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
f
32
1/4
f1 f8 f32 fC32
• Timer mode
• One-shot mode
• PWM mode
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer A0
Noise
filter
TA0IN
TA1IN
TA2IN
TA3IN
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A1
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A2
Timer A3
Timer A4
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Noise
filter
TA4IN
TB0IN
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B0 interrupt
Timer B1 interrupt
Noise
filter
Timer B0
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
TB1IN
TB2IN
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B2 interrupt
Noise
filter
Timer B2
• Event counter mode
Figure 1.16.1. Block diagram of timer
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A
Figure 1.16.2 shows the block diagram of timer A. Figures 1.16.3 to 1.16.5 show the timer A-related
registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f
1
Low-order
8 bits
High-order
8 bits
f8
• Timer
(gate function)
f
32
Reload register (16)
f
C32
• Event counter
Clock selection
Counter (16)
Polarity
selection
Up count/down count
TAiIN
Always down count except
in event counter mode
(i = 0 to 4)
Count start flag
(Address 038016
)
TAi
Addresses
TAj
TAk
Down count
Timer A0 038716 038616
Timer A1 038916 038816
Timer A2 038B16 038A16 Timer A1 Timer A3
Timer A3 038D16 038C16 Timer A2 Timer A4
Timer A4 038F16 038E16 Timer A3 Timer A0
Timer A4 Timer A1
Timer A0 Timer A2
TB2 overflow
External
trigger
Up/down flag
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
(Address 038416
)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Figure 1.16.2. Block diagram of timer A
Timer Ai mode register
Symbol
Address
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
TAiMR(i=0 to 4) 039616 to 039A16
R W
Bit symbol
TMOD0
Bit name
Function
b1 b0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Figure 1.16.3. Timer A-related registers (1)
71
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer Ai register (Note)
Symbol
TA0
TA1
TA2
TA3
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
(b15)
(b8)
b0 b7
038716,038616
038916,038816
038B16,038A16
038D16,038C16
038F16,038E16
b7
b0
TA4
Values that can be set
000016 to FFFF16
Function
R W
• Timer mode
Counts an internal count source
• Event counter mode
Counts pulses from an external source or timer overflow
000016 to FFFF16
000016 to FFFF16
• One-shot timer mode
Counts a one shot width
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
000016 to FFFE16
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FE16
(Both high-order
and low-order
addresses)
Note: Read and write data in 16-bit units.
Count start flag
Symbol
TABSR
Address
038016
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
R W
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Up/down flag
Symbol
UDF
Address
038416
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
TA0UD
Bit name
Function
Timer A0 up/down flag
0 : Down count
1 : Up count
TA1UD
TA2UD
TA3UD
TA4UD
TA2P
Timer A1 up/down flag
Timer A2 up/down flag
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
Timer A3 up/down flag
Timer A4 up/down flag
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
Timer A2 two-phase pulse
signal processing select bit
TA3P
TA4P
Timer A3 two-phase pulse
signal processing select bit
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
Timer A4 two-phase pulse
signal processing select bit
Figure 1.16.4. Timer A-related registers (2)
72
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
One-shot start flag
Symbol
ONSF
Address
038216
When reset
b7 b6 b5 b4 b3 b2 b1 b0
00X00000
2
R W
Bit symbol
Bit name
Function
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA0OS
TA1OS
TA2OS
TA3OS
TA4OS
1 : Timer start
When read, the value is “0”
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
b7 b6
TA0TGL
Timer A0 event/trigger
select bit
0 0 : Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
TA0TGH
Note: Set the corresponding port direction register to “0”.
Trigger select register
Symbol
TRGSR
Address
038316
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA1TGL
Bit name
Function
R W
b1 b0
Timer A1 event/trigger
select bit
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
TA1TGH
TA2TGL
b3 b2
Timer A2 event/trigger
select bit
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
TA2TGH
TA3TGL
TA3TGH
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
b7 b6
Timer A4 event/trigger
select bit
TA4TGL
TA4TGH
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”.
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
2
Bit symbol
Bit name
Function
R W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
0 : No effect
1 : Prescaler is reset
CPSR
Clock prescaler reset flag
(When read, the value is “0”)
Figure 1.16.5. Timer A-related registers (3)
73
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.16.1.) Figure 1.16.6
shows the timer Ai mode register in timer mode.
Table 1.16.1. Specifications of timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Down count
•
When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing When the timer underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or gate input
Programmable I/O port or pulse output
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
• Gate function
Select function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i=0 to 4) 039616 to 039A16
0
0 0
Bit symbol
Bit name
Function
R W
b1 b0
Operation mode
select bit
TMOD0
TMOD1
MR0
0 0 : Timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
b4 b3
Gate function select bit
MR1
MR2
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN pin is
held “L” (Note 3)
1 1 : Timer counts only when TAiIN pin is
held “H” (Note 3)
MR3
0 (Must always be fixed to “0” in timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Figure 1.16.6. Timer Ai mode register in timer mode
74
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 1.16.2 lists timer specifications when counting a single-phase external signal.
Figure 1.16.7 shows the timer Ai mode register in event counter mode.
Table 1.16.3 lists timer specifications when counting a two-phase external signal. Figure 1.16.8 shows
the timer Ai mode register in event counter mode.
Table 1.16.2. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
•
External signals input to TAiIN pin (effective edge can be selected by software)
• TB2 overflow, TAj overflow
Count operation
• Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
1/ (FFFF16 - n + 1) for up count
Divide ratio
1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing The timer overflows or underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or count source input
Programmable I/O port, pulse output, or up/down count select input
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TAiMR(i = 0, 1)
Address
039616, 039716
When reset
0016
0
0 1
Bit symbol
Bit name
Function
R W
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
0 1 : Event counter mode (Note 1)
0 : Pulse is not output
Pulse output function
select bit
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TAiOUT pin is a pulse output pin)
MR1
MR2
Count polarity
select bit (Note 3)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 4)
MR3
0 (Must always be fixed to “0” in event counter mode)
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
Invalid in event counter mode
Can be “0” or “1”
TCK1
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Figure 1.16.7. Timer Ai mode register in event counter mode
75
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Table 1.16.3. Timer specifications in event counter mode (when processing two-phase pulse
signal with timers A2, A3, and A4)
Item
Count source
Count operation
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pin
• Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
Divide ratio
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing Timer overflows or underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Two-phase pulse input
Two-phase pulse input
Count value can be read out by reading timer A2, A3, or A4 register
• When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
• When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
reload register. (Transferred to counter at next reload time.)
• Normal processing operation
Select function
The timer counts up rising edges or counts down falling edges on the TAiIN
pin when input signal on the TAiOUT pin is “H”
TAiOUT
TAiIN
(i=2,3)
Up
count
Up
count
Up
Down
Down
count
Down
count
count count
• Multiply-by-4 processing operation
If the phase relationship is such that the TAiIN pin goes “H” when the input
signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count down all edges
Count down all edges
Count up all edges
TAiIN
(i=3,4)
Count up all edges
Note: This does not apply when the free-run function is selected.
76
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer Ai mode register
(When not using two-phase pulse signal processing)
Symbol
Address
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
TAiMR(i = 2 to 4) 039816 to 039A16
0
0 1
R W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode select bit
0 1 : Event counter mode
Pulse output function
select bit
0 : Pulse is not output
MR0
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
Count polarity
select bit (Note 2)
0 : Counts external signal's falling edges
1 : Counts external signal's rising edges
MR1
MR2
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 3)
Up/down switching
cause select bit
0 : (Must always be “0” in event counter mode)
MR3
TCK0
0 : Reload type
1 : Free-run type
Count operation type
select bit
Two-phase pulse signal
processing operation
select bit (Note 4)(Note 5)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0”.
Note 4: This bit is valid for the timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0 ”or “1”.
Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Timer Ai mode register
(When using two-phase pulse signal processing)
Symbol
Address
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
TAiMR(i = 2 to 4) 039816 to 039A16
0
1 0 0 0 1
Bit symbol
Bit name
Function
R W
b1 b0
TMOD0
TMOD1
Operation mode select bit
0 1 : Event counter mode
0 (Must always be “0” when using two-phase pulse signal
processing)
MR0
MR1
MR2
0 (Must always be “0” when using two-phase pulse signal
processing)
1 (Must always be “1” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
MR3
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK0
Two-phase pulse
processing operation
select bit (Note 1)(Note 2)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: This bit is valid for timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0” or “1”.
Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Figure 1.16.8. Timer Ai mode register in event counter mode
77
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.16.4.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.16.9 shows the timer Ai mode register in one-shot
timer mode.
Table 1.16.4. Timer specifications in one-shot timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio
1/n
n : Set value
Count start condition
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing The count reaches 000016
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or trigger input
Programmable I/O port or pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i = 0 to 4) 039616 to 039A16
0
1 0
Bit symbol
Bit name
R W
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
1 0 : One-shot timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
MR2
0 : Falling edge of TAiIN pin's input signal (Note 3)
1 : Rising edge of TAiIN pin's input signal (Note 3)
External trigger select
bit (Note 2)
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
Trigger select bit
MR3
0 (Must always be “0” in one-shot timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0”.
Figure 1.16.9. Timer Ai mode register in one-shot timer mode
78
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.16.5.) In this mode, the counter functions
as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.16.10 shows the configuration of the
timer Ai mode register in pulse width modulation mode. Figure 1.16.11 shows an example of how a 16-bit pulse width
modulator operates. Figure 1.16.12 shows an example of how an 8-bit pulse width modulator operates.
Table 1.16.5. Timer specifications in pulse width modulation mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
The timer reloads a new count at a rising edge of PWM pulse and continues counting
•
• The timer is not affected by a trigger that occurs when counting
16-bit PWM
• High level width
n / fi n : Set value
- 1) / fi fixed
16
• Cycle time
(2
8-bit PWM
•
•
High level width n X (m+1) / fi n : values set to timer Ai register’s high-order address
Cycle time (28 - 1) X (m +1) / fim : values set to timer Ai register’s low-order address
Count start condition
• External trigger is input
• The timer overflows
• The count start flag is set (= 1)
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing PWM pulse goes “L”
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or trigger input
Pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
1
1 1
TAiMR(i=0 to 4) 039616 to 039A16
R W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode
select bit
1 1 : PWM mode
1 (Must always be fixed to “1” in PWM mode)
External trigger select
MR1
0: Falling edge of TAiIN pin's input signal (Note 2)
bit (Note 1)
1: Rising edge of TAiIN pin's input signal (Note 2)
MR2
Trigger select bit
0: Count start flag is valid
1: Selected by event/trigger select register
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
16/8-bit PWM mode
select bit
MR3
b7 b6
TCK0
TCK1
Count source select bit
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0
Note 2: Set the corresponding port direction register to “0”.
Figure 1.16.10. Configuration of timer Ai mode register in pulse width modulation mode
79
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Condition : Reload register = 000316, when external trigger
(rising edge of TAiIN pin input signal) is selected
1 / fi X
(216 – 1)
Count source
“H”
“L”
TAiIN pin
input signal
Trigger is not generated by this signal
1 / f
i
X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
Timer Ai interrupt
request bit
fi
: Frequency of count source
(f , f , f32, fC32
1
8
)
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: n = 000016 to FFFE16
.
Figure 1.16.11. Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi
X (m + 1) X (28 – 1)
Count source (Note1)
TAiIN pin input signal
“H”
“L”
1 / fi X (m + 1)
“H”
“L”
Underflow signal of
8-bit prescaler (Note2)
1 / fi X (m + 1) X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
Timer Ai interrupt
request bit
f
i
: Frequency of count source
(f , f , f32, fC32
Cleared to “0” when interrupt request is accepted, or cleaerd by software
1
8
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FE16; n = 0016 to FE16
.
Figure 1.16.12. Example of how an 8-bit pulse width modulator operates
80
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer B
Figure 1.16.13 shows the block diagram of timer B. Figures 1.16.14 and 1.16.15 show the timer B-related
registers.
Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
f
1
• Timer
Reload register (16)
• Pulse period/pulse width measurement
f
f
8
32
fC32
Counter (16)
• Event counter
Count start flag
Polarity switching
and edge pulse
TBiIN
(i = 0 to 2)
(address 038016
)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Address
TBj
TBj overflow
(j = i – 1. Note, however,
j = 2 when i = 0)
Timer B0 039116 039016 Timer B2
Timer B1 039316 039216 Timer B0
Timer B2 039516 039416 Timer B1
Figure 1.16.13. Block diagram of timer B
Timer Bi mode register
Symbol
Address
When reset
00XX00002
b7 b6 b5 b4 b3 b2 b1 b0
TBiMR(i = 0 to 2) 039B16 to 039D16
R
W
Bit symbol
Function
Bit name
b1 b0
TMOD0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
TMOD1
MR0
MR1
MR2
Function varies with each operation mode
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0.
Note 2: Timer B1, timer B2.
Figure 1.16.14. Timer B-related registers (1)
81
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer Bi register (Note)
Symbol
TB0
TB1
Address
When reset
(b15)
(b8)
039116, 039016 Indeterminate
039316, 039216 Indeterminate
039516, 039416 Indeterminate
b7
b0 b7
b0
TB2
Values that can be set
000016 to FFFF16
Function
R W
• Timer mode
Counts the timer's period
• Event counter mode
000016 to FFFF16
Counts external pulses input or a timer overflow
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
Count start flag
Symbol
TABSR
Address
038016
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
R W
Bit name
Function
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Clock prescaler reset flag
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
Bit name
Function
R W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
Clock prescaler reset flag
Figure 1.16.15. Timer B-related registers (2)
82
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.16.6.) Figure 1.16.16
shows the timer Bi mode register in timer mode.
Table 1.16.6. Timer specifications in timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Programmable I/O port
Count value is read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
00XX0000
TBiMR(i=0 to 2) 039B16 to 039D16
2
0
0
Bit symbol
R
W
Bit name
Function
0 0 : Timer mode
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
Invalid in timer mode
Can be “0” or “1”
MR1
MR2
0 (Fixed to “0” in timer mode ; i = 0)
(Note 1)
(Note 2)
Nothing is assiigned (i = 1,2).
In an attempt to write to this bit, write “0” . The value, if read, turns out
to be indeterminate.
Invalid in timer mode.
MR3
In an attempt to write to this bit, write “0” . The value, if read in
timer mode, turns out to be indeterminate.
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
0 1 : f
1
8
1 0 : f32
1 1 : fC32
Note 1: Timer B0.
Note 2: Timer B1, timer B2.
Figure 1.16.16. Timer Bi mode register in timer mode
83
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.16.7.)
Figure 1.16.17 shows the timer Bi mode register in event counter mode.
Table 1.16.7. Timer specifications in event counter mode
Item
Specification
• External signals input to TBiIN pin
Count source
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Count source input
Count value can be read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
00XX00002
TBiMR(i=0 to 2) 039B16 to 039D16
0
1
R
W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
0 1 : Event counter mode
b3 b2
Count polarity select
bit (Note 1)
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
MR1
1 0 : Counts external signal's
falling and rising edges
1 1 : Inhibited
0 (Fixed to “0” in event counter mode; i = 0)
MR2
MR3
(Note 2)
(Note 3)
Nothing is assigned (i = 1, 2).
In an attempt to write to this bit, write “0” . The value, if read,
turns out to be indeterminate.
Invalid in event counter mode.
In an attempt to write to this bit, write “0” . The value, if read
in event counter mode, turns out to be indeterminate.
Invalid in event counter mode.
Can be “0” or “1”.
TCK0
TCK1
0 : Input from TBiIN pin (Note 4)
1 : TBj overflow
Event clock select
(j = i – 1; however, j = 2 when i = 0)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Timer B0.
Note 3: Timer B1, timer B2.
Note 4: Set the corresponding port direction register to “0”.
Figure 1.16.17. Timer Bi mode register in event counter mode
84
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.16.8.)
Figure 1.16.18 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.16.19 shows the operation timing when measuring a pulse period. Figure 1.16.20 shows the operation
timing when measuring a pulse width.
Table 1.16.8. Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start flag is set (= 1)
Count start condition
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function
Read from timer
Measurement pulse input
When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
00XX0000
TBiMR(i=0 to 2) 039B16 to 039D16
2
1
0
R
W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 0 : Pulse period / pulse width
measurement mode
b3 b2
MR0
MR1
Measurement mode
select bit
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
MR2
0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0)
(Note 2)
(Note 3)
Nothing is assigned (i = 1, 2).
In an attempt to write to this bit, write “0” . The value, if read, turns out to be
indeterminate.
Timer Bi overflow
flag ( Note 1)
0 : Timer did not overflow
1 : Timer has overflowed
MR3
b7 b6
TCK0
TCK1
Count source
select bit
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
Note 1: The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Note 2: Timer B0.
Note 3: Timer B1, timer B2.
Figure 1.16.18. Timer Bi mode register in pulse period/pulse width measurement mode
85
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
When measuring measurement pulse time interval from falling edge to falling edge
Count source
“H”
“L”
Measurement pulse
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.16.19. Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
“L”
Transfer
(measured value)
Transfer
(measured value)
Transfer
(indeterminate
value)
Transfer
(measured
value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.16.20. Operation timing when measuring a pulse width
86
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O
Serial I/O is configured as three channels: UART0, UART1 and UART2. UART0, UART1 and UART2 each
have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figure 1.17.1 shows the block diagram of UART0, UART1 and UART2. Figure 1.17.2 and figure 1.17.3
show the block diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a
UART.
UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is
compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode
(Note). It also has the bus collision detection function that generates an interrupt request if the TXD pin and
the RXD pin are different in level.
Note: SIM : Subscriber Identity Module
Table 1.17.1 shows the comparison of functions of UART0 through UART2, and Figures 1.17.4 through
1.17.8 show the registers related to UARTi.
Table 1.17.1. Comparison of functions of UART0 through UART2
Function
UART0
UART1
UART2
Possible
CLK polarity selection
Possible
Possible
(Note 1) Possible (Note 1)
(Note 1) Possible (Note 1)
(Note 1) Possible (Note 1)
Possible (Note 1)
(Note 1)
(Note 2)
(Note 1)
LSB first / MSB first selection
Possible
Continuous receive mode selection
Possible
Possible
Transfer clock output from multiple
pins selection
Impossible
Possible
Impossible
Impossible
Possible
Separate CTS/RTS pins
Serial data logic switch
Sleep mode selection
Impossible
Impossible
Possible
Impossible
(Note 4)
(Note 3) Possible (Note 3)
Impossible
Impossible
Possible
TxD, RxD I/O polarity switch
TxD, RxD port output format
Parity error signal output
Bus collision detection
Impossible
N-channel open-drain
output
CMOS output
Impossible
Impossible
CMOS output
Impossible
Impossible
Possible
Possible
(Note 4)
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
87
Mitsubishi microcomputers
M16C / 61 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(UART0)
RxD
0
TxD
0
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
Bit rate generator
f
f
f
1
Internal
(address 03A116
)
8
Transmit
clock
UART transmission
32
1/16
1 / (n0+1)
Transmission
control circuit
Clock synchronous type
External
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK0
CTS/RTS disabled
CTS/RTS selected
RTS
0
CTS0 / RTS0
Vcc
CTS/RTS disabled
CTS/RTS separated
CTS
0
CTS0 from UART1
(UART1)
RxD1
TxD
1
UART reception
Receive
clock
1/16
Transmit/
receive
unit
Reception
control circuit
Clock source selection
Bit rate generator
(address 03A916
Clock synchronous type
f1
)
Internal
f
8
UART transmission
1/16
Transmit
clock
1 / (n1+1)
f32
Transmission
control circuit
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
1/2
External
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK1
CTS/RTS disabled
CTS/RTS separated
RTS
1
CTS
CTS
1
0
/ RTS1
V
CC
/ CLKS
1
Clock output pin
select switch
CTS/RTS disabled
CTS
1
CTS
0
CTS0 to UART0
(UART2)
TxD
RxD polarity
reversing circuit
polarity
reversing
circuit
RxD
2
TxD2
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
Bit rate generator
(address 037916
f
f
f
1
Internal
)
8
UART transmission
1/16
Transmit
clock
32
1 / (n2+1)
Transmission
control circuit
Clock synchronous type
Clock synchronous type
External
(when internal clock is selected)
1/2
Clock synchronous type
(when external clock is
selected)
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
CLK2
CTS/RTS
selected
CTS/RTS disabled
RTS
2
CTS
2
/ RTS
2
Vcc
CTS/RTS disabled
CTS
2
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)
Figure 1.17.1. Block diagram of UARTi (i = 0 to 2)
88
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M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Clock
synchronous type
UART (7 bits)
UART (8 bits)
Clock
UARTi receive register
synchronous
type
UART (7 bits)
PAR
disabled
1SP
2SP
SP
SP
PAR
RxDi
PAR
enabled
UART
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
UARTi receive
buffer register
0
0
0
0
0
0
0
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
UARTi transmit
buffer register
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
D
8
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UART (9 bits)
PAR
enabled
UART
2SP
1SP
SP
SP
PAR
TxDi
Clock
synchronous
type
PAR
disabled
UART (7 bits)
UARTi transmit register
UART (7 bits)
UART (8 bits)
SP: Stop bit
PAR: Parity bit
“0”
Clock synchronous
type
Figure 1.17.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
89
Mitsubishi microcomputers
M16C / 61 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
No reverse
Reverse
RxD data
reverse circuit
RxD2
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
type
UART2 receive register
PAR
disabled
UART(7 bits)
1SP
SP
PAR
SP
2SP
Clock
synchronous type
PAR
enabled
UART
UART
(9 bits)
UART
(8 bits)
UART
(9 bits)
UART2 receive
buffer register
0
0
0
0
0
0
0
D
8
D7
D6
D5
D
4
D3
D2
D
1
D0
Address 037E16
Address 037F16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
UART2 transmit
buffer register
D7
D6
D
5
D
4
D3
D
2
D
1
D
0
D8
Address 037A16
Address 037B16
UART
(8 bits)
UART
(9 bits)
UART
(9 bits)
Clock
synchronous type
PAR
enabled
UART
2SP
SP
SP
PAR
1SP
Clock
synchronous
type
PAR
disabled
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART2 transmit register
“0”
Clock
synchronous type
Error signal output
disable
No reverse
TxD data
reverse circuit
Error signal
output circuit
TxD2
Reverse
Error signal output
enable
SP: Stop bit
PAR: Parity bit
Figure 1.17.3. Block diagram of UART2 transmit/receive unit
90
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit buffer register
Symbol
U0TB
U1TB
U2TB
Address
When reset
(b15)
b7
(b8)
03A316, 03A216
03AB16, 03AA16
037B16, 037A16
Indeterminate
Indeterminate
Indeterminate
b0 b7
b0
Function
R W
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
UARTi receive buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
U2RB
Address
When reset
Indeterminate
Indeterminate
Indeterminate
b0
03A716, 03A616
03AF16, 03AE16
037F16, 037E16
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
Receive data
Receive data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
OER
Overrun error flag (Note)
0 : No overrun error
0 : No overrun error
1 : Overrun error found
1 : Overrun error found
FER
Framing error flag (Note)
Invalid
0 : No framing error
1 : Framing error found
PER
SUM
Parity error flag (Note)
Error sum flag (Note)
Invalid
Invalid
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016
,
03A816 and 037816) are set to “000 ” or the receive enable bit is set to “0”.
2
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out.
UARTi bit rate generator
Symbol
U0BRG
U1BRG
U2BRG
Address
03A116
03A916
037916
When reset
Indeterminate
Indeterminate
Indeterminate
b7
b0
R W
Function
Values that can be set
0016 to FF16
Assuming that set value = n, BRGi divides the count source by
n + 1
Figure 1.17.4. Serial I/O-related registers (1)
91
Mitsubishi microcomputers
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Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
Must be fixed to 001
b2 b1 b0
SMD0
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR
STPS
PRY
Internal/external clock
select bit
0 : Internal clock
1 : External clock
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
SLEP
Parity enable bit
Sleep select bit
Invalid
0 : Sleep mode deselected
1 : Sleep mode selected
Must always be “0”
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
SMD0
Must be fixed to 001
b2 b1 b0
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
SMD1
SMD2
1 1 1 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR
STPS
PRY
Internal/external clock
select bit
0 : Internal clock
1 : External clock
Must always be “0”
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
Parity enable bit
Invalid
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
IOPOL
Usually set to “0”
Usually set to “0”
Figure 1.17.5. Serial I/O-related registers (2)
92
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0(i=0,1)
Address
03A416, 03AC16
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
R W
Bit name
b1 b0
b1 b0
CLK0 BRG count source
select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
CLK1
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CRS
CTS/RTS function
select bit
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
CRD
NCH
CTS/RTS disable bit
Data output select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Must always be “0”
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
UFORM Transfer format select bit
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C0
Address
037C16
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
R W
Bit name
b1 b0
b1 b0
CLK0
CLK1
BRG count source
select bit
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CRS
CTS/RTS function
select bit
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions programmable
I/O port)
CRD
CTS/RTS disable bit
programmable I/O port)
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Must always be “0”
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
0 : LSB first
1 : MSB first
Transfer format select bit
(Note 3)
UFORM
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Figure 1.17.6. Serial I/O-related registers (3)
93
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M16C / 61 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1(i=0,1)
Address
03A516,03AD16
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C1
Address
037D16
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Bit
Function
(During UART mode)
Bit name
symbol
R W
TE
TI
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
U2IRS UART2 transmit interrupt 0 : Transmit buffer empty
0 : Transmit buffer empty
(TI = 1)
cause select bit
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
1 : Transmit is completed
(TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
U2ERE Error signal output
enable bit
Must be fixed to “0”
0 : Output disabled
1 : Output enabled
Figure 1.17.7. Serial I/O-related registers (4)
94
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
When reset
X0000000
2
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0IRS UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS UART1 transmit
interrupt cause select bit
U0RRM UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Invalid
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
CLKMD0 CLK/CLKS select bit 0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD1 CLK/CLKS select
bit 1 (Note)
0 : Normal mode
Must always be “0”
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Separate CTS/RTS bit
RCSP
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
Figure 1.17.8. Serial I/O-related registers (5)
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Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.17.2
and table 1.17.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.17.9 shows the
UARTi transmit/receive mode register.
Table 1.17.2. Specifications of clock synchronous serial I/O mode (1)
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “1”) : Input from CLKi pin
_______
_______
_______ _______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
_______
_______
_
When CTS function selected, CTS input level = “L”
Furthermore, if external clock is selected, the following requirements must also be met:
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
•
_
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
Reception start condition • To start reception, the following requirements must be met:
_
Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
• When transmitting
Interrupt request
generation timing
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
_
Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 2)
Error detection
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
96
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
Table 1.17.3. Specifications of clock synchronous serial I/O mode (2)
Item
Specification
Select function
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1) (Note)
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
_______ _______
• Separate CTS/RTS pins (UART0) (Note)
_______
_______
UART0 CTS and RTS pins each can be assigned to separate pins
• Switching serial data logic (UART2)
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected.
• TXD, RXD I/O polarity reverse (UART2)
This function is reversing TXD port output and RXD port input. All I/O data
level is reversed.
_______ _______
Note: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be
selected simultaneously.
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Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
0
0 0 1
Bit symbol
Bit name
Function
R W
b2 b1 b0
SMD0
SMD1
SMD2
CKDIR
Serial I/O mode select bit
0 0 1 : Clock synchronous serial
I/O mode
Internal/external clock
select bit
0 : Internal clock
1 : External clock
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
0 (Must always be “0” in clock synchronous serial I/O mode)
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
When reset
0016
0
0 0 1
Bit symbol
Bit name
Function
R W
b2 b1 b0
SMD0
SMD1
SMD2
CKDIR
Serial I/O mode select bit
0 0 1 : Clock synchronous serial
I/O mode
Internal/external clock
select bit
0 : Internal clock
1 : External clock
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
0 : No reverse
1 : Reverse
Note: Usually set to “0”.
Figure 1.17.9. UARTi transmit/receive mode register in clock synchronous serial I/O mode
98
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
Table 1.17.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This
_______
table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/
_______
RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is
selected to when transfer starts, the TXDi pin outputs a “H”. (If the N-channel open-drain is selected, this
pin is in floating state.)
Table 1.17.4. Input/output pin functions in clock synchronous serial I/O mode
Pin name
TxDi
(P6 , P67, P70)
Function
Method of selection
Serial data output
(Outputs dummy data when performing reception only)
3
Serial data input
RxDi
(P6 , P6
Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16,
bit 1 at address 03EF16)= “0”
(Can be used as an input port when performing transmission only)
2
6
, P7
1
)
)
CLKi
(P6 , P6
Transfer clock output
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0”
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “1”
1
5
, P7
2
Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16,
bit 2 at address 03EF16) = “0”
CTSi/RTSi
(P6 , P6 , P73)
CTS input
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0”
0
4
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0”
Port P6 , P6 and P7 direction register (bits 0 and 4 at address 03EE16
0
4
3
,
bit 3 at address 03EF16) = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1”
_______ _______
(when transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected)
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Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
“0”
“1”
“0”
“H”
Data is set in UARTi transmit buffer register
bit (TE)
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
CTSi
CLKi
T
CLK
“L”
Stopped pulsing because CTS = “H”
Stopped pulsing because transfer enable bit = “0”
TxDi
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D6
D7
Transmit
register empty
flag (TXEPT)
“1”
“0”
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = TCLK = 2(n + 1) / fi
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
fi: frequency of BRGi count source (f
n: value set to BRGi
1, f8, f32)
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
“1”
Transmit enable
bit (TE)
“0”
“1”
“0”
“H”
Dummy data is set in UARTi transmit buffer register
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
RTSi
CLKi
RxDi
“L”
1 / fEXT
Receive data is taken in
D
0
D1
D
2
D3
D
4
D5
D6
D0
D
1
D
2
D4
D5
D
7
D3
Transferred from UARTi receive register
to UARTi receive buffer register
Read out from UARTi receive buffer register
“1”
“0”
Receive complete
flag (Rl)
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
fEXT: frequency of external clock
Figure 1.17.10. Typical transmit/receive timings in clock synchronous serial I/O mode
100
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
(a) Polarity select function
As shown in Figure 1.17.11, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16)
allows selection of the polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLK
i
Note 1: The CLK pin level when not
transferring data is “H”.
D0
D
1
D
2
D
3
3
D
4
D
5
5
D
6
6
D
7
7
TXDi
D0
D
1
D
2
D
D4
D
D
D
RXDi
• When CLK polarity select bit = “1”
CLK
i
Note 2: The CLK pin level when not
transferring data is “L”.
D
0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
D
0
D
1
D
2
D
3
D
D
5
D
6
D7
RXDi
Figure 1.17.11. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.17.12, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16,
037C16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format select bit = “0”
CLK
i
D0
D
1
D
2
D
3
D
D
4
4
D
5
D
6
D7
TXDi
LSB first
D
1
D
2
D
3
D
5
D
6
D7
D
0
RXDi
• When transfer format select bit = “1”
CLK
i
D
D
7
7
D
6
D
5
D
4
D
D
3
3
D
2
D
1
D0
TXDi
MSB first
D
6
D
5
D
4
D
2
D
1
D0
RXDi
Note: This applies when the CLK polarity select bit = “0”.
Figure 1.17.12. Transfer format
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Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.17.13.)
The multiple pins function is valid only when the internal clock is selected for UART1. Note that when
_______ _______
this function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
T
XD1
(P6
7)
CLKS
1
1
(P6
4
)
)
CLK
(P65
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 1.17.13. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is
set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register
is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to
the transmit buffer register back again.
_______ _______
(e) Separate CTS/RTS pins function (UART0)
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method
of setting and the input/output pin functions are both the same, so refer to select function in the next
section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the
transfer clock output from the multiple pins function is selected.
(f) Serial data logic switch function (UART2)
When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or
reading from receive buffer register, data is reversed. Figure 1.17.14 shows the example of serial data
logic switch timing.
•When LSB first
“H”
Transfer clock
“L”
“H”
TxD2
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
(no reverse)
“L”
“H”
“L”
TxD2
(reverse)
Figure 1.17.14. Serial data logic switch timing
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Clock asynchronous serial I/O (UART) mode
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Table 1.17.5 and table 1.17.6 list the specifications of the UART mode. Figure 1.17.15
shows the UARTi transmit/receive mode register.
Table 1.17.5. Specifications of UART Mode (1)
Item
Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
Transfer data format
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock
•
When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
•
When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) :
fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2)
_______
_______
_______ _______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
-
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
_______ _______
- When CTS function selected, CTS input level = “L”
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
- Start bit detection
Interrupt request
generation timing
• When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
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Table 1.17.6. Specifications of UART Mode (2)
Item
Specification
_______ _______
Select function
• Separate CTS/RTS pins (UART0)
_______ _______
UART0 CTS and RTS pins each can be assigned to separate pins
• Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave micro-
computers
• Serial data logic switch (UART2)
This function is reversing logic value of transferring data. Start bit, parity bit
and stop bit are not reversed.
• TXD, RXD I/O polarity switch
This function is reversing TXD port output and RXD port input. All I/O data
level is reversed.
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Clock asynchronous serial I/O (UART) mode
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
CKDIR
STPS
PRY
Internal / external clock
select bit
0 : Internal clock
1 : External clock
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
SLEP
Parity enable bit
Sleep select bit
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
UART2 transmit / receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
When reset
0016
0
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
CKDIR
STPS
PRY
Internal / external clock
select bit
Must always be “0”
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
0 : No reverse
1 : Reverse
Note: Usually set to “0”.
Figure 1.17.15. UARTi transmit/receive mode register in UART mode
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Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.17.7 lists the functions of the input/output pins during UART mode. This table shows the pin
_______ _______
functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the
UARTi operation mode is selected to when transfer starts, the TXDi pin outputs a “H”. (If the N-channel
open-drain is selected, this pin is in floating state.)
Table 1.17.7. Input/output pin functions in UART mode
Pin name
TxDi
(P6 , P67, P70)
Function
Method of selection
Serial data output
3
RxDi
(P6 , P6
Serial data input
Port P6
bit 1 at address 03EF16)= “0”
(Can be used as an input port when performing transmission only)
2
, P6
6
and P7
1
direction register (bits 2 and 6 at address 03EE16,
2
6
, P7
1
)
)
CLKi
(P6 , P6
Programmable I/O port
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0”
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1”
1
5
, P7
2
Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = “0”
(Do not set external clock for UART2)
CTSi/RTSi
(P6 , P6 , P73)
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0”
CTS input
0
4
Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16,
bit 3 at address 03EF16) = “0”
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1”
RTS output
Programmable I/O port
________ _______
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1”
(when separate CTS/RTS pins function is not selected)
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Clock asynchronous serial I/O (UART) mode
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
“0”
“1”
“0”
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag(TI)
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
“L”
CTSi
Stopped pulsing because transmit enable bit = “0”
Start
bit
Parity Stop
bit bit
TxDi
ST
D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5
D7
P
D6
SP
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
Data is set in UARTi transmit buffer register
“0”
“1”
Transmit buffer
empty flag(TI)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop Stop
Start
bit
bit
bit
TxDi
ST
D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7 D8
ST D0 D1 D2 D3 D4 D5
D7 D8
SPSP
SP SP
D6
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32)
• Two stop bits.
• CTS function is disabled.
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
• Transmit interrupt cause select bit = “0”.
Figure 1.17.16. Typical transmit timings in UART mode (UART0, UART1)
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Tc
Transfer clock
“1”
Transmit enable
bit(TE)
Data is set in UART2 transmit buffer register
“0”
“1”
Note
Transmit buffer
empty flag(TI)
“0”
Transferred from UART2 transmit buffer register to UARTi transmit register
Stop
Parity
bit
Start
bit
bit
TxD2
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
D6
D6
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
• Transmit interrupt cause select bit = “1”.
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Figure 1.17.17. Typical transmit timings in UART mode (UART2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
“1”
Receive enable bit
“0”
Stop bit
Start bit
D1
D7
RxDi
D0
Sampled “L”
Receive data taken in
Transfer clock
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Receive
complete flag
“0”
“H”
“L”
RTSi
Receive interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Figure 1.17.18. Typical receive timing in UART mode
_______ _______
(a) Separate CTS/RTS pins function (UART0)
_______ _______
_______
Setting the CTS/RTS separate bit (bit 6 of address 03B016) to "1" inputs/outputs the CTS signal and
_______
_______
_______
_______ _______
RTS signal from different pins. Choose which to use, CTS or RTS, by use of the CTS/RTS function
select bit (bit 2 of address 03A416). This function is effective in UART0 only. With this function chosen,
_______ _______
_______ _______
the user cannot use the CTS/RTS function. Set "0" both to the CTS/RTS function select bit (bit 2 of
_______ _______
address 03AC16) and to the CTS/RTS disable bit (bit 4 of address 03AC16).
Microcomputer
IC
TXD
0
(P6
3
)
IN
R
XD0
(P6
2)
OUT
RTS0 (P6
CTS0 (P6
0
)
)
CTS
RTS
4
Note : The user cannot use CTS and RTS at the same time.
_______ _______
Figure 1.17.19. The separate CTS/RTS pins function usage
(b) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(c) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 1.17.20 shows the ex-
ample of timing for switching serial data logic.
• When LSB first, parity enabled, one stop bit
“H”
Transfer clock
“L”
“H”
TxD
2
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
(no reverse)
“L”
“H”
“L”
TxD
(reverse)
2
ST : Start bit
P : Even parity
SP : Stop bit
Figure 1.17.20. Timing for switching serial data logic
(d) TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
usual use.
(e) Bus collision detection function (UART2)
This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.17.21
shows the example of detection timing of a buss collision (in UART mode).
“H”
Transfer clock
“L”
“H”
TxD
RxD
2
2
ST
ST
SP
SP
“L”
“H”
“L”
Bus collision detection
interrupt request signal
“1”
“0”
Bus collision detection
interrupt request bit
“1”
“0”
ST : Start bit
SP : Stop bit
Figure 1.17.21. Detection timing of a bus collision (in UART mode)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(3) Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some
extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table
1.17.8 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface).
Table 1.17.8. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Item
Specification
Transfer data format
• Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”)
• One stop bit (bit 4 of address 037816 = “0”)
• With the direct format chosen
Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 037D16 = “0”).
Set transfer format to LSB (bit 7 of address 037C16 = “0”).
• With the inverse format chosen
Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 037D16 = “1”)
Set transfer format to MSB (bit 7 of address 037C16 = “1”)
Transfer clock
• With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32
(Do not set external clock)
_______
_______
Transmission / reception control • Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)
Other settings • The sleep mode select function is not available for UART2
•
Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”)
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 037D16) = “1”
- Transmit buffer empty flag (bit 1 of address 037D16) = “0”
Reception start condition
• To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 037D16) = “1”
- Detection of a start bit
Interrupt request
generation timing
• When transmitting
When data transmission from the UART2 transfer register is completed
(bit 4 of address 037D16 = “1”)
• When receiving
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
Error detection
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TXD2 pin by use of the parity error
signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the RXD2 pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLK2 pin.
Note 3: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
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Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
“0”
“1”
Note
Data is set in UART2 transmit buffer register
Transmit buffer
empty flag(TI)
“0”
Transferred from UART2 transmit buffer register to UART2 transmit register
Start
bit
Parity
bit
Stop
bit
TxD
2
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
P
D
6
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
D
6
SP
SP
SP
RxD
2
A “L” level returns from TxD
the occurrence of a parity error.
2 due to
Signal conductor level
(Note 1)
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
The level is
D
6
SP
ST
D
0
D1
D2
D3
D4
D5
D7
D
6
detected by the
interrupt routine.
The level is detected by the
interrupt routine.
“1”
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
fi : frequency of BRG2 count source (f
n : value set to BRG2
1, f8, f32)
• Transmit interrupt cause select bit = “1”.
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Tc
Transfer clock
“1”
Receive enable
bit (RE)
“0”
Parity
bit
Stop
bit
Start
bit
SP
RxD
2
ST
D
0
D
1
D
D
2
D
D
3
D
D
4
D
D
5
D
7
P
ST
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
P
D
D
6
SP
D6
TxD
2
A “L” level returns from TxD
the occurrence of a parity error.
2 due to
Signal conductor level
(Note 1)
SP
ST
D
0
D
1
2
3
4
5
D
7
P
D
0
D
1
D
2
D
3
D
4
D
5
D7
6
SP
D6
“1”
Receive complete
flag (RI)
“0”
Read to receive buffer
Read to receive buffer
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
n : value set to BRG2
1, f8, f32)
• Transmit interrupt cause select bit = “0”
Figure 1.17.22. Typical transmit/receive timing in UART mode (compliant with the SIM interface)
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Clock asynchronous serial I/O (UART) mode
(a) Function for outputting a parity error signal
With the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you can output an “L”
level from the TXD2 pin when a parity error is detected. In step with this function, the generation timing
of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure
1.17.23 shows the output timing of the parity error signal.
• LSB first
“H”
Transfer
“L”
clock
“H”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RxD
2
“L”
“H”
“L”
Hi-Z
TxD
2
“1”
“0”
Receive
complete flag
ST : Start bit
P : Even Parity
SP : Stop bit
Figure 1.17.23. Output timing of the parity error signal
(b) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D0 data is output from TXD2. If you choose the inverse format, D7 data is inverted
and output from TXD2.
Figure 1.17.24 shows the SIM interface format.
Transfer
clcck
TxD2
(direct)
D0
D7
D1
D6
D2
D5
D3
D4
D4
D3
D5
D2
D6
D1
D7
D0
P
P
TxD2
(inverse)
P : Even parity
Figure 1.17.24. SIM interface format
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Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.17.25 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-
up.
Microcomputer
SIM card
TxD
2
2
RxD
Figure 1.17.25. Connecting the SIM interface
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A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling
amplifier. Pins P10 to P10 , P9 , and P9 also function as the analog signal input pins. The direction registers of
0
7
5
6
these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be
used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D
converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power
dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF
.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low
8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low
8 bits are stored in the even addresses.
Table 1.18.1 shows the performance of the A-D converter. Figure 1.18.1 shows the block diagram of the A-
D converter, and Figures 1.18.2 and 1.18.3 show the A-D converter-related registers.
Table 1.18.1. Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock φAD (Note 2) VCC = 5V
fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
VCC = 3V
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5V
• Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
AN0 to AN7 input : ±3LSB
ANEX0 and ANEX1 input (including mode in which external
operation amp is connected) : ±7LSB
• Without sample and hold function (8-bit resolution)
±2LSB
VCC = 3V
Operating modes
Analog input pins
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is “1” and the
___________
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 AD cycles 10-bit resolution: 59
• With sample and hold function
8-bit resolution: 28 AD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the AD frequency to 250kHz min.
With the sample and hold function, set the AD frequency to 1MHz min.
φ
,
φAD cycles
φ
, 10-bit resolution: 33 φAD cycles
φ
φ
115
Mitsubishi microcomputers
M16C / 61 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CKS1=1
CKS1=0
CKS0=1
CKS0=0
φ
AD
fAD
1/2
1/2
A-D conversion rate
selection
VREF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register
A-D control register 1 (address 03D716)
A-D control register 0 (address 03D616)
Addresses
(03C116, 03C016
)
)
)
A-D register 0(16)
(03C316, 03C216
(03C516, 03C416
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
Vref
VIN
(03C716, 03C616
(03C916, 03C816
(03CB16, 03CA16
(03CD16, 03CC16
(03CF16, 03CE16
)
Decoder
)
A-D register 4(16)
)
A-D register 5(16)
A-D register 6(16)
Comparator
)
)
A-D register 7(16)
Data bus high-order
Data bus low-order
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
OPA1,OPA0=0,0
OPA1, OPA0
0
0
1
1
0 : Normal operation
1 : ANEX0
0 : ANEX1
1 : External op-amp mode
OPA1,OPA0=1,1
OPA0=1
OPA1=1
ANEX0
ANEX1
OPA1,OPA0=0,1
Figure 1.18.1. Block diagram of A-D converter
116
Mitsubishi microcomputers
M16C / 61 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 0 (Note)
Symbol
ADCON0
Address
03D616
When reset
b7 b6 b5 b4 b3 b2 b1 b0
00000XXX
2
R W
Bit symbol
Bit name
Function
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
b2 b1 b0
CH0
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
b4 b3
0
1
2
3
4
5
6
7
Analog input pin select bit
CH1
CH2
MD0
MD1
A-D operation mode
select bit 0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
ADST
CKS0
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
Bit symbol
Bit name
Function
R W
When single sweep and repeat sweep
A-D sweep pin select bit
mode 0 are selected
b1 b0
SCAN0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
When repeat sweep mode 1 is selected
b1 b0
SCAN1
MD2
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pin)
, AN
1
(2 pins)
to AN
to AN
2
3
(3 pins)
(4 pins)
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
BITS
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
0 : Vref not connected
1 : Vref connected
VCUT
OPA0
OPA1
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Figure 1.18.2. A-D converter-related registers (1)
117
Mitsubishi microcomputers
M16C / 61 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 2 (Note)
Symbol
ADCON2
Address
03D416
When reset
0000XXX0
b7 b6 b5 b4 b3 b2 b1 b0
2
0
0 0
Bit symbol
SMP
Bit name
Function
R W
0 : Without sample and hold
1 : With sample and hold
A-D conversion method
select bit
Always set to “0”
Reserved bit
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out
to be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
ADi(i=0 to 7)
Address
When reset
A-D register i
(b15)
b7
03C016 to 03CF16 Indeterminate
(b8)
b0 b7
b0
Function
R W
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be “0”.
Figure 1.18.3. A-D converter-related registers (2)
118
Mitsubishi microcomputers
M16C / 61 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-
sion. Table 1.18.2 shows the specifications of one-shot mode. Figure 1.18.4 shows the A-D control regis-
ter in one-shot mode.
Table 1.18.2. One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Writing “1” to A-D conversion start flag
Start condition
Stop condition
•
End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
One of AN0 to AN7, as selected
Read A-D register corresponding to selected pin
Reading of result of A-D converter
A-D control register 0 (Note 1)
Symbol
ADCON0
Address
03D616
When reset
b7 b6 b5 b4 b3 b2 b1 b0
00000XXX
2
0
0
Bit symbol
Bit name
Function
R W
b2 b1 b0
Analog input pin select
bit
CH0
CH1
CH2
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
(Note 2)
(Note 2)
b4 b3
MD0
MD1
A-D operation mode
select bit 0
0 0 : One-shot mode
0 : Software trigger
1 : ADTRG trigger
Trigger select bit
TRG
ADST
CKS0
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
0: fAD/4 is selected
1: fAD/2 is selected
Frequency select bit 0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
R W
Invalid in one-shot mode
SCAN0
SCAN1
select bit
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
MD2
BITS
CKS1
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Frequency select bit1
Vref connect bit
1 : Vref connected
VCUT
OPA0
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Figure 1.18.4. A-D conversion register in one-shot mode
119
Mitsubishi microcomputers
M16C / 61 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Repeat mode
I
n repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
Table 1.18.3 shows the specifications of repeat mode. Figure 1.18.5 shows the A-D control register in
repeat mode.
Table 1.18.3. Repeat mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Writing “1” to A-D conversion start flag
Star condition
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
One of AN0 to AN7, as selected
Read A-D register corresponding to selected pin
Reading of result of A-D converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
0
1
Bit symbol
Bit name
Function
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
R W
b2 b1 b0
Analog input pin
select bit
CH0
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
CH1
CH2
(Note 2)
(Note 2)
b4 b3
MD0
MD1
A-D operation mode
select bit 0
0 1 : Repeat mode
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
Frequency select bit 0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
R W
Invalid in repeat mode
SCAN0
SCAN1
select bit
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
BITS
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
Frequency select bit 1
Vref connect bit
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Figure 1.18.5. A-D conversion register in repeat mode
120
Mitsubishi microcomputers
M16C / 61 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Single sweep mode
I
n single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 1.18.4 shows the specifications of single sweep mode. Figure 1.18.6 shows the A-D
control register in single sweep mode.
Table 1.18.4. Single sweep mode specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Writing “1” to A-D converter start flag
Start condition
Stop condition
• End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX
0
1
2
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in single sweep mode
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 0 : Single sweep mode
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
Function
R W
A-D sweep pin select bit When single sweep and repeat sweep mode 0
SCAN0
SCAN1
are selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
BITS
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Figure 1.18.6. A-D conversion register in single sweep mode
121
Mitsubishi microcomputers
M16C / 61 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 1.18.5 shows the specifications of repeat sweep mode 0. Figure 1.18.7 shows the
A-D control register in repeat sweep mode 0.
Table 1.18.5. Repeat sweep mode 0 specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Writing “1” to A-D conversion start flag
Start condition
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
1
1
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in repeat sweep mode 0
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 0
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
SCAN0
Bit name
Function
R W
A-D sweep pin select bit When single sweep and repeat sweep mode 0
are selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
BITS
CKS1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Frequency select bit 1
Vref connect bit
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither “01” nor “10” can be selected with the external op-amp connection mode bit.
Figure 1.18.7. A-D conversion register in repeat sweep mode 0
122
Mitsubishi microcomputers
M16C / 61 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected
using the A-D sweep pin select bit. Table 1.18.6 shows the specifications of repeat sweep mode 1. Figure
1.18.8 shows the A-D control register in repeat sweep mode 1.
Table 1.18.6. Repeat sweep mode 1 specifications
Item
Specification
Function
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected AN0
AN1
AN0
AN2
AN0
AN3, etc
Start condition
Stop condition
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Read A-D register corresponding to selected pin (at any time)
Reading of result of A-D converter
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in repeat sweep mode 1
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
0 : fAD/4 is selected
1 : fAD/2 is selected
Frequency select bit 0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
1
Bit symbol
SCAN0
Bit name
Function
R W
A-D sweep pin select bit When repeat sweep mode 1 is selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pin)
, AN (2 pins)
1
SCAN1
to AN
to AN
2
3
(3 pins)
(4 pins)
A-D operation mode
select bit 1
1 : Repeat sweep mode 1
MD2
BITS
CKS1
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Figure 1.18.8. A-D conversion register in repeat sweep mode 1
123
Mitsubishi microcomputers
M16C / 61 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 AD cycle is
achieved with 8-bit resolution and 33 AD with 10-bit resolution. Sample and hold can be selected in all
φ
φ
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and
hold is to be used.
(b) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is
converted from analog to digital. The result of conversion is stored in A-D register 0.
When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is
converted from analog to digital. The result of conversion is stored in A-D register 1.
(c) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can
be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7 is
output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the
corresponding A-D register. The speed of A-D conversion depends on the response of the external op-
eration amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.18.9 is an example of how to
connect the pins in external operation amp mode.
Resistor ladder
Successive conversion register
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
Analog
input
AN7
ANEX0
ANEX1
Comparator
External op-amp
Figure 1.18.9. Example of external op-amp connection mode
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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of
this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the
target port to output mode if D-A conversion is to be performed.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 1.19.1 lists the performance of the D-A converter. Figure 1.19.1 shows the block diagram of the D-A
converter. Figure 1.19.2 shows the D-A control register. Figure 1.19.3 shows the D-A converter equivalent
circuit.
Table 1.19.1. Performance of D-A converter
Item
Conversion method
Resolution
Performance
R-2R method
8 bits
Analog output pin
2 channels
Data bus low-order bits
D-A register0 (8)
(Address 03D816
)
D-A0 output enable bit
P9 /DA
3
0
R-2R resistor ladder
D-A register1 (8)
(Address 03DA16
D-A1 output enable bit
P9 /DA
)
4
1
R-2R resistor ladder
Figure 1.19.1. Block diagram of D-A converter
125
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DACON
Address
03DC16
When reset
0016
Bit symbol
DA0E
Bit name
Function
R W
0 : Output disabled
1 : Output enabled
D-A0 output enable bit
D-A1 output enable bit
0 : Output disabled
1 : Output enabled
DA1E
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
D-A register
b7
Symbol
DAi (i = 0,1)
Address
03D816, 03DA16
When reset
Indeterminate
b0
Function
R W
Output value of D-A conversion
Figure 1.19.2. D-A control register
D-A0 output enable bit
"0"
R
R
R
R
R
R
R
2R
DA0
"1"
2R
MSB
2R
2R
2R
2R
2R
2R
2R
LSB
D-A0 register0
AVSS
REF
V
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16
.
Note 2: The same circuit as this is also used for D-A1.
Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to
0016 so that no current flows in the resistors Rs and 2Rs.
Figure 1.19.3. D-A converter equivalent circuit
126
Mitsubishi microcomputers
M16C / 61 Group
CRC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom-
16
12
5
puter uses a generator polynomial of CRC_CCITT (X + X + X + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC
code is set in a CRC data register each time one byte of data is transferred to a CRC input register after
writing an initial value into the CRC data register. Generation of CRC code for one byte of data is com-
pleted in two machine cycles.
Figure 1.20.1 shows the block diagram of the CRC circuit. Figure 1.20.2 shows the CRC-related registers.
Figure 1.20.3 shows the calculation example using the CRC calculation circuit
Data bus high-order bits
Data bus low-order bits
Eight low-order bits
Eight high-order bits
CRC data register (16)
(Addresses 03BD16, 03BC16
)
CRC code generating circuit
16
12
5
x
+ x + x + 1
CRC input register (8) (Address 03BE16
)
Figure 1.20.1. Block diagram of CRC circuit
CRC data register
(b15)
b7
(b8)
b0 b7
Symbol
CRCD
Address
03BD16, 03BC16
When reset
Indeterminate
b0
Values that
can be set
Function
R W
CRC calculation result output register
000016 to FFFF16
CRC input register
b7
b0
Symbo
CRCIN
Address
03BE16
When reset
Indeterminate
Values that
can be set
Function
R W
Data input register
0016 to FF16
Figure 1.20.2. CRC-related registers
127
Mitsubishi microcomputers
M16C / 61 Group
CRC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
b15
b0
b0
CRC data register CRCD
(1) Setting 000016
(2) Setting 0116
[03BD16, 03BC16]
b7
CRC input register
2 cycles
CRCIN
[03BE16]
After CRC calculation is complete
b15
b0
CRC data register
Stores CRC code
CRCD
[03BD16, 03BC16]
118916
The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
16
12
5
16
(X + X + X + 1), becomes the remainder resulting from dividing (1000 0000) X by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
LSB
MSB
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
1 0001 0000 0010 0001
1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
LSB
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
MSB
9
8
1
1
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
b7
b0
CRC input register
CRCIN
[03BE16]
(3) Setting 2316
After CRC calculation is complete
b15
b0
CRC data register
Stores CRC code
CRCD
[03BD16, 03BC16]
0A4116
Figure 1.20.3. Calculation example using the CRC calculation circuit
128
Mitsubishi microcomputers
M16C / 61 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is
an input-only port and has no built-in pull-up resistance.
Figures 1.21.1 to 1.21.4 show the programmable I/O ports. Figure 1.21.5 shows the I/O pins.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-
verter), they function as outputs regardless of the contents of the direction registers. When pins are to be
used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.21.6 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
Note: There is no direction register bit for P85.
(2) Port registers
Figure 1.21.7 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.21.8 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
However, in memory expansion mode and microprocessor mode, the pull-up control register of P0 to P5
is invalid.
129
Mitsubishi microcomputers
M16C / 61 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up selection
Direction register
P0
P2
P4
P5
0
0
0
6
to P0
to P2
to P4
7, P1
7, P3
7, P5
0
0
0
to P1
to P3
to P5
7,
7,
4,
Data bus
Port latch
(Note)
Pull-up selection
P5
P8
P9
5
1
7
, P6
2
, P6
6
, P7
5
, P7
7
,
,
Direction register
to P8
4
, P9
0
to P9
2
Data bus
Port latch
(Note)
Input to respective peripheral functions
Pull-up selection
Direction register
P63, P6
7
“1”
Output
Data bus
Port latch
(Note)
Pull-up selection
P5
7
, P6
0
, P6
1
, P6
4
, P65,
Direction register
P72
to P7
4
, P76, P80
“1”
Output
Data bus
Port latch
(Note)
Input to respective peripheral functions
Note :
symbolizes a parasitic diode.
Do not apply a voltage higher than VCC to each port.
Figure 1.21.1. Programmable I/O ports (1)
130
Mitsubishi microcomputers
M16C / 61 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up selection
Direction register
P82 to P84
Port latch
Data bus
(Note 1)
Input to respective peripheral functions
Direction register
“1”
P7
0
output
Port latch
Data bus
(Note 2)
Direction register
Port latch
P7
1
Data bus
(Note 2)
Input to respective peripheral functions
P85
Data bus
(Note 1)
NMI interrupt input
Note 1 :
symbolizes a parasitic diode.
Do not apply a voltage higher than VCC to each port.
Note 2 :
symbolizes a parasitic diode.
Figure 1.21.2. Programmable I/O ports (2)
131
Mitsubishi microcomputers
M16C / 61 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up selection
Direction register
P95, P96, P100 to P103
(inside dotted-line not included)
P104 to P107
(inside dotted-line included)
Data bus
Port latch
(Note)
Analog input
Pull-up selection
D-A output enabled
Direction register
P93, P94
Data bus
Port latch
(Note)
Analog input
D-A output enabled
Note :
symbolizes a parasitic diode.
Do not apply a voltage higher than VCC to each port.
Figure 1.21.3. Programmable I/O ports (3)
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Mitsubishi microcomputers
M16C / 61 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up selection
Direction register
P87
Data bus
Port latch
(Note)
fc
Input to respective peripheral functions
Pull-up selection
Rf
Rd
Direction register
“1”
P86
output
Data bus
Port latch
(Note)
Note :
symbolizes a parasitic diode.
Do not apply a voltage higher than VCC to each port.
Figure 1.21.4. Programmable I/O ports (4)
(Note 2)
(Note 1)
BYTE
BYTE signal input
(Note 2)
(Note 1)
CNVSS
CNVSS signal input
RESET
RESET signal input
(Note 1)
Note 1 :
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each pin.
Note 2 : A parasitic diode on the VCC side is added to the mask ROM version.
Do not apply a voltage higher than Vcc to each pin.
Figure 1.21.5. I/O pins
133
Mitsubishi microcomputers
M16C / 61 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi direction register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PDi (i = 0 to 10, except 8)
Address
When reset
0016
03E216, 03E316, 03E616, 03E716, 03EA16
03EB16, 03EE16, 03EF16, 03F316, 03F616
Bit symbol
PDi_0
Bit name
direction register
Function
R W
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
0 : Input mode
(Functions as an input port)
1 : Output mode
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
1
direction register
direction register
direction register
direction register
direction register
direction register
2
(Functions as an output port)
3
(i = 0 to 10 except 8)
4
Port Pi
Port Pi
Port Pi
5
6
7
PDi_7
direction register
Note: Set bit 2 of protect register (address 000A16) to “1” before rewriting to
the port P9 direction register.
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address
03F216
When reset
00X00000
2
Bit symbol
PD8_0
Bit name
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
R W
Port P8
Port P8
Port P8
0
direction register
direction register
direction register
direction register
direction register
PD8_1
PD8_2
PD8_3
PD8_4
1
2
(Functions as an output port)
Port P8
Port P8
3
4
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
0 : Input mode
(Functions as an input port)
1 : Output mode
PD8_6
PD8_7
Port P8
Port P8
6
7
direction register
direction register
(Functions as an output port)
Figure 1.21.6. Direction register
134
Mitsubishi microcomputers
M16C / 61 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi register
Symbol
Pi (i = 0 to 10, except 8)
Address
When reset
03E016, 03E116, 03E416, 03E516, 03E816 Indeterminate
03E916, 03EC16, 03ED16, 03F116, 03F416 Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Pi_0
Bit name
Function
R W
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
1
2
3
4
register
register
register
register
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
Pi_1
Pi_2
Pi_3
1 : “H” level data (Note)
Pi_4
(i = 0 to 10 except 8)
Pi_5
Port Pi
Port Pi
Port Pi
5
6
7
register
register
register
Pi_6
Pi_7
Note : Since P70 and P71 are N-channel open drain ports, the data is high-impedance.
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P8
Address
03F016
When reset
Indeterminate
Bit symbol
P8_0
Bit name
Function
R W
Port P80 register
Port P81 register
Port P82 register
Port P83 register
Port P84 register
Port P85 register
Port P86 register
Port P87 register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P85)
0 : “L” level data
1 : “H” level data
P8_1
P8_2
P8_3
P8_4
P8_5
P8_6
P8_7
Figure 1.21.7. Port register
135
Mitsubishi microcomputers
M16C / 61 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FC16
When reset
0016
Bit symbol
PU00
Bit name
Function
R W
P0
P0
P1
P1
P2
P2
P3
P3
0
to P0
to P0
to P1
to P1
to P2
to P2
to P3
to P3
3
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU01
PU02
PU03
PU04
PU05
PU06
PU07
4
0
4
0
4
0
4
7
3
7
3
7
3
7
1 : Pulled high
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FD16
When reset
0016
Bit symbol
PU10
Bit name
Function
R W
P4
0
4
to P4
3
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU11
P4
to P4
7
pull-up
PU12
PU13
P5
P5
0
4
to P5
to P5
3
7
pull-up
pull-up
1 : Pulled high
PU14
PU15
PU16
P60
P64
P70
to P6
to P6
to P7
3
7
3
pull-up
pull-up
pull-up (Note)
PU17
P7
4
to P7
7
pull-up
Note: Since P7
0
and P71 are N-channel open drain ports, pull-up is not available for them.
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03FE16
When reset
0016
Bit symbol
PU20
Bit name
Function
R W
P8
0
4
to P8
3
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU21
P8
to P8
7
pull-up
5)
(Except P8
P9 to P9
P9 to P9
P10
P10
1 : Pulled high
PU22
0
3
pull-up
PU23
PU24
4
7 pull-up
0
to P10
3
pull-up
pull-up
PU25
4
to P10
7
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Figure 1.21.8. Pull-up control register
136
Mitsubishi microcomputers
M16C / 61 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.21.1. Example connection of unused pins in single-chip mode
Pin name
Connection
Ports P0 to P10
After setting for input mode, connect every pin to VSS via a resistor; or
after setting for output mode, leave these pins open.
(excluding P8
5)
XOUT (Note)
Open
Connect via resistor to VCC (pull-up)
Connect to VCC
NMI
AVCC
AVSS, VREF, BYTE
CNVSS
Connect to VSS
Connect via resistor to VSS (pull-down)
Note: With external clock input to XIN pin.
Table 1.21.2. Example connection of unused pins in memory expansion mode and microprocessor mode
Pin name
Connection
Ports P6 to P10
(excluding P85)
After setting for input mode, connect every pin to VSS or VCC via a resistor; or
after setting for output mode, leave these pins open.
Open
BHE, ALE, HLDA,
OUT(Note), BCLK
X
Connect via resistor to VCC (pull-up)
Connect to VCC
HOLD, RDY, NMI
AVCC
AVSS, VREF
CNVSS
Connect to VSS
Connect via resistor to VSS (pull-down) in the memory expansion mode
Connect via resistor to VCC (pull-up) in the microprocessor mode
Note: With external clock input to XIN pin.
Microcomputer
Microcomputer
Port P6 to P10 (except for P85)
Port P0 to P10 (except for P85)
(Input mode)
(Input mode)
·
·
·
·
·
·
·
·
·
·
·
·
(Input mode)
(Input mode)
(Output mode)
(Output mode)
Open
Open
NMI
NMI
BHE
HLDA
ALE
XOUT
BCLK
XOUT
Open
VCC
Open
VCC
AVCC
0.47µs
HOLD
RDY
BYTE
AVSS
0.47µs
CNVSS(microprocessor mode)
VREF
AVCC
AVSS
CNVSS
VREF
CNVSS(memory expansion mode)
VSS
VSS
In single-chip mode
In memory expansion mode or
in microprocessor mode
Figure 1.21.9. Example connection of unused pins
137
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Usage Precaution
Timer A (timer mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16”. Reading the
timer Ai register after setting a value in the timer Ai register with a count halted but before the counter
starts counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16” by underflow
or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with
a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”.
(2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0”
after the above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0”
after the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance,
the level does not change, and the timer Ai interrupt request bit does not becomes “1”.
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the
value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the
timer Bi register after setting a value in the timer Bi register with a count halted but before the counter
starts counting gets a proper value.
138
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit
0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-
D conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the
WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction
queue are prefetched and then the program stops. So put at least four NOPs in succession either to
the WAIT instruction or to the instruction that sets the every-clock stop bit to 1.
Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number
and interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an
interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to
set a value in the stack pointer before accepting an interrupt.
_______
When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning
_______
the first instruction immediately after reset, generating any interrupts including the NMI interrupt is
prohibited.
139
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
_______
(3) The NMI interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a
resistor (pull-up) if unused. Be sure to work on it.
_______
• Do not get either into stop mode or into wait mode with the NMI pin set to “L”.
(4) External interrupt
________
________
• When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to
"1". After changing the polarity, set the interrupt request bit to "0".
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt
request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt
control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP
NOP
FSET
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
I
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0
; Dummy read.
; Enable interrupts.
FSET
I
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
; Disable interrupts.
FCLR
I
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled,
the interrupt request bit is not set sometimes even if the interrupt request for that register has
been generated. This will depend on the instruction. If this creates problems, use the below
instructions to change the register.
Instructions : AND, OR, BCLR, BSET
140
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
External ROM version
The external ROM version is operated only in microprocessor mode, so be sure to perform the following:
• Connect CNVSS pin to VCC.
• Fix the processor mode bit to “112”
Built-in PROM version
(1) All built-in PROM versions
High voltage is required to program to the built-in PROM. Be careful not to apply excessive voltage.
Be especially careful during power-on.
(2) One Time PROM version
One Time PROM versions shipped in blank (M30612E4FP, M30612E4GP, M30610ECFP,
M30610ECGP), of which built-in PROMs are programmed by users, are also provided. For these
microcomputers, a programming test and screening are not performed in the assembly process and
the following processes. Therefore ROM write defectiveness occurs around 5 %. To improve their
reliability after programming, we recommend to program and test as flow shown in Figure 1.22.1
before use.
Programming with PROM programmer
Screening (Note)
(Leave at 150˚C for 40 hours)
Verify test PROM programmer
Function check in target device
Note: Never expose to 150˚C exceeding 100 hours.
Figure 1.22.1. Programming and test flow for One Time PROM version
(3) EPROM version
• Cover the transparent glass window with a shield or others during the read mode because exposing
to sun light or fluorescent lamp can cause erasing the information.
A shield to cover the transparent window is available from Mitsubishi Electric Corp. Be careful that
the shield does not touch the EPROM lead pins.
• Clean the transparent glass before erasing. Fingers’ flat and paste disturb the passage of ultraviolet
rays and may affect badly the erasure capability.
• The EPROM version is a tool only for program development (for evaluation), and do not use it for the
mass product run.
141
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Items to be submitted when ordering masked ROM version
Please submit the following when ordering masked ROM products:
(1) Mask ROM confirmation form
(2) Mark specification sheet
(3) ROM data : EPROMs or floppy disks
*: In the case of EPROMs, there sets of EPROMs are required per pattern.
*: In the case of floppy disks, 3.5-inch double-sided high-density disk (IBM format) is required per pattern.
142
Mitsubishi microcomputers
M16C / 61 Group
Electrical characteristics
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.24.1. Absolute maximum ratings
Symbol
Vcc
Parameter
Condition
CC = AVCC
Rated value
–0.3 to 6.5
Unit
V
Supply voltage
V
(Note 3)
(Note 3)
AVcc
–0.3 to 6.5
V
Analog supply voltage
V
CC = AVCC
V
I
P0
P3
0
0
to P0
to P3
7
, P1
, P4
0
0
to P17, P2
to P47, P5
0
0
to P2
to P5
7
,
,
Input voltage
7
7
P6
P9
RESET, VREF, XIN
P7 , P7 , CNVss, BYTE
0
to P6
to P9
7
, P7
, P10
2
to P77, P8
0 to P107,
0 to P87,
V
V
–0.3 to Vcc+0.3
–0.3 to 6.5
0
7
VI
(Note 1, Note 3)
Input voltage
0
1
Output voltage P0
0
to P0
to P3
7
, P1
, P4
0
0
to P17, P2
to P47, P5
0
to P2
to P57,
to P84,
7,
V
O
O
P30
7
0
V
P6
P8
0
6
to P6
7
, P7
2
to P77, P8
0
–0.3 to Vcc+0.3
,P8
7, P9
0
to P97, P10
0 to P107,
X
OUT
–0.3 to 6.5
300
(Note 3)
(Note 2)
V
mW
C
V
Output voltage
P7
0
, P7
1
P
T
T
d
Power dissipation
Ta=25 C
opr
stg
Operating ambient temperature
Storage temperature
–20 to 85 / –40 to 85
–65 to 150
C
Note 1: When writing to EPROM ,only CNVSS is –0.3 to 13 (V) .
Note 2: Specify a product of –40 to 85°C to use it.
Note 3: –0.3V to 6.5V for M30610M8A, M30610MAA, M30610MCA, M30612M4A, M30612M8A, M30612MAA, M30612MCA,
M30610SA and M30612SA.
Otherwise, –0.3V to 7.0V is used.
143
Mitsubishi microcomputers
M16C / 61 Group
Electrical characteristics (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.24.2. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = –20 to
o
o
85 C / –40 to 85 C (Note 3) unless otherwise specified)
Standard
Unit
Symbol
Parameter
Min
2.7
Typ.
5.0
Vcc
0
Max.
5.5
Supply voltage
Vcc
V
V
V
V
AVcc
Vss
Analog supply voltage
Supply voltage
AVss
Analog supply voltage
0
P3
P7
1
2
to P3
to P7
7
, P4
, P8
0
0
to P4
to P8
7
, P5
, P9
0
0
to P57, P6
to P97, P10
0
to P67,
0 to P107,
V
IH
HIGH input voltage
7
7
0.8Vcc
Vcc
V
X
IN, RESET, CNVSS, BYTE
P7 , P7
P0 to P0
0
1
0.8Vcc
0.8Vcc
6.5
V
V
0
7
, P1
0
to P1
7, P2
0
to P2
7
, P3
0
0
Vcc
(during single-chip mode)
P00 to P07, P10 to P17, P2
0
to P2
7
, P3
(data input function during memory expansion
and microprocessor modes)
0.5Vcc
Vcc
V
P3
P7
IN, RESET, CNVSS, BYTE
1
to P3
to P7
7
, P4
, P8
0
to P4
to P8
7
, P5
, P9
0
to P57, P6
0
to P6
0
7,
, P10 to P107,
VIL
LOW input voltage
0
0
0
0.2Vcc
0.2Vcc
0.16Vcc
V
V
V
0
7
0
7
0
to P9
7
X
P0
0
to P0
7
, P1
0
to P1
7, P2
(during single-chip mode)
0
to P2
7, P30
P00 to P07, P10 to P17, P2
0
to P2
7
, P3
0
(data input function during memory expansion
and microprocessor modes)
P00 to P07, P10 to P17, P20 to P2
7
,P3
,P7
to P10
0
to P3
to P77,
7,
HIGH peak output
current
IOH (peak)
-10.0
mA
P4 to P4 , P5 to P5 , P6 to P6
to P84,P86,P87,P9 to P97,P10
to P0 , P1 to P1 , P2 to P2 ,P3
to P4 , P5 to P5 , P6 to P6 ,P7
to P84,P86,P87,P9 to P97,P10 to P10
to P0 , P1 to P1 , P2 to P2 ,P3
to P4 , P5 to P5 , P6 to P6 ,P7
to P84,P86,P87,P9 to P97,P10 to P10
to P0 , P1 to P1 , P2 to P2 ,P3
to P4 , P5 to P5 , P6 to P6 ,P7
to P84,P86,P87,P9 to P97,P10 to P10
0
7
0
7
0
7
2
P8
0
0
0
0
7
P0
7
0
7
0
7
0
to P37,
IOH (avg)
HIGH average output
current
P4
P8
P0
P4
P8
P0
P4
P8
0
7
0
7
0
7
2 to P77,
-5.0
mA
mA
0
0
0
7
0
7
0
7
0
7
0
to P37,
LOW peak output
current
IOL (peak)
10.0
0
0
7
0
7
0
7
0
to P7
7
,
0
0
7
0
7
0
7
0
7
0
to P37
,
IOL (avg)
LOW average output
current
0
0
7
0
7
0
7
0 to P77,
5.0
10
mA
0
0
7
VCC =4.0V to 5.5V
VCC =2.7V to 4.0V
VCC =4.0V to 5.5V
0
0
0
0
MHz
MHz
MHz
MHz
kHz
f (XIN
)
Main clock input oscillation
frequency
No wait
5 X VCC
–10.000
10
With wait
2.31 X VCC
+0.760
V
CC =2.7V to 4.0V
32.768
50
f (XcIN
)
Subclock oscillation frequency
Note 1: The mean output current is the mean value within 100ms.
Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1,
P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be
80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max.
Note 3: Specify a product of –40 to 85°C to use it.
Note 4: The relationship between main clock input frequency and power supply voltage is as below.
Main clock input oscillation frequency
(No wait)
Main clock input oscillation frequency
(With wait)
10.0
10.0
7.0
5 X VCC –10.000MH
Z
2.31 X VCC –0.760MHZ
3.5
0.0
0.0
2.7
4.2
5.5
2.7
4.2
5.5
Supply voltage[V]
Supply voltage[V]
(BCLK: no division)
(BCLK: no division)
144
Mitsubishi microcomputers
M16C / 61 Group
Electrical characteristics (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Table 1.24.3. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25 C, f(XIN) =
10MH
Z
unless otherwise specified)
Standard
Parameter
Unit
Symbol
Measuring condition
Typ. Max.
Min
HIGH output
voltage
P0
P3
P6
0
0
0
to P0
to P3
to P6
7
7
7
, P1
, P4
, P7
0
0
2
to P1
to P4
to P7
7
7
7
, P2
, P5
, P8
0
0
0
to P2
to P5
to P8
7
7
4
,
,
,
V
OH
OH
OH
I
OH=-5mA
3.0
V
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
P00
P30
P60
to P0
to P3
to P6
7, P1
7, P4
7, P7
0
0
2
to P1
to P4
to P7
7
7
7
, P2
, P5
, P8
0
to P2
to P5
to P8
7
,
,
,
HIGH output
voltage
0
0
7
4
V
V
IOH=-200µA
4.7
V
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
HIGHPOWER
I
I
OH=-1mA
3.0
3.0
HIGH output
voltage
X
OUT
V
V
LOWPOWER
OH=-0.5mA
HIGH output
voltage
3.0
1.6
With no load applied
With no load applied
HIGHPOWER
LOWPOWER
X
COUT
LOW output
voltage
P0
0
to P0
to P3
to P6
7
, P1
0
0
to P1
to P4
to P7
7
7
, P2
, P5
, P8
0
0
to P2
to P5
to P8
7
7
,
,
,
P30
7, P4
I
OL=5mA
V
V
OL
OL
2.0
V
V
P6
0
7, P7
0
7
0
4
P86
, P8
7, P9
0
to P9
7
, P10
0
to P10
to P2
7
P00
to P0
7
, P1
0
to P1
7
, P2
0
7
,
LOW output
voltage
P3
P6
0
0
to P3
to P6
7
7
, P4
, P7
0
0
to P4
to P7
7
, P5
, P8
0
0
to P5
to P8
7
,
,
IOL=200µA
0.45
7
4
P86
, P8
7, P9
0
to P9
7
, P10
0
to P107
I
OL=1mA
2.0
HIGHPOWER
LOWPOWER
LOW output
voltage
X
OUT
V
V
I
OL=0.5mA
2.0
V
OL
0
0
With no load applied
With no load applied
HIGHPOWER
LOWPOWER
LOW output
voltage
X
COUT
HOLD, RDY, TA0IN to TA4IN
TB0IN to TB2IN, INT to INT
ADTRG, CTS to CTS2, CLK
CLK
KI to KI
,
Hysteresis
0
2
,
0
0
to
V
T+-
V
T-
0.2
0.2
0.8
V
2
,TA2OUT to TA4OUT,NMI,
0
3, RxD0 to RxD2
Hysteresis
V
T+-VT-
RESET
1.8
5.0
V
P0
P3
P6
P9
0
0
0
0
to P0
to P3
to P6
to P9
7
7
7
7
, P1
, P4
, P7
0
0
0
to P1
to P4
to P7
7
7
7
, P2
, P5
, P8
0
0
0
to P2
to P5
to P8
7,
HIGH input
current
7
,
,
µA
IIH
7
V
V
I
=5V
=0V
, P100 to P107,
X
IN, RESET, CNVss, BYTE
P00
P30
P60
P90
to P0
to P3
to P6
to P9
7
7
7
7
, P1
, P4
, P7
0
0
0
to P1
to P4
to P7
7
7
7
, P2
, P5
, P8
0
0
0
to P2
to P5
to P8
7
,
,
,
LOW input
current
7
7
µA
IIL
I
-5.0
, P100 to P107,
X
IN, RESET, CNVss, BYTE
RPULLUP
Pull-up
resistance
P00
P30
P60
P86
to P0
to P3
to P6
7
7
7
, P1
, P4
, P7
0
0
2
to P1
to P4
to P7
7
7
7
, P2
, P5
, P8
0
0
0
to P2
to P5
to P8
7
,
7
4
,
,
kΩ
V
I
=0V
30.0
2.0
50.0 167.0
, P8
7, P9
0
to P9
7
, P10
0
to P10
7
MΩ
RfXIN
Feedback resistance
Feedback resistance
X
X
IN
CIN
1.0
6.0
MΩ
RfXCIN
RAM retention voltage
Power supply current
V
V
When clock is stopped
RAM
f(XIN)=10MHz
Square wave, no division
In single-chip
mode, the
output pins
are open
and other
pins are VSS
19.0
90.0
38.0
mA
f(XCIN)=32kHz
Square wave
µA
µA
Icc
f(XCIN)=32kHz
4.0
When a WAIT instruction is
executed(Note)
Ta=25°C
when clock is stopped
1.0
µA
Ta=85°C
when clock is stopped
20.0
Note: With one timer operated using fc32.
145
Mitsubishi microcomputers
M16C / 61 Group
Electrical characteristics (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Table 1.24.4. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, VSS = AVSS
=
o
0V at Ta = 25 C, f(XIN) = 10MHZ unless otherwise specified)
Standard
Symbol
Parameter Measuring condition
Unit
Min. Typ. Max.
V
REF
REF = VCC = 5V
AN
=
V
CC
10 Bits
Resolution
Sample & hold function not available
Absolute
accuracy
V
LSB
LSB
±3
±3
0
to AN7 input
Sample & hold function available(10bit)
V
REF =VCC
ANEX0, ANEX1 input,
External op-amp connection mode
LSB
±7
= 5V
V
REF = VCC = 5V
Sample & hold function available(8bit)
LSB
±2
40
R
LADDER
kΩ
V
REF
=
V
CC
10
3.3
Ladder resistance
Conversion time(10bit)
Conversion time(8bit)
Sampling time
t
CONV
µs
t
CONV
2.8
0.3
2
µs
µs
V
t
SAMP
V
CC
V
REF
IA
Reference voltage
V
0
V
REF
V
Analog input voltage
Table 1.24.5. D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V
o
at Ta = 25 C, f(XIN) = 10MHZ unless otherwise specified)
Standard
Min. Typ. Max.
Symbol
Parameter
Measuring condition
Unit
Resolution
Absolute accuracy
Setup time
Bits
%
8
1.0
3
tsu
µs
RO
Output resistance
kΩ
4
10
20
IVREF
Reference power supply input current
1.5
mA
(
Note)
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”.
The A-D converter's ladder resistance is not included.
Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
146
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25 C unless otherwise specified)
Table 1.24.6. External clock input
Standard
Symbol
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
Unit
Min.
100
40
Max.
t
c
ns
ns
ns
ns
ns
t
w(H
)
t
w(L)
40
t
r
15
15
t
f
External clock fall time
Table 1.24.7. Memory expansion and microprocessor modes
Standard
Symbol
Parameter
Data input access time (no wait)
Unit
Min.
Max.
t
ac1(RD-DB)
ns
ns
ns
(Note)
t
ac2(RD-DB)
ac3(RD-DB)
(Note)
(Note)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
Data input setup time
t
t
t
su(DB-RD)
40
30
40
0
ns
ns
ns
ns
ns
ns
ns
su(RDY-BCLK )
RDY input setup time
HOLD input setup time
Data input hold time
t
su(HOLD-BCLK )
h(RD-DB)
h(BCLK -RDY)
t
t
0
RDY input hold time
t
h(BCLK-HOLD )
d(BCLK-HLDA )
0
HOLD input hold time
HLDA output delay time
t
40
Note: Calculated according to the BCLK frequency as follows:
109
f(BCLK) X 2
– 45
t
t
t
ac1(RD – DB) =
ac2(RD – DB) =
ac3(RD – DB) =
[ns]
3 X 109
f(BCLK) X 2
– 45
– 45
[ns]
[ns]
3 X 109
f(BCLK) X 2
147
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25 C unless otherwise specified)
Table 1.24.8. Timer A input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
40
Table 1.24.9. Timer A input (gating input in timer mode)
Standard
Symbol
Parameter
Unit
Min.
400
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.24.10. Timer A input (external trigger input in one-shot timer mode)
Standard
Min. Max.
200
Symbol
Parameter
Unit
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
100
100
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.24.11. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.24.12. Timer A input (up/down input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN)
t
h(TIN-UP)
400
148
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25 C unless otherwise specified)
Table 1.24.13. Timer B input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
100
Max.
tc(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
40
200
80
tw(TBH)
tw(TBL)
80
Table 1.24.14. Timer B input (pulse period measurement mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 1.24.15. Timer B input (pulse width measurement mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
ns
ns
ns
TBiIN input cycle time
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 1.24.16. A-D trigger input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
tc(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
tw(ADL)
Table 1.24.17. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
tc(CK)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
80
0
30
90
RxDi input setup time
RxDi input hold time
_______
Table 1.24.18. External interrupt INTi inputs
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
tw(INH)
tw(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
149
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25 C, CM15 = “1” unless
otherwise specified)
Table 1.24.19. Memory expansion mode and microprocessor mode (no wait)
Standard
Measuring condition
Symbol
Parameter
Unit
ns
Min.
Max.
25
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
th(RD-AD)
Address output hold time (BCLK standard)
Address output hold time (RD standard)
4
0
0
ns
ns
th(WR-AD)
td(BCLK-CS)
Address output hold time (WR standard)
Chip select output delay time
ns
ns
25
25
th(BCLK-CS)
td(BCLK-ALE)
Chip select output hold time (BCLK standard)
ALE signal output delay time
4
– 4
0
ns
ns
th(BCLK-ALE)
ALE signal output hold time
ns
Figure 1.24.1
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
RD signal output delay time
RD signal output hold time
25
25
40
ns
ns
WR signal output delay time
WR signal output hold time
ns
ns
0
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
ns
ns
4
(Note1)
Data output delay time (WR standard)
ns
ns
Data output hold time (WR standard)(Note2)
0
Note 1: Calculated according to the BCLK frequency as follows:
10 9
td(DB – WR) =
– 40
[ns]
f(BCLK) X 2
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
R
C
DBi
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
150
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25 C, CM15 = “1” unless
otherwise specified)
Table 1.24.20. Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
Standard
Measuring condition
Symbol
Parameter
Address output delay time
Unit
Min.
Max.
25
t
t
d(BCLK-AD)
h(BCLK-AD)
ns
ns
Address output hold time (BCLK standard)
4
0
0
t
t
h(RD-AD)
Address output hold time (RD standard)
Address output hold time (WR standard)
ns
ns
h(WR-AD)
t
t
d(BCLK-CS)
h(BCLK-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
25
25
25
25
ns
ns
4
– 4
0
ns
t
t
d(BCLK-ALE)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
h(BCLK-ALE)
ns
ns
Figure 1.24.1
t
d(BCLK-RD)
h(BCLK-RD)
t
t
RD signal output hold time
WR signal output delay time
ns
ns
d(BCLK-WR)
t
t
h(BCLK-WR)
d(BCLK-DB)
WR signal output hold time
Data output delay time (BCLK standard)
0
ns
ns
40
4
t
t
t
h(BCLK-DB)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)(Note2)
ns
ns
ns
(Note1)
d(DB-WR)
h(WR-DB)
0
Note 1: Calculated according to the BCLK frequency as follows:
10 9
td(DB – WR) =
– 40
[ns]
f(BCLK)
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC
)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC
)
= 6.7ns.
151
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25 C, CM15 = “1” unless
otherwise specified)
Table 1.24.21. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Standard
Measuring condition
Symbol
Parameter
Address output delay time
Unit
Min.
Max.
25
t
d(BCLK-AD)
h(BCLK-AD)
ns
ns
ns
t
Address output hold time (BCLK standard)
Address output hold time (RD standard)
4
(Note)
t
h(RD-AD)
(Note)
th(WR-AD)
Address output hold time (WR standard)
ns
t
d(BCLK-CS)
h(BCLK-CS)
Chip select output delay time
25
25
ns
ns
ns
ns
ns
ns
t
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
4
(Note)
th(RD-CS)
(Note)
t
h(WR-CS)
t
d(BCLK-RD)
h(BCLK-RD)
t
RD signal output hold time
0
0
t
t
t
d(BCLK-WR)
WR signal output delay time
25
40
ns
ns
ns
h(BCLK-WR)
d(BCLK-DB)
WR signal output hold time
Data output delay time (BCLK standard)
Figure 1.24.1
t
h(BCLK-DB)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
4
ns
ns
(Note)
t
d(DB-WR)
h(WR-DB)
(Note)
t
Data output hold time (WR standard)
ns
ns
ns
ns
t
d(BCLK-ALE)
h(BCLK-ALE)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
25
t
– 4
(Note)
t
d(AD-ALE)
h(ALE-AD)
t
ALE signal output hold time (Adderss standard)
Post-address RD signal output delay time
50
0
ns
ns
td(AD-RD)
t
d(AD-WR)
Post-address WR signal output delay time
Address output floating start time
0
ns
ns
t
dZ(RD-AD)
8
Note: Calculated according to the BCLK frequency as follows:
109
th(RD – AD) =
[ns]
f(BCLK) X 2
109
th(WR – AD) =
th(RD – CS) =
[ns]
[ns]
f(BCLK) X 2
109
f(BCLK) X 2
109
th(WR – CS) =
td(DB – WR) =
[ns]
[ns]
f(BCLK) X 2
9 X 3
10
f(BCLK) X 2
– 40
– 25
109
th(WR – DB) =
td(AD – ALE) =
[ns]
[ns]
f(BCLK) X 2
109
f(BCLK) X 2
152
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
30pF
Figure 1.24.1. Port P0 to P10 measurement circuit
153
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
tc(TA)
t
w(TAH)
TAiIN input
t
w(TAL)
tc(UP)
t
w(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
t
h(TIN–UP)
t
su(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
t
c(TB)
t
w(TBH)
TBiIN input
t
w(TBL)
t
t
c(AD)
tw(ADL)
ADTRG input
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
su(D–C)
t
d(C–Q)
t
h(C–D)
t
w(INL)
INTi input
t
w(INH)
Figure 1.24.2. VCC=5V timing diagram (1)
154
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Memory Expansion Mode and Microprocessor Mode
(Valid only with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Valid with or without wait)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA)
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
Hi–Z
P50 to P52
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of
ports P40 to P43.
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
• Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 1.24.3. VCC=5V timing diagram (2)
155
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Memory Expansion Mode and Microprocessor Mode
(With no wait)
Read timing
BCLK
t
d(BCLK–CS)
25ns.max
t
h(BCLK–CS)
4ns.min
CSi
t
h(RD–CS)
0ns.min
tcyc
t
d(BCLK–AD)
25ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
d(BCLK–ALE)
t
h(BCLK–ALE)
t
h(RD–AD)
0ns.min
–4ns.min
25ns.max
ALE
RD
DB
t
h(BCLK–RD)
0ns.min
t
d(BCLK–RD)
25ns.max
t
ac1(RD–DB)
Hi–Z
t
SU(DB–RD)
40ns.min
t
h(RD–DB)
0ns.min
Write timing
BCLK
t
h(BCLK–CS)
t
d(BCLK–CS)
25ns.max
4ns.min
CSi
t
h(WR–CS)
0ns.min
tcyc
t
d(BCLK–AD)
25ns.max
t
h(BCLK-AD)
4ns.min
ADi
BHE
0ns.min
th(WR–AD)
t
h(BCLK–ALE)
–4ns.min
t
d(BCLK–ALE)
25ns.max
ALE
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
25ns.max
WR,WRL,
WRH
t
d(BCLK–DB)
40ns.max
Hi-Z
t
h(BCLK–DB)
4ns.min
DB
t
h(WR–DB)
0ns.min
t
d(DB–WR)
(tcyc/2–40)ns.min
Figure 1.24.4. VCC=5V timing diagram (3)
156
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
Read timing
BCLK
th(BCLK–CS)
4ns.min
td(BCLK–CS)
25ns.max
CSi
th(RD–CS)
tcyc
0ns.min
td(BCLK–AD)
25ns.max
th(BCLK–AD)
4ns.min
ADi
BHE
25ns.max
td(BCLK–ALE)
th(BCLK–ALE)
–4ns.min
th(RD–AD)
0ns.min
ALE
RD
DB
th(BCLK–RD)
0ns.min
td(BCLK–RD)
25ns.max
tac2(RD–DB)
Hi–Z
th(RD–DB)
0ns.min
tSU(DB–RD)
40ns.min
Write timing
BCLK
td(BCLK–CS)
25ns.max
th(BCLK–CS)
4ns.min
CSi
th(WR–CS)
0ns.min
tcyc
td(BCLK–AD)
25ns.max
th(BCLK–AD)
4ns.min
ADi
BHE
td(BCLK–ALE)
25ns.max
th(WR–AD)
0ns.min
th(BCLK–ALE)
–4ns.min
ALE
th(BCLK–WR)
0ns.min
td(BCLK–WR)
25ns.max
WR,WRL,
WRH
td(BCLK–DB)
40ns.max
th(BCLK–DB)
4ns.min
DBi
th(WR–DB)
0ns.min
td(DB–WR)
(tcyc–40)ns.min
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with: VIL=0.8V, VIH=2.5V
• Output timing voltage : Determined with: VOL=0.8V, VOH=2.0V
Figure 1.24.5. VCC=5V timing diagram (4)
157
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
Read timing
BCLK
tcyc
t
h(BCLK–CS)
4ns.min
t
d(BCLK–CS)
25ns.max
t
h(RD–CS)
(tcyc/2)ns.min
CSi
t
d(AD–ALE)
(tcyc/2-25)ns.min
t
h(ALE–AD)
50ns.min
ADi
Address
Data input
Address
t
h(RD–DB)
0ns.min
/DBi
t
dz(RD–AD)
8ns.max
tac3(RD–DB)
t
SU(DB–RD)
40ns.min
t
d(AD–RD)
0ns.min
t
d(BCLK–AD)
25ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
d(BCLK–ALE)
t
h(BCLK–ALE)
–4ns.min
t
h(RD–AD)
(tcyc/2)ns.min
25ns.max
ALE
RD
t
h(BCLK–RD)
0ns.min
t
d(BCLK–RD)
25ns.max
Write timing
BCLK
t
h(BCLK–CS)
tcyc
t
d(BCLK–CS)
25ns.max
4ns.min
t
h(WR–CS)
(tcyc/2)ns.min
CSi
t
h(BCLK–DB)
4ns.min
t
d(BCLK–DB)
40ns.max
Data output
ADi
Address
Address
/DBi
t
d(DB–WR)
t
h(WR–DB)
t
d(AD–ALE)
(tcyc/2–25)ns.min
(tcyc*3/2–40)ns.min
(tcyc/2)ns.min
t
d(BCLK–AD)
25ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
h(BCLK–ALE)
–4ns.min
t
d(AD–WR)
0ns.min
t
d(BCLK–ALE)
25ns.max
t
h(WR–AD)
(tcyc/2)ns.min
ALE
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
25ns.max
WR,WRL,
WRH
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with VIL=0.8V, VIH=2.5V
• Output timing voltage : Determined with VOL=0.8V, VOH=2.0V
Figure 1.24.6. VCC=5V timing diagram (5)
158
Mitsubishi microcomputers
M16C / 61 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Table 1.24.22. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25 C, f(XIN) =
7MHZ, with wait)
Standard
Min Typ. Max.
Unit
Measuring condition
Symbol
Parameter
HIGH output
voltage
P0
P3
P6
0
0
0
to P0
to P3
to P6
7
7
7
,P1
,P4
,P7
0
0
2
to P1
to P4
to P7
7
7
7
,P2
,P5
,P8
0
0
0
to P2
to P5
to P8
7,
7,
4,
7
V
OH
V
I
OH=-1mA
2.5
P8
6
,P8
7
,P9
0
to P9
7
,P10
0
to P10
HIGHPOWER
LOWPOWER
I
I
OH=-0.1mA
2.5
2.5
X
X
OUT
HIGH output voltage
HIGH output voltage
V
OH
V
V
OH=-50µA
HIGHPOWER
LOWPOWER
With no load applied
With no load applied
3.0
1.6
COUT
LOW output
voltage
P0
P3
0
0
to P0
to P3
7
7
,P1
,P4
0
0
to P1
to P4
7
7
,P2
,P5
0
0
to P2
to P5
7
7
,
,
V
V
OL
OL
0.5
V
I
OL=1mA
P6
0
to P6
7
,P7
0
to P7
7
,P8
0
to P8
4,
P8
6
,P8 ,P9
7
0
to P9
7
,P10
0
to P10
7
0.5
I
OL=0.1mA
HIGHPOWER
LOWPOWER
LOW output voltage
X
OUT
V
V
I
OL=50µA
0.5
With no load applied
With no load applied
0
0
HIGHPOWER
LOWPOWER
LOW output voltage
Hysteresis
XCOUT
HOLD, RDY, TA0IN to TA4IN
to INT
to CTS , CLK
,TA2OUT to TA4OUT,NMI,
to KI , RxD to RxD
,
2,
0 to
TB0IN to TB2IN, INT
ADTRG, CTS
CLK
KI
0
V
V
T+-
T+-
V
T-
T-
0
2
0.2
0.2
0.8
V
2
0
3
0
2
V
Hysteresis
RESET
1.8
4.0
V
P0
P3
P6
P9
0
0
0
0
to P0
to P3
to P6
to P9
7
7
7
7
,P1
,P4
,P7
0
0
0
to P1
to P4
to P7
7
7
7
,P2
,P5
,P8
0
0
0
to P2
to P5
to P8
7
7
7
,
,
,
HIGH input
current
I
IH
µA
V
I
I
=3V
=0V
,P100 to P107,
X
IN, RESET, CNVss, BYTE
LOW input
current
P0
P3
P6
P9
0
0
0
0
to P0
to P3
to P6
to P9
7
7
7
7
,P1
,P4
,P7
0
0
0
to P1
to P4
to P7
7
7
7
,P2
,P5
,P8
0
0
0
to P2
to P5
to P8
7
7
7
,
,
I IL
-4.0
µA
, V
,P100 to P107,
X
IN, RESET, CNVss, BYTE
R PULLUP
Pull-up
resistance
P00
P30
P60
P86
to P0
to P3
to P6
7
7
7
,P1
,P4
,P7
0
0
2
to P1
to P4
to P7
7
7
7
,P2
,P5
,P8
0
0
0
to P2
to P5
to P8
7,
7,
4,
7
kΩ
V
I
=0V
66.0
2.0
120.0 500.0
,P87,P90 to P97,P100 to P10
MΩ
R fXIN
R fXCIN
V RAM
Feedback resistance
Feedback resistance
RAM retention voltage
X
IN
CIN
3.0
MΩ
X
10.0
V
When clock is stopped
f(XIN)=7MHz
Square wave, no division
6.0
15.0
mA
f(XCIN)=32kHz
Square wave
40.0
µA
µA
In single-chip
mode, the
output pins
are open
and other
pins are VSS
f(XCIN)=32kHz
When a WAITinstruction is
executed.
Oscillation capacity High
(Note)
2.8
0.9
Icc
Power supply current
f(XCIN)=32kHz
When a WAIT instruction is
executed.
Oscillation capacity Low
(Note)
µA
µA
Ta=25°C
when clock is stopped
1.0
Ta=85°C
when clock is stopped
20.0
Note: With one timer operated using fc32.
159
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Table 1.24.23. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, VSS = AVSS
=
o
0V at Ta = 25 C, f(XIN) = 7MHZ unless otherwise specified)
Standard
Min. Typ. Max
Symbol
Parameter
Measuring condition
Unit
Resolution
VREF = VCC
10
±2
Bits
Absolute accuracy Sample & hold function not available (8 bit)
LSB
VREF = VCC = 3V, φAD = f(XIN)/2
kΩ
RLADDER
VREF = VCC
Ladder resistance
Conversion time(8bit)
Reference voltage
Analog input voltage
40
10
14.0
2.7
tCONV
VREF
µs
V
VCC
VIA
0
VREF
V
Table 1.24.24. D-A conversion characteristics (referenced to VCC = 3V, VSS = AVSS = 0V, VREF = 3V
o
at Ta = 25 C, f(XIN) = 7MHZ unless otherwise specified)
Standard
Min. Typ. Max
8
Symbol
Parameter
Measuring condition
Unit
Bits
Resolution
Absolute accuracy
Setup time
1.0
3
%
µs
tsu
RO
kΩ
Output resistance
4
10
20
Reference power supply input current
(Note)
1.0
IVREF
mA
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”.
The A-D converter's ladder resistance is not included.
Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
160
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25 C unless otherwise specified)
Table 1.24.25. External clock input
Standard
Symbol
Parameter
Unit
Min.
143
60
Max.
ns
ns
ns
ns
ns
t
c
External clock input cycle time
t
w(H
)
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
t
w(L)
60
t
r
18
18
t
f
External clock fall time
Table 1.24.26. Memory expansion and microprocessor modes
Standard
Symbol
Parameter
Unit
Min.
Max.
(Note)
t
ac1(RD-DB)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input access time (no wait)
Data input access time (with wait)
t
ac2(RD-DB)
ac3(RD-DB)
su(DB-RD)
(Note)
(Note)
t
t
Data input access time (when accessing multiplex bus area)
Data input setup time
80
60
80
0
t
su(RDY-BCLK )
RDY input setup time
t
su(HOLD-BCLK )
HOLD input setup time
Data input hold time
t
h(RD-DB)
h(BCLK -RDY)
h(BCLK-HOLD )
t
0
RDY input hold time
HOLD input hold time
HLDA output delay time
t
0
t
d(BCLK-HLDA)
100
Note: Calculated according to the BCLK frequency as follows:
109
f(BCLK) X 2
– 90
t
ac1(RD – DB) =
[ns]
3 X 109
f(BCLK) X 2
– 90
– 90
t
ac2(RD – DB) =
ac3(RD – DB) =
[ns]
[ns]
3 X 109
f(BCLK) X 2
t
161
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25 C unless otherwise specified)
Table 1.24.27. Timer A input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
60
Table 1.24.28. Timer A input (gating input in timer mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
Table 1.24.29. Timer A input (external trigger input in one-shot timer mode)
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
Table 1.24.30. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
ns
ns
t
w(TAL)
Table 1.24.31. Timer A input (up/down input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
t
c(UP)
TAiOUT input cycle time
ns
ns
ns
ns
ns
t
w(UPH)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
t
w(UPL)
t
su(UP-TIN)
t
h(TIN-UP)
TAiOUT input hold time
600
162
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25 C unless otherwise specified)
Table 1.24.32. Timer B input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
t
c(TB)
TBiIN input cycle time (counted on one edge)
ns
ns
ns
ns
ns
ns
t
w(TBH)
w(TBL)
c(TB)
w(TBH)
w(TBL)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
t
60
t
300
160
160
t
t
Table 1.24.33. Timer B input (pulse period measurement mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
w(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
Table 1.24.34. Timer B input (pulse width measurement mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
w(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
Table 1.24.35. A-D trigger input
Standard
Symbol
Parameter
Unit
Min.
1500
200
Max.
t
c(AD)
w(ADL)
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
ns
ns
t
Table 1.24.36. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(CK)
w(CKH)
w(CKL)
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
ns
ns
ns
ns
ns
ns
ns
t
t
t
d(C-Q)
h(C-Q)
su(D-C)
160
t
0
50
90
t
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 1.24.37. External interrupt INTi inputs
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
t
w(INH)
INTi input HIGH pulse width
INTi input LOW pulse width
ns
ns
t
w(INL)
163
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25 C, CM15 = “1” unless
otherwise specified)
Table 1.24.38. Memory expansion and microprocessor modes (with no wait)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
t
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
60
ns
ns
ns
4
0
0
t
h(RD-AD)
t
t
t
h(WR-AD)
Address output hold time (WR standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
ns
ns
ns
d(BCLK-CS)
60
60
60
h(BCLK-CS)
4
t
t
d(BCLK-ALE)
h(BCLK-ALE)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
ns
ns
ns
ns
—4
Figure 1.24.1
t
t
d(BCLK-RD)
h(BCLK-RD)
0
t
t
t
t
d(BCLK-WR)
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
60
80
ns
ns
ns
ns
ns
h(BCLK-WR)
d(BCLK-DB)
0
h(BCLK-DB)
4
(Note1)
0
t
d(DB-WR)
h(WR-DB)
Data output hold time (WR standard)(Note2)
t
ns
Note 1: Calculated according to the BCLK frequency as follows:
10 9
td(DB – WR) =
– 80
[ns]
f(BCLK) X 2
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC
)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC
)
= 6.7ns.
164
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25 C, CM15 = “1” unless
otherwise specified)
Table 1.24.39. Memory expansion and microprocessor modes
(when accessing external memory area with wait)
Standard
Measuring condition
Symbol
Parameter
Unit
ns
Min.
Max.
60
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
t
t
Address output hold time (BCLK standard)
Address output hold time (RD standard)
4
0
0
ns
ns
h(RD-AD)
t
h(WR-AD)
Address output hold time (WR standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
ns
ns
ns
t
t
t
t
t
t
d(BCLK-CS)
60
60
60
h(BCLK-CS)
d(BCLK-ALE)
h(BCLK-ALE)
4
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
ns
ns
ns
ns
– 4
0
Figure 1.24.1
d(BCLK-RD)
h(BCLK-RD)
t
t
t
t
d(BCLK-WR)
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
60
80
ns
ns
ns
ns
h(BCLK-WR)
d(BCLK-DB)
0
h(BCLK-DB)
4
(Note1)
0
t
d(DB-WR)
h(WR-DB)
Data output delay time (WR standard)
ns
ns
Data output hold time (WR standard)(Note2)
t
Note 1: Calculated according to the BCLK frequency as follows:
109
td(DB – WR) =
– 80
[ns]
f(BCLK)
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC
by a circuit of the right figure.
)
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC
)
= 6.7ns.
165
Mitsubishi microcomputers
M16C / 61 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25 C, CM15 = “1” unless
otherwise specified)
Table 1.24.40. Memory expansion and microprocessor modes
(when accessing external memory area with wait, and select multiplexed bus)
Standard
Measuring condition
Symbol
Parameter
Address output delay time
Unit
Min.
Max.
60
t
t
d(BCLK-AD)
h(BCLK-AD)
ns
ns
Address output hold time (BCLK standard)
4
t
h(RD-AD)
Address output hold time (RD standard)
Address output hold time (WR standard)
(Note)
(Note)
ns
ns
t
h(WR-AD)
t
t
d(BCLK-CS)
h(BCLK-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
60
ns
ns
4
t
h(RD-CS)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
(Note)
(Note)
ns
ns
ns
t
h(WR-CS)
t
d(BCLK-RD)
h(BCLK-RD)
60
60
80
t
RD signal output hold time
WR signal output delay time
0
0
ns
ns
Figure 1.24.1
t
d(BCLK-WR)
t
t
h(BCLK-WR)
d(BCLK-DB)
WR signal output hold time
Data output delay time (BCLK standard)
ns
ns
t
h(BCLK-DB)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
4
ns
ns
ns
t
t
d(DB-WR)
(Note)
(Note)
h(WR-DB)
t
t
d(BCLK-ALE)
h(BCLK-ALE)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
60
ns
ns
– 4
t
t
d(AD-ALE)
h(ALE-AD)
ALE signal output delay time (Address standard)
ALE signal output hold time(Address standard)
(Note)
50
ns
ns
t
d(AD-RD)
d(AD-WR)
dZ(RD-AD)
Post-address RD signal output delay time
Post-address WR signal output delay time
Address output floating start time
0
0
ns
ns
ns
t
t
8
Note: Calculated according to the BCLK frequency as follows:
10 9
th(RD – AD) =
[ns]
[ns]
f(BCLK) X 2
10 9
th(WR – AD) =
f(BCLK) X 2
10 9
th(RD – CS) =
th(WR – CS) =
[ns]
[ns]
f(BCLK) X 2
10 9
f(BCLK) X 2
10 9 X 3
– 80
– 60
td(DB – WR) =
th(WR – DB) =
td(AD – ALE) =
[ns]
[ns]
[ns]
f(BCLK) X 2
10 9
f(BCLK) X 2
10 9
f(BCLK) X 2
166
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
th(TIN–UP)
tsu(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
t
h(C–Q)
TxDi
RxDi
td(C–Q)
tsu(D–C)
th(C–D)
tw(INL)
INTi input
tw(INH)
Figure 1.24.7. VCC=3V timing diagram (1)
167
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
Memory Expansion Mode and Microprocessor Mode
(Valid only with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Valid with or without wait)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA)
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
Hi–Z
P50 to P52
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of
ports P40 to P43.
Measuring conditions :
• VCC=3V
• Input timing voltage : Determined with VIL=0.6V, VIH=2.4V
• Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
Figure 1.24.8. VCC=3V timing diagram (2)
168
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
Memory Expansion Mode and Microprocessor Mode
(With no wait)
Read timing
BCLK
CSi
t
h(BCLK–CS)
4ns.min
t
d(BCLK–CS)
60ns.max
t
h(RD–CS)
tcyc
0ns.min
t
d(BCLK–AD)
60ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
h(BCLK–ALE)
0ns.min
h(RD–AD)
t
d(BCLK–ALE)
t
–4ns.min
60ns.max
ALE
RD
DB
t
d(BCLK–RD)
60ns.max
t
h(BCLK–RD)
0ns.min
t
ac1(RD–DB)
Hi–Z
t
h(RD–DB)
0ns.min
t
SU(DB–RD)
80ns.min
Write timing
BCLK
t
d(BCLK–CS)
t
h(BCLK–CS)
4ns.min
60ns.max
CSi
t
h(WR–CS)
0ns.min
tcyc
t
d(BCLK–AD)
t
h(BCLK–AD)
4ns.min
60ns.max
ADi
BHE
t
d(BCLK–ALE)
t
h(BCLK–ALE)
–4ns.min
t
h(WR–AD)
0ns.min
60ns.max
ALE
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
60ns.max
WR,WRL,
WRH
t
d(BCLK–DB)
t
h(BCLK–DB)
4ns.min
80ns.max
Hi–Z
DB
t
h(WR–DB)
0ns.min
t
d(DB–WR)
(tcyc/2–80)ns.min
Figure 1.24.9. VCC=3V timing diagram (3)
169
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
Read timing
BCLK
t
h(BCLK–CS)
t
d(BCLK–CS)
60ns.max
4ns.min
CSi
tcyc
t
h(RD–CS)
0ns.min
t
d(BCLK–AD)
60ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
d(BCLK–ALE)
60ns.max
t
h(RD–AD)
0ns.min
t
h(BCLK–ALE)
–4ns.min
ALE
RD
DB
0ns.min
t
d(BCLK–RD)
60ns.max
t
h(BCLK–RD)
t
ac2(RD–DB)
Hi–Z
0ns.min
th(RD–DB)
t
SU(DB–RD)
80ns.min
Write timing
BCLK
CSi
t
d(BCLK–CS)
t
h(BCLK–CS)
60ns.max
4ns.min
tcyc
t
h(WR–CS)
0ns.min
t
d(BCLK–AD)
60ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
h(BCLK–ALE)
–4ns.min
t
d(BCLK–ALE)
t
h(WR–AD)
0ns.min
60ns.max
ALE
t
d(BCLK–WR)
60ns.max
t
h(BCLK–WR)
0ns.min
WR,WRL,
WRH
t
h(BCLK–DB)
4ns.min
t
d(BCLK–DB)
80ns.max
DBi
t
h(WR–DB)
0ns.min
t
d(DB–WR)
(tcyc–80)ns.min
Measuring conditions :
• VCC=3V
• Input timing voltage : Determined with VIL=0.48V, VIH=1.5V
• Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
Figure 1.24.10. VCC=3V timing diagram (4)
170
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
Read timing
BCLK
t
h(BCLK–CS)
4ns.min
tcyc
t
d(BCLK–CS)
60ns.max
t
h(RD–CS)
(tcyc/2)ns.min
CSi
(tcyc/2–60)ns.min
td(AD–ALE)
t
dz(RD–AD)
8ns.max
ADi
/DBi
Address
h(ALE–AD)
Data input
Address
t
h(RD–DB)
0ns.min
t
t
tac3(RD–DB)
t
SU(DB–RD)
80ns.min
50ns.min
t
d(AD–RD)
0ns.min
t
h(BCLK–AD)
4ns.min
d(BCLK–AD)
60ns.max
ADi
BHE
t
h(BCLK–ALE)
–4ns.min
t
d(BCLK–ALE)
t
h(RD–AD)
(tcyc/2)ns.min
60ns.max
ALE
RD
t
h(BCLK–RD)
0ns.min
t
d(BCLK–RD)
60ns.max
Write timing
BCLK
t
h(BCLK–CS)
4ns.min
tcyc
t
d(BCLK–CS)
60ns.max
t
h(WR–CS)
(tcyc/2)ns.min
CSi
t
d(BCLK–DB)
80ns.max
t
h(BCLK–DB)
4ns.min
ADi
Address
Data output
Address
/DBi
t
d(DB–WR)
t
d(AD–ALE)
t
h(WR–DB)
(tcyc*3/2–80)ns.min
(tcyc/2–60)ns.min
(tcyc/2)ns.min
t
h(BCLK–AD)
4ns.min
t
d(BCLK–AD)
60ns.max
ADi
BHE
t
d(BCLK–ALE)
t
h(BCLK–ALE)
–4ns.min
t
d(AD–WR)
0ns.min
t
h(WR–AD)
(tcyc/2)ns.min
60ns.max
ALE
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
60ns.max
WR,WRL,
WRH
Measuring conditions :
• VCC=3V
• Input timing voltage : Determined with VIL=0.48V,VIH=1.5V
• Output timing voltage : Determined with VOL=1.5V,VOH=1.5V
Figure 1.24.11. VCC=3V timing diagram (5)
171
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 53B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610M8A-XXXFP/GP
Date :
MASK ROM CONFIRMATION FORM
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
Date :
issued
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30610M8A-XXXFP
Checksum code for total EPROM area :
EPROM type :
M30610M8A-XXXGP
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30610M8A -
containing ASCII
code for M30610M8A -
0000F16
0001016
0000F16
0001016
2FFFF16
3000016
6FFFF16
7000016
ROM(64K)
ROM(64K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'M '
'3 '
'0 '
'6 '
'1 '
'0 '
'M '
'8 '
= 4D16
= 3316
= 3016
= 3616
= 3116
= 3016
= 4D16
= 3816
' A ' = 4116
' — ' = 2D16
FF16
0000916
0000A16
0000B16
0000216
0000316
0000416
The ASCII code for 'M30610M8A-' is shown at right.
The data in this table must be written to address
0000016 to 0000F16.
FF16
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000516
0000616
0000716
Both address and data are shown in hex.
0000F16
FF16
172
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 53B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610M8A-XXXFP/GP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30610M8A- '
.BYTE
' M30610M8A- '
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
Note:
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30610M8A-XXXFP
M30610M8A-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30610M8A-XXXFP, submit the 100P6S mark specification sheet. For the M30610M8A-XXXGP,
submit the 100P6Q mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
173
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 53B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610M8A-XXXFP/GP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
174
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 52B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MAA-XXXFP/GP
Date :
MASK ROM CONFIRMATION FORM
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
Date :
issued
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
Checksum code for total EPROM area :
EPROM type :
M30610MAA-XXXFP
M30610MAA-XXXGP
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30610MAA -
containing ASCII
code for M30610MAA -
0000F16
0001016
0000F16
0001016
27FFF16
2800016
67FFF16
6800016
ROM(96K)
ROM(96K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
M
3
0
6
1
0
M
A
'
'
'
'
'
'
= 4D16
= 3316
= 3016
= 3616
= 3116
= 3016
= 4D16
= 4116
'
'
A
— '
'
= 4116
= 2D16
FF16
0000916
0000A16
0000B16
'
'
'
'
'
'
0000216
0000316
0000416
The ASCII code for 'M30610MAA-' is shown at right.
The data in this table must be written to address
FF16
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
175
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 52B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MAA-XXXFP/GP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30610MAA- '
.BYTE
' M30610MAA- '
Note:
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30610MAA-XXXFP
M30610MAA-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30610MAA-XXXFP, submit the 100P6S mark specification sheet. For the M30610MAA-XXXGP,
submit the 100P6Q mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
176
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 52B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MAA-XXXFP/GP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
177
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 51B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MCA-XXXFP/GP
Date :
MASK ROM CONFIRMATION FORM
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
Date :
issued
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30610MCA-XXXFP
Checksum code for total EPROM area :
EPROM type :
M30610MCA-XXXGP
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30610MCA -
containing ASCII
code for M30610MCA -
0000F16
0001016
0000F16
0001016
1FFFF16
2000016
5FFFF16
6000016
ROM(128K)
ROM(128K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
M
3
0
6
1
0
M
C
'
'
'
'
'
'
= 4D16
= 3316
= 3016
= 3616
= 3116
= 3016
= 4D16
= 4316
'
'
A
— '
'
= 4116
= 2D16
FF16
0000916
0000A16
0000B16
'
'
'
'
'
0000216
0000316
0000416
The ASCII code for 'M30610MCA-' is shown at right.
The data in this table must be written to address
FF16
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
'
178
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 51B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MCA-XXXFP/GP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30610MCA- '
.BYTE
' M30610MCA- '
Note:
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30610MCA-XXXFP
M30610MCA-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30610MCA-XXXFP, submit the 100P6S mark specification sheet. For the M30610MCA-XXXGP,
submit the 100P6Q mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
179
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 51B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30610MCA-XXXFP/GP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
180
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 35B <79A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M4A-XXXFP/GP
Date :
MASK ROM CONFIRMATION FORM
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
Date :
issued
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30612M4A-XXXFP
Checksum code for total EPROM area :
EPROM type :
M30612M4A-XXXGP
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30612M4A -
containing ASCII
code for M30612M4A -
0000F16
0001016
0000F16
0001016
37FFF16
3800016
77FFF16
7800016
ROM(32K)
ROM(32K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
M
3
0
6
1
2
M
4
'
'
'
'
'
'
= 4D16
= 3316
= 3016
= 3616
= 3116
= 3216
= 4D16
= 3416
'
'
A
— '
'
= 4116
= 2D16
FF16
0000916
0000A16
0000B16
'
'
'
'
'
'
0000216
0000316
0000416
The ASCII code for 'M30612M4A-' is shown at right.
The data in this table must be written to address
FF16
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
181
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 35B <79A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M4A-XXXFP/GP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30612M4A- '
.BYTE
' M30612M4A- '
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
Note:
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30612M4A-XXXFP
M30612M4A-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30612M4A-XXXFP, submit the 100P6S mark specification sheet. For the M30612M4A-XXXGP,
submit the 100P6Q mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
182
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 35B <79A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M4A-XXXFP/GP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
183
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 34B <79A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M8A-XXXFP/GP
Date :
MASK ROM CONFIRMATION FORM
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
Date :
issued
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30612M8A-XXXFP
Checksum code for total EPROM area :
EPROM type :
M30612M8A-XXXGP
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30612M8A -
containing ASCII
code for M30612M8A -
0000F16
0001016
0000F16
0001016
2FFFF16
3000016
6FFFF16
7000016
ROM(64K)
ROM(64K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
M
3
0
6
1
2
M
8
'
'
'
'
'
'
= 4D16
= 3316
= 3016
= 3616
= 3116
= 3216
= 4D16
= 3816
'
'
A
— '
'
= 4116
= 2D16
FF16
0000916
0000A16
0000B16
'
'
'
'
'
0000216
0000316
0000416
The ASCII code for 'M30612M8A-' is shown at right.
The data in this table must be written to address
FF16
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
0000F16
FF16
'
'
184
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 34B <79A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M8A-XXXFP/GP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30612M8A- '
.BYTE
' M30612M8A- '
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
Note:
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30612M8A-XXXFP
M30612M8A-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30612M8A-XXXFP, submit the 100P6S mark specification sheet. For the M30612M8A-XXXGP,
submit the 100P6Q mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
185
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 34B <79A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612M8A-XXXFP/GP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
186
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 55B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MAA-XXXFP/GP
Date :
MASK ROM CONFIRMATION FORM
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
Date :
issued
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30612MAA-XXXFP
Checksum code for total EPROM area :
EPROM type :
M30612MAA-XXXGP
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30612MAA -
containing ASCII
code for M30612MAA -
0000F16
0001016
0000F16
0001016
27FFF16
2800016
67FFF16
6800016
ROM(96K)
ROM(96K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
M
3
0
6
1
2
M
A
'
'
'
'
'
'
= 4D16
= 3316
= 3016
= 3616
= 3116
= 3216
= 4D16
= 4116
'
'
A
— '
'
= 4116
= 2D16
FF16
0000916
0000A16
0000B16
'
'
'
'
'
0000216
0000316
0000416
The ASCII code for 'M30612MAA-' is shown at right.
The data in this table must be written to address
FF16
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
'
187
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 55B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MAA-XXXFP/GP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30612MAA- '
.BYTE
' M30612MAA- '
Note:
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30612MAA-XXXFP
M30612MAA-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30612MAA-XXXFP, submit the 100P6S mark specification sheet. For the M30612MAA-XXXGP,
submit the 100P6Q mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
188
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 55B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MAA-XXXFP/GP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
189
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 54B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MCA-XXXFP/GP
Date :
MASK ROM CONFIRMATION FORM
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
Date :
issued
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30612MCA-XXXFP
Checksum code for total EPROM area :
EPROM type :
M30612MCA-XXXGP
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30612MCA -
containing ASCII
code for M30612MCA -
0000F16
0001016
0000F16
0001016
1FFFF16
2000016
5FFFF16
6000016
ROM(128K)
ROM(128K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'M '
'3 '
'0 '
'6 '
'1 '
'2 '
'M '
'C '
= 4D16
= 3316
= 3016
= 3616
= 3116
= 3216
= 4D16
= 4316
' A ' = 4116
' — ' = 2D16
FF16
0000916
0000A16
0000B16
0000216
0000316
0000416
The ASCII code for 'M30612MCA-' is shown at right.
The data in this table must be written to address
FF16
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
0000F16
FF16
190
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 54B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MCA-XXXFP/GP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30612MCA- '
.BYTE
' M30612MCA- '
Note:
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30612MCA-XXXFP
M30612MCA-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30612MCA-XXXFP, submit the 100P6S mark specification sheet. For the M30612MCA-XXXGP,
submit the 100P6Q mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
191
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH11 54B <71A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30612MCA-XXXFP/GP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
192
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
100P6S-A
Plastic 100pin 14✕20mm body QFP
EIAJ Package Code
QFP100-P-1420-0.65
JEDEC Code
–
Weight(g)
1.58
Lead Material
Alloy 42
MD
HD
D
100
81
1
80
I
2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
Nom
–
0.1
Max
3.05
0.2
–
A
A
A
1
2
–
2.8
b
0.25
0.13
13.8
19.8
–
16.5
22.5
0.4
–
0.3
0.4
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.15
14.0
20.0
0.65
16.8
22.8
0.6
c
D
E
e
30
51
31
50
A
L1
H
H
D
E
L
1.4
L1
y
–
0°
–
1.3
–
–
–
0.1
10°
–
–
–
F
b2
0.35
–
14.6
20.6
e
b
L
I
2
Detail F
y
M
M
D
E
–
–
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
EIAJ Package Code
JEDEC Code
–
Weight(g)
Lead Material
Cu Alloy
MD
LQFP100-P-1414-0.50
HD
D
100
76
I2
1
75
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A
A
1
0
0.1
2
–
1.4
b
0.13
0.105
13.9
13.9
–
0.18
0.125
14.0
14.0
0.5
0.28
0.175
14.1
14.1
–
25
51
c
D
E
e
26
50
A
H
H
L
D
E
15.8
15.8
0.3
–
–
0°
–
1.0
–
16.0
16.0
0.5
1.0
–
16.2
16.2
0.7
–
0.1
10°
–
–
–
–
L1
F
e
L1
y
–
b
y
b2
0.225
–
14.4
14.4
L
I
2
Detail F
M
M
D
E
–
193
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Differences between M16C/61 group and M30600M8
M30600M8
Type name
M16C/61 group
See Figure 4. ROM Expansion
4 K to 10 K bytes
ROM
RAM
64 K bytes
10 K bytes
Internal memory
size
Chip select
CS0 3000016 to FFFFF16
(besides internal area)
CS0 9000016 to FFFFF16
(besides internal area)
CS1 2800016 to 2FFFF16
CS2 0800016 to 27FFF16
CS3 0400016 to 07FFF16
CS1 1000016 to 8FFFF16
CS2 0800016 to 0FFFF16
CS3 0400016 to 07FFF16
SFR area 0000016 to 003FF16
RAM area 0040016 to 03FFF16
ROM area D000016 to FFFFF16
(PM16=0)
SFR area 0000016 to 003FF16
RAM area 0040016 to 03FFF16
ROM area D000016 to FFFFF16
(FIX)
Internal area on memory
expansion mode
ROM area F800016 to FFFFF16
(PM16=1) (Note)
2 channel
(clocked SIO / UART)
3 channel
(clocked SIO / UART) :2 channel
(clocked SIO / UART / SIM)
Serial I/O
Port P7
function
0 to P73
Port P7
Port P7
Port P7
Port P7
0
1
2
3
T
R
CLK
CTS
X
D
D
2
/ TA0OUT
/ TA0IN
/ TA1OUT
Port P7
Port P7
Port P7
Port P7
0
1
2
3
TA0OUT
TA0IN
TA1OUT
TA1IN
X
2
2
2
/ RTS
2
/ TA1IN
Port output
style
Port P7
open drain
0
and Port P7
1
are N-channel
All Ports are CMOS
Others are CMOS
Port P93 and P94
pull-up set up condition
All of the following:
• Pull-up is selected.
• DA output is enabled.
• Input port is selected.
Both of the following:
• Pull-up is selected.
• Input port is selected.
Interrupt
sources
Internal 20 sources
External 5 sources
Software 4 sources
Internal 17 sources
External
5 sources
Software 4 sources
Add 3 sources -trans., recv. and
arbit. for UART2
DMA request
DMA0
DMA1
DMA0
DMA1
1100 UART2 trans. UART2 trans.
1101 UART2 recv. UART2 recv.
1100 UART1 trans. UART1 trans.
1101 UART1 recv. UART1 recv.
1110 A-D
A-D
1110 A-D
A-D
prohibited
1111 UART1 trans. UART1 recv.
1111 prohibited
Note: M30612M4A/E4 only.
194
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
195
Keep safety first in your circuit designs!
●
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble may
occur with them. Trouble with semiconductors may lead to personal injury, fire or
property damage. Remember to give due consideration to safety when making your
circuit designs, with appropriate measures such as (i) placement of substitutive,
auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any
malfunction or mishap.
Notes regarding these materials
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These materials are intended as a reference to assist our customers in the selection
of the Mitsubishi semiconductor product best suited to the customer's application;
they do not convey any license under any intellectual property rights, or any other
rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in
these materials.
All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication
of these materials, and are subject to change by Mitsubishi Electric Corporation
without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical
errors. Mitsubishi Electric Corporation assumes no responsibility for any damage,
liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation
by various means, including the Mitsubishi Semiconductor home page (http://
www.mitsubishichips.com).
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●
When using any or all of the information contained in these materials, including
product data, diagrams, charts, programs, and algorithms, please be sure to evaluate
all information as a total system before making a final decision on the applicability of
the information and products. Mitsubishi Electric Corporation assumes no
responsibility for any damage, liability or other loss resulting from the information
contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human life is
potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor when considering the use of a product
contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint
or reproduce in whole or in part these materials.
●
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If these products or technologies are subject to the Japanese export control
restrictions, they must be exported under a license from the Japanese government
and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan
and/or the country of destination is prohibited.
●
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon
ductor product distributor for further details on these materials or the products con
tained therein.
MITSUBISHI SEMICONDUCTORS
M16C/61 Group Specification REV.E
Apr. First Edition 1999
Editioned by
Committee of editing of Mitsubishi Semiconductor
Published by
Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without
permission of Mitsubishi Electric Corporation.
©1999 MITSUBISHI ELECTRIC CORPORATION
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