M2V56S20AKT-7UL [MITSUBISHI]
Synchronous DRAM, 64MX4, 6ns, CMOS, PDSO64, STSOP2-64;
| 型号： | M2V56S20AKT-7UL |
| 厂家： | 
Mitsubishi Group |
| 描述： | Synchronous DRAM, 64MX4, 6ns, CMOS, PDSO64, STSOP2-64 存储 内存集成电路 光电二极管 动态存储器 时钟 |
| 文件： | 总49页 (文件大小：616K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20AKT is a 4-bank x 16777216-word x 4-bit,
M2V56S30AKT is a 4-bank x 8388608-word x 8-bit,
M2V56S40AKT is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M2V56S20/30/40AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),
166MHz(-5) and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v±0.3V power supply
- Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 10.65mm width x 13.1mm length, 64-pin STSOP(II) with 0.4mm lead pitch
Max. Frequency
@CL2
Max. Frequency
@CL3
Standard
M2V56S20/30/40AKT-5
M2V56S20/30/40AKT-6
M2V56S20/30/40AKT-7
133MHz
100MHz
100MHz
166MHz
133MHz
100MHz
PC133 (CL2)
PC133 (CL3)
PC100 (CL2)
MITSUBISHI ELECTRIC
1
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
x4
x8
x16
VSS
DQ15 DQ7
VSSQ VSSQ VSSQ
DQ14
DQ13 DQ6
VDDQ VDDQ VDDQ
DQ12
DQ11 DQ5
VSSQ VSSQ VSSQ
DQ10
DQ9
VDDQ VDDQ VDDQ
DQ8
NC
NC
NC
NC
VSS
VSS
VSS
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
VDD
NC
VDD
DQ0
VDD
DQ0
VDDQ VDDQ VDDQ
NC
NC
DQ3
NC
DQ0
VSSQ
NC
NC
DQ1
VSSQ
NC
DQ1
DQ2
VSSQ
DQ3
DQ4
NC
NC
NC
NC
DQ2
VDDQ VDDQ VDDQ
NC
DQ4
NC
DQ2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
DQ1
VSSQ
NC
NC
NC
NC
VDD
NC
NC
DQ3
VSSQ
NC
NC
NC
NC
VDD
NC
DQ5
DQ6
VSSQ
DQ7
NC
NC
NC
VDD
NC
LDQM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
UDQM DQM DQM
NC
NC
NC
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
NC
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
NC
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
/WE
/CAS
/RAS
/CS
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
BA0
BA1
A10/AP A10/AP A10/AP
A0
A1
A2
A3
A0
A1
A2
A3
VDD
A0
A1
A2
A3
VDD
A4
VSS
A4
VSS
A4
VSS
VDD
TOP VIEW
CLK
: Master Clock
: Clock Enable
: Chip Select
CKE
/CS
/RAS
/CAS
/WE
: Row Address Strobe
: Column Address Strobe
: Write Enable
DQ0-15
: Data I/O
DQM, DQMU/L : Output Disable / Write Mask
A0-12
BA0,1
Vdd
: Address Input
: Bank Address Input
: Power Supply
VddQ
Vss
: Power Supply for Output
: Ground
VssQ
: Ground for Output
MITSUBISHI ELECTRIC
2
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
BLOCK DIAGRAM
DQ0-3 (x4), 0-7 (x8), 0 - 15 (x16)
I/O Buffer
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode Register
Address Buffer
Control Circuitry
Control Signal Buffer
Clock Buffer
A0-12 BA0,1
CLK
CKE
/CS /RAS /CAS /WE DQMU/L
This rule is applied to only Synchronous DRAM family.
Type Designation Code
M 2 V 56 S 4 0 A KT - 5
Speed Grade 5: 166MHz@CL3, 133MHz@CL2
6: 133MHz@CL3, 100MHz@CL2
7: 100MHz@CL2
Package Type KT: STSOP(II)
Process Generation A:2nd. gen.
Function Reserved for Future Use
n
Organization 2 2: x4, 3: x8, 4: x16
SDRAM Data Rate Type S:Single Data Rate
Density 56: 256M bits
Interface V:LVTTL
Memory Style (DRAM)
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
3
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
PIN FUNCTION
CLK
Input
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
Clock Enable: CKE controls internal clock. When CKE is low, internal
clock for the following cycle is ceased. CKE is also used to select auto
/ self refresh. After self refresh mode is started, CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.
CKE
/CS
Input
Input
Chip Select: When /CS is high, any command means No Operation
Combination of /RAS, /CAS, /WE defines basic commands.
/RAS, /CAS, /WE
A0-12 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-12. The Column Address is
specified by A0-9,11. A10 is also used to indicate precharge option.
When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
A0-12
BA0,1
Input
Input
Bank Address: BA0,1 specifies one of four banks to which a command
is applied. BA0,1 must be set with ACT, PRE, READ, WRITE
commands.
DQ0-15
Input / Output Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for
DQM
Input
the current cycle is masked. When DQMU/L is high in burst read, Dout
is disabled at the next but one cycle.
DQMU/L
Vdd, Vss
Power Supply Power Supply for the memory array and peripheral circuitry.
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
VddQ, VssQ
MITSUBISHI ELECTRIC
4
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
BASIC FUNCTIONS
The M2V56S20/30/40AKT provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.
CLK
Chip Select : L=select, H=deselect
Command
/CS
/RAS
/CAS
/WE
Command
Command
define basic commands
Refresh Option @refresh command
CKE
A10
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this
command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
5
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
COMMAND TRUTH TABLE
CKE CKE
A10 A0-9,
/AP 11-12
note
COMMAND
MNEMONIC
/CS
/RAS /CAS /WE BA0,1
n-1
n
Deselect
DESEL
NOP
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
No Operation
H
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
Precharge All Banks
PRE
H
H
X
X
L
L
L
L
H
H
L
L
V
X
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with
WRITEA
READ
H
H
X
X
L
L
H
H
L
L
L
V
V
H
L
V
V
Auto-Precharge
Column Address Entry
& Read
H
Column Address Entry
& Read with
READA
H
X
L
H
L
H
V
H
V
Auto-Precharge
Auto-Refresh
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
V
Self-Refresh Entry
L
L
H
H
X
X
X
H
H
L
X
H
H
L
Self-Refresh Exit
REFSX
L
Burst Terminate
TBST
MRS
H
H
1
Mode Register Set
L
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-9,11-12=L, A0-A6 =Mode
Address
MITSUBISHI ELECTRIC
6
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
FUNCTION TRUTH TABLE
Current State
/CS
/RAS /CAS /WE
Address
Command
DESEL
Action
H
X
X
X
X
NOP
IDLE
L
L
H
H
H
H
H
L
X
X
NOP
NOP
TBST
ILLEGAL*2
L
L
L
L
H
L
L
L
L
H
H
L
X
H
L
BA, CA, A10
BA, RA
READ / WRITE ILLEGAL*2
ACT Bank Active, Latch RA
PRE / PREA NOP*4
BA, A10
H
X
REFA
MRS
Auto-Refresh*5
Op-Code,
Mode-Add
L
L
L
L
Mode Register Set*5
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESEL
NOP
NOP
NOP
NOP
ROW ACTIVE
TBST
Begin Read, Latch CA,
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA
Determine Auto-Precharge
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL*2
PRE / PREA Precharge / Precharge All
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
READ
TBST
Terminate Burst, Latch CA,
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA Begin New Read, Determine
Auto-Precharge*3
Terminate Burst, Latch CA,
WRITE /
Begin Write, Determine Auto-
WRITEA
Precharge*3
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL*2
PRE / PREA Terminate Burst, Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MITSUBISHI ELECTRIC
7
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS
/RAS /CAS /WE
Address
Command
DESEL
Action
WRITE
H
X
X
X
X
NOP (Continue Burst to END)
L
L
H
H
H
H
H
L
X
X
NOP
NOP (Continue Burst to END)
Terminate Burst
TBST
Terminate Burst, Latch CA,
L
H
L
H
BA, CA, A10
READ / READA Begin Read, Determine Auto-
Precharge*3
Terminate Burst, Latch CA,
WRITE /
L
L
H
L
L
L
BA, CA, A10
BA, RA
Begin Write, Determine Auto-
WRITEA
Precharge*3
H
H
ACT
Bank Active / ILLEGAL*2
L
L
L
L
H
L
L
BA, A10
X
PRE / PREA Terminate Burst, Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
READ with
AUTO
L
L
L
H
H
H
H
H
L
H
L
X
NOP
NOP (Continue Burst to END)
ILLEGAL
PRECHARGE
X
TBST
H
BA, CA, A10
READ / READA ILLEGAL
WRITE /
L
H
L
L
BA, CA, A10
ILLEGAL
WRITEA
L
L
L
L
H
H
H
L
BA, RA
ACT
Bank Active / ILLEGAL*2
BA, A10
PRE / PREA ILLEGAL*2
L
L
L
L
L
L
H
L
X
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
WRITE with
AUTO
X
PRECHARGE
X
TBST
H
BA, CA, A10
READ / READA ILLEGAL
WRITE /
ILLEGAL
WRITEA
L
H
L
L
BA, CA, A10
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL*2
PRE / PREA ILLEGAL*2
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MITSUBISHI ELECTRIC
8
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS
/RAS /CAS /WE
Address
Command
DESEL
Action
H
X
X
X
X
NOP (Idle after tRP)
PRE -
CHARGING
L
L
H
H
H
H
H
L
X
X
NOP
NOP (Idle after tRP)
ILLEGAL*2
TBST
L
L
L
L
H
L
L
L
L
H
H
L
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA NOP*4 (Idle after tRP)
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESEL
NOP
NOP (Row Active after tRCD)
NOP (Row Active after tRCD)
ILLEGAL*2
ROW
ACTIVATING
TBST
L
L
H
L
L
X
H
BA, CA, A10
BA, RA
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA ILLEGAL*2
H
L
L
L
L
H
L
L
BA, A10
X
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP
WRITE RE-
COVERING
X
NOP
X
TBST
ILLEGAL*2
X
H
BA, CA, A10
BA, RA
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA ILLEGAL*2
H
L
L
L
L
H
L
L
BA, A10
X
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
MITSUBISHI ELECTRIC
9
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS
/RAS /CAS /WE
Address
Command
DESEL
Action
H
X
X
X
X
NOP (Idle after tRC)
RE-
FRESHING
L
L
H
H
H
H
H
L
X
X
NOP
NOP (Idle after tRC)
ILLEGAL
TBST
L
L
L
L
H
L
L
L
L
H
H
L
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESEL
NOP
NOP (Idle after tRSC)
NOP (Idle after tRSC)
ILLEGAL
MODE
REGISTER
SETTING
TBST
L
L
H
L
L
X
H
BA, CA, A10
BA, RA
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
H
L
L
L
L
H
L
L
BA, A10
H
X
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending
on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC
10
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
CKE CKE
Current State
/CS /RAS /CAS /WE Add
Action
n-1
H
L
n
X
H
H
H
H
H
X
H
L
L
L
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
INVALID
SELF-
REFRESH*1
Exit Self-Refresh (Idle after tRC)
Exit Self-Refresh (Idle after tRC)
ILLEGAL
L
L
L
X
X
ILLEGAL
L
X
ILLEGAL
L
L
X
X
X
X
X
X
X
X
X
X
NOP (Maintain Self-Refresh)
INVALID
H
X
POWER
DOWN
L
L
H
L
H
L
L
L
L
L
X
X
X
L
X
X
X
L
X
X
X
L
X
X
X
H
X
H
L
X
X
X
X
X
X
X
X
Exit Power Down to Idle
NOP (Maintain Power Down)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
H
H
H
H
H
H
ALL BANKS
IDLE*2
H
L
X
H
H
H
X
H
H
L
L
L
X
ILLEGAL
H
L
L
L
L
X
X
X
X
X
X
ILLEGAL
X
X
X
Refer to Current State =Power Down
H
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Refer to Function Truth Table
Begin CLK Suspend at Next Cycle*3
Exit CLK Suspend at Next Cycle*3
Maintain CLK Suspend
ANY STATE
other than
listed above
H
L
L
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously .
A minimum setup time must be satisfied before any command other than EXIT.
2. Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
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256M Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
REFS
REFSX
MRS
REFA
IDLE
ACT
CKEL
CKEH
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
TBST
WRITE
TBST
READ
WRITEA
READA
READ
CKEL
CKEH
CKEL
WRITE
READ
WRITE
CKEH
WRITEA
READA
WRITEA
READA
PRE
CKEL
CKEH
CKEL
CKEH
PRE
WRITEA
READA
PRE
POWER
APPLIED
PRE
CHARGE
POWER
ON
PRE
Automatic Sequence
Command Sequence
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256M Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the
inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 100µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
CLK
Burst Length, Burst Type and /CAS Latency can be programmed by
/CS
setting the mode register (MRS). The mode register stores these data
/RAS
until the next MRS command, which may be issued when all banks are in
/CAS
/WE
idle state. After tRSC from a MRS command, the SDRAM is ready for
new command.
V
BA0,1 A12-A0
BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
SW
0
0
LTMODE
BT
BL
0
1
Burst Write
Single Write
SW
BL
BT=0
BT=1
1
1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
2
2
CL
/CAS LATENCY
4
4
BURST
8
8
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
2
LENGTH
R
R
R
R
R
R
R
LATENCY
MODE
3
Full Page
R
R
R
R
BURST
TYPE
0
1
SEQUENTIAL
INTERLEAVED
R: Reserved for Future Use
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256M Synchronous DRAM
CLK
Read
Write
Y
Command
Address
DQ
Y
Q0
Q1
Q2
Q3
D0
D1
D2
D3
/CAS Latency
CL= 3
BL= 4
Burst Length
Burst Length
Burst Type
Initial Address BL
A2 A1 A0
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
1
2
3
4
5
6
7
0
1
2
2
3
4
5
6
7
0
1
2
3
3
4
5
6
7
0
1
2
3
0
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
1
0
3
2
5
4
7
6
1
0
2
3
0
1
6
7
4
5
2
3
3
2
1
0
7
6
5
4
3
2
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
1
1
0
1
2
3
3
0
0
1
1
2
2
3
3
2
0
1
1
0
-
-
-
-
0
1
0
1
1
0
0
1
1
0
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OPERATIONAL DESCRIPTION
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-12.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of
open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-9,11-12
A10
ACT
Xa
ACT
Xb
READ
Yb
PRE
ACT
Xa
tRRD
tRCD
tRP
Xa
Xb
0
1
Xa
BA0-1
00
01
01
00
DQ
Qb0
Qb1
Qb2
Qb3
Precharge All
READ
A READ command can be issued to any active bank. The start address is specified by A0-9,11(x4), A0-
9 (x8), A0-8 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive
data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst
Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ,
WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The
internal precharge starts at the BL after READA. The next ACT command can be issued after (BL +
tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met.
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Multi Bank Interleaving Read (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
ACT
Xa
READ
Ya
ACT
Xb
READ PRE
Yb
ACT
tRCD
tRCD
tRP
Xa
Xa
0
Xb
0
01
0
00
Xa
BA0-1
00
00
01
00
DQ
Qa0 Qa1
Qa2
Qa3
Qb0
Qb1 Qb2
Qb3
Read with Auto-Precharge (CL=2, BL=4)
CLK
Command
ACT
Xa
READ
Ya
ACT
tRCD
BL
tRP
A0-9,11-12
A10
Xa
Xa
00
Xa
1
BA0-1
DQ
00
00
Qa0 Qa1
Qa2
Qa3
internal precharge starts
Auto-Precharge Timing (READ, BL=4)
CLK
Command
ACT
READ
ACT
Qa3
tRCD
BL
DQ
DQ
CL=2
CL=3
Qa0 Qa1
Qa2
Qa1
Qa3
Qa2
Qa0
internal precharge starts
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256M Synchronous DRAM
WRITE
A WRITE command can be issued to any active bank.The start address is specified by A0-9,11(x4),
A0-9 (x8), A0-8 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length
to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst
Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD.
From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is
high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE,
PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal
precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL
+ tWR -1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be
met.
Write (BL=4)
CLK
Command
A0-9,11-12
A10
ACT
Xa
Write
Ya
PRE
ACT
Xa
BL
tRCD
tRP
Xa
0
0
Xa
BA0-1
00
00
00
tWR
DQ
Da0
Da1
Da2
Da3
Write with Auto-Precharge (BL=4)
CLK
Command
ACT
Xa
Write
ACT
Xa
tRCD
BL
tRP
A0-9,11-12
A10
Ya
1
Xa
Xa
BA0-1
DQ
00
00
00
tWR
Da0
Da1
Da2
Da3
internal precharge starts
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256M Synchronous DRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any active bank. Random column access is
allowed. READ to READ interval is minimum 1 CLK.
Read interrupted by Read (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
READ
Ya
READ READ
Yb
0
Yc
0
0
BA0-1
00
00
10
DQ
Qa0
Qa1 Qa2
Qb0
Qc0
Qc1
Qc2
Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access is allowed.
In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention.
The output is disabled automatically 2 cycle after WRITE assertion.
Read interrupted by Write (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
ACT
Xa
READ
Ya
Write
Ya
0
Xa
0
BA0-1
00
00
00
DQM
DQ
Qa0
Da0
Da1
Da2
Da3
Output disable by DQM by WRITE
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256M Synchronous DRAM
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is
minimum 1 CLK.
A PRE command to output disable latency is equivalent to the /CAS Latency.
Read interrupted by Precharge (BL=4)
CLK
Command
READ
PRE
Q1
DQ
Q0
Q2
Command
READ
PRE
CL=2
DQ
Q0
Q1
Command
READ PRE
DQ
Q0
Command
READ
PRE
Q0
DQ
Q1
Q1
Q2
Command
READ
PRE
CL=3
DQ
Q0
Q0
Command
READ PRE
DQ
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256M Synchronous DRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, a burst terminate command can interrupt the burst read operation and
disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1
CLK. A TBST command to output disable latency is equivalent to the /CAS Latency.
Read interrupted by Terminate (BL=4)
CLK
Command
READ
TBST
Q1
DQ
Q0
Q2
Command
READ
TBST
CL=2
DQ
Q0
Q1
Command
READ TBST
DQ
Q0
Command
READ
TBST
Q0
DQ
Q1
Q1
Q2
Command
READ
TBST
CL=3
DQ
Q0
Q0
Command
READ TBST
DQ
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256M Synchronous DRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write interrupted by Write (BL=4)
CLK
Command
A0-9,11-12
A10
Write
Ya
Write Write
Yb
0
Yc
0
0
BA0-1
00
00
10
DQ
Da0
Da1
Da2
Db0
Dc0
Dc1
Dc2
Dc3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column access is allowed.
WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
"Don't Care".
Write interrupted by Read (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
ACT
Xa
Write
Ya
READ
Yb
Xa
0
0
BA0-1
00
00
00
DQ
Da0
Da1
Qb0
Qb1 Qb2
Qb3
don't care
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July '01
256M Synchronous DRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is
required from the last data to PRE command. During write recovery, data inputs must be masked by
DQM.
Write interrupted by Precharge (BL=4)
CLK
Command
A0-9,11-12
A10
ACT
Xa
0
Write
Ya
0
PRE
ACT
Xa
0
tRP
0
BA0-1
00
00
00
00
DQM
tWR
DQ
Da0
Da1
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the write recovery time is
not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write interrupted by Terminate (BL=4)
CLK
Command
A0-9,11-12
A10
ACT
Xa
0
Write
Ya
TBST
Write
Yb
0
0
BA0-1
00
00
00
DQ
Da0
Da1
Db0
Db1
Db2
Db3
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256M Synchronous DRAM
[ Write with Auto-Precharge Interrupted by Write / Read to another Bank ]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT
comand can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a
command to the same bank is inhibited.
WRITEA interrupted by WRITE to another bank (BL=4)
CLK
ACT
Xa
Command
A0-9,11-12
A10
Write
Ya
Write
BL
tRP
Yb
tWR
Xa
1
0
00
BA0-1
00
10
DQ
Da0
Da1
Db0
Db1
Db2
Db3
auto-precharge interrupted
activate
WRITEA interrupted by READ to another bank (CL=2, BL=4)
CLK
ACT
Xa
Command
Write
Ya
Read
BL
tRP
A0-9,11-12
A10
Yb
tWR
Xa
1
0
00
BA0-1
DQ
00
10
Da0
Da1
Qb0
Qb1
Qb2
Qb3
activate
auto-precharge interrupted
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July '01
256M Synchronous DRAM
[ Read with Auto-Precharge Interrupted by Read to another Bank ]
Burst read with auto-precharge can be interrupted by read to another bank. Next ACT comand can
be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same
bank is inhibited.
READA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
Read
Ya
1
Read
BL
ACT
Xa
tRP
Yb
0
Xa
BA0-1
00
10
00
DQ
Qa0
Qa1
Qb0
Qb1
Qb2
activate
Qb3
auto-precharge interrupted
Full Page Burst
Full page burst length is available for only the sequential burst type. Full page burst read / write is
repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst,
a read / write with auto-precharge command is illegal.
Single Write
When sigle write mode is set, burst length for write is always one, independently of Burst Length
defined by (A2-0).
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AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H)
command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbit
memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-
refresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any
command must not be issued before tRFC from the REFA command.
Auto-Refresh
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
A0-12
BA0-1
minimum tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
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SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and
ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh,
supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After
tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be
issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK
NOP
/CS
/RAS
/CAS
/WE
CKE
new command
X
A0-12
BA0-1
00
Self Refresh Entry
Self Refresh Exit
minimum tRFC
for recovery
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CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By
negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output
suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK
suspend can be performed either when the banks are active or idle. A command at the suspended cycle is
ignored.
ext.CLK
tIH
tIS
tIH
tIS
CKE
int.CLK
Power Down by CKE
CLK
CKE
Standby Power Down
Active Power Down
Command
PRE NOP NOP NOP
CKE
Command
ACT NOP NOP NOP
DQ Suspend by CKE
CLK
CKE
Command
Write
Read
D0
D1
D2
D3
DQ
Q0
Q1
Q2
Q3
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256M Synchronous DRAM
DQM CONTROL
DQMU/L is a dual functional signal defined as the data mask for writes and the output disable for
reads. During writes, DQMU/L masks input data word by word. DQMU/L to Data In latency is 0.
During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2.
DQM Function
CLK
Command
DQMU/L
Write
Read
D0
D2
D3
Q0
Q1
Q3
DQ
masked by DQMU/L=H
disabled by DQMU/L=H
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256M Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
Parameter
Conditions
Ratings
Unit
V
-0.5 ~ 4.6
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
VddQ
VI
Supply Voltage for Output with respect to VssQ
V
V
V
-0.5 ~ Vdd+0.5
-0.5 ~ VddQ+0.5
Input Voltage
with respect to Vss
with respect to VssQ
VO
Output Voltage
IO
Output Current
50
mA
Pd
Power Dissipation
Ta=25'C
1000
0~ 70
mW
Topr
Tstg
Operating Temprature
Storage Tempreture
'C
'C
-65~ 150
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70¡C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
3.0
Typ.
3.3
Max.
3.6
Vdd
Vss
Supply Voltage
Supply Voltage
V
V
0
0
0
VddQ
Supply Voltage for Output
3.0
3.3
3.6
V
VssQ
Supply Voltage fo Output
0
0
0
V
V
V
VIH
VIL
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
2.0
-0.3
Vdd+0.3
0.8
CAPACITANCE
(Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Limits
Symbol
Parameter
Test Condition
Unit
Min. Max.
CI(A)
CI(C)
CI(K)
CI/O
Input Capacitance,address pin
Input Capacitance,control pin
Input Capacitance,CLK pin
Input Capacitance,I/O pin
2.5
2.5
2.5
4.0
3.8
3.8
3.5
6.5
pF
pF
pF
pF
VI=1.4V
f=1MHz
VI=25mVrms
MITSUBISHI ELECTRIC
29
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Limits(max)
Organi
Symbol
Icc1
Parameter
Test Conditions
Unit Note
zation
-5
-6
-7
x4
110
115
90
95
80
Operating Current
(1bank)
tCLK=min, tRC=min, BL=1
x8
85 mA
90
1
2
x16
120 100
Icc2P
tCLK=min, CKE<VILmax
tCLK=L, CKE<VILmax
2
1
1.5
1
1
1
mA
mA
Idle Standby Current
in Power Down Mode
Icc2PS
tCLK=min, CKE>VIHmin,
/CS>VIHmin
Icc2N
30
6
25
6
20 mA 2,3
mA 2,4
Idle Standby Current
in Normal Mode
Icc2NS
Icc3N
tCLK=L, CKE>VIHmin
6
tCLK=min, CKE>VIHmin,
/CS> VIHmin
Active Standby
Current
35
30
25 mA 3,5
in Normal Mode
Icc3NS
tCLK=L, CKE>VIHmin
15
15
15 mA 4,5
90
x4
140 110
140 110
Burst Operating
Current
tCLK=min, BL=4, gapless
data
Icc4
x8
90 mA
5
x16
150 120 100
Icc5
Icc6
Auto-Refresh Current tCLK=min, tRFC=min
Self-Refresh Current CKE<0.2v -5/-6/-7
220 180 170 mA
3
3
3
mA
Notes
1. addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle
2. all banks are idle
3. input signals are changed one time during 3xtCLK
4. input signals are stable
5. all banks are active
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Limits
Min. Max.
Symbol
Parameter
Test Conditions
Unit
High-Level Output Voltage (DC) IOH=-2mA
Low-Level Output Voltage (DC) IOL= 2mA
VOH(DC)
VOL(DC)
IOZ
2.4
V
V
0.4
10
10
Off-state Output Current
Input Current
Q floating Vo=0 ~ VddQ
-10
-10
µA
µA
VIH=0 ~ VddQ+0.3V, other input pins=0V
II
MITSUBISHI ELECTRIC
30
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
1.4V
Input Timing Measurement Level:
Limits
-6
Symbol
Parameter
Unit Note
-5
-7
Min.
7.5
6
Max.
Min.
Max.
Min.
10
10
3
Max.
CL=2
CL=3
10
7.5
2.5
2.5
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK CLK cycle time
tCH
tCL
tT
CLK High pulse width
CLK Low pulse width
2.5
2.5
1
3
Transition time of CLK
Input Setup time (all inputs)
Input Hold time (all inputs)
Row Cycle time
10
10
1
10
tIS
1.5
0.8
60
1.5
0.8
67.5
75
2
tIH
tRC
1
70
80
20
tRFC Refresh Cycle time
60
tRCD Row to Column Delay
15
20
tRAS Row Active time
42
120000
45
120000
50
120000 ns
tRP
Row Precharge time
Write Recovery time
15
12
12
20
15
15
20
20
20
ns
ns
ns
tWR
tRRD ACT to ACT Delay time
Mode Register Set Cycle
tRSC
time
12
15
20
ns
tREF Average Refresh Interval
7.8
7.8
7.8
µs
CLK
1.4V
AC timing is referenced to the
input signal crossing through
1.4V.
Signal
1.4V
MITSUBISHI ELECTRIC
31
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Limits
Symbol
tAC
Parameter
-5
-6
-7
Unit
Min. Max Min. Max Min. Max
CL=2
CL=3
CL=2
CL=3
5.4
5.4
6
6
6
ns
ns
ns
ns
Access Time from CLK
5.4
3
3
3
3
3
3
tOH
Output Hold Time from CLK
Delay Time, Output Low
impedance from CLK
tOLZ
0
0
0
ns
CL=2
CL=3
3
3
5.4
5.4
3
3
6
3
3
6
6
ns
ns
Delay Time, Output High
impedannce from CLK
tOHZ
5.4
Note. If tr (CLK rising time) is > 1ns, (tr/2 - 0.5ns) should be added to the parameters.
Output Load Condition
Vout
50pF
CLK
1.4V
DQ
1.4V
tOLZ
tAC
tOHZ
tOH
MITSUBISHI ELECTRIC
32
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Burst Write (Single Bank) [BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
tWR
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
0
Y
A12
0
0
0
0
BA0,1
DQ
D0 D0 D0 D0
D0 D0 D0 D0
ACT#0 WRITE#0
PRE#0 ACT#0 WRITE#0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
33
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Burst Write (Multi Bank) [BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRC
tRAS
tRP
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
tWR
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
1
Y
X
X
X
0
Y
X
X
X
1
A12
0
1
0
0
0
BA0,1
DQ
D0 D0 D0 D0 D1 D1 D1 D1
D0 D0 D0 D0
ACT#0 WRITE#0
ACT#1
PRE#0 ACT#0 WRITE#0
PRE#0
WRITEA#1
ACT#1
(Auto-Precharge)
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
34
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Burst Read (Single Bank) [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRAS
tRP
tRAS
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
0
Y
A12
0
0
0
0
BA0,1
DQ
Q0 Q0 Q0 Q0
Q0 Q0 Q0 Q0
ACT#0 READ#0
PRE#0 ACT#0 READ#0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
35
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Burst Read (Multi Bank) [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRC
tRRD
tRAS
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
1
Y
X
X
X
0
Y
X
X
X
1
A12
0
1
0
0
BA0,1
DQ
Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q0 Q0 Q0 Q0
ACT#0 READA#0
ACT#1
ACT#0 READ#0
PRE#0
ACT#1
READA#1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
36
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Write Interrupted by Write [BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
1
Y
Y
Y
X
X
X
1
A12
0
0
1
0
0
BA0,1
DQ
D0 D0 D0 D0 D0 D1 D1 D1 D0 D0 D0 D0
ACT#0 WRITE#0
ACT#1
WRITE#0 WRITEA#1
WRITE#0
interrupt
other
PRE#0
interrupt
same
interrupt
other
ACT#1
bank
bank
bank
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
37
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Read Interrupted by Read [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
1
Y
Y
Y
X
X
X
1
A12
0
1
1
0
BA0,1
DQ
Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q1 Q0 Q0 Q0 Q0
ACT#0 READ#0
ACT#1
READ#1 READA#1
READ#0
interrupt
interrupt
other
interrupt
ACT#1
same bank other
bank
bank
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
38
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
X
Y
Y
Y
X
X
1
A12
0
1
1
1
BA0,1
DQ
D0 D0
Q1 Q1
D1 D1 D1 D1
ACT#0
WRITE#0 READ#1
ACT#1
WRITE#1
PRE#1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
39
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Write / Read Terminated by Precharge [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRP
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
0
Y
X
X
X
0
A12
0
0
0
0
BA0,1
DQ
D0 D0
Q0 Q0
ACT#0 WRITE#0
ACT#0
READ#0 PRE#0
Terminate
ACT#0
PRE#0
Terminate
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
40
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Write / Read Terminated by Burst Terminate [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
/RAS
/CAS
/WE
tRCD
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
Y
Y
A12
0
0
0
0
BA0,1
DQ
D0 D0
Q0 Q0
D0 D0 D0 D0
ACT#0 WRITE#0
READ#0 TBST
WRITE#0
PRE#0
TBST
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
41
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Single Write Burst Read [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
Y
A12
0
0
BA0,1
DQ
D0
Q0 Q0 Q0 Q0
ACT#0 WRITE#0 READ#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
42
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Power-Up Sequence and Intialize
CLK
100µs
/CS
tRP
tRFC
tRFC
tRSC
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
MA
0
X
X
X
0
0
A12
0
BA0,1
DQ
NOP
Power On
PRE ALL REFA
REFA
REFA
MRS
ACT#0
Minimum 8 REFA cycles
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
43
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Auto Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRFC
tRP
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
A12
0
BA0,1
DQ
D0 D0 D0 D0
PRE ALL REFA
All banks must be idle before REFA is issued.
ACT#0 WRITE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
44
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Self Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRFC
tRP
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
X
X
X
0
A12
BA0,1
DQ
PRE ALL Self Refresh Entry
All banks must be idle before REFS is issued.
Self Refresh Exit
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
45
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
CLK Suspension [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
Y
A12
0
0
BA0,1
DQ
D0 D0
D0 D0
Q0 Q0
Q0
Q0
ACT#0 WRITE#0 internal
CLK
READ#0
internal
CLK
suspended
suspended
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
46
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Power Down
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
DQM
A0-9,11
A10
X
X
X
0
A12
BA0,1
DQ
PRE ALL
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
47
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customerÕs application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or
a third party.
2. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any
third-partyÕs rights, originating in the use of any product data, diagrams, charts, programs, algorithms,
or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Mitsubishi Electric Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor for the latest product information before
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The information described here may contain technical inaccuracies or typographical errors. Mitsubishi
Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these
inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric
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Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device
or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
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regulations of Japan and/or the country of destination is prohibited.
8. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for further details on these materials or the products contained therein.
MITSUBISHI ELECTRIC
48
MITSUBISHI LSIs
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
Revison History
Rev.
1.01
Date
Description
July / '01 1st edition
MITSUBISHI ELECTRIC
49
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