M2S56D40ATP75A [MITSUBISHI]
256M Double Data Rate Synchronous DRAM; 256M双数据速率同步DRAM
| 型号： | M2S56D40ATP75A |
| 厂家： | 
Mitsubishi Group |
| 描述： | 256M Double Data Rate Synchronous DRAM |
| 文件： | 总37页 (文件大小：822K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2S56D20ATP is a 4-bank x 16,777,216-word x 4-bit,
M2S56D30ATP is a 4-bank x 8,388,608-word x 8-bit,
M2S56D40ATP is a 4-bank x 4,194,304-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40ATP achieves very
high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture;
two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- JEDEC standard
Operating Frequencies
Speed
Grade
Clock Rate
CL=2 *
CL=2.5 *
133MHz
-75A
-75
133MHz
100MHz
100MHz
133MHz
125MHz
-10
* CL = CAS(Read) Latency
MITSUBISHI ELECTRIC
1
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
PIN CONFIGURATION(TOP VIEW)
x4
x8
x16
VDD
NC
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
1
2
3
4
5
6
7
8
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
66pin TSOP(II)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
400mil width
x
875mil length
NC
NC
NC
VSSQ
UDQS
NC
VREF
VSS
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
0.65mm
Lead Pitch
UDM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
/CS
NC
BA0
ROW
A12
A11
A12
A11
A0-12
BA1
A10/AP
A0
BA1
A10/AP
A0
A9
A8
A7
A6
A5
A4
A9
A8
A7
A6
A5
A4
Column
A0-9,11(x4)
A0-9 (x8)
A0-8 (x16)
A1
A2
A3
A1
A2
A3
A1
A2
A3
VDD
VDD
VDD
VSS
VSS
VSS
CLK,/CLK
: Master Clock
: Clock Enable
: Chip Select
A0-12
: Address Input
CKE
/CS
BA0,1
Vdd
: Bank Address Input
: Power Supply
/RAS
/CAS
/WE
DQ0-7
DQS
DM
: Row Address Strobe
: Column Address Strobe
: Write Enable
VddQ
Vss
: Power Supply for Output
: Ground
VssQ
: Ground for Output
: Data I/O
: Data Strobe
: Write Mask
Vref
: Reference Voltage
MITSUBISHI ELECTRIC
2
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
PIN FUNCTION
SYMBOL
TYPE
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
CLK, /CLK
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self refresh.
After self refresh mode is started, CKE becomes asynchronous input. Self refresh
is maintained as long as CKE is low.
CKE
Input
/CS
Input
Input
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
/RAS, /CAS, /WE
A0-11 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
A0-12
Input
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
BA0,1
Input
DQ0-15(x16),
DQ0-7(x8),
DQ0-3(x4),
Input / Output
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
Input / Output
DQS
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
DM
Input
Vdd, Vss
VddQ, VssQ
Vref
Power Supply
Power Supply
Input
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
SSTL_2 reference voltage.
MITSUBISHI ELECTRIC
3
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
DQ0 - 15
UDQS,LDQS
QS Buffer
BLOCK DIAGRAM
DLL
I/O Buffer
Memory
Array
Memory
Memory
Array
Memory
Array
Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode Register
Control Circuitry
Address Buffer
Control Signal Buffer
Clock Buffer
/CS /RAS /CAS /WE UDM,
LDM
A0-12
BA0,1
CLK /CLK CKE
This rule is applied to only Synchronous DRAM family.
Type Designation Code
M 2 S 56 D 3 0 A TP –75A
Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0
75: 133MHz@CL=2.5,100MHz@CL=2.0
75A: 133MHz@CL=2.5,133MHz@CL=2.0
Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
n
Organization 2
2: x4, 3: x8, 4: x16
DDR Synchronous DRAM
Density 56: 256M bits
Interface V:LVTTL, S:SSTL_3, _2
Memory Style (DRAM)
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
4
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
BASIC FUNCTIONS
The M2S56D20/30/40ATP provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CLK
CLK
Chip Select : L=select, H=deselect
Command
/CS
/RAS
/CAS
/WE
CKE
A10
Command
define basic commands
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA)
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated
internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
5
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
COMMAND TRUTH TABLE
CKE CKE
A10 A0-9,
note
COMMAND
MNEMONIC
/CS /RAS /CAS /WE BA0,1
n-1
H
n
/AP 11-12
Deselect
DESEL
NOP
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
No Operation
H
H
X
H
Row Address Entry &
Bank Activate
ACT
L
L
H
H
V
V
V
Single Bank Precharge
Precharge All Banks
PRE
H
H
H
H
L
L
L
L
H
H
L
L
V
X
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
H
H
H
H
L
L
H
H
L
L
L
L
V
V
L
V
V
Column Address Entry
& Write with
WRITEA
H
Auto-Precharge
READ
H
H
L
H
L
H
V
L
V
Column Address Entry
& Read
Column Address Entry
& Read with
READA
H
H
H
H
L
L
H
L
L
L
H
H
V
X
H
X
V
X
Auto-Precharge
Auto-Refresh
REFA
REFS
Self-Refresh Entry
H
L
L
H
L
H
H
H
L
H
L
L
L
X
H
H
L
X
H
H
H
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
Self-Refresh Exit
REFSX
Burst Terminate
TERM
MRS
1
2
Mode Register Set
H
H
L
L
L
L
L
L
V
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for
read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register;BA0=1 ,
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the
op-code to be written to the selected Mode Register.
MITSUBISHI ELECTRIC
6
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address
Command
DESEL
Action
Notes
IDLE
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
NOP
X
NOP
NOP
BA
TERM
ILLEGAL
ILLEGAL
Bank Active, Latch RA
NOP
2
2
X
H
L
BA, CA, A10
BA, RA
BA, A10
READ / WRITE
ACT
H
H
L
L
PRE / PREA
REFA
4
5
L
H
X
Auto-Refresh
Op-Code, Mode-
L
L
L
L
MRS
Mode Register Set
5
Add
X
ROW ACTIVE
H
L
L
X
H
H
X
H
H
X
H
L
DESEL
NOP
NOP
NOP
NOP
X
BA
TERM
Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA
WRITE / WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA, RA
ACT
Bank Active / ILLEGAL
2
BA, A10
PRE / PREA
REFA
Precharge / Precharge All
ILLEGAL
H
X
Op-Code, Mode-
L
L
L
L
MRS
ILLEGAL
Add
X
H
L
L
X
H
H
X
H
H
X
H
L
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
READ(Auto-
Precharge
Disabled)
X
BA
TERM
Terminate Burst, Latch CA, Begin
New Read, Determine Auto-
Precharge
L
H
L
H
BA, CA, A10
READ / READA
3
2
L
L
L
L
H
L
L
L
L
H
H
L
L
H
L
BA, CA, A10
BA, RA
BA, A10
X
WRITE / WRITEA ILLEGAL
ACT
Bank Active / ILLEGAL
PRE / PREA
REFA
Terminate Burst, Precharge
ILLEGAL
H
Op-Code, Mode-
Add
L
L
L
L
MRS
ILLEGAL
MITSUBISHI ELECTRIC
7
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command
Action
Notes
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
WRITE(Auto-
Precharge
Disabled)
X
BA
TERM
Terminate Burst, Latch CA, Begin
Read, Determine Auto-Precharge
Terminate Burst, Latch CA, Begin
Write, Determine Auto-Precharge
Bank Active / ILLEGAL
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA
3
WRITE / WRITEA
3
2
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
PRE / PREA
REFA
Terminate Burst, Precharge
ILLEGAL
H
Op-Code, Mode-
Add
X
L
L
L
L
MRS
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
DESEL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
READ with
Auto-Precharge
X
NOP
BA
TERM
L
L
L
L
L
H
H
L
L
L
L
L
H
H
L
H
L
BA, CA, A10
BA, CA, A10
BA, RA
READ / READA
ILLEGAL for Same Bank
6
6
2
2
WRITE / WRITEA ILLEGAL for Same Bank
H
L
ACT
Bank Active / ILLEGAL
Precharge / ILLEGAL
ILLEGAL
BA, A10
X
PRE / PREA
REFA
H
Op-Code, Mode-
Add
X
L
L
L
L
MRS
ILLEGAL
H
L
X
H
X
H
X
H
DESEL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
WRITE with
Auto-Precharge
X
NOP
L
L
L
L
H
H
H
L
H
L
L
H
L
H
L
BA
TERM
BA, CA, A10
BA, CA, A10
BA, RA
READ / READA
WRITE / WRITEA ILLEGAL for Same Bank
ACT
ILLEGAL for Same Bank
7
7
2
H
Bank Active / ILLEGAL
Precharge / ILLEGAL
ILLEGAL
L
L
L
L
H
L
L
BA, A10
X
PRE / PREA
REFA
2
H
Op-Code, Mode-
Add
L
L
L
L
MRS
ILLEGAL
MITSUBISHI ELECTRIC
8
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command
Action
Notes
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP (Idle after tRP)
NOP (Idle after tRP)
ILLEGAL
PRE-
CHARGING
X
NOP
BA
TERM
2
2
2
4
X
H
L
BA, CA, A10
BA, RA
BA, A10
READ / WRITE
ACT
ILLEGAL
H
H
L
ILLEGAL
L
PRE / PREA
REFA
NOP (Idle after tRP)
ILLEGAL
L
H
X
Op-Code, Mode-
Add
X
L
L
L
L
MRS
ILLEGAL
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
DESEL
NOP (Row Active after tRCD)
NOP (Row Active after tRCD)
ILLEGAL
ROW
X
NOP
ACTIVATING
BA
TERM
2
2
2
2
X
H
L
BA, CA, A10
BA, RA
BA, A10
READ / WRITE
ACT
ILLEGAL
H
H
L
ILLEGAL
L
PRE / PREA
REFA
ILLEGAL
L
H
X
ILLEGAL
Op-Code, Mode-
Add
X
L
L
L
L
MRS
ILLEGAL
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
L
DESEL
NOP
WRITE RE-
COVERING
X
NOP
NOP
BA
TERM
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
2
2
2
2
X
H
L
BA, CA, A10
BA, RA
BA, A10
READ / WRITE
ACT
L
PRE / PREA
REFA
L
H
X
Op-Code, Mode-
Add
L
L
L
L
MRS
ILLEGAL
MITSUBISHI ELECTRIC
9
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command
Action
Notes
REFRESHING
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP (Idle after tRC)
NOP (Idle after tRC)
ILLEGAL
X
NOP
BA
TERM
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE
ACT
ILLEGAL
H
H
L
ILLEGAL
L
PRE / PREA
REFA
ILLEGAL
L
H
ILLEGAL
Op-Code, Mode-
Add
X
L
L
L
L
MRS
ILLEGAL
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
DESEL
NOP (Row Active after tRSC)
NOP (Row Active after tRSC)
ILLEGAL
MODE
REGISTER
SETTING
X
NOP
BA
TERM
X
H
L
BA, CA, A10
BA, RA
BA, A10
READ / WRITE
ACT
ILLEGAL
H
H
L
ILLEGAL
L
PRE / PREA
REFA
ILLEGAL
L
H
X
ILLEGAL
Op-Code, Mode-
Add
L
L
L
L
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
6. Refer to Read with Auto-Precharge in page 24.
7. Refer to Write with Auto-Precharge in page 26.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC
10
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
FUNCTION TRUTH TABLE for CKE
Current State CKE n-1 CKE n
/CS
X
H
L
/RAS
X
X
H
H
H
L
/CAS
X
X
H
H
L
/WE Address
Action
Notes
H
L
L
L
L
L
L
H
L
L
H
H
H
H
H
H
H
L
H
H
L
L
X
H
H
H
H
H
L
X
H
L
H
L
L
L
L
L
L
X
H
L
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
1
1
1
1
1
1
1
SELF-
REFRESHING
Exit Self-Refresh (Idle after tRC)
Exit Self-Refresh (Idle after tRC)
ILLEGAL
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
X
X
X
X
X
X
L
ILLEGAL
X
X
X
X
X
L
X
X
X
X
X
L
NOP (Maintain Self-Refresh)
INVALID
POWER
DOWN
Exit Power Down to Idle
NOP (Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
2
2
2
2
2
2
2
2
ALL BANKS
IDLE
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
Enter Power Down
L
ILLEGAL
L
X
X
X
X
X
X
X
ILLEGAL
L
X
X
X
X
X
X
ILLEGAL
X
X
X
X
X
X
X
X
X
X
Refer to Current State =Power Down
Refer to Function Truth Table
Begin CLK Suspend at Next Cycle
Exit CLK Suspend at Next Cycle
Maintain CLK Suspend
ANY STATE
other than listed
above
3
3
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MITSUBISHI ELECTRIC
11
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
SIMPLIFIED STATE DIAGRAM
POWER
PRE
APPLIED
POWER
PREA
SELF
CHARGE
ALL
REFRESH
ON
REFS
MRS
REFSX
MODE
REGISTER
SET
MRS
AUTO
REFA
IDLE
ACT
REFRESH
CKEL
CKEH
Active
POWER
DOWN
Power
Down
CKEL
CKEH
ROW
BURST
STOP
ACTIVE
WRITE
READ
READ
WRITE
WRITEA
READA
READ
WRITE
READ
TERM
WRITEA
READA
READA
PRE
WRITEA
READA
PRE
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
MITSUBISHI ELECTRIC
12
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or multifunctioning.
1. Apply VDD before or the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS
6. Issue MRS for the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable condition for 200 cycle
After these sequence, the DDR SDRAM is idle state and ready for normal operation.
CLK
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be
/CLK
programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command, which
may be issued when both banks are in idle state. After tMRD
from a MRS command, the DDR SDRAM is ready for new
command.
/CS
/RAS
/CAS
/WE
BA0
BA1
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
LTMODE
BL
0
0
0
0
0
0
DR
0
BT
V
A11-A0
BL
0 0 0
BT=0
R
BT=1
R
CL
0 0 0
/CAS Latency
R
0 0 1
0 1 0
2
4
2
4
0 0 1
0 1 0
R
2
Burst
Length
0 1 1
1 0 0
8
R
8
R
Latency
Mode
0 1 1
1 0 0
R
R
1 0 1
1 1 0
1 1 1
R
R
R
R
R
R
1 0 1
1 1 0
1 1 1
R
2.5
R
0
Sequential
Interleaved
Burst Type
1
0
NO
YES
DLL Reset
1
R: Reserved for Future Use
MITSUBISHI ELECTRIC
13
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
EXTENDED MODE REGISTER
DLL disable / enable mode can be programmed by setting the extended
mode register (EMRS). The extended mode register stores these data
until the next EMRS command, which may be issued when all banks are
in idle state. After tMRD from a EMRS command, the DDR SDRAM is
ready for new command.
CLK
/CLK
/CS
/RAS
/CAS
/WE
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BA0
DS DD
0
1
0
0
0
0
0
0
0
0
0
0
0
BA1
V
A11-A0
0
1
DLL Enable
DLL Disable
DLL Disable
Drive
Strength
0
1
Normal
Weak
MITSUBISHI ELECTRIC
14
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
/CLK
CLK
Read
Write
Y
Command
Address
Y
DQS
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Burst
Burst
CL= 2
BL= 4
/CAS
Length
Length
Latency
Initial Address BL
A2 A1 A0
Column Addressing
Interleaved
Sequential
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
1
2
3
4
5
6
7
0
1
2
2
3
4
5
6
7
0
1
2
3
3
4
5
6
7
0
1
2
3
0
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
1
0
3
2
5
4
7
6
1
0
2
3
0
1
6
7
4
5
2
3
3
2
1
0
7
6
5
4
3
2
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
1
1
0
1
2
3
3
0
0
1
1
2
2
3
3
2
0
1
1
0
-
-
-
-
0
1
0
1
1
0
0
1
1
0
MITSUBISHI ELECTRIC
15
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
VddQ
VI
Parameter
Supply Voltage
Conditions
Ratings
-0.5 ~ 3.7
-0.5 ~ 3.7
-0.5 ~ Vdd+0.5
-0.5 ~ VddQ+0.5
50
Unit
V
with respect to Vss
with respect to VssQ
with respect to Vss
with respect to VssQ
Supply Voltage for Output
Input Voltage
V
V
VO
Output Voltage
V
IO
Output Current
mA
mW
oC
Ta = 25 oC
Pd
Power Dissipation
Operating Temperature
Storage Temperature
1000
Topr
Tstg
0 ~ 70
oC
-65 ~ 150
DC OPERATING CONDITIONS
(Ta=0 ~ 70oC, unless otherwise noted)
Limits
Symbol
Parameter
Unit Notes
Min.
2.3
Typ.
2.5
Max.
2.7
Vdd
Supply Voltage
Supply Voltage for Output
Input Reference Voltage
V
V
VddQ
2.3
2.5
2.7
Vref
0.49*VddQ 0.50*VddQ 0.51*VddQ
V
V
V
V
V
V
5
VIH(DC)
VIL(DC)
VIN(DC)
High-Level Input Voltage
Low-Level Input Voltage
Input Voltage Level, CLK and /CLK
Vref + 0.15
-0.3
VddQ+0.3
Vref - 0.15
VddQ + 0.3
VddQ + 0.6
Vref + 0.04
-0.3
VID(DC) Input Differential Voltage, CLK and /CLK
VTT I/O Termination Voltage
0.36
7
6
Vref - 0.04
CAPACITANCE
(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Limits
Delta
Cap.(Max.)
Symbol
Parameter
Test Condition
Unit Notes
Min. Max.
CI(A)
CI(C)
CI(K)
CI/O
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CLK pin
VI=1.25v
2.0
2.0
2.0
4.0
3.0
3.0
3.0
5.0
pF
pF
pF
pF
11
11
11
11
0.50
f=100MHz
VI=25mVrms
0.25
0.50
I/O Capacitance, I/O, DQS, DM pin
MITSUBISHI ELECTRIC
16
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Limits(Max.)
Symbol
Parameter/Test Conditions
Organization
Unit
Notes
-75A
105
110
120
110
-75
105
110
120
110
-10
100
105
115
105
x4
x8
OPERATING CURRENT: One Bank; Active-Precharge; t RC = t RC MIN; t CK
IDD0 = t CK MIN; DQ, DM and DQS inputs changing twice per clock cycle; address
and control inputs changing once per clock cycle
x16
x4
OPERATING CURRENT: One Bank; Active-Read-Precharge;
IDD1 Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0mA;
Address and control inputs changing once per clock cycle
x8
115
135
115
135
110
130
x16
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-
IDD2P
x4/x8/x16
20
40
30
20
40
30
20
40
30
down mode; CKE <VIL (MAX); t CK = t CK MIN
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
IDD2F CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs changing x4/x8/x16
once per clock cycle
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; power-
down mode; CKE < VIL (MAX); t CK = t CK MIN
IDD3P
IDD3N
x4/x8/x16
x4/x8/x16
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN); One
bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN; DQ,DM and
DQS inputs changing twice per clock cycle; address and other control inputs
changing once per clock cycle
60
60
55
mA
65
65
60
75
75
70
x4
x8
150
170
210
145
165
200
185
150
170
210
145
165
200
185
140
160
200
135
155
180
175
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One bank active;
IDD4R Address and control inputs changing once per clock cycle;CL=2.5; t CK = t CK
MIN; IOUT = 0 mA
x16
x4
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active;
IDD4W Address and control inputs changing once per clock cycle; CL=2.5; t CK = t CK
MIN;DQ, DM and DQS inputs changing twice per clock cycle
x8
x16
IDD5 AUTO REFRESH CURRENT: t RC = t RFC (MIN)
IDD6 SELF REFRESH CURRENT: CKE < 0.2V
x4/x8/x16
x4/x8/x16
3
3
3
x4
x8
250
260
290
250
260
290
230
240
280
20
20
20
OPERATING CURRENT-Four bank Operation: Four bank interleaving with
BL=4 -Refer to the Notes 20
IDD7
x16
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Limits
Symbol
Parameter / Test Conditions
Unit
Notes
Min.
Max.
VIH(AC) High-Level Input Voltage (AC)
Vref + 0.31
V
V
V
V
VIL(AC) Low-Level Input Voltage (AC)
Vref - 0.31
VddQ + 0.6
VID(AC) Input Differential Voltage, CLK and /CLK
VIX(AC) Input Crossing Point Voltage, CLK and /CLK
IOZ Off-state Output Current /Q floating Vo=0~VddQ
0.7
7
8
0.5*VddQ - 0.2 0.5*VddQ + 0.2
-5
-2
5
2
A
A
m
m
II
Input Current / VIN=0 ~ VddQ
IOH Output High Current (VOUT = VTT+0.84V)
IOL Output High Current (VOUT = VTT-0.84V)
-16.8
16.8
mA
mA
MITSUBISHI ELECTRIC
17
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
AC TIMING REQUIREMENTS
(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)
-75A
-75
-10
Symbol
tAC
AC Characteristics Parameter
Unit Notes
Min.
Max
0.75
Min.
Max
0.75
Min.
-0.8
Max
0.8
DQ Output Valid data delay time from CLK//CLK
-0.75
-0.75
ns
ns
tDQSCK DQ Output Valid data delay time from CLK//CLK
-0.75
0.45
0.45
7.5
0.75
0.55
0.55
15
-0.75
0.45
0.45
7.5
0.75
0.55
0.55
15
-0.8
0.45
0.45
8
0.8
0.55
0.55
15
tCH
tCL
CLK High level width
CLK Low level width
tCK
tCK
ns
CL=2.5
CL=2
tCK
CLK cycle time
7.5
15
10
15
10
15
ns
tDS
Input Setup time (DQ,DM)
Input Hold time(DQ,DM)
0.5
0.5
0.6
0.6
2
ns
tDH
0.5
0.5
ns
tDIPW DQ and DM input pulse width (for each input)
1.75
-0.75
-0.75
1.75
-0.75
-0.75
ns
tHZ
tLZ
Data-out-high impedance time from CLK//CLK
Data-out-low impedance time from CLK//CLK
0.75
0.75
0.5
0.75
0.75
0.5
-0.8
-0.8
0.8
0.8
0.6
ns
ns
ns
14
14
tDQSQ DQ Valid data delay time from DQS
tCLmin or
tCHmin
tCLmin or
tCHmin
tCLmin or
tCHmin
tHP
Clock half period
ns
tQH
Output DQS valid window
tHP-0.75
0.75
0.35
0.35
0.2
tHP-0.75
0.75
0.35
0.35
0.2
tHP-1.0
0.75
0.35
0.35
0.2
ns
tDQSS Write command to first DQS latching transition
tDQSH DQS input High level width
tDQSL DQS input Low level width
tDSS DQS falling edge to CLK setup time
tDSH DQS falling edge hold time from CLK
tMRD Mode Register Set command cycle time
tWPRES Write preamble setup time
tWPST Write postamble
1.25
1.25
1.25
tCK
tCK
tCK
tCK
tCK
ns
0.2
0.2
0.2
15
15
15
0
0
0
ns
16
15
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tCK
ns
tWPRE Write preamble
0.25
0.9
0.25
0.9
0.25
1.1
tIS
Input Setup time (address and control)
Input Hold time (address and control)
19
19
tIH
0.9
0.9
1.1
ns
tRPST Read postamble
tRPRE Read preamble
0.4
0.6
1.1
0.4
0.6
1.1
0.4
0.6
1.1
tCK
tCK
0.9
0.9
0.9
MITSUBISHI ELECTRIC
18
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
AC TIMING REQUIREMENTS(Continues)
(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)
-75A
-75
-10
Symbol
AC Characteristics Parameter
Unit
Notes
Min.
45
Max
120,000
Min.
45
Max
120,000
Min.
50
Max
120,000
tRAS Row Active time
ns
ns
tRC
Row Cycle time(operation)
65
65
70
tRFC Auto Ref. to Active/Auto Ref. command period
tRCD Row to Column Delay
75
20
20
15
15
35
1
75
20
20
15
15
35
1
80
20
20
15
15
35
1
ns
ns
tRP
Row Precharge time
ns
tRRD Act to Act Delay time
ns
tWR Write Recovery time
ns
tDAL Auto Precharge write recovery + precharge time
tWTR Internal Write to Read Command Delay
tXSNR Exit Self Ref. to non-Read command
tXSRD Exit Self Ref. to -Read command
tXPNR Exit Power down to command
tXPRD Exit Power down to -Read command
tREFI Average Periodic Refresh interval
ns
tCK
ns
75
200
1
75
200
1
80
200
1
tCK
tCK
tCK
1
1
1
18
17
7.8
7.8
7.8
s
m
Output Load Condition
VREF
VREF
DQS
VTT=VREF
DQ
50W
OUT
V
Zo=50W
VREF
30pF
Output Timing
Measurement
Reference Point
MITSUBISHI ELECTRIC
19
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
Notes
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the
range between VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively
switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5*VddQ of the transmittingdevice, and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed +2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be
set equal to VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level
of the same.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is properly initialized.
11. This parameter is sampled. VddQ = 2.5V+0.2V, Vdd = 2.5V + 0.2V , f = 100 MHz, Ta = 25oC, VOUT(DC) =
VddQ/2, VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that they are
matched in loading (to facilitate trace matching at the board level).
12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK
cross; the input reference level for signals other than CLK//CLK, is VREF.
13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes,
CKE< 0.3VddQ is recognized as LOW.
14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving
(LZ).
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before
this CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a
previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time,
depending on tDQSS.
17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.
19. For command/address and CK & /CK slew rate > 1.0V/ns.
20. IDD7 : Operating current:Four Bank
For Bank are being interleaved with tRC(min),Burst Mode,Address and Control inputs on NOP edge are not
changing.Iout = 0mA
Timing patterns:
tCK=min,tRRD=2*tCK,BL=4,tRCD=3*tCK,Read with Autoprecharge
Read:A0 N A1 R0 A2 R1 N R3 A0 N A1 R0 – repeat the same timing with random address changing
*100% of data changing at every burst
Legend: A=Activate,R=Read,P=Precharge,N=NOP
MITSUBISHI ELECTRIC
20
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
Jun. '01 Preliminary
Read Operation
tCK
tCH
tCL
/CLK
CLK
tIS tIH
Valid Data
tRPST
Cmd &
Add.
VREF
tDQSCK
tQH
tRPRE
DQS
tDQSQ
DQ
tAC
Write Operation / tDQSS=max.
/CLK
CLK
tDQSS
tWPST
tDSS
tWPRES
DQS
tDQSL
tDS
tDQSH
tDH
tWPRE
DQ
Write Operation / tDQSS=min.
/CLK
CLK
tDSH
tDQSS
tWPST
tWPRES
DQS
tDQSL
tDS
tDQSH
tDH
tWPRE
DQ
MITSUBISHI ELECTRIC
21
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank addresses (BA0,1). A row is indicated by the row address A12-0. The minimum activation
interval between one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the
precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same time. After
tRP from the precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=8, CL=2)
/CLK
CLK
2 ACT command / tRCmin
tRCmin
ACT
ACT READ
PRE
ACT
Xb
Command
A0-9,11
tRP
tRRD
tRAS
BL/2
Xa
Xb
tRCD
Y
0
Xa
00
Xb
1
Xb
01
A10
BA0,1
01
00
DQS
DQ
Q a 0
Q a 1
Q a 2
Q a 3
Q a 4
Q a 5
Q a 6
Q a 7
Precharge all
A precharge command can be issued at BL/2 from a read command without data loss.
MITSUBISHI ELECTRIC
22
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
READ
After tRCD from the bank activation, a READ command can be issued. 1st Output data is available
after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length
is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8)/A8-A0(x16), and the address
sequence of burst data is defined by the Burst Type. A READ command may be applied to any
active bank, so the row precharge time (tRP) can be hidden behind continuous output data by
interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge
(READA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till
the internal precharge is complete. The internal precharge starts at BL/2 after READA. The next
ACT command can be issued after (BL/2+tRP) from the previous READA.
Multi Bank Interleaving READ (BL=8, CL=2)
/CLK
CLK
Command
A0-9,11
A10
ACT
Xa
READ ACT
READ PRE
tRCD
Y
0
Xb
Xb
Y
Xa
0
0
00
00
10
10
00
BA0,1
DQS
DQ
Q a 0
Q a 1
Q a 2
Q a 3
Q a 4
Q a 5
Q a 6
Q a 7
Qb0
Qb1
Qb2
Qb3
Qb4
Qb5
Qb7
Qb8
Burst Length
/CAS latency
MITSUBISHI ELECTRIC
23
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
READ with Auto-Precharge (BL=8, CL=2,2.5)
0
1
2
3
4
5
6
7
8
9
10
11
12
/CLK
CLK
BL/2 + tRP
Command
ACT
READA
tRCD
BL/2
tRP
Xa
Xa
00
Y
1
A0-9,11
A10
00
BA0,1
DQS
CL=2
Q a 0
Q a 1
Q a 2
Q a 3
Q a 4 Q a 5
Q a 6
Q a 7
DQ
DQS
CL=2.5
Q a 0
Q a 1
Q a 2
Q a 3
Q a 4
Q a 5
Q a 6
Q a 7
DQ
Internal Precharge Start Timing
For Different Bank
Asserted
Command
3
4
5
6
7
8
9
10
READ
Legal
Legal
Legal
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Legal Legal
Legal Legal
Legal Legal Legal
Legal Legal Legal
READA
WRITE(CL=2)
WRITE(CL=2.5)
WRITEA(CL=2)
Illegal Illegal Illegal Illegal Illegal Legal Legal Legal
Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal
Illegal Illegal Illegal Illegal Illegal Legal Legal Legal
WRITEA(CL=2.5) Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal
ACT
PCG
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Legal
Legal
Legal
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Legal Legal
Legal Legal
Legal Legal Legal
Legal Legal Legal
Operating description when new command asserted.
MITSUBISHI ELECTRIC
24
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from
the WRITE command with data strobe input, following (BL-1) data are written into RAM, when
the Burst Length is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8)/A8-A0(x16),
and the address sequence of burst data is defined by the Burst Type. A WRITE command may be
applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input
data by interleaving the multiple banks. From the last data to the PRE command, the write recovery
time (tWRP) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The next ACT command can be issued after tDAL from the last input data
cycle.
Multi Bank Interleaving WRITE (BL=8)
/CLK
CLK
ACT
Xa
WRITE ACT
WRITE
PRE
Command
A0-9,11
PRE
tRCD
tRCD
Ya
0
Xb
Xb
10
Yb
0
Xa
Xa
0
0
A10
BA0,1
10
00
00
10
00
DQS
DQ
D a 0
D a 1
D a 2
D a 3
D a 4
D a 5
D a 6
D a 7
Db0
Db1
Db2
Db3
Db4
Db5
Db6
Db7
MITSUBISHI ELECTRIC
25
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
WRITE with Auto-Precharge (BL=8)
0
1
2
3
4
5
6
7
8
9
10
11
12
/CLK
CLK
ACT
WRITEA
Y
ACT
Xb
Command
tDAL
tRC
Xa
A0-9,11
Xa
1
Xb
00
A10
00
00
BA0,1
DQS
DQ
D a 0
D a 1
D a 2 D a 3
D a 4
D a 5
D a 6
D a 7
Asserted
For Different Bank
Command
3
4
5
6
7
8
9
10
READ
READA
WRITE
WRITEA
ACT
Illegal Illegal
Illegal Illegal
Illegal Illegal Illegal
Illegal Illegal Illegal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
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Legal
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Legal
Legal
PCG
Operating description when new command asserted.
MITSUBISHI ELECTRIC
26
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
Read Interrupted by Read (BL=8, CL=2)
/CLK
CLK
Command
A0-9,11
A10
READ READ
READ
Yk
READ
Yi
0
Yj
0
Yl
0
0
00
00
10
01
BA0,1
DQS
Qai0 Qai1 Qaj0 Qaj1
Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2
Qal3 Qal4 Qal5 Qal6 Qal7
DQ
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to PRE interval determines valid data length to be output. The figure below
shows examples of BL=8.
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
DQ
Q0
Q1
Q1
Q1
Q2
Q3
Q4
Q5
Command
DQS
READ
PRE
CL=2.5
Q0
Q2
Q3
DQ
Command
READ PRE
DQS
DQ
Q0
MITSUBISHI ELECTRIC
27
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
DQ
Q0
Q1
Q2
Q3
Q4
Q5
PRE
Command
DQS
READ
CL=2.0
Q0
Q1
Q2
Q3
DQ
Command
DQS
READ PRE
Q0
Q1
DQ
MITSUBISHI ELECTRIC
28
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
[Read Interrupted by Burst Stop]
Burst read operation can be interrupted by a burst stop command(TERM). READ to TERM interval
is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to TERM interval determines valid data length to be output. The figure below
shows examples of BL=8.
Read Interrupted by TERM (BL=8)
/CLK
CLK
TERM
READ
READ
READ
Command
DQS
Q0
Q1
Q2
Q3
Q4
Q5
DQ
TERM
Command
DQS
DQ
CL=2.5
Q0
Q1
Q2
Q3
TERM
Command
DQS
DQ
Q0
Q1
READ
TERM
Command
DQS
Q0
Q1
Q2
Q3
Q4 Q5
DQ
TERM
READ
Command
DQS
CL=2.0
Q0
Q1
Q2
Q3
DQ
READ TERM
Command
DQS
DQ
Q0
Q1
MITSUBISHI ELECTRIC
29
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
[Read Interrupted by Write with TERM]
Read Interrupted by TERM (BL=8)
/CLK
CLK
Command
READ
TERM
WRITE
DQS
DQ
CL=2.5
CL=2.0
Q0
Q1
Q2
Q3
D 0 D1
D2
D3
D4 D5
Command
READ
TERM
WRITE
DQS
DQ
D0
D1
D2
D3
D4
D5
D6 D7
Q0
Q1
Q2
Q3
MITSUBISHI ELECTRIC
30
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
[Write interrupted by Write]
Burst write operation can be interrupted by write of any bank. Random column access is allowed.
WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=8)
/CLK
CLK
WRITE WRITE
WRITE
Yk
WRITE
Yl
Command
A0-9,11
Yi
Yj
A10
0
0
0
0
BA0,1
00
00
10
00
DQS
DQ
Dai1 Daj0
Daj1 Daj2 Daj3 Dak0 Dak1 Dak2 Dak3 Dak4 Dak5 Dal0
Dal1 Dal2 Dal3 Dal4 Dal5 Dal6
Dal7
Dai0
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column
access is allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The
input data on DQ at the interrupting READ cycle is "don't care". tWTR is referenced from the first
positive edge after the last data input.
Write Interrupted by Read (BL=8, CL=2.5)
/CLK
CLK
READ
WRITE
Command
A0-9,11
Yi
0
Yj
0
A10
BA0,1
00
00
DM
tWTR
QS
Dai0
Dai1
Qaj0
Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6
Qaj7
DQ
MITSUBISHI ELECTRIC
31
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
[Write interrupted by Precharge]
Burst write operation can be interrupted by precharge of the same or all bank. Random column
access is allowed. tWR is referenced from the first positive CLK edge after the last data input.
Write Interrupted by Precharge (BL=8, CL=2.5)
/CLK
CLK
WRITE
Yi
PRE
Command
A0-9,11
A10
0
00
00
BA0,1
DM
tWR
QS
Dai0
Dai1
DQ
MITSUBISHI ELECTRIC
32
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
[Initialize and Mode Register sets]
Initialize and MRS
/CLK
CLK
CKE
Command
A0-9,11
NOP
PRE
EMRS
Code
MRS
Code
PRE
AR
AR
MRS
ACT
Xa
Code
1 0
Code
0 0
Code
0 0
Xa
Xa
1
1
A10
BA0,1
DQS
DQ
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
Extended Mode
Register Set
Mode Register Set,
Reset DLL
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H)
command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh
256Mbits memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing
an auto refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum
tRFC . Any command must not be supplied to the device before tRFC from the REFA command.
Auto-Refresh
/CLK
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
tRFC
A0-11
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
MITSUBISHI ELECTRIC
33
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
[SELF REFRESH]
Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-
refresh mode, CKE is asynchronous and the only enable input, all other inputs including CLK are
disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the
self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting
CKE for longer than tXSNR/tXSRD.
Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
X
X
Y
Y
A0-11
BA0,1
tXSRD
tXSNR
Self Refresh Exit
MITSUBISHI ELECTRIC
34
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous input except during the self-
refresh mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time
is NOT required in the condition of the stable CLK operation during the power down mode.
Power Down by CKE
/CLK
CLK
Standby Power Down
CKE
Command
PRE
NOP
NOP
NOP
Valid
tXPNR/tXPRD
Active Power Down
CKE
Command
ACT NOP
Valid
[DM CONTROL]
DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM
to write mask latency is 0.
DM Function(BL=8,CL=2)
/CLK
CLK
Command
DM
READ
WRITE
Don't Care
DQS
DQ
Q0
Q1
Q2
Q3
Q4
Q5 Q6
D0 D1
D3 D4
D5 D6
D7
masked by DM=H
MITSUBISHI ELECTRIC
35
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,
but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal
injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii)
prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor
product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or
any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights,
originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms
represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that
customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the
latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric
Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the
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When using any or all of the information contained in these materials, including product data, diagrams, charts, programs,
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Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is
used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further
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MITSUBISHI ELECTRIC
36
DDR SDRAM (Rev.1.2)
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
Jun. '01 Preliminary
256 M Double Data Rate Synchronous DRAM
Revision History
Rev. Date
Description
1.02
1.1
May ’01
Jun.’01
-New registration (May. ‘01)
-Added -75A Spec.
-Added IDD7 Spec.
-Changed VIH(DC)min Spec. from Vref+0.18V to Vref+0.15V
-Changed VIL(DC)min Spec. from Vref-0.18V to Vref-0.15V
-Changed VIH(AC)min Spec. from Vref+0.35V to Vref+0.31V
-Changed VIL(AC)max Spec. from Vref-0.35V to Vref-0.31V
-Changed IOH Spec. from -15.2mA to -16.8mA
-Changed IOL Spec. from +15.2mA to +16.8mA
1.2
Jun.’01
-Added Operating description Table when new command asserted while
write & read with auto precharge is issued.
MITSUBISHI ELECTRIC
37
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