MT9160AS [MITEL]
ISO2-CMOS 5 Volt Multi-Featured Codec (MFC); ISO2 - CMOS 5伏多功能的编解码器（ MFC）
| 型号： | MT9160AS |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| 文件： | 总28页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO2-CMOS MT9160
5 Volt Multi-Featured Codec (MFC)
Preliminary Information
ISSUE 3
May 1995
Features
Ordering Information
•
•
Programmable µ-Law/A-Law Codec and Filters
MT9160AE
MT9160AS
24 Pin Plastic DIP
20 Pin SOIC
Programmable CCITT (G.711)/sign-magnitude
coding
•
•
Programmable transmit, receive and side-tone
gains
-40°C to +85°C
Description
Fully differential interface to handset
transducers - including 300 ohm receiver driver
•
•
•
•
•
Flexible digital interface including ST-BUS/SSI
Serial microport or default controllerless mode
Single 5 volt supply
The MT9160 5V Multi-featured Codec incorporates a
built-in Filter/Codec, gain control and programmable
sidetone path as well as on-chip anti-alias filters,
reference voltage and bias source. The device
supports both A-Law and µ-Law requirements.
Low power operation
CCITT G.714 compliant
Complete telephony interfaces are provided for
connection to handset transducers. Internal register
access is provided through a serial microport
Applications
compatible
micro-controllers.
controllerless operation utilizing the default register
conditions.
with
various
industry
standard
•
•
•
•
•
Digital telephone sets
Cellular radio sets
The device also supports
Local area communications stations
Pair Gain Systems
2
The MT9160 is fabricated in Mitel's ISO -CMOS
technology ensuring low power consumption and
high reliability.
Line cards
VSSD
VDD
FILTER/CODEC GAIN
M -
ENCODER
DECODER
7dB
VSSA
M +
-7dB
Transducer
Interface
VBias
VRef
HSPKR +
HSPKR -
Din
Timing
Dout
STB/F0i
Flexible
Digital
Interface
ST-BUS
C & D
Channels
CLOCKin
Serial Microport
A/µ/IRQ
IC
CS
DATA1 DATA2
SCLK
PWRST
Figure 1 - Functional Block Diagram
7-77
MT9160
Preliminary Information
1
2
3
4
5
6
7
8
VBias
VRef
PWRST
M +
M -
20
19
18
17
16
15
14
13
12
11
VSSA
HSPKR +
HSPKR -
VDD
CLOCKin
STB/F0i
Din
IC
A/µ/IRQ
VSSD
CS
SCLK
DATA1
DATA2
20 PIN SOIC
9
10
Dout
VBias
VRef
NC
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
M +
M -
VSSA
NC
HSPKR +
HSPKR -
VDD
CLOCKin
NC
STB/F0i
PWRST
IC
A/µ/IRQ
VSSD
CS
24 PIN PDIP
NC
9
SCLK
DATA1
DATA2
10
11
12
Din
Dout
Figure 2 - Pin Connections
Description
Pin Description
Pin #
Name
SOIC DIP
1
1
V
Bias Voltage (Output). (V /2) volts is available at this pin for biasing external
DD
Bias
amplifiers. Connect 0.1 µF capacitor to V
.
SSA
2
2
V
Reference Voltage for Codec (Output). Nominally [(V /2)-1.5] volts. Used
DD
Ref
internally. Connect 0.1 µF capacitor to V
.
SSA
3
4
5
4
5
6
PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).
IC Internal Connection. Tie externally to V for normal operation.
A/µ/IRQ A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin governs
SS
the companding law used by the filter/Codec; µ-Law when tied to V and A-Law
SS
when tied to V . Logically OR’ed with A/µ register bit.
DD
IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.
6
7
7
8
V
Digital Ground. Nominally 0 volts.
SSD
CS
Chip Select (Input). This input signal is used to select the device for microport data
transfers. Active low. TTL level compatible.
8
9
10
11
SCLK
Serial Port Synchronous Clock (Input). Data clock for microport. TTL level
compatible.
DATA 1 Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/
National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input TTL level compatible.
10
12
DATA 2 Serial Data Receive. In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input TTL level compatible.
7-78
Preliminary Information
MT9160
Pin Description (continued)
Pin #
Name
Description
SOIC DIP
11
12
13
14
13
14
15
17
D
Data Output. A high impedance three-state digital output for 8 bit wide channel data
being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent with
the rising edge of the bit clock during the timeslot defined by STB, or according to
standard ST-BUS timing.
out
D
Data Input. A digital input for 8 bit wide channel data received from the Layer 1
transceiver. Data is sampled on the falling edge of the bit clock during the timeslot
defined by STB, or according to standard ST-BUS timing. Input level is CMOS
compatible.
in
STB/F0i Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit
timeslot used by the device for both transmit and receive data. This active high signal
has a repetition rate of 8 kHz. Standard frame pulse definitions apply in ST-BUS
mode (refer to Figure 11). CMOS level compatible input.
CLOCKin Clock (Input). (CMOS level compatible). The clock provided to this input pin is used
for the internal device functions. For SSI mode connect the bit clock to this pin when
it is 512 kHz or greater. Connect a 4096 kHz clock to this input when the available bit
clock is 128 kHz or 256 kHz. For ST-BUS mode connect C4i to this pin.
15
16
17
18
19
20
V
Positive Power Supply (Input). Nominally 5 volts.
DD
HSPKR- Inverting Handset Speaker (Output). Output to the handset speaker (balanced).
HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker
(balanced).
18
19
22
23
V
Analog Ground (Input). Nominally 0 volts.
SSA
M-
M+
NC
Inverting Microphone (Input). Inverting input to microphone amplifier from the
handset microphone.
20
24
Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier
from the handset microphone.
3,9,
No Connect. (DIP Package only).
16,21
7-79
MT9160
Preliminary Information
design. This fully differential architecture is
continued into the Transducer Interface section to
provide full chip realization of these capabilities for
the handset functions.
Overview
The 5V Multi-featured Codec (MFC) features
complete
Analog/Digital
and
Digital/Analog
conversion of audio signals (Filter/Codec) and an
analog interface to a standard handset transmitter
and receiver (Transducer Interface). The receiver
amplifier is capable of driving a 300 ohm load.
A reference voltage (V ), for the conversion
requirements of the Codec section, and a bias
Ref
voltage (V
), for biasing the internal analog
Bias
sections, are both generated on-chip. V
is also
Bias
brought to an external pin so that it may be used for
biasing external gain setting amplifiers. A 0.1µF
Each of the programmable parameters within the
functional blocks is accessed through a serial
capacitor must be connected from V
ground at all times. Likewise, although V
to analog
may only
®
Bias
microcontroller port compatible with Intel MCS-51 ,
®
Ref
Motorola SPI
Microwire
and National Semiconductor
These parameters
be used internally, a 0.1µF capacitor from the V
®
Ref
specifications.
pin to ground is required at all times. The analog
ground reference point for these two capacitors must
be physically the same point. To facilitate this the
include: gain control, power down, mute, B-Channel
select (ST-BUS mode), C&D channel control/access,
law control, digital interface programming and
loopback. Optionally the device may be used in a
controllerless mode utilizing the power-on default
settings.
V
and V
pins are situated on adjacent pins.
Ref
Bias
The transmit filter is designed to meet CCITT G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0 dB). Gain control allows the output
signal to be increased up to 7 dB. An anti-aliasing
filter is included. This is a second order lowpass
implementation with a corner frequency at 25 kHz.
Functional Description
Filter/Codec
The receive filter is designed to meet CCITT G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0dB). Gain control allows the output
signal to be attenuated up to 7 dB. Filter response is
peaked to compensate for the sinx/x attenuation
caused by the 8 kHz sampling rate.
The Filter/Codec block implements conversion of the
analog 0-3.3 kHz speech signals to/from the digital
domain compatible with 64 kb/s PCM B-Channels.
Selection of companding curves and digital code
assignment are programmable. These are CCITT
G.711 A-law or µ-Law, with true-sign/ Alternate Digit
Inversion or true-sign/Inverted Magnitude coding,
respectively. Optionally, sign- magnitude coding may
also be selected for proprietary applications.
Side-tone is derived from the input of the Tx filter and
is not subject to the gain control of the Tx filter
section. Side-tone is summed into the receive
handset transducer driver path after the Rx filter gain
control section so that Rx gain adjustment will not
affect side-tone levels. The side-tone path may be
enabled/disabled with the gain control bits located in
Gain Control Register 2 (address 01h).
The Filter/Codec block also implements transmit and
receive audio path gains in the analog domain. A
programmable gain, voice side-tone path is also
included to provide proportional transmit speech
feedback to the handset receiver. This side tone path
feature is disabled by default. Figure 3 depicts the
nominal half-channel and side-tone gains for the
MT9160.
Transmit and receive filter gains are controlled by the
TxFG -TxFG
and RxFG -RxFG
control bits,
0
2
0
2
respectively. These are located in Gain Control
Register 1 (address 00h). Transmit filter gain is
adjustable from 0 dB to +7 dB and receive filter gain
from 0dB to -7 dB, both in 1 dB increments.
In the event of PWRST, the MT9160 defaults such
that the side-tone path is off, all programmable gains
are set to 0dB and CCITT µ-Law is selected. Further,
the digital port is set to SSI mode operation at 2048
kb/s and the FDI and driver sections are powered up.
(See Microport section.)
Side-tone filter gain is controlled by the STG -STG
0
2
control bits located in Gain Control Register 2
(address 01h). Side-tone gain is adjustable from
-9.96 dB to +9.96 dB in 3.32 dB increments.
The internal architecture is fully differential to provide
the best possible noise rejection as well as to allow a
wide dynamic range from a single 5 volt supply
Intel® and MCS-51® are registered trademarks of Intel Corporation
Motorola® and SPI® are registered trademarks of Motorola Corporation
National® and Microwire® are trademarks of National Semiconductor Corporation
7-80
Preliminary Information
MT9160
Companding law selection for the Filter/Codec is
provided by the A/µ companding control bit while
the coding scheme is controlled by the Smag/CCITT
control bit. The A/µ control bit is logically OR’ed with
the A/µ pin providing access in both controller and
controllerless modes. Both A/µ and Smag/CCITT
reside in Control Register 2 (address 04h). Table 1
illustrates these choices.
Control of this gain is provided by the TxINC
control bit (Gain Control register 1, address 00h).
• The handset speaker outputs (receiver), pins
HSPKR+/HSPKR-.This internally compensated
fully differential output driver is capable of driving
the load shown in Figure 4. The nominal handset
receive path gain may be adjusted to either 0 dB,
-6 dB or -12 dB. Control of this gain is provided
by the RxINC control bit (Gain Control register 1,
address 00h). This gain adjustment is in addition
to the programmable gain provided by the receive
filter.
CCITT (G.711)
Sign/
Code
Magnitude
µ-Law
A-Law
+ Full Scale
+ Zero
1111 1111
1000 0000
0000 0000
1000 0000
1111 1111
0111 1111
1010 1010
1101 0101
0101 0101
-Zero
(quiet code)
HSPKR +
- Full Scale
0111 1111
0000 0000
0010 1010
75 Ω
Table 1
Transducer Interfaces
150 ohm
load
MT9160
(speaker)
Standard handset transducer interfaces are provided
by the MT9160. These are:
75 Ω
• The handset microphone inputs (transmitter),
pins M+/M-. The nominal transmit amplifier gain
may be adjusted to either 6.0 dB or 15.3 dB.
HSPKR -
Figure 4 - Handset Speaker Driver
Filter/Codec and Transducer Interface
Serial Port
Default Bypass
HSPKR +
-6.0 dB or
0 dB
Receiver
Driver
Receive
Filter Gain
0 to -7 dB
(1 dB steps)
Handset
Receiver
(150Ω)
PCM
75Ω
HSPKR -
-6 dB
D
in
75Ω
Side-tone
-9.96 to
+9. 96 dB
(3.32 dB steps)
-11 dB
PCM
M+
M-
Transmit
Transmit Filter
Transmitter
Microphone
Transmit Gain
Gain
Gain
-0.37 dB or 8.93 dB
0 to +7 dB
(1 dB steps)
D
6.37 dB
out
INTERNAL TO DEVICE
EXTERNAL TO DEVICE
Figure 3 - Audio Gain Partitioning
7-81
MT9160
Preliminary Information
Microport
these two schemes for normal data bytes. However,
to ensure
decoding of the R/W and address
information, the Command/Address byte is defined
differently for Intel operation than it is for Motorola/
National operation. Refer to the relative timing
diagrams of Figures 5 and 6.
The serial microport, compatible with Intel MCS-51
(mode 0), Motorola SPI (CPOL=0,CPHA=0) and
National Semiconductor Microwire specifications
provides access to all MT9160 internal read and
write registers. This microport consists of a transmit/
receive data pin (DATA1), a receive data pin
(DATA2), a chip select pin (CS) and a synchronous
data clock pin (SCLK). For D-channel contention
control, in ST-BUS mode, this interface provides an
open-drain interrupt output (IRQ).
Receive data is sampled on the rising edge of SCLK
while transmit data is made available concurrent with
the falling edge of SCLK.
Flexible Digital Interface
The microport dynamically senses the state of the
serial clock (SCLK) each time chip select becomes
active. The device then automatically adjusts its
internal timing and pin configuration to conform to
Intel or Motorola/National requirements. If SCLK is
high during chip select activation then Intel mode 0
timing is assumed. The DATA1 pin is defined as a
bi-directional (transmit/receive) serial port and
DATA2 is internally disconnected. If SCLK is low
during chip select activation then Motorola/National
timing is assumed. Motorola processor mode
CPOL=0, CPHA=0 must be used. DATA1 is defined
as the data transmit pin while DATA2 becomes the
data receive pin. Although the dual port Motorola
controller configuration usually supports full-duplex
communication, only half-duplex communication is
possible in the MT9160. The micro must discard
non-valid data which it clocks in during a valid write
transfer to the MT9160. During a valid read transfer
from the MT9160 data simultaneously clocked out by
the micro is ignored by the MT9160.
A serial link is required to transport data between the
MT9160 and an external digital transmission device.
The MT9160 utilizes the ST-BUS architecture
defined by Mitel Semiconductor but also supports a
strobed data interface found on many standard
Codec devices. This interface is commonly referred
to as Synchronous Serial Interface (SSI). The
combination of ST-BUS and SSI provides a Flexible
Digital Interface (FDI) capable of supporting all Mitel
basic rate transmission devices as well as many
other 2B+D transceivers.
The required mode of operation is selected via the
CSL2-0 control bits (Control Register 2, address
04h). Pin definitions alter dependent upon the
operational mode selected, as described in the
following subsections as well as in the Pin
Description tables.
Quiet Code
All data transfers through the microport are two-byte
transfers requiring the transmission of a Command/
Address byte followed by the data byte written or
read from the addressed register. CS must remain
asserted for the duration of this two-byte transfer. As
shown in Figures 5 and 6 the falling edge of CS
indicates to the MT9160 that a microport transfer is
about to begin. The first 8 clock cycles of SCLK after
the falling edge of CS are always used to receive the
Command/Address byte from the microcontroller.
The Command/Address byte contains information
detailing whether the second byte transfer will be a
read or a write operation and at what address. The
next 8 clock cycles are used to transfer the data byte
between the MT9160 and the microcontroller. At the
end of the two-byte transfer CS is brought high again
to terminate the session. The rising edge of CS will
tri-state the output driver of DATA1 which will remain
tri-stated as long as CS is high.
The FDI can be made to send quiet code to the
decoder and receive filter path by setting the RxMute
bit high. Likewise, the FDI will send quiet code in the
transmit path when the TxMute bit is high. Both of
these control bits reside in Control Register 1 at
address 03h. When either of these bits are low their
respective paths function normally. The -Zero entry
of Table 1 is used for the quiet code definition.
ST-BUS Mode
The ST-BUS consists of output (DSTo) and input
(DSTi) serial data streams, in FDI these are named
Dout and Din respectively, a synchronous clock input
signal CLOCKin (C4i), and a framing pulse input
(F0i). These signals are direct connections to the
corresponding pins of Mitel basic rate devices. The
CSL2, CSL1 and CSL0 bits are set to 1 for ST-BUS
operation.
Intel processors utilize least significant bit first
transmission while Motorola/National processors
employ most significant bit first transmission. The
MT9160 microport automatically accommodates
7-82
Preliminary Information
MT9160
The data streams operate at 2048 kb/s and are Time
Division Multiplexed into 32 identical channels of 64
kb/s bandwidth. A frame pulse (a 244 nSec low going
pulse) is used to parse the continuous serial data
streams into the 32 channel TDM frames. Each
frame has a 125 µSecond period translating into an 8
kHz frame rate. A valid frame begins when F0i is
logic low coincident with a falling edge of C4i. Refer
to Figure 11 for detailed ST-BUS timing. C4i has a
frequency (4096 kHz) which is twice the data rate.
This clock is used to sample the data at the 3/4
bit-cell position on DSTi and to make data available
on DSTo at the start of the bit-cell. C4i is also used to
clock the MT9160 internal functions (i.e., Filter/
➃
➄
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
➀
➀
DATA 1
RECEIVE
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
DATA 1
TRANSMIT
②
SCLK
CS
➃
➂
➂
➀
②
Delays due to internal processor timing which are transparent.
The MT9160:-latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
➂
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
➃
➄
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
D7
D0
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
3 bits - Addressing Data
X
X
X
X
A2
A1
A0
R/W
4 bits - Unused
Figure 5 - Serial Port Relative Timing for Intel Mode 0
➃
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
➄
➀
➀
DATA 2
RECEIVE
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DATA 1
TRANSMIT
②
SCLK
CS
➃
➂
➂
➀
②
Delays due to internal processor timing which are transparent .
The MT9160:-latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
➂
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
➃
➄
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
D7
D0
X
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
A2
R/W
X
X
X
A1
A0
Figure 6 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
7-83
MT9160
Preliminary Information
125 µs
F0i
DSTi,
DSTo
CHANNEL 2
B1-channel
CHANNEL 0
D-channel
CHANNEL 3
B2-channel
CHANNEL 1
C-channel
CHANNELS 4-31
Not Used
LSB first
for D-
Channel
MSB first for C, B1- & B2-
Channels
Figure 7 - ST-BUS Channel Assignment
Codec, Digital gain and tone generation) and to
provide the channel timing requirements.
D8:
When 1, D-Channel data is shifted at the rate of 1 bit/
frame (8 kb/s).
The MT9160 uses only the first four channels of the
32 channel frame. These channels are always
defined, beginning with Channel 0 after the frame
pulse, as shown in Figure 7 (ST-BUS channel
assignments).
When 0, D-Channel data is shifted at the rate of 2
bits/frame (16 kb/s default).
16 kb/s D-Channel operation is the default mode
which allows the microprocessor access to a full byte
of D-Channel information every fourth ST-BUS
frame. By arbitrarily assigning ST-BUS frame n as
The first two (D & C) Channels are enabled for use
by the DEN and CEN bits respectively, (Control
Register 2, address 04h). ISDN basic rate service
(2B+D) defines a 16 kb/s signalling (D) Channel. The
MT9160 supports transparent access to this
signalling channel. ST-BUS basic rate transmission
devices, which may not employ a microport, provide
access to their internal control/status registers
through the ST-BUS Control (C) Channel. The
MT9160 supports microport access to this
C-Channel.
the
reference
frame,
during
which
the
microprocessor D-Channel read and write operations
are performed, then:
(a) A microport read of address 04 hex will result in a
byte of data being extracted which is composed of
four di-bits (designated by roman numerals I,II,III,IV).
These di-bits are composed of the two D-Channel
bits received during each of frames n, n-1, n-2 and
n-3. Referring to Fig. 8a: di-bit I is mapped from
frame n-3, di-bit II is mapped from frame n-2, di-bit III
is mapped from frame n-1 and di-bit IV is mapped
from frame n.
DEN - D-Channel
In ST-BUS mode access to the D-Channel (transmit
and receive) data is provided through an 8-bit read/
write register (address 06h). D-Channel data is
accumulated in, or transmitted from this register at
the rate of 2 bits/frame for 16 kb/s operation (1 bit/
frame for 8 kb/s operation). Since the ST-BUS is
asynchronous, with respect to the microport, valid
access to this register is controlled through the use
of an interrupt (IRQ) output. D-Channel access is
enabled via the (DEn) bit.
The D-Channel read register is not preset to any
particular value on power-up (PWRST) or software
reset (RST).
(b) A microport write to Address 04 hex will result in
a byte of data being loaded which is composed of
four di-bits (designated by roman numerals I, II, III,
IV). These di-bits are destined for the two D-Channel
bits transmitted during each of frames n+1, n+2, n+3,
n+4. Referring to Fig. 8a: di-bit I is mapped to frame
n+1, di-bit II is mapped to frame n+2, di bit III is
mapped to frame n+3 and di bit IV is mapped to
frame n+4.
DEn:
When 1, ST-BUS D-channel data (1 or 2 bits/frame
depending on the state of the D8 bit) is shifted into/
out of the D-channel (READ/WRITE) register.
If no new data is written to address 04 hex , the
current D-channel register contents will be
continuously re-transmitted. The D-Channel write
register is preset to all ones on power-up (PWRST)
or software reset (RST).
When 0, the receive D-channel data (READ) is still
shifted into the proper register while the DSTo
D-channel timeslot and IRQ outputs are tri-stated
(default).
7-84
Preliminary Information
MT9160
IRQ
FP
Microport Read/Write Access
n+2 n+3
n-3
n-2
n-1
n
n+1
n+4*
DSTo/
DSTi
Di-bit Group
Receive
D-Channel
I
II
III
IV
D0
D1
D4
D2
No preset value
D3
D5 D6
D7
I
II
III
IV
Di-bit Group
Transmit
D0
D1 D2
D4
D3
D5 D6
D7
D-Channel
Power-up reset to 1111 1111
* note that frame n+4 is equivalent to frame n of the next cycle.
Figure 8a - D-Channel 16 kb/s Operation
FP
C4i
C2
tir =500 nsec max
Rpullup= 10 k
DSTo/
DSTi
D0
D1
tif =500 nsec max
IRQ
8 kb/s operation
Reset coincident with
Read/Write of Address 04 Hex
16 kb/s operation
Microport Read/Write Access
or next FP, whichever occurs first
Figure 8b - IRQ Timing Diagram
FP
Microport Read/Write Access
IRQ
n+2
n+4
n+6
n-7
I
n-6
II
n-5
n-4
n-3
V
n-2
n-1
n
n+1
n+3
n+5
n+7
n+8
D-Channel
III
D2
IV
D3
VI
D5
VII
D6
VIII
D7
Di-bit Group
Receive
D-Channel
D0
D1
D4
I
D0
II
D1
III
D2
IV
D3
VI
D5
VII
D6
VIII
D7
V
D4
No preset value
Di-bit Group
Transmit
D-Channel
Power-up reset to 1111 1111
Figure 8c - D-Channel 8 kb/s Operation
7-85
MT9160
Preliminary Information
An interrupt output is provided (IRQ) to synchronize
microprocessor access to the D-Channel register
during valid ST-BUS periods only. IRQ will occur
every fourth (eighth in 8 kb/s mode) ST-BUS frame
at the beginning of the third (second in 8 kb/s mode)
ST-BUS bit cell period. The interrupt will be removed
following a microprocessor Read or Write of Address
04 hex or upon encountering the following frames’s
SSI Mode
The SSI BUS consists of input and output serial data
streams named Din and Dout respectively, a Clock
input signal (CLOCKin), and a framing strobe input
(STB). The frame strobe must be synchronous with,
and eight cycles of, the bit clock. A 4.096 MHz
master clock is also required for SSI operation if the
bit clock is less than 512 kHz. The timing
requirements for SSI are shown in Figures 12 & 13.
FP input, whichever occurs first.
To ensure
D-Channel data integrity, microport read/write
access to Address 04 hex must occur before the
following frame pulse. See Figure 8b for timing.
In SSI mode the MT9160 supports only B-Channel
operation. The internal C and D Channel registers
used in ST-BUS mode are not functional for SSI
operation. The control bits TxBSel and RxBSel, as
described in the ST-BUS section, are ignored since
the B-Channel timeslot is defined by the input STB
strobe. Hence, in SSI mode transmit and receive
B-Channel data are always in the channel defined by
the STB input.
8 kb/s operation expands the interrupt to every eight
frames and processes data one-bit-per-frame.
D-Channel register data is mapped according to
Figure 8c.
CEn - C-Channel
Channel 1 conveys the control/status information for
the Layer
1
transceiver. C-Channel data is
The data strobe input STB determines the 8-bit
timeslot used by the device for both transmit and
receive data. This is an active high signal with an 8
kHz repetition rate.
transferred MSB first on the ST-BUS by the MT9160.
The full 64 kb/s bandwidth is available and is
assigned according to which transceiver is being
used. Consult the data sheet for the selected
transceiver for its C-Channel bit definitions and order
of bit transfer.
SSI operation is separated into two categories based
upon the data rate of the available bit clock. If the bit
clock is 512 kHz or greater then it is used directly by
the internal MT9160 functions allowing synchronous
operation. If the available bit clock is 128 kHz or 256
kHz, then a 4096 kHz master clock is required to
derive clocks for the internal MT9160 functions.
When CEN is high, data written to the C-Channel
register (address 05h) is transmitted, most
significant bit first, on DSTo. On power-up reset
(PWRST) or software reset (Rst, address 03h) all
C-Channel bits default to logic high.
Receive
C-Channel data (DSTi) is always routed to the read
register regardless of this control bit's logic state.
Applications where Bit Clock (BCL) is below 512 kHz
are designated as asynchronous. The MT9160 will
re-align its internal clocks to allow operation when
the external master and bit clocks are asynchronous.
Control bits CSL2, CSL1 and CSL0 in Control
Register 2 (address 04h) are used to program the bit
rates.
When low, data transmission is halted and this
timeslot is tri-stated on DSTo.
B1-Channel and B2-Channel
Channels 2 and 3 are the B1 and B2 channels,
respectively. B-channel PCM associated with the
Filter/Codec and transducer audio paths is selected
on an independent basis for the transmit and receive
paths. TxBSel and RxBSel (Control Register 1,
address 03h) are used for this purpose.
For synchronous operation data is sampled, from
Din, on the falling edge of BCL during the time slot
defined by the STB input. Data is made available, on
Dout, on the rising edge of BCL during the time slot
defined by the STB input. Dout is tri-stated at all
times when STB is not true. If STB is valid but PDFDI
and PDDR are not true, then quiet code will be
transmitted on Dout during the valid strobe period.
There is no frame delay through the FDI circuit for
synchronous operation.
If no valid transmit path has been selected then the
timeslot output on DSTo is tri-stated (see PDFDI and
PDDR control bits, Control Register 1 address 03h).
For asynchronous operation Dout and Din are as
defined for synchronous operation except that the
allowed output jitter on Dout is larger. This is due to
the resynchronization circuitry activity and will not
7-86
Preliminary Information
MT9160
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the FDI circuit for asynchronous
operation. Refer to the specifications of Figures 12
& 13 for both synchronous and asynchronous SSI
timing.
is no strobe active on STB. If a valid strobe is
supplied to STB, then Dout will be active, during the
defined channel.
To attain complete power-down from a normal
operating condition, write PDFDI = 1 and PDDR = 1
(Control Register 1, address 03h) or put PWRST pin
low.
PWRST/Software Reset (Rst)
While the MT9160 is held in PWRST no device
control or functionality is possible. While in software
reset (Rst=1, address 03h) only the microport is
functional. Software reset can only be removed by
writing Rst logic low or by setting the PWRST pin.
After Power-up reset (PWRST) or software reset
(Rst) all control bits assume their default states;
µ-Law functionality, usually 0 dB programmable
gains as well as the device powered up in SSI mode
2048 kb/s operation with Dout tri-stated while there
5V Multi-featured Codec Register Map
00
01
RxINC
-
RxFG
RxFG
RxFG
TxINC
TxFG
TxFG
TxFG
0
Gain Control
Register 1
2
1
0
2
1
-
-
-
-
STG
-
STG
-
STG
0
Gain Control
Register 2
2
1
02
03
-
-
-
-
-
-
DrGain
R Bsel
Path Control
PDFDI
PDDR
DEN
RST
T Mute
R Mute
T Bsel
Control
Register 1
x
x
x
x
04
05
06
07
CEN
D8
A/µ
Smag/
CCITT
CSL
CSL
CSL
0
Control
Register 2
2
1
C
D
-
C
D
-
C
D
-
C
D
-
C
C
D
C
D
-
C
D
-
C-Channel
Register
7
6
5
4
3
2
2
1
0
0
D
D-Channel
Register
7
6
5
4
3
1
PCM/
loopen
Loop Back
ANALOG
7-87
MT9160
Preliminary Information
Register Summary
Gain Control Register 1
ADDRESS = 00h WRITE/READ VERIFY
Power Reset Value
1000 0000
RxFG RxFG RxFG
TxFG TxFG TxFG
2 1 0
TxINC
3
RxINC
7
2
1
0
6
5
4
2
1
0
Receive Gain
Setting (dB)
Transmit Gain
Setting (dB)
RxFG2
RxFG1
RxFG0
TxFG2
TxFG1
TxFG0
(default) 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(default) 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-1
-2
-3
-4
-5
-6
-7
1
2
3
4
5
6
7
RxFGn = Receive Filter Gain bit n
TxFGn = Transmit Filter Gain bit n
RxINC: When high, the receiver driver nominal gain is set to 0 dB. When low, this gain is -6.0 dB.
TxINC: When high, the transmit amplifier nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB.
Gain Control Register 2
ADDRESS = 01h WRITE/READ VERIFY
Power Reset Value
XXXX X000
-
-
-
-
-
STG
2
STG
1
STG
0
2
1
0
7
6
5
4
3
Side-tone Gain
Setting (dB)
STG2
STG1
STG0
(default) OFF
-9.96
-6.64
-3.32
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3.32
6.64
9.96
STGn = Side-tone Gain bit n
Note: Bits marked "-" are reserved bits and should be written with logic "0"
7-88
Preliminary Information
MT9160
Path Control
ADDRESS = 02h WRITE/READ VERIFY
Power Reset Value
XX00 0000
-
-
-
-
-
-
-
DrGain
7
6
5
4
3
2
1
0
DrGain
When high, the receiver driver gain is set to -6 dB, with sidetone.
When low, the receiver driver gain is set to 0 dB, with no sidetone.
Control Register 1
ADDRESS = 03h WRITE/READ VERIFY
Power Reset Value
0000 0000
_
4
PDFDI PDDR
Rst
5
TxMute RxMute TxBsel RxBsel
7
6
3
2
1
0
PDFDI
PDDR
When high, the FDI PLA and the Filter/Codec are powered down. When low, the FDI is active (default).
When high, the ear driver and Filter/Codec are powered down. In addition, in ST-BUS mode, the selected output
channel is tri-stated. In SSI mode the PCM output code will be -zero code during the valid strobe period. The output will
be tri-stated outside of the valid strobe and for the whole frame if no strobe is supplied. When low, the driver and Filter/
Codec are active if PDFDI is low (default).
Rst
When high, a software reset occurs performing the same function as the hardware reset (PWRST) except that the
microport is not affected. A software reset can be removed only by writing this bit low or by a PWRST. When low, the
reset condition is removed.
TxMute
When high the transmit PCM stream is interrupted and replaced with quiet code; thus forcing the output code into a
mute state (only the output code is muted, the transmit microphone and transmit Filter/Codec are still functional). When
low the full transmit path functions normally (default).
RxMute
TxBsel
RxBsel
When high the received PCM stream is interrupted and replaced with quiet code; thus forcing the receive path into a
mute state. When low the full receive path functions normally (default).
When high, the transmit B2 channel is functional in ST-BUS mode. When low, the transmit B1 channel is functional in
ST-BUS mode. Not used in SSI mode.
When high, the receive B2 channel is functional in ST-BUS mode. When low, the receive B1 channel is functional in
ST-BUS mode. Not used in SSI mode.
Note: Bits marked "-" are reserved bits and should be written with logic "0"
7-89
MT9160
Preliminary Information
Control Register 2
ADDRESS = 04h WRITE/READ VERIFY
Power Reset Value
Smag/
CCITT
0000 0010
CSL
1
CSL
CEn
7
DEn
6
D8
5
CSL
2
A/µ
1
0
2
4
3
0
CEn
DEn
When high, data written into the C-Channel register (address 05h) is transmitted during channel 1 on DSTo. When
low, the channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-Channel
register (address 05h) regardless of the state of CEn. This control bit has significance only for ST-BUS operation
and is ignored for SSI operation.
When high, data written into the D-Channel Register (address 06h) is transmitted (2 bits/frame) during channel 0
on DSTo. The remaining six bits of the D-Channel carry no information. When low, the channel 0 timeslot is
completely tri-stated on DSTo. Channel 0 data received on DSTi is read via the D-Channel register regardless of
the state of DEN. This control bit has significance only for ST-BUS mode and is ignored for SSI operation.
D8
When high, D-channel operates at 8kb/s. When low, D-channel operates at 16kb/s (default).
A/µ
When high, A-Law encoding/decoding is selected for the MT9160. When low, µ-Law encoding/decoding is
selected.
Smag/CCITT
When high, sign-magnitude code assignment is selected for the Codec input/output. When low, CCITT code
assignment is selected for the Codec input/output; true sign, inverted magnitude (µ-Law) or true sign, alternate
digit inversion (A-Law).
External bit Clock Rate
CSL2
CSL1
CSL0
CLOCKin (kHz)
Mode
(kHz)
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
1
0
1
0
1
not applicable
128
4096
4096
4096
512
ST-BUS
SSI
256
SSI
512
SSI
1536
1536
2048
4096
SSI
2048
SSI (default)
SSI
4096
Note: Bits marked "-" are reserved bits and should be written with logic "0"
7-90
Preliminary Information
MT9160
C-Channel Register
ADDRESS = 05h WRITE/READ
Power Reset Value
1111 1111- write
XXXX XXXX - read
C7
7
C6
6
C5
5
C4
4
C3
3
C2
2
C1
1
C0
0
Micro-port access to the ST-BUS C-Channel information read and write
D-Channel Register
ADDRESS = 06h WRITE/READ
Power Reset Value
1111 1111- write
XXXX XXXX - read
D3
3
D7
7
D6 D5
D4
D2
2
D1
D0
6
5
4
1
0
D7-D0
Data written to this register will be transmitted every frame, in channel 0, if the DEn control bit is set (address 04h).
Received D-Channel data is valid, regardless of the state of DEn. These bits are valid for ST-BUS mode only and are
accessible only when IRQ indicates valid access.
ADDRESS = 07h WRITE/READ VERIFY
Loopback Register
Power Reset Value
XXXX 0000
PCM/
ANALOG
-
-
-
-
loopen
-
-
7
6
5
4
3
2
1
0
PCM/ANALOG This control bit functions only when loopen is set high. It is ignored when loopen is low.
For loopback operation when this bit is high, the device is configured for digital-to-digital loopback operation. Data on
Din is looped back to Dout without conversion to the analog domain. However, the receive D/A path (from Din to
HSPKR ±) still functions. When low, the device is configured for analog-to-analog operation. An analog input signal at
M± is looped back to the SPKR± outputs through the A/D and D/A circuits as well as through the normal transmit A/D
path (from M± to Dout).
loopen
When high, loopback operation is enabled and the loopback type is governed by the state of the PCM/ANALOG bit.
When low, loopbacks are disabled, the device operates normally and the PCM/ANALOG bit is ignored.
Note: Bits marked "-" are reserved bits and should be written with logic "0"
7-91
MT9160
Preliminary Information
Applications
Figure 9 shows an application in a digital phone set.
Various configurations of pair gain drops are
depicted in Figures 10a and 10b using the MT9125
and MT9126, respectively.
330Ω
+5V
+
-
330Ω
VBias
T
+
-
+
M+
+5V
0.1 µF
M+
M-
+
10 µF
0.1 µF
511Ω
511Ω
100K
100K
10 µF
R
R
1K
+
Av = 1 + 2R
T
VBias
T
+
Electret
Microphone
VBias
Electret
Microphone
0.1 µF
R
Single-ended Amplifier
-
M-
+
Differential Amplifier
VBias
Typical External Gain
AV= 5-10
M+
M-
(
)
0.1 µF
0.1 µF
1
2
20
19
18
17
75Ω
+5V
3
4
5
A/µ/IRQ
MT9160
16
15
14
13
12
11
150Ω
6
7
+5V
75Ω
INTEL
MCS-51
or
MOTOROLA
SPI
Micro-
Controller
CS
SCLK
DATA1
DATA2
8
9
10
DATA2 Motorola
Mode only
DSTi
+5V
DC to DC
Converter
Lin
ZT
DSTo
MT8972
DNIC
F0i
Twisted Pair
Lout
C4b
10.24 MHz
Figure 9 - Digital Telephone Set
7-92
Preliminary Information
MT9160
2 C S i L n a I G i r a P 2 2 6 8 8 H M
1
S L i I n C a G i r P 2 a 2 6 8 8 H M
7-93
MT9160
Preliminary Information
1
L I C i n a S G i r P 2 a 2 6 8 8 H M
2
L I C i n a S G i r P 2 a 2 6 8 8 H M
7-94
Preliminary Information
MT9160
Absolute Maximum Ratings
Parameter
Symbol
- V
Min
Max
Units
1
2
3
4
5
Supply Voltage
V
- 0.3
7
V
V
DD
SS
Voltage on any I/O pin
V /V
V
- 0.3
V
+ 0.3
DD
I
O
SS
Current on any I/O pin (transducers excluded)
Storage Temperature
I /I
± 20
+ 150
750
mA
°C
I O
T
- 65
S
D
Power Dissipation (package)
P
mW
Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated
Characteristics
Supply Voltage
Sym
Min
Typ
Max
Units
Test Conditions
1
2
V
4.75
2.4
5
5.25
V
V
DD
TTL Input Voltage (high)*
V
V
Includes Noise margin =
400 mV
IHT
DD
3
TTL Input Voltage (low)*
V
V
0.4
V
Includes Noise margin =
400 mV
ILT
SS
4
5
6
CMOS Input Voltage (high)
CMOS Input Voltage (low)
Operating Temperature
V
4.5
V
V
V
IHC
DD
V
V
0.5
ILC
SS
T
- 40
+ 85
°C
A
* Excluding PWRST which is a Schmitt Trigger Input.
Power Characteristics
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
Static Supply Current (clock
disabled, all functions off, PDFDI/
PDDR=1, PWRST=0)
I
350
µA
Outputs unloaded, Input
signals static, not loaded
DDC1
Dynamic Supply Current:
Total all functions enabled
I
8.0
mA
See Note 1 and 2.
DDFT
Note 1: Power delivered to the load is in addition to the bias current requirements.
Note 2: IDDFT is not additive to IDDC1
.
7-95
MT9160
Preliminary Information
DC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
Input HIGH Voltage TTL inputs
Input LOW Voltage TTL inputs
Input HIGH Voltage CMOS inputs
Input LOW Voltage CMOS inputs
VBias Voltage Output
V
2.0
V
V
IHT
V
0.8
1.5
ILT
V
3.5
3.7
V
IHC
V
V
ILC
V
VDD/2
V
Max. Load = 10kΩ
Bias
V
DD/2-1.5
V
Output Voltage
V
V
No load
Ref
Ref
Input Leakage Current
I
0.1
10
µA
V
V =V
to V
DD SS
IZ
IN
Positive Going Threshold
Voltage (PWRST only)
Negative Going Threshold
Voltage (PWRST only)
V
T+
V
1.3
V
T-
9
Output HIGH Current
I
I
- 5
5
- 16
10
mA
mA
µA
pF
V
V
V
= 2.4V
= 0.4V
OH
OH
10 Output LOW Current
11 Output Leakage Current
12 Output Capacitance
13 Input Capacitance
I
OL
OZ
OL
0.01
15
10
= V and V
OUT DD SS
C
o
C
10
pF
i
† DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
Clockin Tolerance Characteristics (ST-BUS Mode)
‡
Characteristics
C4i Frequency
Min
Typ
Max
Units
Test Conditions
1
4095.6 4096 4096.4
kHz
(i.e., 100 ppm)
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
7-96
Preliminary Information
MT9160
AC Characteristics† for A/D (Transmit) Path - 0dBm0 = 1.421Vrms for µ-Law and 1.477Vrms for
A-Law, at the Codec. (VRef=1.0 volts and VBias=2.5 volts.)
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
µ-Law
1
2
Analog input equivalent to
overload decision
A
5.79
6.0
Vp-p
Vp-p
Li3.17
Li3.14
A
A-Law
Both at Codec
Absolute half-channel gain
M ± to Dout
Transmit filter gain=0dB
setting.
TxINC = 0*
G
G
6.0
15.3
dB
dB
AX1
AX2
TxINC = 1*
@1020 Hz
Tolerance at all other transmit
filter settings
±0.2
dB
(1 to 7dB)
3
4
Gain tracking vs. input level
CCITT G.714 Method 2
G
-0.3
-0.6
-1.6
0.3
0.6
1.6
dB
dB
dB
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
TX
Signal to total Distortion vs. input
level.
CCITT G.714 Method 2
D
35
29
24
dB
dB
dB
0 to -30 dBm0
-40 dBm0
-45 dBm0
QX
5
6
Transmit Idle Channel Noise
N
N
15
-71
16
-69
dBrnC0 µ-Law
dBm0p A-Law
CX
PX
Gain relative to gain at 1020Hz
G
RX
<50Hz
60Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
-25
-30
0.0
0.25
0.25
-12.5
-25
dB
dB
dB
dB
dB
dB
dB
-0.25
-0.9
>4600 Hz
7
8
Absolute Delay
D
D
360
µs
at frequency of minimum
delay
AX
DX
Group Delay relative to D
750
380
130
750
µs
µs
µs
µs
500-600 Hz
AX
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
9
Power Supply Rejection
±100mV peak signal on
V
DD
f=1020 Hz
PSSR
PSSR1
PSSR2
PSSR3
37
40
35
40
dB
dB
dB
dB
µ-law
f=0.3 to 3 kHz
f=3 to 4 kHz
f=4 to 50 kHz
PSSR1-3 not production
tested
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: TxINC, refer to Control Register 1, address 00h.
7-97
MT9160
Preliminary Information
AC Characteristics† for D/A (Receive) Path - 0dBm0 = 1.421Vrms for µ-Law and 1.477Vrms for A-Law, at the Codec.
(VRef=1.0 volts and VBias=2.5 volts.)
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
µ-Law
1
2
Analog output at the Codec full
scale
A
5.704
5.906
Vp-p
Vp-p
Lo3.17
Lo3.14
A
A-Law
Absolute half-channel gain.
Din to HSPKR±
G
G
G
G
0
-6
-6
dB
dB
dB
dB
DrGain=0, RxINC =1*
DrGain=0, RxINC =0*
DrGain=1, RxINC =1*
DrGain=1, RxINC =0*
@ 1020 Hz
AR1
AR2
AR3
AR4
-12
Tolerance at all other receive
filter settings
±0.2
dB
(-1 to -7dB)
3
4
Gain tracking vs. input level
CCITT G.714 Method 2
G
-0.3
-0.6
-1.6
0.3
0.6
1.6
dB
dB
dB
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
TR
Signal to total distortion vs. input
level.
CCITT G.714 Method 2
G
35
29
24
dB
dB
dB
0 to -30 dBm0
-40 dBm0
-45 dBm0
QR
5
6
Receive Idle Channel Noise
N
N
13
-78.5
15.5
-77
dBrnC0 µ-Law
dBm0p A-Law
CR
PR
Gain relative to gain at 1020Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
G
RR
0.25
0.25
0.25
-12.5
-25
dB
dB
dB
dB
dB
-0.25
-0.90
>4600 Hz
7
8
Absolute Delay
D
D
240
µs
at frequency of min. delay
AR
DR
Group Delay relative to D
750
380
130
750
µs
µs
µs
µs
500-600 Hz
AR
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
9
Crosstalk
D/A to A/D
A/D to D/A
CT
CT
-74
-80
dB
dB
G.714.16
CCITT
RT
TR
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: RxINC, refer to Control Register 1, address 00h.
7-98
Preliminary Information
MT9160
AC Electrical Characteristics† for Side-tone Path
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
RxINC = 0*
1
Absolute path gain
gain adjust = 0dB
G
G
-16.63
-10.63
dB
dB
AS1
AS2
RxINC = 1*
M± inputs to HSPKR± outputs
1000 Hz at STG2=1
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: RxINC, refer to Control Register 1, address 00h.
Electrical Characteristics† for Analog Outputs
‡
Characteristics
Sym Min Typ
Max
Units
Test Conditions
across HSPKR±
each pin:
1
2
EarpIece load impedance
E
260
300
300
ohms
pF
ZL
Allowable earpiece capacitive
load
E
HSPKR+,
HSPKR-
CL
3
Earpiece harmonic distortion
E
0.5
%
300 ohms load across
HSPKR± (tol-15%),
D
VO≤693mV
, RxINC=1*,
RMS
Rx gain=0dB
† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: RxINC, refer to Control Register 1, address 00h.
Electrical Characteristics† for Analog Inputs
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
1
Input voltage without overloading
Codec
across M+/M-
V
2.90
1.03
Vp-p
Vp-p
TxINC = 0, A/µ = 0*
TxINC = 1, A/µ = 1*
IOLH
Tx filter gain=0dB setting
2
Input Impedance
Z
50
kΩ
M+/M- to V
SS
I
† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: TxINC, refer to Control Register 1, address 00h.
7-99
MT9160
Preliminary Information
AC Electrical Characteristics† - ST-BUS Timing (See Figure 11)
‡
Characteristics
C4i Clock Period
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
9
t
244
122
122
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
C4P
C4i Clock High period
C4i Clock Low period
C4i Clock Transition Time
F0i Frame Pulse Setup Time
F0i Frame Pulse Hold Time
DSTo Delay
t
C4H
t
C4L
t
T
t
50
50
F0iS
F0iH
t
t
100
125
C = 50pF, 1kΩ load.*
L
DSToD
DSTi Setup Time
t
30
30
DSTiS
DSTi Hold Time
t
DSTiH
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: All conditions → data-data, data-HiZ, HiZ-data.
tT
tT
1 bit cell
tC4L
tC4P
tC4H
70%
30%
C4i
tDSToD
70%
30%
DSTo
DSTi
F0i
tDSTiH
tDSTiS
70%
30%
tF0iS
tF0iH
tT
tT
70%
30%
NOTE: Levels refer to %VDD
Figure 11 - ST-BUS Timing Diagram
7-100
Preliminary Information
MT9160
AC Electrical Characteristics† - SSI BUS Synchronous Timing (see Figure 12)
‡
Characteristics
BCL Clock Period
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
tBCL
tBCLH
tBCLL
tR/tF
tENW
tSSS
244
1953
ns
ns
ns
ns
ns
ns
ns
ns
BCL=4096 kHz to 512 kHz
BCL=4096 kHz
BCL=4096 kHz
Note 1
BCL Pulse Width High
122
122
BCL Pulse Width Low
BCL Rise/Fall Time
20
8 x tBCL
Strobe Pulse Width
Note 1
tBCL-80
tBCL-80
90
Strobe setup time before BCL falling
Strobe hold time after BCL falling
80
80
tSSH
Dout High Impedance to Active Low tDOZL
from Strobe rising
CL=150 pF, RL=1K
CL=150 pF, RL=1K
CL=150 pF, RL=1K
CL=150 pF, RL=1K
CL=150 pF, RL=1K
9
Dout High Impedance to Active High tDOZH
from Strobe rising
90
90
90
90
ns
ns
ns
ns
10 Dout Active Low to High Impedance tDOLZ
from Strobe falling
11 Dout Active High to High Impedance tDOHZ
from Strobe falling
12 Dout Delay (high and low) from BCL
rising
tDD
13 Din Setup time before BCL falling
14 Din Hold Time from BCL falling
tDIS
tDIH
50
50
ns
ns
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.
tBCL
tBCLH
tR
tF
CLOCKin
(BCL)
70%
30%
tBCLL
tDIS
tDIH
70%
30%
Din
tDD
tDOZL
70%
30%
Dout
tDOZH
tDOLZ
tDOHZ
tSSH
tENW
tSSS
70%
30%
STB
NOTE: Levels refer to % VDD (CMOS I/O)
Figure 12 - SSI Synchronous Timing Diagram
7-101
MT9160
Preliminary Information
AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (see Figure 13)
‡
Characteristics
Bit Cell Period
Sym
Min
Typ
Max
Units
Test Conditions
1
TDATA
7812
3906
ns
ns
BCL=128 kHz
BCL=256 kHz
2
3
Frame Jitter
Tj
600
ns
ns
Bit 1 Dout Delay from STB
going high
tdda1
Tj+600
CL=150 pF, RL=1K
CL=150 pF, RL=1K
4
5
Bit 2 Dout Delay from STB
going high
tdda2
tddan
600+
TDATA-Tj
600+
TDATA
600 +
TDATA+Tj
ns
ns
Bit n Dout Delay from STB
going high
600 +
(n-1) x
TDATA-Tj
600 +
(n-1) x
TDATA
600 +
(n-1) x
TDATA+Tj
CL=150 pF, RL=1K
n=3 to 8
6
7
Bit 1 Data Boundary
TDATA1
tSU
TDATA-Tj
TDATA+Tj
ns
ns
Din Bit n Data Setup time from
STB rising
TDATA\2
+500ns-Tj
+(n-1) x
TDATA
n=1-8
8
Din Data Hold time from STB
rising
tho
TDATA\2
+500ns+Tj
+(n-1) x
TDATA
ns
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.
Tj
70%
STB
30%
tdda2
tdha1
tdda1
70%
Dout
Bit 1
Bit 2
Bit 3
30%
TDATA
TDATA1
tho
tsu
70%
30%
Din
D2
D3
D1
TDATA/2
TDATA
TDATA
NOTE: Levels refer to % VDD (CMOS I/O)
Figure 13 - SSI Asynchronous Timing Diagram
7-102
Preliminary Information
MT9160
AC Electrical Characteristics† - Microport Timing (see Figure 14)
‡
Characteristics
Input data setup
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
9
tIDS
tIDH
100
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input data hold
Output data delay
Serial clock period
SCLK pulse width high
SCLK pulse width low
CS setup-Intel
tODD
tCYC
tCH
100
CL = 150pF, RL = 1K *
500
250
250
200
100
100
1000
500
tCL
500
tCSSI
tCSSM
tCSH
tOHZ
CS setup-Motorola
CS hold
10 CS to output high impedance
100
CL = 150pF, RL = 1K
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Note: All conditions → data-data, data-HiZ, HiZ-data.
2.0V
DATA INPUT
0.8V
90%
10%
tIDS
2.0V
0.8V
HiZ
DATA OUTPUT
tIDH
tCH
Intel
Mode = 0
tODD
tCYC
2.0V
SCLK
CS
0.8V
tCSSI
tOHZ
tCL
2.0V
0.8V
tCSSM
tCSH
tCH
2.0V
0.8V
Motorola
Mode = 00
SCLK
tCYC
tODD
tCL
tIDH
90%
10%
2.0V
0.8V
DATA OUTPUT
HiZ
tIDS
2.0V
0.8V
DATA INPUT
NOTE: % refers to % VDD
Figure 14 - Microport Timing
7-103
MT9160
Preliminary Information
Notes:
7-104
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