MT90732AP [MITEL]
CMOS E2/E3 Framer (E2/E3F); CMOS E2 / E3成帧器（ E2 / E3F ）
| 型号： | MT90732AP |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | CMOS E2/E3 Framer (E2/E3F) |
| 文件： | 总8页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT90732
CMOS
E2/E3 Framer (E2/E3F)
Advance Information
ISSUE 1
May 1995
Features
•
Framer for CCITT Recommendations
Ordering Information
- G.742 (8448 kbit/s)
- G.745 (8448 kbit/s)
- G.751 (34368 kbit/s)
- G.753 (34368 kbit/s)
MT90732AP
68 Pin PLCC
-40°C to +85°C
Description
The MT90732 E2/E3 Framer (E2/E3F) is a CMOS
VLSI device that provides the functions needed to
frame a wideband payload to one of four CCITT
Recommendations. G.742, G.745, G.751, or G.753.
The E2/E3 Framer interfaces to line circuitry with
either dual rail or NRZ signals. On the terminal side,
the interface can be either nibble-parallel or bit-
serial.
•
Line side interface
- Dual rail or NRZ
HDB3 codec for dual rail I/O
Terminal side interface
•
•
- Nibble-parallel
- Bit-serial
•
•
•
Transmit reference generator for bit-serial I/O
Microprocessor or control leads
I/O port for service bits
The MT90732 can be operated with or without a
microprocessor.
When
interfaced
with
a
microprocessor, the E2/E3 Framer provides an 8-
byte memory map for control, performance counters
and alarm status. The MT90732 provides a transmit
and receive interface port for accessing the
Applications
•
•
•
•
Line terminals
Wideband data or video transport
Test equipment
overhead
bits
from
each
of
the
four
recommendations. The overhead bits can also be
accessed by the microprocessor via the memory
map.
Multiplexer systems
RDL
RCKL
SERIAL
PARALLEL
Data
RSD
TDOUT
TCG
TFOUT
RSC
RSF
RCG
RNIB3
RNIB2
RNIB1
RNIB0
RNC
RNF
N.C.
Data
Clock
Frame
Data
RP/RDL
Clock
Frame
Line
Decoder
RN
RCK/RCKL
CV
Interpreter
Framer
Clock
Output
RAIS
RLOC
BIP-4E
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
SEL
ALE
RD
WR
RDY
RLOF
ROD
ROC
ROF
Micro-
processor
I/O
FE
NRZ LINE
BIP-4
M0
M1
MICRO
SER
Control
DAIS
TLBK
PLBK
TAIS
LPT
TLCINV
TLOC
Transmit
Reference
Generator
FORCEFE
TOD
XSF
N.C.
TCIN
XSD
XNIB3
XNIB2
XNIB1
XNIB0
TOC
TOF
RESET
TP/TDL
TCK/TCKL
TCKL
TDL
Input
Clock
Data
Framing
XCK
XNF
XNC
XCK
N.C.
TCOUT
Data
Clock
G.7XX
Send
Line
Encoder
TN
Line Side
Terminal Side
Figure 1 - Functional Block Diagram
U.S. Patent Number 5040170
5-15
MT90732 CMOS
Advance Information
10
ROC
ROF
BIP-4E
XNC/TCOUT
XNF
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FE
NRZLINE
BIP-4
M0
XCK
XNIB0/XSD
XNIB1/TCIN
XNIB2
XNIB3/XSF
GND
M1
VDD
GND
VDD
MICRO
SER
TLCINV
DAIS
TLBK
PLBK
TAIS
RDY
WR
RD
LPT
ALE
TLOC
FORCEFE
25
26
SEL
44
Figure 2 - Pin Connections
Pin Description
Power Supply and Ground
Pin #
Name
I/O/P
Description
1,17,35,51
VDD
GND
P
P
VDD. 5-volt supply voltage, +/- 5%
18,34,52,68
Ground.
Note: I = Input; O = Output; P = Power
Line Side Receive
Pin #
Name
I/O/P
Description
2
RP/RDL
I
Receive Positive Rail/Receive NRZ Data. Receive positive rail/NRZ data
generated from line interface circuit.
3
4
RN
I
I
Receive Negative Rail Data. Receive negative rail data generated from line
interface circuit.
RCK/RCKL
Receive Clock Rail/Receive Clock NRZ. The receive clock is used for clock-
ing in the rail/NRZ data signals.
Note: I = Input; O = Output; P = Power
5-16
Advance Information
CMOS MT90732
Line Side Transmit
Pin #
Name
I/O/P
Description
31
TP/TDL
O
Transmit Positive Rail/Transmit NRZ Data. Transmit positive rail/NRZ data
sent out of E2/E3 Framer.
32
33
TCK/TCKL
TN
O
O
Transmit Clock Rail/Transmit Clock NRZ. The transmit clock is used for
clocking out the dual rail/NRZ data signals. The TCK/TCKL clock signal is
derived from the XCK clock.
Transmit Negative Rail Data. Transmit negative rail data sent out of E2/E3
Framer.
Note: I = Input; O = Output; P = Power
Terminal Interface
Pin #
Name
I/O/P
Description
61
RCG
O
Receive Clock Gapped. An active low signal indicates the receive framing
and service bit locations in the serial mode only.
62
63
RNF/RSF
O
O
Receive Framing Pulse. Framing pulse is synchronous with the last nibble for
the nibble-parallel interface, and with the first bit in the frame for the bit-serial
interface.
RNIB3/RSD
Receive Nibble Bit 3/Receive Serial Data. Bit 3 is the most significant bit in
the nibble and corresponds to the first bit received in the nibble. The framing
pattern, service bits, and BIP-4 nibble are not provided as parallel data. In the
serial mode receive data signal consists of all bits, including the framing pat-
tern and service bits.
64
65
RNIB2/TDO
UT
O
O
Receive Nibble Bit 2/Transmit Reference Generator Data Output. In the
nibble-parallel mode, it is Bit 2 of the received nibble.The reference generator
is enabled in the serial mode. The output data signal (TDOUT) consists of all
ones in place of the framing bits and zeros elsewhere in the frame.
RNIB1/TCG
Receive Nibble Bit 1/Transmit Reference Generator Clock Gap Signal. In
the nibble-parallel mode, it is Bit 1 of the received nibble. The active low TCG
signal indicates the location of the framing pattern and the service bits in the
frame.
66
67
53
RNIB0/TFO
UT
O
O
I
Receive Nibble Bit 0/Transmit Reference Generator Framing Pulse. Bit 0
is the least significant bit in the nibble and is the last bit received. The active
low TFOUT signal is synchronous with the first bit in the frame.
RNC/RSC
Receive Nibble Clock/Receive Serial Clock. The nibble and serial clocks are
derived from the line side dual rail/NRZ clock signal (RCK/RCKL). RNC is
gapped during framing pattern, service bit and BIP-4 bit times.
XNIB3/XSF
Transmit Nibble Bit 3/Transmit Serial Framing Pulse. In the nibble-parallel
mode, bit 3 is the most significant bit in the nibble and corresponds to the first
bit transmitted in the nibble. When the terminal interface is serial, the negative
framing pulse is synchronous with the first bit in the frame.
54
55
XNIB2
I
I
Transmit Nibble Bit 2. Bit 2 in the 4-bit nibble.
XNIB1/TCI
N
Transmit Nibble Bit 1/Transmit Reference Generator Clock In. Bit 1 in the
transmit nibble. For a serial interface, the TCIN is used to derive the clock out
(TCOUT), data signal (TDOUT), framing pulse (TFOUT), and gapped clock
signal (TCG).The reference generator signals are provided for multiplexing the
external payload data into the serial frame.
5-17
MT90732 CMOS
Advance Information
Terminal Interface
Pin #
Name
I/O/P
Description
56
XNIB0/XSD
I
Transmit Nibble Bit 0/Transmit Serial Data. In the nibble-parallel mode, bit 0
is the least significant bit in the nibble. For a serial interface, the input must
consist of all the bits in the frame.
57
XCK
XNF
I
Transmit Clock. For the terminal side nibble-parallel interface, the XCK is
used for all transmit timing functions, including deriving the nibble output clock
(XNC) and framing pulse (XNF).For the serial interface, this clock may be
derived from the transmit reference generator clock output (TCOUT).
58
59
O
O
Transmit Nibble Framing Pulse. The XNF and clock signal (XNC) are pro-
vided for multiplexing nibble data into the E2/E3 Framer from external circuitry.
The negative framing pulse identifies the first bit in the frame.
XNC/TCOU
T
Transmit Nibble Clock/Transmit Reference Generator Clock Out. The
XNC is derived from the transmit clock (XCK) and is used as a time base for
clocking data out of the external multiplexer and into the E2/E3 Framer. XNC is
gapped during the framing pattern, service bit and BIP-4 bit times. TCOUT is
derived from the input clock (TCIN), and has the same duty cycle.
Note: I = Input; O = Output; P = Power
Service Bit Interface
Pin #
Name
I/O/P
Description
9
ROD
O
Receive Service Data Bits. These service bits are clocked out of E2/E3
Framer on positive transitions of clock signal (ROC).
10
11
27
28
29
ROC
ROF
TOD
TOC
TOF
O
O
I
Receive Service Bits Clock. A gapped clock that clocks out the service bits.
The clock is active only for clocking out the receive service data bits(ROD).
Receive Service Bits Framing Pulse. A positive framing pulse that is syn-
chronous with the first bit in the frame.
Transmit Service Data Bits. The service bits are clocked into E2/E3 Framer
on positive transitions of clock signal (TOC).
O
O
Transmit Service Bits Clock. A gapped clock that clocks in the service bits.
The clock is active only for clocking in the transmit service data bits (TOD).
Transmit Service Bits Framing Pulse. A positive framing pulse that is syn-
chronous with the first bit in the frame.
Note: I = Input; O = Output; P = Power
Microprocessor Interface
Pin #
Name
I/O/P
Description
36-43
AD(7-0)
I/O Address/Data Bus. These leads constitute the time-multiplexed address and
data bus for accessing the registers which reside in the E2/E3F.
44
45
SEL
ALE
I
I
Select. A low enables the microprocessor to access the E2/E3F memory map
for control, status, and alarm information.
Address Latch Enable. An active high signal generated by the microproces-
sor. Used by the microprocessor to hold an address stable during a read/write
bus cycle.
46
RD
I
Read. An active low signal generated by the microprocessor for reading the
registers which reside in the memory map.
5-18
Advance Information
CMOS MT90732
Microprocessor Interface
Pin #
Name
I/O/P
Description
47
WR
I
Write. An active low signal generated by the microprocessor for writing to the
registers which reside in the memory map.
48
RDY
O
Ready. An active high signal indicating an E2/E3F acknowledgment to the
microprocessor that the addressed memory map location can complete the
data transfer.
Note: I = Input; O = Output; P = Power
Control Interface
Pin #
Name
I/O/P
Description
13
NRZLINE
I
Non-Return to Zero Line Selection. A high enables an NRZ line input (RP
and TP), and causes the HDB3 decoder/encoder to be bypassed. When low
enables the dual rail interface (RP/RN and TP/TN) and the HDB3
decoder/encoder.
14
BIP-4
I
I
Bit Interleaved Parity - 4. A high enables the BIP-4 function. In the transmit
direction, the BIP-4 is calculated for data nibbles only, and is sent as the last
nibble in the frame format. In the receive direction, the BIP-4 is calculated for
the data bits only and compared against the received value which is present in
the last four bits of the frame. An output indication (BIP-4E) occurs when one
or more columns do not match.
16
15
M1
M0
Mode Control. The two controls select the operating rate of the E2/E3F
according to the table given below.
M1
M0
Recommendation Rate (kbit/s)
0
0
1
1
0
1
0
1
G.745
G.742
G.753
G.751
8448
8448
34368
34368
19
MICRO
I
Microprocessor Mode. A high enables the microprocessor interface. When
the microprocessor is enabled, the following hardware control leads are dis-
abled. BIP-4, Mode (M0 and M1), Serial I/O (SER), and transmit AIS (TAIS).
Bits are provided in the memory map for controlling these functions.
20
21
22
23
24
26
SER
TLBK
PLBK
TAIS
LPT
I
I
I
I
I
I
Serial Interface. A high selects the bit-serial interface for the terminal side
interface. A low selects the nibble-parallel interface.
Terminal Loopback. A low enables a transmit to receive loopback at the line
side.
Payload Loopback. A low enables a receive to transmit loopback at the termi-
nal side in the serial mode of operation only.
Transmit Alarm Indication Signal. A low causes an all ones signal (AIS) to
be sent in place of a G.7XX frame format.
Loop Timing. A low enables the loop timing feature. Loop timing disables the
transmit clock and enables the receive clock to be used as the transmit clock.
FORCEFE
Force Framing Error. The errored bit is sent into the framing pattern upon the
high-to-low transition of this pin.
5-19
MT90732 CMOS
Advance Information
Control Interface
Pin #
Name
I/O/P
Description
30
RESET
I
Reset. A positive pulse applied to this pin resets the internal counters, logic
circuits, and the performance counters and control bits in the memory map to
zero. The reset pulse is applied after the power becomes stable.
49
50
5
DAIS
TLCINV
CV
I
Disable AIS. A low disables the automatic insertion of AIS into the terminal
side receive nibble/serial bit stream.
I
Transmit Line Clock Invert. A low inverts the output clock TCK/TCKL when
operating in the dual rail mode.
O
O
Coding Violation. A positive pulse, one clock cycle wide, is generated when
an illegal coding violation is detected.
6
RAIS
Receive Alarm Indication Signal. An active low alarm occurs within one milli-
second after the E2/E3F detects an all ones condition, including in the pres-
-3
ence of a 10 error rate. An incoming signal with a framing pattern and all
ones in the data field is not mistaken as an AIS.
7
RLOC
O
Receive Loss of Clock. An active low alarm occurs when there are no transi-
tions in the received clock (RCK/RCKL). Recovery occurs on the first clock
transition.
RLOF
FE
8
O
O
O
O
Receive Loss of Frame. An active low alarm occurs when a valid frame can-
not be detected accordingly to G.7XX recommendations.
12
25
60
Framing Error. An active high alarm occurs when one or more framing bits
are in error.
TLOC
BIP-4E
Transmit Loss of Clock. An active low alarm occurs when there are no transi-
tions in the transmit clock (TCK). Recovery occurs on the first clock transition.
BIP-4E. A positive pulse occurs when the comparison between the received
BIP-4 value and the calculated value does not match in a column.
Note: I = Input, O = Output, P = Power
regardless of frame alignment. The external alarm
indications (latched and unlatched states) are provided
Functional Description
in the memory map, and unlatched alarm indications
are provided at signal leads.
The block diagram for the E2/E3F is shown in Figure
1. The E2/E3F receives NRZ data signal (RDL) and
clock signal (RCKL), or a positive (RP) and negative
(RN) rail signal and clock signal (RCK), from a line
interface circuit. The selection of the line interface,
dual rail or NRZ, is controlled by the external lead
labeled NRZ LINE. Indications of HDB3 coding viola-
tion errors are provided on an external signal lead
(CV) as pulses. Coding violation errors are also
counted in an 8-bit saturating counter accessed by the
microprocessor through the memory map.
The E2/E3F terminal side output block provides either
a bit-serial or a nibble-parallel interface. The interface
is selected by an external control lead (SER) or by the
microprocessor. The bit-serial interface consists of the
following signals: a data output signal (RSD), a clock
output signal (RSC), a receive clock gapped output
signal (RCG), and a framing pulse (RSF). The receive
clock gapped signal (RCG) identifies framing and ser-
vice bit times. The nibble-parallel interface consists of
data output signal having a nibble format (RNIB3
through RNIB0), a clock output signal (RNC), and a
framing pulse (RNF). In the nibble mode, the framing
pattern, service bits and BIP-4 nibble are not provided
at the interface. The receive nibble clock (RNC) is
gapped during framing pattern, service bit and BIP-4
times.
The selection of the framing format (G.742, G.745,
G.751 or G.753) is done by external control leads (M1
and M0), or by the microprocessor. The Framer Block
performs frame alignment and alarm detection includ-
ing Loss of Frame (RLOF), Loss of Clock (RLOC), AIS
detection (RAIS) and BIP-4 detection (BIP-4E). A
framing error (FE) output is also provided to indicate
when any of the framing bits in the G. 7XX frame are in
error. The disable AIS (DAIS) control lead permits the
E2/E3F to provide receive data on the terminal side
5-20
Advance Information
CMOS MT90732
The transmitter operates independently of the receiver,
unless the loop timing feature(LPT) is selected, when
the receive clock becomes the transmitted clock. In the
transmit direction, the terminal side bit-serial interface
consists of: data input signal (XSD), a clock input sig-
nal (XCK), and a framing pulse (XSF). The nibble-par-
allel interface consists of the following signals: a data
input signal having a nibble format (XNIB3 - XNIB0), a
clock input signal (XCK), a framing output pulse (XNF),
and a nibble output clock signal (XNC). The transmit
nibble clock (XNC) is stretched to accommodate the
framing pattern, service bit and BIP-4 times.
also controls the receive interface selection. When the
internal HDB3 Encoder Block is bypassed, the trans-
mit line interface consists of a data signal (TDL) and a
clock signal (TCKL). When the HDB3 encoder is
enabled, the transmit line interface consists of positive
(TP) and negative (TN) rail signals and a clock signal
(TCK).
A high placed on the microprocessor control lead
(MICRO) selects the microprocessor interface. All the
external control leads, except the loop timing (LPT),
receive AIS disable (DAIS), and the line interface con-
trol leads (NRZLINE) are disabled when the micropro-
cessor interface is selected.
MT90372 provides interface to service bits as defined
in G.7XX recommendations.The receive service bit
interface consists of: data output (ROD), clock output
(ROC), and framing pulse (ROF) output. The clock sig-
nal (ROC) is gapped and is provided for clocking out
the service bits. The service bit states are also written
into E2/E3F memory locations, which can be read by
the microprocessor. The transmitted service bits are
inserted into the frame format from either an external
interface or from memory map locations. The transmit
service bit interface consists of data input signal
(TOD), a clock output (TOC), and a framing pulse
(TOF) output.
The microprocessor interface consists of eight bidirec-
tional data and address leads (AD7 - AD0), along with
other microprocessor control leads, including a ready
(RDY) signal.
Typical Application
The E2/E3 Framer is used for wideband data
transport as shown in Figure 2. In the receive
direction, the E2/E3 Framer receives NRZ or dual rail
data from LIU, removes overhead bits and puts out
only the payload of the incoming signal to the
terminal. Overhead bits can be accessed through
microprocessor or by service bit interface. In the
transmit direction, the E2/E3 Framer receives data
generated from Data Source, adds framing pattern
and service bits and sends it out to LIU. The E2/E3
Framer handles wideband data at either 8448 or 34
368 Kb/s, and can optionally perform BIP-4 making
data transport more reliable.
To fix transmit time-base for the terminal payload multi-
plexer circuitry, while operating in the bit-serial mode,
the E2/E3F provides a transmit frame reference gener-
ator. The transmit frame reference generator accepts
an external 8.448 or 34.368 MHz clock signal (TCIN)
and produces a clock out signal (TCOUT), a framing
pulse (TFOUT), a clock gap signal (TCG), and a data
signal (TDOUT). The data signal consists of G.7XX
framing bits and zeros elsewhere.
The selection of the transmit line interface, dual rail or
NRZ, is controlled by the NRZLINE control lead, which
Line Side
Terminal Side
Rx
Line
E2/E3
Framer
Wideband
Interface
Data Sink/ Source
Unit
Tx
Overhead bit-I/O
Figure 2. Wideband Data Transport using E2/E3 Framer
5-21
MT90732 CMOS
Advance Information
Notes.
5-22
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