MT8910-1AP [MITEL]
CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit; CMOS ST- BUS⑩系列数字用户线接口电路
| 型号： | MT8910-1AP |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| 文件： | 总26页 (文件大小：422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS ST-BUS FAMILY MT8910-1
Digital Subscriber Line Interface Circuit
Preliminary Information
ISSUE 1
August 1993
Features
•
•
•
Compatible with ISDN U-Interface standard
Ordering Information
Over 40dB (@40 kHz) of loop attenuation
MT8910-1AC 28 Pin Ceramic DIP
Full duplex transmission over single twisted
pair
MT8910-1AP 44 Pin PLCC
0°C to +70°C
•
•
•
•
•
•
•
Advanced echo cancelling technology
High performance 2B1Q line code
Full activation/deactivation state machine
QSNR and line attenuation diagnostics
Frame and superframe synchronization
On-chip 15 second timer
Description
The MT8910-1 Digital Subscriber Line Interface
Circuit (DSLIC) is designed to provide ISDN basic
rate access (2B+D) at the U-interface. Full duplex
digital transmission at 160 kbit/s on a single twisted
pair is achieved using echo cancelling hybrid (ECH)
Insertion loss measurement test signal & quiet
mode
•
•
Mitel ST-BUS compatible
Single 5V power supply
technology.
This, in conjunction with the high
performance 2B1Q line code, allows the DSLIC to
meet the loop length requirements of the digital
subscriber loops at the U-interface over the entire
non-loaded telephone loop plant.
Applications
•
•
•
•
ISDN NT1 and NT2 DSL interface
Digital PABX line cards and telephone sets
Digital multiplexers and concentrators
Pair gain system
The MT8910-1 is compatible with the complete
range of Mitel Semiconductor ISDN components
through the use of the ST-BUS interface.
DAC and
Scrambler
& Encoder
DSTi
Transmit
Interface
+
-
Lout+
Lout-
Tx Filter
CDSTi
Non-
Linear
Jitter
Compen-
sator
Linear
Echo
Canceller
Control
Register
MRST
F0b
Compen-
sator
C4b
Tone
SFb
TRANSMIT/
RECEIVE TIMING
& CONTROL
Framing
&
Detector
F0od
MS0
MS1
Decision
Feedback
Equalizer
Maintenance
INTERFACE
NT/LT
Lin+
Lin-
2nd Order
PDM ADC
Status
Register
Quantizer
FIR
Digital Filter
Descrambler,
Decoder &
Diagnostics
Receive
Interface
CDSTo
DSTo
Timing
Adaptation
Circuit
Bias &
Voltage Ref.
VRef VBias
TSTen
TSTin TSTout
VSS AVSS VDD AVDD
OSC2 OSC1
Figure 1 - Functional Block Diagram
9-3
MT8910-1
Preliminary Information
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
40
44 43 42 41
6 5 4 3 2
Lout-
Lout+
AVSS
TSTin
CDSTi
DSTi
Lin+
Lin-
1
7
39
NC
CDSTi
NC
NC
8
38
37
36
35
34
33
32
31
30
29
AVDD
3
4
5
6
7
VRef
VBias
AVDD
IC
VDD
MRST
OSC1
OSC2
F0b
9
NC
10
11
12
13
14
15
16
NC
NC
NC
NC
DSTi
VSS
DSTo
CDSTo
F0od
NC
IC
VSS
VDD
DSTo
CDSTo
F0od
TSTout
MS0
8
9
MRST
OSC1
OSC2
NC
10
11
12
13
14
17
18 19 20 21 22 23 24 25 26 27 28
C4b
SFb
TSTen
MS1
NT/LT
28 PIN CERDIP
44 PIN PLCC
Figure 2 - Pin Connections
Description
Pin Description
Pin #
Name
DIP PLCC
1
1
L
Line Out Minus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q
signal, biased at V
out-
.
Bias
2
3
L
Line Out Plus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal,
biased at V
out+
.
Bias
3
4
5
6
AV
Analog Ground. Tie to V
.
SS
SS
TSTin I/O Structure Test Input. When TSTen is high, TSTin is used as a source to all output
drivers. Refer to “I/O Structure Test" in functional description for more details. Tie to V
for normal operation.
SS
5
6
8
CDSTi Control/Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D- and
C-channels in Dual mode. Unused in Single mode and should be connected to V
.
SS
12
DSTi Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are input.
7
8
13
14
V
Ground.
SS
DSTo Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are output. This output is
placed in high impedance during the unused channel times.
9
15
16
18
CDSTo Control/Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D- and
C- channels in Dual mode. It is placed in high impedance in Single mode, and during the
unused channel times in Dual mode.
10
11
F0od Delayed Frame Pulse Output. A 244 ns wide negative going pulse indicating the end of
the active ST-BUS channel times of the device to allow for daisy-chaining of other ST-BUS
devices. Active after channel 0 in Dual Port mode and Channel 3 in Single Port Mode.
TSTout I/O Structure Test Output. When TSTen is high, the TSTout provides the output of an
XOR chain which is sourced from all digital inputs. Refer to “I/O Structure Test" in
functional description for more details. Leave unconnected for normal operation.
12
13
19
20
MS0 Mode Select 0. CMOS input. Refer to Table 1.
MS1 Mode Select 1. CMOS input. Refer to Table 1.
9-4
Preliminary Information
MT8910-1
Pin Description (continued)
Pin #
Name
Description
DIP PLCC
14
21
NT/LT NT/LT Mode Select. CMOS Input. When high, the DSLIC is setup in NT mode. When
low, LT mode is selected.
15
22
TSTen I/O Structure Test Enable Input. This active high input enables the built-in test of all
digital input and output structures. Refer to “I/O Structure Test" in functional description for
more details. Tie to V for normal operation.
SS
16
23
SFb
Superframe Pulse. In LT mode, an input pulse once every superframe (12 ms) which,
when low during a falling edge of C4b within an F0b low pulse, sets the transmit
superframe boundary.
In NT mode, a 244 ns wide output pulse once every 12 ms indicating the boundary of the
transmit superframe. In NT mode, the superframe timing is generated from the line signal
time base and, as such, SFb will only be valid once the transceiver has achieved full
activation.
17
18
25
27
C4b
F0b
4096 kHz Data Clock. In LT mode, a 4096 kHz ST-BUS clock input. In NT mode, a 4096
kHz ST-BUS clock output frequency locked to the line signal.
Frame Pulse. In LT mode, an 8 kHz input pulse indicating the start of the active ST-BUS
channel times. In NT mode, an 8 kHz output pulse extracted from the line signal indicating
the start of the active ST-BUS channel times.
19
30
OSC2 Oscillator Output. When the MT8910-1 operates with an External Clock (typically LT
mode) connect OSC2 to the output of an external inverter providing a 10.24 MHz ±5ppm
clock (see “10.24 MHz Clock Interface" section).
When operating with a crystal (typically NT mode) connect one lead of the fundamental
mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).
20
31
OSC1 Oscillator Input. When the DSLIC operates with an External Clock (typically LT mode)
connect OSC1 to the input of an external inverter (see Fig.11).
When operating with a crystal (typically NT mode) connect the other lead of the
fundamental mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).
21
22
23
24
25
26
27
28
32
33
34
38
41
42
43
44
MRST Master Reset. Active low CMOS input performs a master reset of the DSLIC.
V
Power Supply Input.
DD
IC
Internal Connection. Leave unconnected.
AV
Analog Power Supply. Connect to V
.
DD
DD
V
Bias Voltage. Decouple to AV through a 1.0 µF ceramic capacitor.
SS
Bias
V
Reference Voltage. Decouple to AV through a 1.0 µF ceramic capacitor.
SS
Ref
L
Line Signal Input Minus. Internally biased at V
Bias.
in-
L
Line Signal Input Plus. Internally biased at V
No Connection. Leave circuit open.
in+
Bias.
2,4,7,
9 -11,
17,24
26,28
29,35
36,37
39,40
NC
9-5
MT8910-1
Preliminary Information
response filter which converts the digital
representation into an analog waveform. The
Functional Description
transmitted pulse is then passed through
a
The MT8910-1 Digital Subscriber Line Interface
Circuit (DSLIC) is a high performance, full duplex
transceiver which provides a complete interface to
the U-reference point as specified in ANSI T1.601-
1988. Operating in either master Line Terminator
(LT) mode or slave Network Terminator (NT) mode,
the DSLIC can be configured to operate at either end
of the Digital Subscriber Line (DSL). The DSLIC
supports full duplex transmission of a 2B + D-
channel format at 160 kbit/s over a single twisted
pair with about 40 dB of loop attenuation at 40 kHz.
To achieve this transmission performance, the
DSLIC uses a 2B1Q line code which is a four level
pulse amplitude modulated (PAM) signal with no
redundancy. This line code was approved by the
American National Standards Institute technical
committee T1E1. Using this line code, two binary
bits are converted into one four level quaternary
symbol. This results in an effective baud rate
reduction from 160 to 80 kbaud/s allowing the
transmission to benefit from reduced line attenuation
and improved immunity to near end crosstalk
(NEXT).
smoothing filter whose output is passed to a
differential line driver which is driving the line through
a passive hybrid network and line pulse transformer.
On the receive side, the pre-cancelled signal drives
a balanced receiver which feeds the input to an over-
sampled second-order delta sigma A/D converter.
The digital representation of the received signal
yields a Pulse Density Modulated (PDM) stream
which is digitally filtered and decimated to the 80 kHz
baseband. Intersymbol interference (ISI) introduced
by the loop is cancelled by a decision feedback
equalizer. This is achieved by taking a convolution
of the received pulse with the estimated impulse
response of the loop. The cancellation of ISI is
performed in parallel with the echo cancellation.
Estimated received echo is obtained by taking the
convolution of the transmit signal with the estimated
impulse response of the loop. Feedback from the
jitter compensator and the non-linear corrector
interact with the coefficients of the echo canceller to
reduce the error introduced by jitter and non-
linearities in the analog circuitry. The output of all
these blocks is summed together and the result is
the received data which is passed through a decoder
and descrambler before being sent out in TDM
bursts on the ST-BUS.
To complement the performance of the 2B1Q line
code, the DSLIC uses an advanced echo cancelling
hybrid (ECH) technique, by means of a transversal
filter, that provides greater than 60 dB of echo
cancellation.
This cancellation, along with all
equalization, is performed in the digital domain using
dedicated DSP hardware. Since a digital transversal
echo canceller gives a linear representation of the
echo, the MT8910-1 also has a non-linear echo
canceller which works in parallel with the transversal
filter to compensate for non-linearities in the transmit
path and the passive line termination. In addition, a
jitter compensator is used to correct errors in the
echo estimates which are sourced from corrections
in the received timebase. The jitter compensator will
interact directly with the echo taps in the transversal
filter.
Line Port
The DSLIC interfaces to the U-reference point as
defined in the ISDN Basic Access Reference model.
As such, the transceiver transfers full duplex, time
division multiplexed data at 160 kbit/s. This includes
two 64 kbit/s PCM voice or data channels (B-
channels), a 16 kbit/s signalling channel (D-channel)
and 16 kbit/s for synchronization and overhead.
The two 64 kbit/s channels are defined as the B1-
and B2-channels and they carry subscriber
information such as digitally encoded voice, circuit
switched data or packet switched data. The DSLIC
will transfer both B-channels transparently from the
ST-BUS port to the line port and vice versa once the
device has acquired superframe synchronization.
A block diagram of the DSLIC is shown in Figure 1.
The DSLIC has two ports consisting of a serial
system interface (Mitel's standard ST-BUS), and a
line port which interfaces directly to the single
twisted pair via a passive termination hybrid and a
line pulse transformer.
The 16 kbit/s D-channel is primarily intended to carry
signalling information for circuit switching the B-
channels through the ISDN network. The D-channel
can optionally carry packetized information and
telemetry services. The D-channel is transmitted
transparently through the DSLIC from the ST-BUS
port to the line port and vice versa once the device
has acquired superframe synchronization. It is to be
The two B-channels and the D-channel to be
transmitted on the line are input to the DSLIC (on the
ST-BUS) into the transmit interface block. The sync
word and maintenance bits are added to the data
which is then formatted, scrambled and digitally
encoded into 2B1Q symbols.
This digital
representation is passed through a finite impulse
9-6
Preliminary Information
MT8910-1
noted that the system interface has dedicated a full
64 kbit/s for the D-channel of which only the two first
bits (D0 and D1) are actually carrying information.
The other bits of the ST-BUS D-channel are reserved
for future use.
Before converting the bit fields into output symbols,
all bits except the framing pattern are scrambled with
polynomials:
-5
-23
-23
1
x
x
for LT
-18
1
x
x
for NT
A third type of channel, the C-channel, is a non-
bearer channel which provides a means for the
system to control and monitor the functionality of the
DSLIC. This control/status channel is accessed by
the system through the ST-BUS. The C-channel
provides access to three control registers and four
status registers which provide complete control or
status of all built-in features. Access to the control
register is provided by two bits in the Control
Register itself (CRS0 and CRS1). Selection of the
desired status register is performed using two bits in
(where is modulo two summation)
Framing
The frame structure in the DSLIC is 1.5 ms long and
consists of twelve 2B+D-channels delimited by the
framing pattern at the start of the frame and the
maintenance channel at the end. Framing for both
the LT and the NT is performed using a 9 symbol
synchronization word. This sync word (SW) has the
following structure:
Control Register 1 (SRS0 and SRS1).
The C-
channel also carries a control and status register for
the 4 kbit/s M-channel which can be used as an
additional maintenance channel.
description of these registers is discussed in the ST-
BUS port interface section.
A
detailed
Sync Word: +3, +3, -3, -3, -3, +3, -3, +3, +3
Eight DSLIC frames are grouped into a superframe
delimited by inverting the sync word (ISW):-3,-3, +3,
+3, +3, -3, +3, -3, -3. This second level of framing is
used to assign the M-channel bits as defined in the
ANSI T1.601-1988. The framing structure is shown
in Figure 4.
Line Code
The DSLIC transceiver uses the 2B1Q line code
which is a four level Pulse Amplitude Modulated
(PAM) code with no redundancy. The generation of
the 2B1Q signal is achieved by grouping two
consecutive bits into a bit field of which the first bit
represents the sign bit and the second represents
the magnitude. This yields four possible output
codes as shown in Figure 3 (note that +3, +1, -1 and
-3 are only symbols and they do not reflect the
voltage on the line).
Transmission between the LT and NT is fully
synchronous.
As such, the frame/superframe
boundaries between the NT receive frame and the
NT transmit frame have a fixed phase relationship.
The transmitted frame/superframe from the NT is
delayed by 60 ± 2 quaternary symbols (quats) with
respect to its received frame/superframe. Since the
NT extracts all its timing from the line, the DSLIC will
maintain the required phase relationship between
the frames and superframes and will insert the SW
and ISW during the proper time interval.
The bit fields are grouped relative to the borders of
the defined channels where the first bit field consists
of bit 1 and bit 2 of the B1-channel, the second bit
field consists of bit 3 and bit 4 of the B1-channel
and so on.
+3
+1
-1
-3
time
QUATS -1 +3
+1
-3
-3
+1
+3
-3
-1
-1
+1
-1
-3
+3
+3
-1
+1
BITS 0 1 1 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 0 1 0 0 1 1 1
Figure 3 - Example of 2B1Q Quaternary Symbols
9-7
MT8910-1
Preliminary Information
12 ms
Frame 4
1.5 ms
Superframe
Frame 1
Frame 2
Frame 3
Frame 5
Frame 6
Frame 7
Frame 8
Frame
SW 2B + D 2B + D 2B + D 2B + D 2B + D 2B + D 2B + D 2B + D 2B + D 2B + D 2B + D 2B + D
M
Information
Channels
B11 B12 B13 B14 B15 B16 B17 B18 B21 B22 B23 B24 B25 B26 B27 B28 D1 D2
50 µs 12.5 µs
50 µs
Corresponding
ST-BUS
B7 B6
B5 B4
B3 B2
B1 B0 B7 B6
B5
B4
B3 B2 B1
B0 D0
D1
Figure 4 - Frame Structure
Basic Frame Synchronization (BFS) is achieved
using the algorithm shown in Figure 5. The DSLIC
searches for the sync word or the inverted sync word
within the received data stream. After detecting
three consecutive synchronization patterns spaced
exactly 120 quats apart, the DSLIC declares terminal
synchronization by setting the bits of the Internal
State Indicator to 111 in Status Register 1. A loss of
synchronization is declared by the DSLIC when at
least one of the nine quats at the beginning of each
Basic Frame differs by more than one quantization
level for two consecutive frames.
status of internal state bits IS2, IS1 and IS0 found in
Status Register 1.
The DSLIC will lose superframe sync under three
conditions;
1) if the DSLIC loses basic frame sync,
2) if the ISW does not occur exactly eight basic
frames apart,
3) if the ISW is received when it is not expected.
A search for superframe synchronization will begin
only after Basic Frame sync has been found. The
DSLIC will declare superframe sync (SFS) on the
first occurrence of the properly spaced Inverted Sync
Word (ISW) once Basic Frame sync has been
acquired. The synchronized state is identified by the
Activation/Deactivation
The DSLIC has a complete activation/deactivation
state machine which allows the user to activate or
deactivate the link as per the requirements in the
> One-Level Error in SW
STATE : LOSING
BFS : 1
STATE : LOST
BFS
: 0
One
Valid
SW
Error in
SW
Error in
SW
> One-Level
Error in SW
Valid
SW
STATE : SENSING1
BFS
: 0
One
Valid
SW
STATE : SENSING2
BFS : 0
STATE : SYNC
BFS : 1
One Valid SW
Figure 5 - Frame Synchronization State Diagram
9-8
Preliminary Information
MT8910-1
T1.601-1988 standards. The activation sequence for
the DSLIC is mode dependent and is outlined in
Figures 6a) and b).
This handshaking of information is required to allow
individual transceivers to train both their echo
cancellers and decision feedback equalizers. All
possible signals are described below.
In the LT mode, the request for activation can be
initiated in two ways. Setting the start/stop bit in the
Control Register 1 will result in the generation of a
repeated pattern of four +3 symbols followed by four
-3 symbols producing a 10 kHz activation tone (TL)
for 3 milliseconds. The DSLIC can also be activated
by receiving a 10 kHz activation tone from the NT
•
TN:
A 10 kHz activation tone sourced by the
NT which is generated by sending a
continuous pattern of four +3 symbols
followed by four -3 symbols.
•
•
SN0: SN0 is a no signal condition which is
used to indicate to the LT that the NT
has finished training its echo canceller.
(TN).
Once the NT has generated a tone,
progression through the state machine follows the
algorithm as shown in Figure 6a.
SN1: An NT generated signal consisting of a
framed (but not superframed),
scrambled 2B1Q signal which carries all
1s in the B-, D- and M-channels. This
signal is used to train the NT’s echo
canceller.
In the NT mode, the request for activation can be
initiated in two ways. Setting the start/stop bit in the
Control Register 1 will result in the generation of a
repeated pattern of four +3 symbols followed by four
-3 symbols resulting in the transmission of the NT
•
•
SN2: An NT generated signal consisting of a
framed (but not superframed),
activation tone (TN).
The DSLIC can also be
scrambled 2B1Q signal which carries all
1s in the B-, D- and M-channels. This
signal is used to train the LT’s DFE.
activated by receiving TL from the LT to which the
NT will respond with its own activation tone (TN).
Progression through the state machine will follow the
algorithm as shown in Figure 6b.
SN3: An NT generated signal consisting of a
fully framed and superframed scrambled
2B1Q signal which carries information in
all the B-, D- and M-channels.
During the activation sequence, there is an extensive
exchange of signals between the LT and the NT.
ST.Tx = Start Timer x
STP.Tx = Stop Timer x
MRST Pin
LAR = Local Activation Request
LDR = Local Deactivation Request
SFS = Superframe Synchronization Acquired
Full Reset
Tx-SL0
Alerting
Tx-TL (3ms)
LAR
Expiry of T2
ST.T0
ST.T1
RCV Reset
Tx-SL0
RCV TN
ST.T0
Expiry of
T1
RCV TN
Awaiting Reply
Awake
Tx-SL0
RCV TN
STP.T1
ST.T0
STP.T2
Tx-SL0
End SN1
of T0
Expiry
EC Training
Tx-SL1
Expiry of T0
Expiry of T0
ST.T3
EC
Converged
(Loss of signal
and LDR) or
Expiry of T3
(Loss of
Framing
Tx-SL2
signal and
Expiry of T0
LDR),
ST.T2
STP.T3
ST.T3
SFS
STP.T0
Pending Deact.
Active
Tx-SL3
BFS Lost > 480ms1
Tx-SL0
or LDR
ST.T3
Note1: Loss of received signal will result in loss of sync.
T0 = 15 sec timer
T1 = 480 ms timer
T2 = 40 ms timer
T3 = 520 ms timer
Figure 6a - Activation/Deactivation State Diagram - LT Mode
9-9
MT8910-1
Preliminary Information
•
TL:
A 10 kHz activation tone sourced by the
LT which is generated by sending a
continuous pattern of four +3 symbols
followed by four -3 symbols.
•
•
SL2: An LT generated signal consisting of a
fully framed and superframed
scrambled 2B1Q signal which carries all
0s in the B- and D-channels with
information in the M-channel. This
signal is used to train the NT’s DFE.
•
•
SL0: SL0 is a no signal condition generated
from the LT.
SL3: An LT generated signal consisting of a
fully framed and superframed scrambled
2B1Q signal which carries information in
all the B-, D- and M-channels.
SL1: An LT generated signal consisting of a
framed (but not superframed),
scrambled 2B1Q signal which carries all
1s in the B-, D- and M-channels. This
signal is used to train the LT’s echo
canceller.
ST.Tx = Start Timer x
STP.Tx = Stop Timer x
MRST Pin
LAR = Local Activation Request
LDR = Local Deactivation Request
SFS = Superframe Synchronization Acquired
Full Reset
(Power down
Tx-SNO
Expiry of T2
RCV TL or
LAR
ST.T0
Loss of signal
RCV Reset
Tx-SN0
STP.T3
ST.T2
RCV TL
ST.T0
Alerting
Tx-TN (9 ms)
STP.T2
EC Training
Tx-SN1
Expiry of T0
Expiry of T0
Expiry of T0
EC
Converged
Expiry of T1
ST.T1
Quiet
Tx-SN0
Signal
Detected
STP.T1
Train
DFE/Timing
Tx-SN0
Loss of
far-end
signal
STP.T3
ST.T2
SL2
Detected
Expiry
of T3
Framing
Tx-SN2
ST.T3
SFS
ST.T3
T0 = 15 sec timer
T1 = 480 ms timer
T2 = 40 ms timer
T3 = 520 ms timer
Tear Down
Tx-SN0
Active
Tx-SN3
Pending Deact.
LDR
Tx-SN3
ST.T3
Loss of BFS > 480ms1
ST.T3
Note1: Loss of received signal will
result in a loss of sync.
Figure 6b - Activation/Deactivation State Diagram - NT Mode
9-10
Preliminary Information
MT8910-1
The reset state consists of two substates, the
receive reset state and full reset state. The full reset
state is entered following a power-up or after the
expiry of the receive reset timer (40 ms). The
receive reset state is a transient state which is
entered once the DSLIC has detected a loss of
received signal while the transceiver is not
transmitting. In this state, the transceiver will not
initiate the start-up sequence but is capable of
responding to the appropriate activation tone. When
the timer in the receive reset state has timed out (40
ms), the transceiver enters the full reset state.
The MT8910-1 is production tested for error free
performance for 2.5 sec (20,000 ST-BUS) frames
over a 4.6km (15 kft) 26 AWG simulated loop
(equivalent to 40dB attenuation @ 40 kHz).
ST-BUS Interface
The ST-BUS is
a
synchronous time division
multiplexed serial bussing scheme with data streams
operating at 2048 kbit/s configured as 32, 64 kbit/s
channels (refer to Figure 7). Synchronization of the
data transfer is provided from a frame pulse which
identifies the frame boundaries and repeats at an 8
KHz rate. Figure 7 shows how the frame pulse (F0b)
defines the ST-BUS frame boundaries. All data is
clocked into the device on the rising edge of the
4096 kHz clock (C4b) three quarters of the way into
the bit cell, while data is clocked out on the falling
edge of the 4096 kHz clock at the start of the bit cell.
All timers surrounding the reset states are included
in the DSLIC and have been set as per the ANSI-
T1.601-1988:
•
•
Failure to complete a start-up sequence
timer is set at 15 seconds.
Loss of received signal timer is set at
480 ms as is the loss of
synchronization.
The bits on the ST-BUS are numbered bit 7 to bit 0
as outlined in Figure 7. Information transferred from
the system port to the line port, will maintain the
integrity of the bit order.
•
•
The receive reset state timer is set to
40 ms.
A fourth timer (not specified in ANSI
T1.601-1988) has been included which
will restrict the time to 520 ms for a
deactivation sequence.
All timing signals, i.e., F0b, C4b and SFb, are
bidirectional. The I/O configuration of these pins is
controlled by the mode of operation (LT or NT). In
the LT mode, these timing signals must be supplied
from an external source and the MT8910-1 will in
turn uses these timing signals to transfer information
to and from the line port or the ST-BUS port. In the
NT mode, timing is generated from an on board
digital phase locked loop which extracts timing from
the received data on the DSL and generates the
system frame pulse (F0b), the system 4096 kHz
clock (C4b) and the system superframe pulse (SFb).
The DSLIC will enter a deactivated state on the
assertion of a deactivation request (setting the Start/
Stop bit to 0 in Control Register 1,
and the
subsequent loss of the received signal). Once the
deactivation process has been completed, the
request for activation can follow a warm start
process as defined in ANSI T1.601-1988.
Loop Performance
The superframe timing signal (SFb) is an active low
signal with a period of 12ms which is required to
provide a reference for structuring the maintenance
channel (M channel). In the LT mode, the SFb is an
input which, when set low during the system frame
pulse (F0b), will set the phase of the transmit
superframe. As an alternative, the SFb pin can be
tied high and the device will automatically establish
The MT8910-1 operates on a digital subscriber line
(DSL) which is a two wire twisted pair metallic
medium typically used for transmission between the
central office (LT) and the customer premise
equipment (more commonly referred to as "Basic
Access Interface on the Network side of the NT").
F0b
C4b
ST-BUS
CHANNEL 31
BIT 0
CHANNEL 0
BIT 7
CHANNEL 0
BIT 6
CHANNEL 0
BIT 5
CHANNEL 0
BIT 4
CHANNEL 0
BIT 3
CHANNEL 0
BIT 2
Bit
Cells
Figure 7 - ST-BUS Functional Timing
9-11
MT8910-1
Preliminary Information
the superframe position. This function can also be
activated in software (LT mode only) through a bit in
Control Register 1 (TxSFB). The transition of this bit
from a 1 to a 0 will reset the superframe counter, and
the beginning of the transmitted superframe will be
referenced to the ST-BUS frame after the frame in
which the transition in the TxSFB bit occurred.
superframe synchronization has been achieved. In
the NT mode, the TxSFB bit is ignored since the
transmit superframe has a fixed phase relationship
with respect to the received superframe.
The MT8910-1 has two possible system port
configurations; single port mode or dual port mode.
In the single port mode, the MT8910-1 uses the first
four timeslots of the DSTi and DSTo data streams
(as shown in Figure 8). ST-BUS Channel 0 is
allocated to the D-channel, ST-BUS Channel 1 to the
C-channel, while ST-BUS Channel 2 and 3 are
In the NT mode, the SFb pin is an output which
generates an active low signal at the boundary of the
transmit superframe. Since the SFb is referenced to
the receive time base, SFb is only valid after
F0b
C4b
DSTo
D0 D1
D0 D1
C7 C6
C7 C6
C1 C0 B7 B6
B1 B0 B7 B6
B1 B0
B1 B0
D0
D0
DSTi
F0od
C1 C0 B7 B6
B1 B0 B7 B6
15.6 µsec
Channel Time 0
D-Channel
Channel Time 1
C-Channel
Channel Time 2
B1-Channel
Channel Time 3
B2-Channel
Reserved
Figure 8 - ST-BUS Channel Assignments in Single Port Mode
F0b
C4b
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
B7
DSTi
C7 C6 C5 C4 C3 C2 C1 C0
D0 D1
C7
B7
C7
CDSTi
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
DSTo
CDSTo
F0od
C7 C6 C5 C4 C3 C2 C1 C0
D0 D1
3.9 µsec
62.5 µsec
125 µsec
Channel Time 16
Channel Time 0
Reserved
Figure 9 - ST-BUS Channel Assignment in Dual Port Mode
9-12
Preliminary Information
MT8910-1
allocated to the B1 and B2 channels, respectively. In
this mode, the CDSTi and CDSTo streams are not
used. In the dual port mode, the MT8910-1 uses
both the DSTi/DSTo streams as well as the CDSTi/
CDSTo streams to allow the separation of the data
and control. The two B-channels are routed through
the DSTi/DSTo streams and the C- and D-channels
are routed through the CDSTi/CDSTo streams. In
each case, timeslot 0 and 16 will carry the respective
channels (refer to Figure 9). To simplify line card
designs, the MT8910-1 provides a delayed frame
pulse (F0od) to eliminate the need for a channel
assignment circuit. This signal is used to drive
subsequent devices in the daisy chain configuration.
In this type of arrangement, only the first MT8910-1
in the chain will receive the system frame pulse (F0b)
with the following devices receiving its predecessor's
delayed frame pulse. In conjunction with the delayed
frame pulse, the unused timeslots on the ST-BUS
will be placed into a high impedance state to avoid
having contention on the system bus.
CRS1
CRS0 Definition
0
0
0
1
0
1
0
1
Control Register 1
Control Register 2
Control Register 3
Reserved
The C-channel on the ST-BUS must be continuously
written to every frame. If the user accesses a
Control Register, the information in the other Control
Registers is latched. Any input requested through
the Control Registers will be activated on the next
frame boundary.
Control Register 1
Setting CRS0 and CRS1=0 routes the C-channel to
Control Register 1 allowing access to the functions
described in Table 2.
described below.
These bits are further
Bits 7 and 6 of Control Register 1, SRS1 & SRS0,
select which status register will be output in the next
ST-BUS frame. The selection of the Status Register
is as follows:
Selecting the single port or the dual port mode is
performed using Mode Select 1 (MS1). With MS1=0,
the DSLIC is in the single port mode while MS1=1
places the DSLIC in the dual port mode. Mode
Select 0 (MS0) determines the order of the D- and C-
channels while the DSLIC is operating in the dual
port mode. With MS0 = 0, the C-channel is found
in timeslot 0 and the D-channel is found in timeslot
16. With MS0=1, the D-channel is found in timeslot
0 and the C-channel is found in timeslot 16 (refer to
Table 1).
SRS1
SRS0
Definition
0
0
1
1
0
1
0
1
Status Register 1
Status Register 2
Status Register 3
Status Register 4
Bit 5 of Control Register 1, TxSFB, is used to
establish the position of the transmit superframe (LT
mode only). Setting this bit from a logic one to a
logic zero will reset the frame counters on the next
occurrence of the frame pulse establishing the
superframe position. Once the boundaries to the
superframe have been established, the device will
sustain the position of the superframe by allowing
the counters to wrap around. The user can also
elect to set this bit to a logic zero with a periodicity of
12 ms.
Operating Mode
MS1
MS0
Dual/Single
DC/CD
0
0
1
1
0
1
0
1
Single
Single
Dual
DC
DC
CD
DC
Dual
Table 1. Truth Table for Mode Select Pins
Control/Status Channels
The Control and Status information between the
DSLIC transceiver and the controlling entity is
carried by the C-channel. The DSLIC has three input
registers; Control Register 1, 2 and 3 (selected
through the CRS0 and CRS1 bits) and four output
registers; Status Register 1 through Status Register
4 (selected through the SRS0 and SRS1 bits in
Control Register 1).
Bit 4 of Control Register 1, BSWAP, allows the
multiplexing of the two B-channels transferred over
the digital subscriber line with the B-channels
presented at the system interface. A logic high on
the bit will result in the B1-channel on the system
interface to be transmitted in the B2-channel on the
line port and vice versa. The same principle applies
to the B2-channel at the system interface.
The input C-channel is used to access Control
Registers 1, 2 and 3. Bit 0 and 1 of the C-channel
(CRS0 and CRS1) allows the selection of the desired
Control Register as described following.
Bit 3 of Control Register 1, CCRC, allows the user to
introduce errors in the CRC bits calculated by the
DSLIC. This allows the user to verify the error
detection protocol used over the M-channel.
9-13
MT8910-1
Preliminary Information
Bit 2 of Control Register 1, START/STOP, provides a
mechanism to allow the user to initiate a line
activation or deactivation. This bit is edge sensitive
with a low to high transition requesting an activation,
of a +3 or +1 symbol once every 1.5 ms. This will
generate pulses that can be used for template
measurements. The Insertion Loss Measurement
(ILM) test signal is a scrambled all 1s 2B1Q coded
signal which contain both the SW and ISW. This test
signal can be used to make insertion loss
measurements over the DSL loop. Lastly, the DSLIC
can be placed into a quiet mode to allow a Remote
Test Unit (RTU) to perform impulse noise, crosstalk
and other transient impairment measurements as
described in the ANSI "ISDN Management - Basic
Rate Physical Layer".
and
a
high to low transition requesting
a
deactivation.
The activation and deactivation
procedure will follow the protocol defined in the ANSI
T1.601-1988. The activation request will only be
recognized if the transceiver is in a full reset state.
Any activation attempt while the transceiver is in any
other state will be ignored.
Similarly, any
deactivation request generated while the transceiver
is not in the active state will be ignored.
Bit 3 of Control Register 2 (ADCGAIN) controls the
gain value of the A/D converter. This function can be
used to introduce more gain in the receive path when
the transceiver is being used over long loops.
Control Register 2
Setting CRS0=1 and CRS1=0 routes the C-channel
to Control Register 2 allowing access to the
functions described in Table 3. These bits are further
described below.
Bit 2 of Control Register 2 (MSWAP) may be used
when the DSLIC is operating as an LT within a line
card application. The mode swap feature has the
effect of changing the scrambling polynomial and
activation state machine such that it can simulate the
operation of an NT transceiver. This allows a
transmission test between two devices on the same
line card. (For this function to work properly, the
input clocks to the two devices must be frequency
locked.)
Bits 7 to 4 of Control Register 2 (DS4 to DS1)
provide access to the multiple diagnostic features
supported on the DSLIC as outlined in Table 3.
These include the per-channel loopbacks at the
system interface as well as a loopback at the line
interface.
Along with the extensive loopback
capabilities, the DSLIC also allows the generation of
multiple signals which can be used during
qualification and servicing of a DSL. The isolated
pulse test diagnostics signal causes the transmission
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRS1
SRS0
TxSFB
BSWAP
CCRC
START/STOP
CRS1
CRS0
Bit
Name
Description
7,6
SRS1, SRS0 Status Register Select. Selects which of the four status registers will be output in the next ST-
BUS frame.
5
TxSFB
Transmit Superframe Reset. In LT mode, transition from a 1 to a 0 on this bit resets the
superframe counters in the next ST-BUS frame in order to establish the transmit superframe
boundary. If the external pin is being used to set the superframe boundary this bit can be held
high or low. Not used in NT mode.
4
BSWAP
CCRC
When this bit is set to 1, the location of the B1 channel on the ST-BUS is swapped with the
location of the B2 channel. This affects both directions of the ST-BUS.
3
2
Corrupt CRC. When set to 1, the 12 bit CRC transmitted on the line is corrupted.
START/STOP A low to high transition while the transceiver is in the full reset state will initiate one activation
attempt. A high to low transition of this bit while the transceiver is in the active state will initiate a
deactivation procedure. During start-up, 2B+D channels should remain set to 0 or 1 until
transparency of network is achieved (indicated by act=1).
1, 0
CRS1, CRS0 Control Register Select 1 and 0. Must be set to 0, 0 to address Control Register 1.
Table 2. Control Register 1
9-14
Preliminary Information
MT8910-1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS4
DS3
DS2
DS1
ADCGAIN
MSWAP
CRS1
CRS0
Bit
Name
Description
7,6,
5,4
DS4 - DS1
Diagnostic Select Bits.
DS4
0
DS3
0
DS2
0
DS1
Channels
Function
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-
Normal Operation
1
0
0
0
B1
STi to STo Loopback
1
0
0
1
B2
STi to STo Loopback
1
0
0
1
B1 + B2
STi to STo Loopback
1
0
1
0
2B + D
STi to STo Loopback
2
0
1
0
B1
STo to STi Loopback
2
0
1
1
B2
STo to STi Loopback
2
0
1
1
B1 + B2
STo to STi Loopback
2
1
0
0
2B + D
STo to STi Loopback
1 3
1
0
0
ALL
L
to L Loopback
out in
4
4
1
0
1
-
-
-
-
-
-
Isolated +3 pulse
Isolated +1 pulse
1
0
1
1
1
0
Transmit 10 kHz Tone
5
1
1
0
ILM Test Signal
1
1
1
Quiet Mode
Reserved
1
1
1
3
2
ADCGAIN
MSWAP
Selects between two gain values in the delta-sigma A/D converter. When high, selects a 3 dB
higher gain.
Mode Swap. In the LT mode, MSWAP=1 will result in the DSLIC using the NT’s scrambling/
descrambling polynomials and activation sequence. This allows two DSLICs on the same LT line
card to exchange static data in the B- and D- channels.
MSWAP can also be used in the NT mode.
1, 0
CRS1, CRS0 Control Register Select 1 and 0. Must be set to 0, 1 respectively to address Control Register 2.
Table 3. Control Register 2
The ST-BUS incoming data is still output on the line if the MT8910-1 is activated. Supported in both SINGLE and DUAL port modes.
The incoming data from the line is still output on to the ST-BUS. The other incoming channels on the ST-BUS are still output on to
the line if the device is activated. Supported in both SINGLE and DUAL port modes.
Signal is internally looped back and is still output to the line and overrides the internal activation state machine.
One pulse is transmitted every 1.5 ms.
The Insertion Loss Measurement Test Signal is a scrambled (all one’s data), framed 2B1Q signal.
1
2
3
4
5
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
M1
M2
M3
M4
M5
M6
CRS1
CRS0
Bit
Name
Description
7 - 2
M1 - M6
Tx Maintenance Channel Bits 1 to 6. M-bits which will be transmitted at the end of the next DSL
Basic Frame. Refer to “Maintenance Channel“ section in the functional description
1, 0
CRS1, CRS0 Control Register Select 1 and 0. Must be set to 1, 0 respectively to address Control Register 3.
Table 4. Control Register 3
9-15
MT8910-1
Preliminary Information
Control Register 3
Control Register 2:
C7 C6 C5 C4 C3 C2 C1 C0
Setting CRS1 and CRS0 to 1, 0, respectively, routes
the input C-channel to Control Register 3, allowing
access to the transmit M-bits as shown in Table 4.
The transmit M-channel is a 4 kbit/s maintenance
channel which may carry the EOC messages (with
overhead) as specified in T1.601-1988. Except for
the CRC bits, the M-bits are treated as a transparent
data channel through the DSLIC. CRC bits will be
generated by the transceiver and will be inserted into
the M-channel during their respective M-bit time
slots. (This implies that all input M-bits which are
defined as CRC bits will be overwritten by the
transceiver.) Structuring of the M-bits is described in
the “Maintenance Channel" section of the functional
description.
0
0
0
0
0
0
0
1
Control Register 3:
C7 C6 C5 C4 C3 C2 C1 C0
1
1
1
1
1
1
1
0
Status Register 1
When SRID1=0 and SRID0=0, the contents of
Status Register 1 are being output in the C-channel
allowing the system to monitor the functions
described below. (Refer to Table 5.)
Control Words After Reset
Bits 7 and 6 of Status Register 1, SRID1 and SRID0,
are used to identify which status register is being
carried in the output C-channel. These bits are
encoded as follows:
Applying a logic low to the MRST pin will result in the
three control registers assuming a reset state.
Following a master reset, the three Control Registers
will take the following states:
SRID1 SRID0 Definition
0
0
1
1
0
1
0
1
Status Register 1
Status Register 2
Status Register 3
Status Register 4
Control Register 1:
C7 C6 C5 C4 C3 C2 C1 C0
0
0
1
0
0
0
0
0
bit 7
SRID1
bit 6
bit 5
bit 4
IS1
bit 3
bit 2
bit 1
bit 0
SRID0
IS2
IS0
RxSFIB
RSV
CRCERR
Bit
Name
SRID1, SRID0 Status Register ID. Always reads 0,0 when Status Register 1 is output.
IS2, IS1, IS0 Internal State Indication.
Description
7,6
5,4,3
IS2
0
IS1
0
IS0
0
Definition
Full Reset State
0
0
1
Training with no Basic Frame Sync
0
1
0
Training with Basic Frame Sync but no Superframe Sync
Training with Basic Frame Sync and Superframe Sync
Loss of synchronization after E.C. has converged
NA
0
1
1
1
0
0
1
0
1
1
1
0
Loss of superframe sync after E.C. has converged
Active State
1
1
1
2
RxSFIB
Received superframe Indication. When low, indicates the beginning of the received superframe.
This bit is low for one ST-BUS frame, then high for 95 ST-BUS frames.
1
0
RSV
Reserved. Always read a 0.
CRCERR
When “1”, the received CRC code did not match with a locally generated CRC code, indicating
that the received data included an error. When “0”, the received CRC code matched with the
internally generated CRC.
Table 5. Status Register 1
9-16
Preliminary Information
MT8910-1
Bits 5, 4 and 3 of Status Register 1, IS2, IS1 and
IS0, provide an indication of the internal state of the
device. The decoded states are as follows:
Status Register 2
When SRID1=0 and SRID0=1, the contents of Status
Register 2 are being output in the C-channel allowing
the system to monitor the status of the quantizer
signal to noise ratio bits (refer to Table 6). The
QSNR bits reflect the eye closure of the received
signal and represent the signal (+1 symbol) to noise
ratio at the input of the quantizer. This information
can be used to indicate the error performance of the
IS2
0
IS1 IS0 Definition
0
0
1
0
1
0
Full Reset
0
Training with no sync
0
Training with sync but no
superframe sync
0
1
1
Training with sync and superframe
sync
transceiver.
For a more accurate indication of
QSNR, these bits should be averaged over a period
of 64 ST-BUS frames (640 baud). The conversion of
the five bit output to QSNR is shown in Table 6. For
a bit error rate of greater than 10 , the theoretical
QSNR should be greater than 15.7dB.
1
1
1
1
0
0
1
1
0
1
0
1
Loss of sync
NA
-7
Loss of superframe sync
Active
Status Register 3
Bit 2 of Status Register 1, RxSFIB, is used to
indicate the reception of the receive superframe
boundary in both the LT and NT modes.
When SRID1=1 and SRID0=0, the contents of Status
Register 3 are being output in the C-channel allowing
the system to monitor the mean level of the received
symbols (refer to Table 7). The Received Pulse
Amplitude bits (RPA4 to RPA0) provide an estimate
of the attenuation of the loop. The representation of
the RPA bits is shown in Table 7.
Bit 0 of Status Register 1, CRCERR, indicates the
state of the CRC check. A logic high on this bit
states that the CRC check calculated by the
MT8910-1 did not correspond to the CRC bits
received in the M-channel. This bit will only be
updated once every superframe.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRID1
SRID0
QSNR4
QSNR3
QSNR2
QSNR1
QSNR0
NA
Bit
Name
Description
7,6
SRID1, SRID0 Status Register ID. Always reads 0, 1, respectively, when Status Register 2 is output.
5,4,3,
2,1
QSNR4,
QSNR3,
QSNR2,
QSNR1,
QSNR0
Quantizer Signal to Noise Ratio Bits. (see Note 1)
QSNR4 (MSB) -
QSNR0 (LSB)
00000
MEAN
QSNR (dB)
>36.1
36.1
QSNR4 (MSB) -
QSNR0 (LSB)
10000
MEAN
QSNR( dB)
12.1
11.5
11.0
10.6
10.1
9.7
00001
10001
10010
10011
10100
00010
30.1
00011
26.6
00100
24.1
00101
22.2
10101
00110
20.6
10110
9.3
00111
19.2
10111
8.9
01000
18.1
11000
8.5
01001
17.1
11001
8.2
01010
16.1
11010
7.9
01011
15.3
11011
7.5
01100
14.6
11100
7.2
01101
13.9
11101
6.9
01110
13.2
11110
6.6
01111
12.6
11111
6.3
0
NA
Reserved. Always reads 0.
Table 6. Status Register 2
Note 1) Not Production Tested
9-17
MT8910-1
Preliminary Information
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRID1
SRID0
RPA4
RPA3
RPA2
RPA1
RPA0
RSV
Bit
Name
Description
7,6
SRID1, SRID0 Status Register ID. Always reads 1, 0, respectively, when Status Register 3 is output.
5,4,3,
2,1
RPA4-RPA0
Receive Pulse Amplitude bits (see Note 1).
Relative
Relative
Amplitude (dB)
-7.76
-6.02
-4.57
-3.33
-1.74
0
RPA4 - RPA0
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
Amplitude (dB)
-31.85
-30.10
-28.65
-27.41
-25.83
-24.08
-22.63
-21.39
-19.80
-18.06
-16.61
-15.37
-13.78
-12.04
-10.59
-9.35
RPA4 - RPA0
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
1.45
2.69
4.28
6.02
NA
NA
NA
NA
NA
NA
Notes:
Loop length can be calculated by dividing Receive Pulse Amplitude (RPA) by the typical
cable attenuation for a 2B1Q pulse.
Relative amplitude is based on RPA reading of zero line length with recommended
termination and transformer (ADC Gain = 0).
0
RSV
Reserved. Always reads 0.
Table 7. Status Register 3
Note 1) Not Production Tested
bit 7
bit 6
SRID0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRID1
M1
M2
M3
M4
M5
M6
Bit
Name
Description
7,6
SRID1, SRID0 Status Register ID. Always reads 1, 1, respectively, when Status Register 4 is output.
5,4,3,
2,1,0
M1 - M6
Rx Maintenance Channel Bits 1 to 6. M-bits which were received at the end of the last DSL Basic
Frame. Refer to the "Maintenance Channel" section in the functional description for the
structuring of the received M-bits.
Table 8. Status Register 4
ST-BUS Frame Access
M1
M2
M3
M4
M5
M6
0 - 9
M11
M12
M13
M14
M15
M16
M17
M18
M21
M22
M23
M24
M25
M26
M27
M28
M31
M32
M33
M34
M35
M36
M37
M38
M41
M42
M43
M44
M45
M46
M47
M48
M51
M52
M61
M62
12 -21
24 - 33
36 - 45
48 - 57
60 - 69
72 - 81
84 - 93
CRC1
CRC3
CRC5
CRC7
CRC9
CRC11
CRC2
CRC4
CRC6
CRC8
CRC10
CRC12
Table 9. Maintenance Channel Bit Assignment on ST-BUS Port
9-18
Preliminary Information
MT8910-1
Status Register 4
bits for all DSL basic frames are written to Control
Register 3 once every 1.5ms within the ST-BUS
frames indicated in Table 9. If the user fails to
update the contents of Control Register 3 within the
allocated window, the M-bits will be substituted by
ones until the information in Control Register 3 is
updated. On the receive path, the Rx M-bits from
each DSL basic frame are available in Status
Register 4 within the ST-BUS frames indicated in
Table 9. The Rx M-bits will be updated every DSL
basic frame (or 1.5 ms).
When SRID1=1 and SRID0=1, the contents of the
Status Register 4 are being output in the C-channel
allowing the system to monitor the received
maintenance channel bits M1 to M6 as specified in
Table 8. The received M-bits may carry the EOC
message (with overhead) as specified in T1.601-
1988. Refer to the “Maintenance Channel“ section
for further details.
Maintenance Channel
The M-bits are structured according to the transmit
and receive superframe boundary signals output on
the ST-BUS. The transmit superframe boundary is
defined relative to the input or output SFb signal. (In
LT mode, the transmit superframe boundary can also
be defined in the frame following the TxSFB bit being
set to zero.) The ST-BUS frame in which the SFb
signal is active is defined as transmit frame 0. The
superframe boundary in the receive path is defined
relative to the RxSFIB bit found in Status Register 1.
The ST-BUS frame with RxSFIB=0 is defined as the
receive frame 0. The functional timing diagram for
the phase of the SFb and RxSFIB signals for both
the LT and NT modes is shown in Figure 10.
The MT8910-1 has provisions for transmitting and
receiving a 4 kbit/s maintenance channel from the
system port to the line port. The maintenance
channel at the line port is structured into six columns
of which M5 and M6 carry the results of a CRC
calculation (refer to Table 9). All bits except these
CRC bits are treated as a transparent channel to the
MT8910-1. The 12 bit cyclical redundancy check is
computed using the generator polynomial:
12
11
3
2
x
x
x
x
x
1
(where is modulo two summation)
The CRC calculation covers all 2B + D-channels
within a superframe as well as the M4 column within
the maintenance channel.
In applications which do not utilize the maintenance
channel, 2B+D data at the NT and the LT should be
all set to 0 or 1 until activation occurs at the LT.
Since the NT trains up before the LT, the activation at
the LT can be detected at the NT by the reception of
random data. Only then the NT can transmit normal
2B+D data.
Access to the maintenance channel is granted
through Control Register 3 (Tx M-Channel) and
Status Register 4 (Rx M-Channel) and is structured
on the ST-BUS port as shown in Table 9. The Tx M-
LT Mode
ISW
12x(2B + D)
ISW
M
SW
12x(2B + D)
SW
M
SW
12x(2B + D)
M
Tx Line Signal
12x(2B + D)
M
12x(2B + D)
Rx Line Sigmal
SFb pin
RxSFIB bit
NT Mode
Rx Line Signal
ISW
12x(2B + D)
ISW
M
SW
12x(2B + D)
SW
M
SW
12x(2B + D)
M
Tx Line Signal
12x(2B + D)
M
12x(2B + D)
SFb pin
RxSFIB bit
7 ST-BUS Frames
Figure 10 - Functional Timing for Superframe Signals
9-19
MT8910-1
Preliminary Information
10.24 MHz Clock Interface
I/O Structure Test
The MT8910-1 can operate either with an external
clock or with a built-in oscillator clock using a 10.24
MHz parallel resonance crystal. While using the
external clock, the timing relationship between C4b
and the external clock should be as shown in Figure
15. This is typically used in LT mode. To meet the
specified line performance, the tolerance of the
external clock should be ±5ppm. In NT mode, the
MT8910-1 can use the built-in crystal oscillator
circuit for internal timing, and to meet the specified
line performance, the tolerance of the crystal is
specified to be ±50ppm.
The MT8910-1 has a built-in test structure that
allows verification of all digital I/O structures. The “I/
O Structure Test“ is a static test designed to allow a
parity check on all digital inputs, force all digital
output drivers to any state as well as placing all
digital outputs into a high impedance state. These
three variables can be used to verify the integrity of
the connections between the MT8910-1 and the
printed circuit board.
The I/O structure test has three dedicated pins which
are used to; enable the test structure (TSTen),
provide an output (TSTout) of an XOR chain that is
used to verify all digital input pins, as well as
providing an input signal (TSTin) to all output drivers.
Before enabling the test structure, the default I/O
structure must be cleared to avoid interference with
the test results. This can be accomplished by
inserting the test vectors as defined in Table 10
below. Once the initialization procedure has been
run, the respective testing mode can be enabled
using the three mode select pins MS0, MS1 and NT/
LT.
The oscillator in the MT8910-1 uses the Pierce
circuit configuration. In this type of oscillator, the
necessary phase shift is obtained by the two
components connected in series; one of them is the
crystal itself, and the other is the RC combination of
the output impedance of the inverter and the
capacitor connected to its output and the ground.
This requires the output impedance of the inverter to
be high for minimizing the power consumption of the
MT8910-1. When OSC1 is used as an input for an
external clock (typically in LT mode), the high output
impedance of the inverter coupled with any stray
capacitance on the OSC2 pin can distort the
waveform and change the duty cycle of the clock
signal fed to the internal blocks of the MT8910-1.
This may result in improper operation. Hence, it is
recommended that an external inverter be connected
in parallel strengthening the internal inverter as
shown in Figure 11.
The I/O structure test allows the verification of the
connection between the printed circuit board and the
digital input pins to the MT8910-1. After running the
initialization sequence described above, the I/O input
structure test can be enabled by setting TSTen to a
logic high with the mode select pins MS0, MS1 and
NT/LT set to 1, 0, 1 respectively. This forces all
digital inputs to be linked into an XOR chain whose
output drives the I/O structure test output (TSTout)
1
pin . The TSTout pin will carry the output of the XOR
comparison from signals on pins, CDSTi, DSTi,
Initialization
Input Tests
Output Tests
Time Stamp (e.g.: 1 µs)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
1
1
1
0
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
0
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
TSTen
MS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
Input
Signals
MS1
NT/LT
TSTin
CDSTi
DSTi
MRST
OSC1
DSTo
CDSTo
F0od
OSC2
TSTout
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
H
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
X
X
X
X
L
X
X
X
X
H
X
X
X
X
X
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
Z
Z
Z
1
Z
Output
Signals
C4b
F0b
SFb
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
0
0
0
0
0
1
X
X
X
0
0
0
1
1
1
0
0
0
Z
Z
Z
Bidirectional
Signals
Table 10. I/O Structure Test Vectors
X=Don’t Care
9-20
Z=High Impedance State
Preliminary Information
MT8910-1
VDD
MT8910-1
OSC1
10.24 MHz Clock
74HC04
20
19
22
VDD
0.1µF
0.1µF
1µF
74HC04
24
*
OSC2
AVDD
Lout+
Lin+
1µF
17
18
4.096 MHz Clock
2
28
27
C4b
F0b
1:1.3
8 kHz Frame Pulse
M
H
8
9
1
0
1
12ms Superframe Pulse16
SFb
1.5µF
6
PCM or Data In
Lin-
DSTi
PLT
8
PCM or Data Out
1
25
26
Lout-
DSTo
MS0
MS1
12
13
14
4
VBias
VRef
TO LINE FEED
SUPPLY
NT/LT
TSTin
TSTen
CDSTi
MRST
1.0µF
1.0µF
9
23
11
CDSTo
15
IC
5
TSTout
*Duty cycle: 45% to 55%
21
System Reset
TO NEXT DSLIC
IN CHAIN
10
F0od
7
3
VSS
AVSS
Figure 11 - Typical Connections for LT Mode (Single Port)
MRST, OSC1, C4b, F0b and SFb. TSTout=0 if all
Applications
input signals carry an even number of ones and
TSTout=1 if all input signals carry an odd number of
ones.
The typical connection diagrams are shown in
Figures 11 and 12.
In Figure 11, the MT8910-1
receives all its timing from the system including the
C4b, F0b and a frequency-locked 10.24 MHz master
clock. In Figure 12, the MT8910-1 is configured in
the NT mode which implies that all timing signals
including the F0b, C4b and SFb are being sourced
The I/O structure test also allows the verification of
the connection between the digital output pins and
the printed circuit board.
After running the
initialization sequence, the I/O structure output test
can be enabled by setting the TSTen to a logic high
with the mode select pins MS0, MS1 and NT/LT set
to 1, 1, 0 respectively. This causes all digital outputs
to be driven from the I/O structure test input (TSTin)
from the MT8910-1.
These timing signal are
generated from an internal DPLL which divides a
10.24 MHz reference frequency down to a baseband
160 kHz. A comparison is performed on the
reference signal with the received line signal to
determine if the timing signals on the MT8910-1
have to be corrected.
pin1.
The outputs affected include the DSTo,
CDSTo, F0od and TSTout
These same outputs can also be placed into a high
impedance state to allow the bed-of-nails tester or
some other in-circuit tester to drive a known signal or
pattern on any circuitry that may be connected to the
output pins of the MT8910-1. The high impedance
state is enabled by running the initialization pattern
described above then setting TSTen to a logic one
with the mode select pins MS0, MS1 and NT/LT set
to 1, 0, 0 respectively.
The MT8910-1 is interfaced to the transmission line
through the Passive Line Termination network (PLT)
and transformer. The PLT provides the two to four
wire
conversion
and
additional
frequency
compensation for the received signal. The whole
circuit is DC isolated from the line by the low
inductance transformer.
Note 1
:
Allow a propagation delay of approximately 800ns
from digital input to XOR output or TSTin to any
digital output.
9-21
MT8910-1
Preliminary Information
VDD
MT8910-1
22
20
19
VDD
OSC1
OSC2
1µF
0.1µF
0.1µF
10.24 MHz
Xtal
24
AVDD
33pF
33pF
1µF
17
18
2
C4b
F0b
SFb
Lout+
M
H
8
CLOCKS
16
28
27
Lin+
Lin-
9
1.5µF
1
6
8
DSTi
PCM OR
DATA
0
1
DSTo
PLT
VDD
1
Lout-
12
MS0
MS1
13
14
4
25
VBias
VRef
CDSTo
IC
26
9
NT/LT
TSTin
TSTen
CDSTi
MRST
TO DC-DC
CONVERTER
23
11
15
1.0µF
1.0µF
5
TSTout
F0od
21
10
System Reset
7
3
VSS
AVSS
Figure 12 - Typical Connections for NT Mode (Single Port)
Passive Line Termination Network (PLT)
Transformer Specification
The termination network is an all passive circuit
which allows the MT8910-1 to interface to the DSL
line through a line pulse transformer. The passive
line termination consists of three blocks which
includes a hybrid network, a compensator circuit and
a line pulse transformer (refer to Figures 13 and 14).
All subscriber equipment which is to be connected to
a digital subscriber line, must deliver an output pulse
which satisfies both the pulse template and the pulse
PSD as specified earlier.
The output drive
characteristics of the MT8910-1 requires
a
transformer with a turns ratio of 1:1.3 having the
electrical characteristics specified in Figure 14.
The hybrid network is a 2 to 4 wire converter which
provides limited precancellation of near end echo.
The hybrid specified in Figure 13 was optimized for
the specified transformer and a 10 ohm series
protection resistor (Rp).
For supporting initial design activities, Mitel
Semiconductor has made available the MB6024
Magnetic Kit which contains the transformer shown
in Fig. 14.
The compensator circuit, in conjunction with the
transformer, acts as a high pass filter which is
designed to increase the cut-off frequency in the
receiver path. This has the effect of reducing the low
frequency content in the received line signal which in
turn reduces the effects of ISI and near end echo
thereby improving transceiver performance.
The low inductance transformer allows for the
possibility of passing a sealing current and/or
phantom feed supply through the secondary winding
without saturating the magnetic core.
The
transformer specified in Figure 14 has been
designed to carry typically 50 mA of DC current.
9-22
Preliminary Information
MT8910-1
Rs = 30.2 Ω
Lout+
3.3 nF
680 pF
Rb1
Rb2
1 KΩ
1.6 KΩ
10 Ω ±10%
1:1.3
XFM+
130 KΩ
20 KΩ
Lin+
5.5 mH
1.5 µF
Power
Feed/Extract
7.8 KΩ
68.2 KΩ
7 mH
Lin-
5.5 mH
10 Ω ±10%
20 KΩ
130 KΩ
XFM-
Rb2
Rb1
1 KΩ
1.6 KΩ
680 pF
3.3 nF
Lout
-
Rs = 30.2 Ω
Note 1: All resistors have a tolerance of ±1% unless indicated otherwise. All capacitors have a tolerance of ±10%.
Note 2: May be incorporated on to a ceramic substrate.
Figure 13 - Passive Line Termination (PLT)
➃
2
TURNS RATIO
RESISTANCE
INDUCTANCE
1:1.3
7
R1 = 5-8 3.7 Ω
R2 = 2-12 6.8 Ω
➂
➀
8
5
11
1
LP = 5-8 7 mH
LS = 2-12 11 mH
②➂
Leakage Inductance (Sec. Short Circuit) < 75µH @ 40 kHz.
LONGT. BAL.
0 - 4 kHz
4-160 kHz
min 63 dB
min 58 dB
6
12
NOTES:
➀
②
➂
➃
Open Circuit Secondary
Open Circuit Primary
With pins 1 and 11 shorted together
Filtran Part Number TPW 4671
Figure 14 - Transformer Specification
9-23
MT8910-1
Preliminary Information
Absolute Maximum Ratings*
Parameters
Symbol
Min
Max
Units
1
2
3
4
5
Supply Voltage
V
-0.3
-0.3
7.0
V
V
DD
Voltage on any I/O pin
Current on any I/O pin
Storage Temperature
Package Power Dissipation
V
V
+0.3
DD
I/O
I/O
I
20
mA
°C
T
-55
125
ST
P
1000
mW
D
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Note 1: Except for V , AV , V , AV , L and L
.
out-
DD DD SS SS out+
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Supply Voltage
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
V
4.75
4.75
5.00
5.00
5.25
5.25
V
V
(see Note 1)
DD
Analog Supply Voltage
AV
Relative to AV
(Note 1)
SS
DD
Input Low Voltage (except OSC1,
MRST, MS0, MS1, NT/LT
V
0.4
for 400mV noise margin
for 400mV noise margin
IL
4
5
6
7
Input High Voltage (except OSC1,
MRST, MS0, MS1, NT/LT
V
2.4
V
V
IH
Input Low Voltage for OSC1/2,
MRST, MS0, MS1, NT/LT
V
1.0
70
IL
Input High Voltage for OSC1/2,
MRST, MS0, MS1, NT/LT
V
4.0
0
V
IH
Operating Temperature
T
°C
A
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Note 1: To obtain optimum line performance, noise level on supply must be less than 25 mVpp.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym Min
Typ
Max Units
Test Conditions
1
2
3
4
5
Input High Voltage (except OSC1,
MRST, MS0, MS1, NT/LT
V
2.0
3.0
V
IH
Input Low Voltage (except OSC1,
MRST, MS0, MS1, NT/LT
V
0.8
V
V
IL
I
N
P
Input High Voltage for OSC1/2,
MRST, MS0, MS1, NT/LT
V
IH
U Input Low Voltage for OSC1/2,
T
S
MRST, MS0, MS1, NT/LT
V
2.0
10
V
IL
Input Leakage Current (except
OSC1)
I
µA
V
V
= V to V
SS
IL
IN
IN
DD
DD
6
7
Input Current for OSC1
I
50
100
µA
= V to V
SS
IC
Input Impedance (L to L
)
Z
in
250
kΩ
@ DC
in-
in+
9-24
Preliminary Information
MT8910-1
DC Electrical Characteristics (continued) - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Voltage
Sym Min
Typ
Max Units
Test Conditions
8
9
V
V
V
V
0.5AV
V
Relative to AV
Bias
Bias
DD
SS
C =1 µF minimum to AV
L
SS
Voltage
V
-1.9
V
Relative to V
Bias
Ref
Ref
C = 1µF minimum to AV
L
SS
10
11
12
13
14
15
and/or V
load
V
1
MΩ (see Note 2)
Bias
Ref
BL
(1)
Output High Voltage
Output Low Voltage
V
2.4
V
V
V
V
I
I
I
I
=10mA
OH
OH
(1)
V
0.4
= 5.0mA
OL
OL
O
U
T
P
U
T
OSC2 Output High Voltage
OSC2 Output Low Voltage
Differential Output Voltage
V
3.5
1.5
=10µA
OH
OH
V
=10µA
OL
OL
(L
to L
)
V
6.4
0.5
V
R =40Ω
L
out+
out-
out
pp
16
17
Output Impedance
(L
Measured by sourcing and
sinking 10 mA. Line Driver
active.
S
, L
)
Z
Ω
out+ out-
out
Output Capacitance
(L , L
)
C
50
10
pF
µA
(see Note 1)
out+ out-
o
OZ
DD
18
19
High Impedance Leakage
Supply Current
I
I
65
10
mA Line Drivers active and
unloaded.
mA Low Power Mode
I
DD
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
(1) except OSC2
Note
1) This is a specification on the maximum parallel capacitance to AC ground, connected directly to the pins. Higher
capacitance is acceptable when placed in series with resistor networks such as the line termination impedance.
2) Not production tested.
VIH
VIL
C4b
tJC
tOCH
tJC
tMCF
(See Note 3)
VIH
VIL
OSC2
tOCT
tOCT
Figure 15 - External Clock Timing in LT Mode
AC Electrical Characteristics†- External Clock Timing (Ref. Figure 15)
‡
Characteristics
Sym
1/t
Min
Typ
Max
Units
Test Conditions
1
2
OSC2 Clock Frequency
OSC2 Clock Duty Cycle
10.24
50
MHz (see Notes 1, 2 & 3)
%
MCF
t
/
45
55
OCH
t
MCF
3
4
OSC2 Clock Transition Time
C4b Jitter (wrt OSC2)
t
10
ns
OCT
t
-15
+15
ns
(see Note 3)
JC
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Notes: 1)
External clock tolerance of ±5 ppm in LT mode or ±50 ppm in NT mode is required.
Absolute jitter on OSC2 must be less than 2.0ns RMS in order to maximize performance.
In LT mode the C4b and OSC2 clocks must be externally frequency locked (i.e., fOSC2 = 2.5 x fC4b). The relative phase
between the clocks is not critical.
2)
3)
9-25
MT8910-1
Preliminary Information
BIT 0, CHANNEL 31
BIT 7, CHANNEL 0
tFPW
VIH
VIL
F0b
C4b
tP4i
tFPS
tFPH
tC4W
VIH
VIL
tC4W
tSFS
tSFH
VIH
VIL
SFb
tDFD
tDFD
VOH
VOL
F0od
tSIS
tSIH
tDFW
VIH
VIL
DSTi/
CDSTi
tDAZ
tDZA
tDAA
VOH
VOL
DSTo/
CDSTo
Figure 16 - ST-BUS Timing LT Mode
AC Electrical Characteristics† - ST-BUS Timing LT Mode (Ref. Figure 16)
‡
Characteristics
Sym Min Typ
Max Units
Test Conditions
1
2
3
4
5
6
7
8
9
F0b Input Pulse Width
Frame Pulse (F0b) Setup Time
Frame Pulse (F0b) Hold Time
C4b Input Clock Period
C4b Pulse Width High or Low
Superframe Setup Time
Superframe Hold Time
F0od Delay
t
244
ns
ns
ns
ns
ns
ns
ns
FPW
t
50
50
(see Note 2)
FPS
t
(see Note 2)
FPH
t
244
122
P4i
t
C4W
t
50
50
(see Note 2)
(see Note 2)
SFS
SFH
DFD
t
t
60
ns
ns
ns
ns
ns
150 pF Load (see Notes 1 & 2)
150 pF Load (see Note 1)
(see Notes 1 & 2)
F0od Pulse Width
t
244
DFW
10 Serial Input Setup Time
11 Serial Input Hold Time
12 Serial Output Delay
t
30
50
SIS
t
(see Notes 1 & 2)
SIH
Act to Act
High Z to Act
Act to High Z
t
t
t
120
120
120
150 pF Load (see Notes 1 & 2)
150 pF Load (see Notes 1 & 2)
150 pF Load (see Notes 1 & 2)
DAA
DZA
DAZ
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Note
1) These timing parameters are mode independent (NT or LT).
2) Tested @ 5V, 25°C only.
9-26
Preliminary Information
MT8910-1
BIT 7, CHANNEL 0
BIT 0, CHANNEL 31
tFPW
VOH
VOL
F0b
tCFD
tP4o
tCFD
tC4H
VOH
VOL
C4b
SFb
tSFD
tC4T
tC4L
VOH
VOL
tDFD
tDFD
tSFW
VOH
VOL
F0od
tSIS
tSIH
tDFW
VIH
VIL
DSTi/
CDSTi
tDAA
tDAZ
tDZA
VOH
VOL
DSTo/
CDSTo
Figure 17 - ST-BUS Timing NT Mode
AC Electrical Characteristics† - ST-BUS Timing NT Mode (Ref. Figure 17)
‡
Characteristics
Sym Min Typ
Max Units
Test Conditions
1
2
3
4
5
6
7
8
9
F0b Output Pulse Width
F0b Output Delay
t
1
cycles C =150 pF, C4b cycles
FPW
L
t
60
ns
ns
ns
ns
ns
ns
150 pF (see Note 3)
150 pF
CFD
C4b Output Clock Period
C4b Pulse Width High
C4b Pulse Width Low
C4b Transition Time
SFb Output Delay
t
244
88
P4o
t
150 pF
C4H
t
137
15
150 pF (see Note 1)
150 pF
C4L
C4T
SFD
t
t
60
60
C =150 pF (see Note 3)
L
SFb Output Pulse Width
F0od Delay
t
1
1
cycles C =150 pF, C4b cycles
L
SFW
t
ns
C =150 pF (see Notes 2 & 3)
L
DFD
10 F0od Pulse Width
t
cycles C =150 pF, C4b cycles (see
DFW
L
Note 2)
11 Serial Input Setup Time
12 Serial Input Hold Time
13 Serial Output Delay
t
30
50
ns
ns
C =150 pF (see Note 2)
L
SIS
t
C =150 pF (see Note 2)
SIH
L
Act to Act
t
t
t
120
120
120
ns
ns
ns
150 pF load (see Notes 2 & 3)
150 pF load (see Notes 2 & 3)
150 pF load (see Notes 2 & 3)
DAA
DZA
DAZ
High Z to Act
Act to High Z
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Notes
1)
2)
3)
The C4b pulse width low will vary by ±48ns during a phase-correction cycle.
These timing parameters are mode independent (NT or LT).
Tested at 5.0V, 25°C only.
9-27
MT8910-1
Preliminary Information
NOTES:
9-28
相关型号：
MT8920BE1
Telecom Circuit, 1-Func, CMOS, PDIP28, 0.600 INCH, LEAD FREE, PLASTIC, MS-011AB, DIP-28
ZARLINK
©2020 ICPDF网 联系我们和版权申明