MT88L85 [MITEL]
3V Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface; 3V集成DTMFTransceiver与关机及自适应微型接口
| 型号： | MT88L85 |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | 3V Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface |
| 文件： | 总20页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT88L85
3V Integrated DTMF Transceiver
with Power Down & Adaptive
Advance Information
Micro Interface
ISSUE 1
May 1995
Features
•
•
•
External power down pin
Ordering Information
MT88L85AE 24 Pin Plastic DIP
Low voltage operation (2.7V - 3.6V)
Central office quality DTMF transmitter/
receiver
MT88L85AN
MT88L85AP
24 Pin SSOP
28 Pin PLCC
•
•
•
•
•
•
Low power consumption
-40°C to +85°C
High speed adaptive micro interface
Adjustable guard time
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
Automatic tone burst mode
Call progress tone detection to -30dBm
transmitter utilizes
a
switched capacitor D/A
DTMF transmitter/receiver power down via
register control
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
Applications
•
•
•
•
•
Credit card systems
Paging systems
The MT88L85 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT88L85 provides enhanced power down
Repeater systems/mobile radio
Interconnect dialers
Personal computers
features.
The transmitter and receiver may
independently be powered down via register
control. A full chip power down pin provides simple
power and control capability.
Description
The MT88L85 is a monolithic DTMF transceiver with
call progress filter.
It is fabricated in CMOS
technology offering low power consumption and high
reliability.
D0
Data
Row and
D/A
Transmit Data
Bus
D1
D2
D3
∑
Column
TONE
Converters
Register
Buffer
Counters
Status
Register
Interrupt
Logic
Tone Burst
Gating Cct.
Control
Logic
IRQ/CP
Control
Register
A
IN+
IN-
GS
+
-
Dial
Tone
Filter
High Group
Filter
Digital
DS/RD
CS
Algorithm
and Code
Converter
Control
Register
B
I/O
Low Group
Filter
Control
OSC1
OSC2
Oscillator
Circuit
R/W/WR
RS0
Control
Logic
Receive Data
Register
Steering
Logic
Bias
Circuit
VDD VRef VSS
ESt
St/GT
PWDN
Figure 1 - Functional Block Diagram
4-71
MT88L85
Advance Information
24
23
22
21
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W/WR
CS
1
2
3
4
5
6
7
8
VDD
St/GT
ESt
D3
D2
D1
D0
NC
PWDN
IRQ/CP
DS/RD
RS0
•
5
25
NC
D3
NC
VRef
VSS
OSC1
OSC2
NC
6
24
23
22
21
20
19
7
D2
8
D1
D0
NC
PWDN
9
10
11
9
NC
10
11
12
24 PIN DIP/SSOP
28 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
24 28
1
2
3
1
2
4
IN+
IN-
Non-inverting op-amp input.
Inverting op-amp input.
GS
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
5
6
7
6
7
8
9
VRef
VSS
Reference Voltage output (VDD/2).
Ground (0V).
OSC1 Oscillator input. This pin can also be driven directly by an external clock.
OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
10 12
TONE Output from internal DTMF transmitter.
11 13 R/W(WR) (Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible.
12 14
CS
Chip Select input. This signal must be qualified externally by either address strobe (AS),
valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
13 15
RS0
Register Select input. Refer to Table 3 for bit interpretation. CMOS compatible.
14 17 DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only
required when the device is being accessed. CMOS compatible.
15 18 IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
16 19 PWDN Power Down (input). Active High. Powers down the device and inhibits the oscillator. IRQ
and TONE output are high impedance. Data bus is held in tri-state. This pin is internally
pulled down.
14- 18- D0-D3 Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
17 21
(Intel). TTL compatible.
18 22
ESt
Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
19 23
20 24
St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
VDD
Positive power supply (3V typ.).
4-72
Advance Information
MT88L85
Pin Description
Pin #
Name
Description
24 28
3,5,
10,11
16,
8,9
17
NC
No Connection.
20,
25
Receiver Section
Functional Description
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Table 1). The filters
also incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.
The MT88L85 Integrated DTMF Transceiver consists
of a high performance DTMF receiver with an
internal gain setting amplifier and a DTMF generator,
which employs a burst counter to synthesize precise
tone bursts and pauses. A call progress mode can
be selected so that frequencies within the specified
passband can be detected. The adaptive micro
interface allows microcontrollers, such as the
68HC11, 80C51 and TMS370C50, to access the
MT88L85 internal registers.
Power Down
The MT88L85 provides enhanced power down
functionality to facilitate minimization of supply
current consumption. DTMF transmitter and receiver
circuit blocks may be independently powered down
via register control. When asserted, the RxEN
control bit powers down all analog and digital
circuitry associated solely with the DTMF and Call
Progress receiver. The TOUT control bit is used to
disable the transmitter and put all circuitry
associated only with the DTMF transmitter in power
down mode. With the TOUT control bit asserted, the
TONE output pin is held in a high impedance
(floating) state. When both power down control bits
are asserted, circuits utilized by both the DTMF
transmitter and receiver are also powered down.
This includes the crystal oscillators, and the VRef
generator. In addition, the IRQ , TONE output and
DATA pins are held in a high impedance state.
Finally, the whole device is put in a power down state
when the PWDN pin is asserted.
MT88L85
IN+
IN-
RIN
C
GS
RF
VOLTAGE GAIN
(AV) = RF / RIN
V
Ref
Figure 3 - Single-Ended Input Configuration
MT88L85
IN+
C1
C2
R1
R4
IN-
R5
R2
GS
Input Configuration
R3
V
Ref
The input arrangement of the MT88L85 provides a
differential-input operational amplifier as well as a
bias source (VRef), which is used to bias the inputs at
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
V
DD/2. Provision is made for connection of a
feedback resistor to the op-amp output (GS) for gain
adjustment. In a single-ended configuration, the
input pins are connected as shown in Figure 3.
VOLTAGE GAIN
(AV diff) - R5/R1
INPUT IMPEDANCE
(ZINdiff) = 2 R12 + (1/ωC)2
Figure 4 shows the necessary connections for a
differential input configuration.
Figure 4 - Differential Input Configuration
4-73
MT88L85
Advance Information
(V ) of the steering logic to register the tone pair,
TSt
latching its corresponding 4-bit code (see Table 1)
into the Receive Data Register. At this point the GT
FLOW
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
FHIGH
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
DIGIT
1
D3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
D1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
output is activated and drives v to VDD. GT
c
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.
2
3
4
5
6
7
8
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
9
0
*
#
A
B
C
D
0= LOGIC LOW, 1= LOGIC HIGH
Table 1. Functional Encode/Decode Table
VDD
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
MT88L85
C1
VDD
Vc
St/GT
ESt
R1
tGTA = (R1C1) In (VDD / VTSt
)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the following inequalities
(see Figure 7):
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
t
REC ≥ tDPmax + tGTPmax - tDAmin
REC ≤ tDPmin + tGTPmin - tDAmax
t
t
t
ID ≥ tDAmax + tGTAmax - tDPmin
DO ≤ tDAmin + tGTAmin - tDPmax
ESt. A logic high on ESt causes v (see Figure 5) to
c
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
The value of tDP is a device parameter (see AC
Electrical Characteristics) and tREC is the minimum
the validation period (tGTP), v reaches the threshold
c
4-74
Advance Information
MT88L85
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independent tone present (tGTP) and
tone absent (tGTA) guard times. This may be
necessary to meet system specifications which place
both accept and reject limits on tone duration and
interdigital pause. Guard time adjustment also allows
the designer to tailor system parameters such as talk
off and noise immunity.
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
t
GTA = (R1C1) In (VDD/VTSt
)
RP = (R1R2) / (R1 + R2)
VDD
C1
R2
St/GT
Increasing tREC improves talk-off performance since
it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short tREC with a long tDO would be appropriate for
extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.
R1
ESt
a) decreasing tGTP; (tGTP < tGTA)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
t
GTA = (RpC1) In (VDD/VTSt
)
VDD
RP = (R1R2) / (R1 + R2)
C1
St/GT
Call Progress Filter
A call progress mode, using the MT88L85, can be
selected allowing the detection of various tones,
which identify the progress of a telephone call on the
network. The call progress tone input and DTMF
input are common, however, call progress tones can
only be detected when CP mode has been selected.
R1
R2
b) decreasing tGTA; (tGTP > tGTA)
ESt
Figure 6 - Guard Time Adjustment
EVENTS
A
B
C
D
E
F
tREC
tID
tDO
tREC
TONE
#n + 1
TONE
#n + 1
TONE #n
Vin
tDA
tDP
ESt
tGTP
tGTA
VTSt
St/GT
tPStRX
RX0-RX3
b3
DECODED TONE # (n-1)
# (n + 1)
# n
tPStb3
b2
Read
Status
Register
IRQ/CP
Figure 7 - Receiver Timing Diagram
4-75
MT88L85
Advance Information
EXPLANATION OF EVENTS
A)
B)
C)
TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.
TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
D)
E)
F)
TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.
END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLS
Vin
DTMF COMPOSITE INPUT SIGNAL.
ESt
St/GT
EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
RX0-RX3 4-BIT DECODED DATA IN RECEIVE DATA REGISTER
b3
DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A
VALID DTMF SIGNAL.
b2
INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS
REGISTER IS READ.
IRQ/CP
INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS
CLEARED AFTER THE STATUS REGISTER IS READ.
tREC
tREC
tID
tDO
tDP
MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.
MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.
MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.
TIME TO DETECT VALID FREQUENCIES PRESENT.
tDA
TIME TO DETECT VALID FREQUENCIES ABSENT.
tGTP
tGTA
GUARD TIME, TONE PRESENT.
GUARD TIME, TONE ABSENT.
Figure 9 - Description of Timing Events
DTMF signals cannot be detected if CP mode has
been selected (see Table 7). Figure 8 indicates the
useful detect bandwidth of the call progress filter.
Frequencies presented to the input, which are within
the ‘accept’ bandwidth limits of the filter, are hard-
limited by a high gain comparator with the IRQ/CP
pin serving as the output. The squarewave output
obtained from the schmitt trigger can be analyzed by
the transmit Data Register.
Note that this is the
same as the receiver output code. The individual
tones which are generated (fLOW and fHIGH) are
referred to as Low Group and High Group tones. As
seen from the table, the low group frequencies are
697, 770, 852 and 941 Hz. The high group
frequencies are 1209, 1336, 1477 and 1633 Hz.
Typically, the high group to low group amplitude ratio
(twist) is 2 dB to com-pensate for high group
attenuation on long loops.
a
microprocessor or counter arrangement to
determine the nature of the call progress tone being
detected. Frequencies which are in the ‘reject’ area
will not be detected and consequently the IRQ/CP
pin will remain low.
LEVEL
(dBm)
DTMF Generator
The DTMF transmitter employed in the MT88L85 is
capable of generating all sixteen standard DTMF
tone pairs with low distortion and high accuracy. All
frequencies are derived from an external 3.579545
MHz crystal. The sinusoidal waveforms for the
individual tones are digitally synthesized using row
and column programmable dividers and switched
capacitor D/A converters. The row and column tones
are mixed and filtered providing a DTMF signal with
low total harmonic distortion and high accuracy. To
specify a DTMF signal, data conforming to the
encoding format shown in Table 1 must be written to
-25
0
250
500
750
FREQUENCY (Hz)
= Reject
= May Accept
= Accept
Figure 8 - Call Progress Response
4-76
Advance Information
MT88L85
Scaling Information
10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz
Figure 10 - Spectrum Plot
The period of each tone consists of 32 equal time
segments. The period of a tone is controlled by
varying the length of these time segments. During
write operations to the Transmit Data Register the 4
bit data on the bus is latched and converted to 2 of 8
coding for use by the programmable divider circuitry.
This code is used to specify a time segment length,
which will ultimately determine the frequency of the
tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse
is issued and the counter starts again. The number
of time segments is fixed at 32, however, by varying
the segment length as described above the
frequency can also be varied. The divider output
clocks another counter, which addresses the
sinewave lookup ROM.
application or by any one of the exchange transmitter
specifications currently existing. Standard DTMF
signal timing can be accomplished by making use of
the Burst Mode. The transmitter is capable of issuing
symmetric bursts/pauses of predetermined duration.
This burst/pause duration is 51 ms±1 ms which is a
standard interval for autodialer and central office
applications. After the burst/pause has been issued,
the appropriate bit is set in the Status Register
indicating that the transmitter is ready for more data.
The timing described above is available when DTMF
mode has been selected. However, when CP mode
(Call Progress mode) is selected, the burst/pause
duration is doubled to 102 ms ±2 ms. Note that when
CP mode and Burst mode have been selected,
DTMF tones may be transmitted only and not
received. In applications where a non-standard
burst/pause time is desirable, a software timing loop
or external timer can be used to provide the timing
pulses when the burst mode is disabled by enabling
and disabling the transmitter.
The lookup table contains codes which are used by
the switched capacitor D/A converter to obtain
discrete and highly accurate DC voltage levels. Two
identical circuits are employed to produce row and
column tones, which are then mixed using a low
noise summing amplifier. The oscillator described
needs no “start-up” time as in other DTMF
generators since the crystal oscillator is running
continuously thus providing a high degree of tone
Single Tone Generation
A single tone mode is available whereby individual
tones from the low group or high group can be
generated. This mode can be used for DTMF test
equipment applications, acknowledgment tone
generation and distortion measurements. Refer to
Control Register B description for details.
burst accuracy.
A
bandwidth limiting filter is
incorporated and serves to attenuate distortion
products above 8 kHz. It can be seen from Figure 6
that the distortion products are very low in amplitude.
Burst Mode
In certain telephony applications it is required that
DTMF signals being generated are of a specific
duration determined either by the particular
4-77
MT88L85
Advance Information
DTMF Clock Circuit
OUTPUT FREQUENCY (Hz)
ACTIVE
INPUT
%ERROR
SPECIFIED
697
ACTUAL
699.1
The internal clock circuit is completed with the
addition of a standard television colour burst crystal
having a resonant frequency of 3.579545 MHz. A
number of MT88L85 devices can be connected as
shown in Figure 11 such that only one crystal is
required. Alternatively, the OSC1 inputs on all
devices can be driven from a TTL buffer with the
OSC2 outputs left unconnected.
L1
L2
L3
L4
H1
H2
H3
H4
+0.30
-0.49
-0.54
+0.74
+0.57
-0.32
-0.35
+0.73
770
766.2
852
847.4
941
948.0
1209
1336
1477
1633
1215.9
1331.7
1471.9
1645.0
MT88L85
MT88L85
MT88L85
OSC1 OSC2
OSC1 OSC2
OSC1 OSC2
Table 2. Actual Frequencies Versus Standard
Requirements
Distortion Calculations
3.579545 MHz
The MT88L85 is capable of producing precise tone
bursts with minimal error in frequency (see Table 2).
The internal summing amplifier is followed by a first-
order lowpass switched capacitor filter to minimize
harmonic components and intermodulation products.
The total harmonic distortion for a single tone can be
calculated using Equation 1, which is the ratio of the
total power of all the extraneous frequencies to the
power of the fundamental frequency expressed as a
percentage.
Figure 11 - Common Crystal Connection
Microprocessor Interface
The MT88L85 design incorporates an adaptive
interface, which allows it to be connected to various
kinds of microprocessors. Key functions of this
interface include the following:
•
•
Continuous activity on DS/RD is not necessary
to update the internal status registers.
2
2
2
2
V
2f + V 3f + V 4f + .... V
nf
THD (%) = 100
senses whether input timing is that of an Intel or
Motorola controller by monitoring the DS (RD),
R/W (WR) and CS inputs.
Vfundamental
Equation 1. THD (%) For a Single Tone
•
•
generates equivalent CS signal for internal
operation for all processors.
The Fourier components of the tone output
correspond to V .... V as measured on the output
2f
nf
waveform. The total harmonic distortion for a dual
tone can be calculated using Equation 2. V and V
L
H
differentiates between multiplexed and non-
multiplexed microprocessor buses. Address
and data are latched in accordingly.
correspond to the low group amplitude and high
2
group amplitude, respectively and V
is the sum
IMD
of all the intermodulation components. The internal
switched-capacitor filter following the D/A converter
keeps distortion products down to a very low level as
shown in Figure 10.
•
compatible with Motorola and Intel processors.
Figure 16 shows the timing diagram for Motorola
microprocessors with separate address and data
buses. Members of this microprocessor family
include 2 MHz versions of the MC6800, MC6802 and
MC6809. For the MC6809, the chip select (CS) input
signal is formed by NANDing the (E+Q) clocks and
address decode output. For the MC6800 and
MC6802, CS is formed by NANDing VMA and
address decode output. On the falling edge of CS,
the internal logic senses the state of data strobe
V22L + V23L + .... V2nL + V2
+
2H
V23H + .. V2nH + V2
IMD
THD (%) = 100
V2L + V2
H
Equation 2. THD (%) For a Dual Tone
4-78
Advance Information
MT88L85
(DS). When DS is low, Motorola processor operation
is selected.
The adaptive micro interface provides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last
valid DTMF digit received. Data entered into the
write-only Transmit Data Register will determine
which tone pair is to be generated (see Table 1 for
coding details). Transceiver control is accomplished
with two control registers (see Tables 6 and 7), CRA
and CRB, which have the same address. A write
operation to CRB is executed by first setting the
most significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the current transceiver state (see Table 8).
Figure 17 shows the timing diagram for the Motorola
MC68HC11 (1 MHz) microcontroller. The chip select
(CS) input is formed by NANDing address strobe
(AS) and address decode output. Again, the
MT88L85 examines the state of DS on the falling
edge of CS to determine if the micro has a Motorola
bus (when DS is low). Additionally, the Texas
Instruments TMS370CX5X is qualified to have a
Motorola interface. Figure 12(a) summarizes
connection of these Motorola processors to the
MT88L85 DTMF transceiver.
Figures 18 and 19 are the timing diagrams for the
Intel 8031/8051 (12 MHz) and 8085 (5 MHz) micro-
controllers with multiplexed address and data buses.
The MT88L85 latches in the state of RD on the
falling edge of CS. When RD is high, Intel processor
A software reset must be included at the beginning
of all programs to initialize the control registers upon
power-up or power reset (see Figure 14). Refer to
Tables 4-7 for bit descriptions of the two control
registers.
operation is selected.
By NANDing the address
latch enable (ALE) output with the high-byte address
(P2) decode output, CS can be generated. Figure
12(b) summarizes the connection of these Intel
processors to the MT88L85 transceiver.
The multiplexed IRQ/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a square-wave output of the
call progress signal. The IRQ/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13).
NOTE: The adaptive micro interface relies on high-
to-low transition on CS to recognize the
microcontroller interface and this pin must not be tied
permanently low.
MT88L85
MT88L85
MC6800/6802
MC68HC11
CS
A0-A15
A8-A15
CS
RS0
D0-D3
AS
VMA
D0-D3
AD0-AD3
DS
RS0
D0-D3
DS/RD
R/W/WR
DS/RD
RW
Φ2
R/W/WR
RW
(a)
8031/8051
8080/8085
MT88L85
MC6809
MT88L85
A0-A15
CS
A8-A15
ALE
CS
RS0
Q
E
D0-D3
RS0
D0-D3
D0-D3
R/W
P0
RD
WR
R/W/WR
DS/RD
DS/RD
R/W/WR
(b)
Figure 12 a) & b) - MT88L85 Interface Connections for Various Intel and Motorola Micros
4-79
MT88L85
Advance Information
Motorola
Intel
WR
RS0
R/W
RD
FUNCTION
Write to Transmit
Data Register
0
0
0
1
1
Read from Receive
Data Register
0
1
0
Write to Control Register
Read from Status Register
1
1
0
1
0
1
1
0
Table 3. Internal Register Functions
b3
b2
b1
b0
RSEL
IRQ
CP/DTMF
TOUT
Table 4. CRA Bit Positions
b3
b2
b1
b0
C/R
S/D
TEST
BURST
ENABLE
Table 5. CRB Bit Positions
BIT
NAME
DESCRIPTION
b0
TOUT
Tone Output Control. A logic high enables the tone output; a logic low turns the tone output
off and places the complete DTMF transmitter circuit in power down mode. This bit
controls all transmit tone functions.
b1
CP/DTMF Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;
a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and
transmitting DTMF signals. In CP mode a retangular wave representation of the received
tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control
register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected.
b2
b3
IRQ
Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the
interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).
RSEL
Register Select. A logic high selects control register B for the next write cycle to the
control register address. After writing to control register B, the following control register
write cycle will be directed to control register A.
Table 6. Control Register A Description
4-80
Advance Information
MT88L85
BIT
NAME
DESCRIPTION
b0
BURST
Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 -
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).
b1
b2
RxEN
S/D
This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both
circuits. A logic high deactivates and puts both receiver circuits into power down mode.
Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (control
register B, b3).
b3
C/R
Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (control register B,
b2).
Table 7. Control Register B Description
BIT
NAME
STATUS FLAG SET
STATUS FLAG CLEARED
b0
IRQ
Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
Interrupt is inactive. Cleared after
Status Register is read.
b1
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2
b3
RECEIVE DATA REGISTER
FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is
read.
DELAYED STEERING
Set upon the valid detection of
the absence of a DTMF signal.
Cleared upon the detection of a
valid DTMF signal.
Table 8. Status Register Description
4-81
MT88L85
Advance Information
VDD
C3
MT88L85
VDD
St/GT
ESt
D3
IN+
IN-
GS
C1
R1
C2
DTMF/CP
INPUT
R4
R3
R2
VRef
VSS
D2
X-tal
D1
OSC1
D0
OSC2
NC
To µP
or µC
NC
PWDN
NC
DTMF
OUTPUT
IRQ/CP
DS/RD
RS0
TONE
R/W/WR
CS
RL
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 Ω 1%
R4 = 3.3 kΩ 10%
RL = 10 k Ω (min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
* Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT88L85 can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
C3 = 100 nF 10%*
X-tal = 3.579545 MHz
Figure 13 - Application Circuit (Single-Ended Input)
4-82
Advance Information
MT88L85
INITIALIZATION PROCEDURE
A software reset must be included at the beginning of all programs to initialize the control registers after
power up.
Description:
Motorola
Intel
WR RD
Data
b2
X
0
0
0
0
X
RS0
R/W
b3
X
0
0
1
b1
X
0
b0
X
0
1) Read Status Register
2) Write to Control Register
3) Write to Control Register
4) Write to Control Register
5) Write to Control Register
6) Read Status Register
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
X
0
0
X
X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS
Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.
Sequence:
RS0
R/W
WR RD
b3
b2
b1
b0
1) Write to Control Register A
1
0
0
0
0
1
1
1
1
1
0
1
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B
(burst mode)
3) Write to Transmit Data Register
(send a digit 7)
1
0
0
0
0
0
0
1
0
1
0
1
4) Wait for an Interrupt or Poll Status Register
5) Read the Status Register
1
1
1
0
1
X
0
X
1
X
0
X
1
-if bit 1 is set, the Tx is ready for the next tone, in which case ...
Write to Transmit Register
(send a digit 5)
0
0
0
-if bit 2 is set, a DTMF tone has been received, in which case ....
Read the Receive Data Register
0
1
1
0
X
X
X
X
-if both bits are set ...
Read the Receive Data Register
Write to Transmit Data Register
0
0
1
0
1
0
0
1
X
0
X
1
X
0
X
1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( ±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)
Figure 14 - Application Notes
4-83
MT88L85
Advance Information
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
1
2
3
4
5
Power supply voltage VDD-VSS
Voltage on any pin
VDD
VI
6
VDD+0.3
10
V
V
VSS-0.3
-65
Current at any pin (Except VDD
Storage Temperature
V
)
mA
°C
and SS
TST
PD
+150
1000
Package power dissipation
mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (V ) unless otherwise stated.
SS
‡
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
Positive power supply
Operating temperature
Crystal clock frequency
VDD
TO
2.7
-40
3
3.6
V
+85
°C
fCLK
3.575965 3.579545 3.583124
MHz
‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics† - V =0 V.
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
Operating supply voltage
Operating supply current
Standby supply current
VDD
IDD
2.7
3
3
3.6
V
S
U
P
mA
Device fully enabled
PWDN= VDD
VDD=3V
25
µA
High level input voltage
(OSC1)
VIHO
VILO
2.1
V
V
V
V
V
I
N
P
U
T
S
5
Low level input voltage
(OSC1)
1.9
VDD=3V
VDD=3V
6
7
Steering threshold voltage
VTSt
1.4
Low level output voltage
(OSC2)
No load
VDD=0V
VOLO
VOHO
0.1
10
O
U
T
P
U
T
8
9
High level output voltage
(OSC2)
No load
VDD=3V
2.97
Output leakage current
(IRQ)
IOZ
VRef
ROR
VIL
1
µA
V
VOH=2.4 V
S
10
11
12
13
14
V
Ref output voltage
1.5
1.3
.9
No load, VDD=3V
VRef output resistance
Low level input voltage
High level input voltage
Input leakage current
kΩ
V
D
i
g
i
VIH
IIZ
2.1
V
10
µA
VIN=VSS to VDD
t
a
l
15
16
17
18
Source current
Sink current
IOH
IOL
IOH
IOL
-6.6
4.0
-3.0
4
mA
mA
mA
mA
VOH=2.4V
VOL=0.4V
VOH=2.4V
VOL=0.4V
Data
Bus
ESt
and
St/GT
Source current
Sink current
IRQ/
CP
19
Sink current
IOL
16
mA
VOL=0.4V
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25 °C, VDD =3V and for design aid only: not guaranteed and not subject to production testing.
* See “Notes” following AC Electrical Characteristics Tables.
4-84
Advance Information
MT88L85
Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (V ) unless otherwise stated, V = 0V, V =3V, T =25°C.
SS
SS
DD
O
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
1
2
3
4
5
6
7
8
9
Input leakage current
Input resistance
IIN
RIN
±100
10
nA
MΩ
mV
dB
V
SS ≤ VIN ≤ VDD
Input offset voltage
VOS
PSRR
CMRR
AVOL
BW
25
Power supply rejection
Common mode rejection
DC open loop voltage gain
Unity gain bandwidth
Output voltage swing
Allowable capacitive load (GS)
60
1 kHz
60
dB
0.75 ≤ VIN ≤ 4.25V
RL ≥ 100 kΩ to VSS
No Load
65
dB
1.5
4.5
100
50
MHz
Vpp
pF
VO
CL
10 Allowable resistive load (GS)
RL
kΩ
11 Common mode range
VCM
3.0
Vpp
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
MT88L85 AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Notes*
Valid input signal levels
(each tone of composite
signal)
-34
-4
dBm
1,2,3,5,6
min @ VDD=3.6V
max @ VDD=2.7V
R
X
1
15.4
489
mVRMS
1,2,3,5,6
† Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13.
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. f =3.579545 MHz.
SS
C
‡
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
2
3
4
5
6
7
Positive twist accept
Negative twist accept
Freq. deviation accept
Freq. deviation reject
Third tone tolerance
Noise tolerance
8
8
dB
dB
2,3,6,9
2,3,6,9
2,3,5
±1.5%± 2Hz
±3.5%
R
X
2,3,5
-16
-12
22
dB
dB
dB
2,3,4,5,9,10
2,3,4,5,7,9,10
2,3,4,5,8,9
Dial tone tolerance
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, V = 3V, and for design aid only: not guaranteed and not subject to production testing.
DD
* *See “Notes” following AC Electrical Characteristics Tables.
4-85
MT88L85
Advance Information
AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated.
‡
Characteristics
Accept Bandwidth
Sym
Min
Typ
Max
Units
Conditions
1
fA
310
500
Hz
@ -25 dBm,
Note 9
2
3
4
Lower freq. (REJECT)
Upper freq. (REJECT)
fLR
290
540
Hz
Hz
@ -25 dBm
@ -25 dBm
fHR
Call progress tone detect level (total
power)
-30
dBm
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V =3V, and for design aid only: not guaranteed and not subject to production testing
DD
AC Electrical Characteristics†- DTMF Reception - Typical DTMF tone accept and reject requirements. Actual
values are user selectable as per Figures 5, 6 and 7.
‡
Characteristics
Sym
Min
Typ
Max
Units
Conditions
1
2
3
4
Minimum tone accept duration
Maximum tone reject duration
Minimum interdigit pause duration
Maximum tone drop-out duration
tREC
tREC
tID
40
20
40
20
ms
ms
ms
ms
tOD
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V =3V, and for design aid only: not guaranteed and not subject to production testing
DD
AC Electrical Characteristics† - Voltages are with respect to ground (V ), unless otherwise stated.
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Conditions
T
O
N
E
1
2
3
4
Tone present detect time
Tone absent detect time
Delay St to b3
tDP
tDA
tPStb3
tPStRX
5
11
4
14
ms Note 11
ms Note 11
0.5
8.5
13
8
µs
µs
See Figure 7
See Figure 7
I
N
Delay St to RX -RX
0
3
5
Tone burst duration
tBST
tPS
tBSTE
tPSE
VHOUT
VLOUT
dB
50
50
52
52
ms DTMF mode
ms DTMF mode
ms Call Progress mode
ms Call Progress mode
dBm RL=10kΩ
6
Tone pause duration
7
Tone burst duration (extended)
Tone pause duration (extended)
High group output level
Low group output level
Pre-emphasis
100
100
-15.1
-17.1
104
104
-11.1
-13.1
T
O
N
E
8
9
10
11
12
13
14
15
16
17
18
19
dBm RL=10kΩ
O
U
T
2
dB
dB
RL=10kΩ
P
Output distortion (Single Tone)
THD
-35
25 kHz Bandwidth
RL=10kΩ
Frequency deviation
fD
RLT
±0.7
±1.5
50
%
fC=3.579545 MHz
Output load resistance
Crystal/clock frequency
Clock input rise and fall time
Clock input duty cycle
Capacitive load (OSC2)
10
kΩ
fC
3.5759 3.5795 3.5831 MHz
X
T
A
L
tCLRF
DCCL
CLO
110
60
ns
%
Ext. clock
Ext. clock
40
50
30
pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
4-86
Advance Information
MT88L85
AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (V ), unless otherwise stated.
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Conditions
Figure 15
1
2
3
4
5
6
7
8
9
DS/RD/WR clock frequency
DS/RD/WR cycle period
DS/RD/WR low pulse width
DS/RD/WR high pulse width
DS/RD/WR rise and fall time
R/W setup time
fCYC
tCYC
tCL
4.0
250
150
100
20
0
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 15
Figure 15
tCH
Figure 15
tR,tF
tRWS
tRWH
tAS
Figure 15
Figures 16 & 17
Figures 16 & 17
Figures 16 - 19
Figures 16 - 19
Figures 16 - 19
Figures 16 - 19
Figures 16 - 19
Figures 16 - 19
Figures 16 - 19
Figures 16 - 19
R/W hold time
26
0
Address setup time (RS0)
Address hold time (RS0)
tAH
26
22
80
35
10
45
40
10 Data hold time (read)
11 DS/RD to valid data delay (read)
12 Data setup time (write)
13 Data hold time (write)
14 Chip select setup time
15 Chip select hold time
tDHR
tDDR
tDSW
tDHW
tCSS
tCSH
100
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V =3V, and for design aid only: not guaranteed and not subject to production testing
DD
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2) Digit sequence consists of all 16 DTMF tones.
3) Tone duration=40 ms. Tone pause=40 ms.
4) Nominal DTMF frequencies are used.
5) Both tones in the composite signal have an equal amplitude.
6) The tone pair is deviated by ± 1.5 %±2 Hz.
7) Bandwidth limited (3 kHz) Gaussian noise.
8) The precise dial tone frequencies are 350 and 440 Hz (±2 %).
9) Guaranteed by design and characterization. Not subject to production testing.
10) Referenced to the lowest amplitude tone in the DTMF signal.
11) For guard time calculation purposes.
tCYC
tR
tF
tCH
tCL
DS/RD/WR
Figure 15 - DS/RD/WR Clock Pulse
4-87
MT88L85
Advance Information
tRWH
tRWS
DS
Q clk*
A0-A15
(RS0)
16 bytes of Addr
R/W(read)
tDDR
tDHR
Read Data
(D3-D0)
R/W (write)
➀
tDSW
tDHW
Write data
(D3-D0)
➀
tCSS
tCSH
tAH
tAS
tAS
CS = (E + Q).Addr [MC6809]
tAH
CS = VMA.Addr [MC6800, MC6802]
*microprocessor pin
➀
tCSS
tCSH
Figure 16 - MC6800/MC6802/MC6809 Timing Diagram
➀ tDSW is from data to DS falling edge; tCSH is from DS rising edge to CS rising edge
tRWS
DS
tRWH
R/W
tDHR
tDDR
tAS
Read
Addr
Addr
Data
AD3-AD0
(RS0, D0-D3)
Write
AD3-AD0
(RS0-D0-D3)
Data
tDHW
tDSW
tAH
tCSH
Addr *
non-mux
High Byte of Addr
AS *
CS = AS.Addr
tCSS
* microprocessor pins
Figure 17 - MC68HC11 Bus Timing (with multiplexed address and data buses)
4-88
Advance Information
MT88L85
tCSS
ALE*
RD
tDHR
tAS
tDDR
tAH
A0-A7
P0*
(RS0,
D0-D3)
Data
P2 *
(Addr)
A8-A15 Address
tCSH
CS = ALE.Addr
* microprocessor pins
Figure 18 - 8031/8051/8085 Read Timing Diagram
ALE*
WR
tCSS
tDSW
tAS
tAH
A0-A7
tDHW
P0*
(RS0,
D0-D3)
Data
P2 *
(Addr)
A8-A15 Address
tCSH
CS = ALE.Addr
* microprocessor pins
Figure 19 - 8031/8051/8085 Write Timing Diagram
4-89
MT88L85
Advance Information
NOTES:
4-90
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