MT88L70AN [MITEL]
3 Volt Integrated DTMF Receiver; 3伏集成DTMF接收器
| 型号： | MT88L70AN |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | 3 Volt Integrated DTMF Receiver |
| 文件： | 总10页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO2-CMOS
MT88L70
3 Volt Integrated DTMF Receiver
ISSUE 2
May 1995
Features
•
•
•
•
•
•
•
•
•
2.7 - 3.6 volt operation
Ordering Information
Complete DTMF receiver
Low power consumption
Internal gain setting amplifier
Adjustable guard time
MT88L70AC
18 Pin Ceramic DIP
MT88L70AE
MT88L70AS
MT88L70AN
MT88L70AT
18 Pin Plastic DIP
18 Pin SOIC
20 Pin SSOP
20 Pin TSSOP
Central office quality
-40 °C to + 85 °C
Power-down mode
Inhibit mode
Description
Functionally compatible with Mitel’s MT8870D
The MT88L70 is a complete 3 Volt, DTMF receiver
integrating both the bandsplit filter and digital
decoder functions. The filter section uses switched
capacitor techniques for high and low group
Applications
•
•
•
•
•
•
Paging systems
Repeater systems/mobile radio
Credit card systems
filters;
the
decoder
uses digital counting
techniques to detect and decode all 16 DTMF tone-
pairs into a 4-bit code. External component count is
minimized by on chip provision of a differential input
amplifier, clock oscillator and latched three-state bus
interface.
Remote control
Personal computers
Telephone answering machine
VDD
VSS
VRef
INH
Bias
Circuit
PWDN
VRef
Buffer
Q1
Chip Chip
Power Bias
High Group
Filter
Digital
Detection
Algorithm
Code
Converter
and Latch
Q2
Q3
Q4
IN +
Dial
Tone
Filter
Zero Crossing
Detectors
IN -
GS
Low Group
Filter
to all
St
GT
Steering
Logic
Chip
Clocks
OSC1
OSC2
St/GT
ESt
STD
TOE
Figure 1 - Functional Block Diagram
4-23
MT88L70
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
IN+
IN-
GS
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
IN+
IN-
GS
VDD
St/GT
ESt
StD
NC
Q4
Q3
Q2
Q1
VRef
INH
PWDN
OSC1
OSC2
VSS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
9
10
TOE
18 PIN CERDIP/PDIP/SOIC
20 PIN SSOP/TSSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
18 20
1
2
3
1
2
3
IN+
IN-
Non-Inverting Op-Amp (Input).
Inverting Op-Amp (Input).
GS
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
5
6
4
5
6
VRef
INH
Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Figure
5 and Figure 6).
Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C
and D. This pin input is internally pulled down.
PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
7
8
8
9
OSC1 Clock (Input).
OSC2 Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
9
10
VSS
Ground (Input). 0V typical.
10 11
TOE Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is
pulled up internally.
11- 12- Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the
14 15
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
15 17
StD
ESt
Delayed Steering (Output).Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below VTSt
.
16 18
Early Steering (Output). Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to
return to a logic low.
17 19 St/GT Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
18 20
VDD
NC
Positive power supply (Input). +3V typical.
7,
No Connection.
16
4-24
MT88L70
Functional Description
Digit
TOE
INH
ESt
Q4
Q3
Q2
Q1
ANY
1
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Z
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
Z
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Z
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
The MT88L70 monolithic DTMF receiver offers small
size, low power consumption and high performance,
with 3 volt operation. Its architecture consists of a
bandsplit filter section, which separates the high and
low group tones, followed by a digital counting
section which verifies the frequency and duration of
the received tones before passing the corresponding
code to the output bus.
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
3
4
5
6
7
8
Filter Section
9
0
Separation of the low-group and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies. The filter section also
incorporates notches at 350 and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.
*
#
A
B
C
D
A
B
C
D
L
L
L
H
H
H
H
undetected, the output code
will remain the same as the
previous detected code
L
L
L
Table 1. Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON‘T CARE
Decoder Section
validation period (tGTP), v reaches the threshold
c
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state (see “Steering Circuit”).
(VTSt) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the output latch. At this point the GT output is
activated and drives v to VDD. GT continues to drive
c
high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the
delayed steering output flag (StD) goes high,
signalling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three
state control input (TOE) to a logic high. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (dropout) too short to
be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
Guard Time Adjustment
In many situations not requiring selection of tone
duration and interdigital pause, the simple steering
circuit shown in Figure 3 is applicable. Component
values are chosen according to the formula:
ESt. A logic high on ESt causes v (see Figure 3) to
c
rise as the capacitor discharges. Provided signal
condition is maintained (ESt remains high) for the
4-25
MT88L70
tREC=tDP+tGTP
tID=tDA+tGTA
tGTP=(RPC1) In [VDD / (VDD-VTSt)]
GTA=(R1C1) In (VDD / VTSt
P = (R1R2) / (R1 + R2)
VDD
t
)
C1
R
St/GT
The value of tDP is a device parameter (see Figure 7)
and tREC is the minimum signal duration to be
recognized by the receiver. A value for C of 0.1 µF is
R1
R2
recommended for most applications, leaving R to be
selected by the designer.
ESt
a) decreasing tGTP; (tGTP < tGTA
)
tGTP=(R1C1) In [VDD / (VDD-VTSt)]
GTA=(RPC1) In (VDD / VTSt
P = (R1R2) / (R1 + R2)
VDD
VDD
t
)
C1
R
C
VDD
St/GT
vc
St/GT
ESt
R2
R1
R
ESt
b) decreasing tGTA; (tGTP > tGTA
)
StD
Figure 4 - Guard Time Adjustment
Differential Input Configuration
tGTA=(RC)In(VDD/VTSt
)
MT88L70
t
GTP=(RC)In[VDD/(VDD-VTSt)]
Figure 3 - Basic Steering Circuit
The input arrangement of the MT88L70 provides a
differential-input operational amplifier as well as a
bias source (VRef) which is used to bias the inputs at
mid-rail. Provision is made for connection of a
feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
Different steering arrangements may be used to
select independently the guard times for tone
present (tGTP) and tone absent (tGTA). This may be
necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters such
as talk off and noise immunity. Increasing tREC
improves talk-off performance since it reduces the
probability that tones simulated by speech will
maintain signal condition long enough to be
registered. Alternatively, a relatively short tREC with a
long tDO would be appropriate for extremely noisy
environments where fast acquisition time and
immunity to tone drop-outs are required. Design
information for guard time adjustment is shown in
Figure 4.
MT88L70
R1
IN+
IN-
C1
+
-
C2
R4
GS
R5
R3
R2
VRef
Power-down and Inhibit Mode
DIFFERNTIAL INPUT AMPLIFIER
A logic high applied to pin 6 (PWDN) will power down
the device to minimize the power consumption in a
standby mode. It stops the oscillator and the
functions of the filters.
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60 kΩ, R3, = 37.5 kΩ
All resistors are ± 1% tolerance.
All capacitors are ± 5% tolerance.
R2R5
R3 =
R2 + R5
R5
R1
VOLTAGE GAIN (AV diff) =
Inhibit mode is enabled by a logic high input to the
pin 5 (INH). It inhibits the detection of tones
representing characters A, B, C, and D. The output
code will remain the same as the previous detected
code (see Table 1).
INPUT IMPEDANCE
2
1
2
R1
+
(ZINDIFF) = 2
ωC
Figure 5 - Differential Input Configuration
4-26
MT88L70
VDD
C1
DTMF
Input
C2
R1
MT88L70
VDD
IN+
IN-
St/GT
ESt
StD
Q4
R3
GS
VRef
R2
INH
PDWN
OSC1
OSC2
VSS
Q3
NOTES:
R1, R2 = 100 kΩ ±1%
R3 = 300 kΩ ±1%
C1,C2 = 100 nF ±5%
Q2
X-tal
Q1
TOE
X-tal = 3.579545 MHz ±0.1%
VDD = 3.0V + 20% / -10%
Figure 6 - Single-Ended Input Configuration
the input pins are connected as shown in Figure 6
with the op-amp connected for unity gain and VRef
biasing the input at 1/2VDD. Figure 5 shows the
differential configuration, which permits the
Applications
A single-ended input configuration is shown in Figure
6. For applications with differential signal inputs the
circuit shown in Figure 5 may be used.
adjustment of gain with the feedback resistor R .
5
Crystal Oscillator
The internal clock circuit is completed with the
addition of an external 3.579545 MHz crystal and is
connected as shown in Figure 6 (Single-ended Input
Configuration).
4-27
MT88L70
Absolute Maximum Ratings†
Parameter
Symbol
Min
Max
Units
1
2
3
4
5
DC Power Supply Voltage
Voltage on any pin
VDD
VI
7
VDD+0.3
10
V
V
VSS-0.3
-65
Current at any pin (other than supply)
Storage temperature
II
mA
°C
TSTG
+150
Package power dissipation
PD
500
mW
† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Derate above 75 °C at 16 mW / °C. All leads soldered to board.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
DC Power Supply Voltage
Operating Temperature
VDD
TO
fc
2.7
-40
3.0
3.6
V
°C
+85
3.579545
Crystal/Clock Frequency
MHz
%
Crystal/Clock Freq.Tolerance
∆fc
±0.1
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - VDD=3.0V+ 20%/-10%, VSS=0V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
PWDN=VDD
S
U
P
P
L
1
2
3
Standby supply current
Operating supply current
Power consumption
IDDQ
IDD
1
2.0
6
10
µA
5.5
mA
PO
mW fc=3.579545 MHz
Y
4
5
6
7
High level input
VIH
VIL
2.1
V
V
VDD=3.0V
Low level input voltage
Input leakage current
Pull up (source) current
0.9
5
VDD=3.0V
IIH/IIL
ISO
0.05
4
µA
µA
VIN=VSS or VDD
I
N
P
U
T
S
15
TOE (pin 10)=0,
V
DD=3.0V
DD=3.0V
8
Pull down (sink) current
ISI
15
40
µA
INH=VDD, PWDN=VDD
V
,
9
Input impedance (IN+, IN-)
Steering threshold voltage
Low level output voltage
High level output voltage
Output low (sink) current
Output high (source) current
RIN
VTSt
VOL
VOH
IOL
10
MΩ
V
@ 1 kHz
0.465VDD
10
11
12
13
14
15
16
VSS+0.03
V
No load
O
U
T
P
U
T
VDD-0.03
1.5
V
No load
8
mA
mA
V
VOUT=0.4 V
VOUT=3.6 V, VDD=3.6V
No load
IOH
1.0
3.0
0.512VDD
V
V
Ref output voltage
VRef
ROR
S
Ref output resistance
1
kΩ
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
4-28
MT88L70
Operating Characteristics - VDD=3.0V+20%/-10%, VSS=0V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.
Gain Setting Amplifier
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
VSS ≤ VIN ≤ VDD
1
2
3
4
5
Input leakage current
Input resistance
IIN
RIN
100
nA
MΩ
mV
dB
10
Input offset voltage
Power supply rejection
Common mode rejection
VOS
25
PSRR
CMRR
50
40
1 kHz
dB
V
SS + 0.75 V ≤ VIN ≤
VDD-0.75
biased at VRef =1.5 V
Load ≥ 100 kΩ to VSS @ GS
No Load
6
7
8
9
DC open loop voltage gain
Unity gain bandwidth
AVOL
fC
32
dB
MHz
Vpp
pF
0.30
Output voltage swing
VO
2.2
1.5
Maximum capacitive load (GS)
CL
100
50
10 Resistive load (GS)
11 Common mode range
RL
kΩ
VCM
Vpp
AC Electrical Characteristics - VDD=3.0V +20%/-10%, VSS=0V, -40°C ≤ TO ≤ +85°C, using Test Circuit shown in Fig. 6.
‡
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
Valid input signal levels
(each tone of composite
signal)
-34
15.4
-4.0
489
dBm
1,2,3,5,6,9
mVRMS Min @ VDD=3.6V
Max @ VDD=2.7V
2
3
4
5
6
7
8
Negative twist accept
Positive twist accept
Frequency deviation accept
Frequency deviation reject
Third zone tolerance
Noise tolerance
8
8
dB
dB
2,3,6,9,12
2,3,6,9,12
2,3,5,9
±1.5% ± 2 Hz
±3.5%
2,3,5,9
-16
-12
+22
dB
dB
dB
2,3,4,5,9,10
2,3,4,5,7,9,10
2,3,4,5,8,9,11
Dial zone tolerance
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES
1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all DTMF tones.
3. Tone duration= 40 ms, tone pause= 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by ±1.5%± 2 Hz.
7. Bandwidth limited (3 kHz ) Gaussian noise.
8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.
9. For an error rate of better than 1 in 10,000.
10. Referenced to lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept level.
12. Guaranteed by design and characterization.
4-29
MT88L70
AC Electrical Characteristics - VDD=3.0V+20%/-10%, VSS=0V, -40°C ≤ To ≤ +85°C, using Test Circuit shown in Figure 6.
‡
Characteristics
Sym
Min
Typ
Max
Units
Conditions
1
2
Tone present detect time
Tone absent detect time
Tone duration accept
tDP
tDA
5
11
4
14
8.5
40
ms Note 1
ms Note 1
ms Note 2
ms Note 2
ms Note 2
ms Note 2
0.5
T
I
M
I
N
G
3
tREC
tREC
tID
4
Tone duration reject
20
20
5
Interdigit pause accept
40
6
Interdigit pause reject
tDO
7
Propagation delay (St to Q)
Propagation delay (St to StD)
Output data set up (Q to StD)
Propagation delay (TOE to Q ENABLE)
tPQ
11
20
µs
µs
µs
TOE=VDD
8
O
U
T
P
U
T
tPStD
tQStD
tPTE
TOE=VDD
TOE=VDD
9
5.0
50
10
ns
load of 10 kΩ,
50 pF
S
11
Propagation delay (TOE to Q DISABLE) tPTD
130
ns
load of 10 kΩ,
50 pF
P
D
W
N
12
13
Power-up time
tPU
tPD
30
20
ms Note 3
ms
Power-down time
14
15
16
17
18
Crystal/clock frequency
Clock input rise time
Clock input fall time
Clock input duty cycle
Capacitive load (OSC2)
fC
3.5759 3.5795 3.5831 MHz
C
L
O
C
K
tLHCL
tHLCL
DCCL
CLO
110
110
60
ns
ns
%
Ext. clock
Ext. clock
Ext. clock
40
50
15
pF
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:
1.
2.
Used for guard-time calculation purposes only and tested at -4dBm.
These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
are recommendations based upon network requirements.
3.
With valid tone present at input, tPU equals time from PDWN going low until ESt going high.
4-30
MT88L70
D
A
B
C
E
F
G
EVENTS
tREC
tDO
tID
tREC
TONE
#n + 1
TONE
#n + 1
TONE #n
Vin
tDP
tDA
ESt
tGTA
tGTP
VTSt
St/GT
tPQ
tQStD
HIGH IMPEDANCE
Q1-Q4
# n
# (n + 1)
DECODED TONE # (n-1)
tPSrD
StD
tPTE
tPTD
TOE
EXPLANATION OF EVENTS
A)
B)
C)
TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED.
TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS.
END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID
TONE.
D)
E)
OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE.
TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY
HIGH IMPEDANCE).
F)
ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED.
G)
END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT
VALID TONE.
EXPLANATION OF SYMBOLS
Vin
DTMF COMPOSITE INPUT SIGNAL.
ESt
EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
4-BIT DECODED TONE OUTPUT.
St/GT
Q1-Q4
StD
DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL.
TOE
tREC
tREC
tID
TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q1-Q4 TO ITS HIGH IMPEDANCE STATE.
MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.
MINIMUM TIME BETWEEN VALID DTMF SIGNALS.
tDO
MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL.
TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS.
TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS.
GUARD TIME, TONE PRESENT.
tDP
tDA
tGTP
tGTA
GUARD TIME, TONE ABSENT.
Figure 7 - Timing Diagram
4-31
MT88L70
NOTES:
4-32
相关型号：
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