MT8888CC-1 [MITEL]
Integrated DTMFTransceiver with Intel Micro Interface; 综合DTMFTransceiver与英特尔微型接口
| 型号： | MT8888CC-1 |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | Integrated DTMFTransceiver with Intel Micro Interface |
| 文件： | 总16页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT8888C/MT8888C-1
Integrated DTMF Transceiver
with Intel Micro Interface
ISSUE 2
May 1995
Features
Ordering Information
•
•
•
•
•
•
Central office quality DTMF transmitter/receiver
MT8888CE/CE-1 20 Pin Plastic DIP
MT8888CC/CC-1 20 Pin Ceramic DIP
MT8888CS/CS-1 20 Pin SOIC
MT8888CN/CN-1 24 Pin SSOP
Low power consumption
High speed Intel micro interface
Adjustable guard time
-40°C to +85°C
Automatic tone burst mode
Call progress tone detection to -30dBm
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
Applications
transmitter utilizes
a
switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
•
•
•
•
•
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
The MT8888C utilizes an Intel micro interface, which
allows the device to be connected to a number of
popular microcontrollers with minimal external logic.
The MT8888C-1 is functionally identical to the
MT8888C except the receiver is enhanced to accept
lower level signals, and also has a specified low
signal rejection level.
Description
The MT8888C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
technology offering low power consumption and high
reliability.
D0
Data
Row and
D/A
Transmit Data
Bus
D1
D2
D3
∑
Column
TONE
Converters
Register
Buffer
Counters
Status
Register
Interrupt
Logic
Tone Burst
Gating Cct.
Control
Logic
IRQ/CP
Control
Register
A
IN+
IN-
GS
+
-
Dial
Tone
Filter
High Group
Filter
Digital
RD
Algorithm
and Code
Converter
Control
Register
B
I/O
Control
CS
Low Group
Filter
OSC1
OSC2
Oscillator
R/W
RS0
Circuit
Control
Logic
Receive Data
Register
Steering
Logic
Bias
Circuit
VDD VRef VSS
ESt
St/GT
Figure 1 - Functional Block Diagram
4-91
MT8888C/MT8888C-1
20
19
18
17
16
15
14
13
12
11
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W
CS
1
2
3
4
5
6
7
8
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
9
10
9
RD
RS0
10
11
12
RD
RS0
20 PIN CERDIP/PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
20 24
1
2
3
1
2
3
IN+ Non-inverting op-amp input.
IN-
GS
Inverting op-amp input.
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
5
6
7
4
5
6
7
V
Reference Voltage output (V /2).
Ref
DD
V
Ground (0V).
SS
OSC1 Oscillator input. This pin can also be driven directly by an external clock.
OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
8
9
10 TONE Output from internal DTMF transmitter.
11 WR Write microprocessor input. TTL compatible.
10 12
CS
Chip Select input. Active Low. This signal must be qualified externally by address latch
enable (ALE) signal, see Figure 12.
11 13
12 14
13 15
RS0 Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
RD Read microprocessor input. TTL compatible.
IRQ/ Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes
CP
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
14- 18- D0-D3 Microprocessor Data Bus. High impedance when CS = 1 or RD = 1.
17 21
TTL compatible.
18 22
ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
19 23 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than V
detected at St
TSt
causes the device to register the detected tone pair and update the output latch. A voltage
less than V frees the device to accept a new tone pair. The GT output acts to reset the
TSt
external steering time-constant; its state is a function of ESt and the voltage on St.
20 24
V
Positive power supply (5V typ.).
No Connection.
DD
8,9
16,17
NC
4-92
MT8888C/MT8888C-1
Functional Description
The
MT8888C/MT8888C-1
Integrated
DTMF
Transceiver consists of a high performance DTMF
receiver with an internal gain setting amplifier and a
DTMF generator which employs a burst counter to
synthesize precise tone bursts and pauses. A call
progress mode can be selected so that frequencies
within the specified passband can be detected. The
Intel micro interface allows microcontrollers, such as
the 8080, 80C31/51 and 8085, to access the
MT8888C/MT8888C-1 internal registers.
R1
IN+
IN-
C1
C2
R4
R5
R2
GS
R3
VRef
Input Configuration
MT8888C/
MT8888C-1
The input arrangement of the MT8888C/MT8888C-1
provides a differential-input operational amplifier as
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
well as a bias source (V ), which is used to bias the
Ref
inputs at V /2. Provision is made for connection of
DD
a feedback resistor to the op-amp output (GS) for
gain adjustment. In a single-ended configuration, the
input pins are connected as shown in Figure 3.
VOLTAGE GAIN
(AV diff) - R5/R1
INPUT IMPEDANCE
(ZINdiff) = 2 R12 + (1/ωC)2
Figure 4 shows the necessary connections for a
differential input configuration.
Figure 4 - Differential Input Configuration
Receiver Section
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Table 1). These
filters incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.
FLOW
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
FHIGH
DIGIT
1
D3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
D1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
2
3
4
5
6
7
8
9
IN+
IN-
0
*
RIN
C
#
GS
A
B
C
D
RF
VRef
MT8888C/
MT8888C-1
VOLTAGE GAIN
(AV) = RF / RIN
0= LOGIC LOW, 1= LOGIC HIGH
Table 1. Functional Encode/Decode Table
Figure 3 - Single-Ended Input Configuration
4-93
MT8888C/MT8888C-1
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
VDD
MT8888C/
MT8888C-1
C1
VDD
Vc
St/GT
ESt
R1
tGTA = (R1C1) In (VDD / VTSt
)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
Steering Circuit
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the following inequalities
(see Figure 7):
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v (see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
t
≥ t
+t
- t
REC
DPmax GTPmax DAmin
c
t
≤ t
+t
- t
- t
REC
DPmin GTPmin
DAmax
t
≥ t
+t
ID
DAmax GTAmax
DPmin
the validation period (t
), v reaches the threshold
t
≤ t
+t
- t
GTP
c
DO
DAmin GTAmin DPmax
(V ) of the steering logic to register the tone pair,
TSt
latching its corresponding 4-bit code (see Table 1)
into the Receive Data Register. At this point the GT
The value of t
Electrical Characteristics) and t
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
is a device parameter (see AC
DP
is the minimum
REC
output is activated and drives v to V . GT
c
DD
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
t
GTA = (R1C1) In (VDD/VTSt
)
RP = (R1R2) / (R1 + R2)
VDD
C1
St/GT
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
R1
R2
ESt
a) decreasing tGTP; (tGTP < tGTA)
t
GTP = (R1C1) In [VDD / (VDD-VTSt)]
t
GTA = (RpC1) In (VDD/VTSt
)
VDD
R
P = (R1R2) / (R1 + R2)
C1
St/GT
R1
R2
b) decreasing tGTA; (tGTP > tGTA)
ESt
Figure 6 - Guard Time Adjustment
4-94
MT8888C/MT8888C-1
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
mode has been selected. DTMF signals cannot be
detected if CP mode has been selected (see Table
7). Figure 8 indicates the useful detect bandwidth of
the call progress filter. Frequencies presented to the
input, which are within the ‘accept’ bandwidth limits
of the filter, are hard-limited by a high gain
comparator with the IRQ/CP pin serving as the
output. The squarewave output obtained from the
schmitt trigger can be analyzed by a microprocessor
or counter arrangement to determine the nature of
the call progress tone being detected. Frequencies
which are in the ‘reject’ area will not be detected and
consequently the IRQ/CP pin will remain low.
used to select independent tone present (t
) and
GTP
tone absent (t
) guard times. This may be
GTA
necessary to meet system specifications which place
both accept and reject limits on tone duration and
interdigital pause. Guard time adjustment also allows
the designer to tailor system parameters such as talk
off and noise immunity.
Increasing t
improves talk-off performance since
REC
it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short t
with a long t
would be appropriate for
LEVEL
(dBm)
REC
DO
extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.
-25
Call Progress Filter
0
250
500
750
FREQUENCY (Hz)
= Reject
A
call progress mode, using the MT8888C/
MT8888C-1, can be selected allowing the detection
of various tones, which identify the progress of a
telephone call on the network. The call progress
tone input and DTMF input are common, however,
call progress tones can only be detected when CP
= May Accept
= Accept
Figure 8 - Call Progress Response
EVENTS
A
B
C
D
E
F
tREC
tDO
tID
tREC
TONE
#n + 1
TONE
#n + 1
TONE #n
Vin
tDA
tDP
ESt
tGTP
tGTA
VTSt
St/GT
tPStRX
RX0-RX3
b3
DECODED TONE # (n-1)
# (n + 1)
# n
tPStb3
b2
Read
Status
Register
IRQ/CP
Figure 7 - Receiver Timing Diagram
4-95
MT8888C/MT8888C-1
EXPLANATION OF EVENTS
A)
B)
C)
TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.
TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
D)
E)
F)
TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.
END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLS
Vin
DTMF COMPOSITE INPUT SIGNAL.
ESt
St/GT
EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
RX0-RX3 4-BIT DECODED DATA IN RECEIVE DATA REGISTER
b3
DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A
VALID DTMF SIGNAL.
b2
INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS
REGISTER IS READ.
IRQ/CP
INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS
CLEARED AFTER THE STATUS REGISTER IS READ.
tREC
tREC
tID
tDO
tDP
MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.
MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.
MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.
TIME TO DETECT VALID FREQUENCIES PRESENT.
tDA
TIME TO DETECT VALID FREQUENCIES ABSENT.
tGTP
tGTA
GUARD TIME, TONE PRESENT.
GUARD TIME, TONE ABSENT.
Figure 9 - Description of Timing Events
write operations to the Transmit Data Register the 4
DTMF Generator
bit data on the bus is latched and converted to 2 of 8
coding for use by the programmable divider circuitry.
This code is used to specify a time segment length,
which will ultimately determine the frequency of the
tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse
is issued and the counter starts again. The number
of time segments is fixed at 32, however, by varying
the segment length as described above the
frequency can also be varied. The divider output
clocks another counter, which addresses the
sinewave lookup ROM.
The DTMF transmitter employed in the MT8888C/
MT8888C-1 is capable of generating all sixteen
standard DTMF tone pairs with low distortion and
high accuracy. All frequencies are derived from an
external 3.579545 MHz crystal. The sinusoidal
waveforms for the individual tones are digitally
synthesized using row and column programmable
dividers and switched capacitor D/A converters. The
row and column tones are mixed and filtered
providing a DTMF signal with low total harmonic
distortion and high accuracy. To specify a DTMF
signal, data conforming to the encoding format
shown in Table 1 must be written to the transmit Data
Register. Note that this is the same as the receiver
output code. The individual tones which are
The lookup table contains codes which are used by
the switched capacitor D/A converter to obtain
discrete and highly accurate DC voltage levels. Two
identical circuits are employed to produce row and
column tones, which are then mixed using a low
noise summing amplifier. The oscillator described
needs no “start-up” time as in other DTMF
generators since the crystal oscillator is running
continuously thus providing a high degree of tone
generated (f
and f
) are referred to as Low
LOW
HIGH
Group and High Group tones. As seen from the
table, the low group frequencies are 697, 770, 852
and 941 Hz. The high group frequencies are 1209,
1336, 1477 and 1633 Hz. Typically, the high group to
low group amplitude ratio (twist) is 2 dB to com-
pensate for high group attenuation on long loops.
burst accuracy.
A
bandwidth limiting filter is
incorporated and serves to attenuate distortion
products above 8 kHz. It can be seen from Figure 8
that the distortion products are very low in amplitude.
The period of each tone consists of 32 equal time
segments. The period of a tone is controlled by
varying the length of these time segments. During
4-96
MT8888C/MT8888C-1
Scaling Information
10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz
Figure 10 - Spectrum Plot
Burst Mode
OUTPUT FREQUENCY (Hz)
ACTIVE
INPUT
%ERROR
SPECIFIED
697
ACTUAL
699.1
In certain telephony applications it is required that
DTMF signals being generated are of a specific
duration determined either by the particular
application or by any one of the exchange transmitter
specifications currently existing. Standard DTMF
signal timing can be accomplished by making use of
the Burst Mode. The transmitter is capable of issuing
symmetric bursts/pauses of predetermined duration.
This burst/pause duration is 51 ms±1 ms, which is a
standard interval for autodialer and central office
applications. After the burst/pause has been issued,
the appropriate bit is set in the Status Register
indicating that the transmitter is ready for more data.
The timing described above is available when DTMF
mode has been selected. However, when CP mode
(Call Progress mode) is selected, the burst/pause
duration is doubled to 102 ms ±2 ms. Note that when
CP mode and Burst mode have been selected,
DTMF tones may be transmitted only and not
received. In applications where a non-standard
burst/pause time is desirable, a software timing loop
or external timer can be used to provide the timing
pulses when the burst mode is disabled by enabling
and disabling the transmitter.
L1
L2
L3
L4
H1
H2
H3
H4
+0.30
-0.49
-0.54
+0.74
+0.57
-0.32
-0.35
+0.73
770
766.2
852
847.4
941
948.0
1209
1336
1477
1633
1215.9
1331.7
1471.9
1645.0
Table 2. Actual Frequencies Versus Standard
Requirements
Distortion Calculations
The MT8888C/MT8888C-1 is capable of producing
precise tone bursts with minimal error in frequency
(see Table 2). The internal summing amplifier is
followed by a first-order lowpass switched capacitor
filter to minimize harmonic components and
intermodulation products. The total harmonic
distortion for a single tone can be calculated using
Equation 1, which is the ratio of the total power of all
the extraneous frequencies to the power of the
fundamental frequency expressed as a percentage.
Single Tone Generation
A single tone mode is available whereby individual
tones from the low group or high group can be
generated. This mode can be used for DTMF test
equipment applications, acknowledgment tone
generation and distortion measurements. Refer to
Control Register B description for details.
V22f + V23f + V24f + .... V2
nf
THD (%) = 100
Vfundamental
Equation 1. THD (%) For a Single Tone
4-97
MT8888C/MT8888C-1
The Fourier components of the tone output
Figures 17 and 18 are the timing diagrams for the
Intel 8031, 8051 and 8085 (5 MHz) microcontrollers.
By NANDing the address latch enable (ALE) output
with the high-byte address (P2) decode output, CS is
generated. Figure 12 summarizes the connection of
these Intel processors to the MT8888C/MT8888C-1
transceiver.
correspond to V .... V as measured on the output
2f
nf
waveform. The total harmonic distortion for a dual
tone can be calculated using Equation 2. V and V
L
H
correspond to the low group amplitude and high
2
group amplitude, respectively and V
is the sum
IMD
of all the intermodulation components. The internal
switched-capacitor filter following the D/A converter
keeps distortion products down to a very low level as
shown in Figure 10.
The microprocessor interface provides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last
valid DTMF digit received. Data entered into the
write-only Transmit Data Register will determine
which tone pair is to be generated (see Table 1 for
coding details). Transceiver control is accomplished
with two control registers (see Tables 6 and 7), CRA
and CRB, which have the same address. A write
operation to CRB is executed by first setting the
most significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the current transceiver state (see Table 8).
V22L + V23L + .... V2nL + V2
+
2H
V23H + .. V2nH + V2
IMD
THD (%) = 100
V2L + V2
H
Equation 2. THD (%) For a Dual Tone
DTMF Clock Circuit
The internal clock circuit is completed with the
addition of a standard television colour burst crystal.
The crystal specification is as follows:
A software reset must be included at the beginning
of all programs to initialize the control registers upon
power-up or power reset (see Figure 17). Refer to
Tables 4-7 for bit descriptions of the two control
registers.
Frequency:
3.579545 MHz
±0.1%
Parallel
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
18pF
The multiplexed IRQ/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a squarewave output of the call
progress signal. The IRQ/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13).
Maximum Series Resistance:150 ohms
Maximum Drive Level:
2mW
e.g. CTS Knights MP036S
Toyocom TQC-203-A-9S
A number of MT8888C/MT8888C-1 devices can be
connected as shown in Figure 11 such that only one
crystal is required. Alternatively, the OSC1 inputs on
all devices can be driven from a TTL buffer with the
OSC2 outputs left unconnected.
RS0
WR
RD
FUNCTION
Write to Transmit
Data Register
0
0
1
Read from Receive
Data Register
0
1
0
MT8888C/
MT8888C/
MT8888C/
MT8888C-1
MT8888C-1
MT8888C-1
Write to Control Register
Read from Status Register
1
1
0
1
1
0
OSC1 OSC2
OSC1 OSC2
OSC1 OSC2
Table 3. Internal Register Functions
3.579545 MHz
b3
b2
b1
b0
Figure 11 - Common Crystal Connection
RSEL
IRQ
CP/DTMF
TOUT
Table 4. CRA Bit Positions
Microprocessor Interface
b3
b2
b1
b0
The MT8888C/MT8888C-1 incorporates an Intel
microprocessor interface which is compatible with
fast versions (16 MHz) of the 80C51. No wait cycles
need to be inserted.
C/R
S/D
TEST
BURST
ENABLE
Table 5. CRB Bit Positions
4-98
MT8888C/MT8888C-1
BIT
NAME
DESCRIPTION
b0
TOUT
Tone Output Control. A logic high enables the tone output; a logic low turns the tone output
off. This bit controls all transmit tone functions.
b1
CP/DTMF Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;
a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and
transmitting DTMF signals. In CP mode a rectangular wave representation of the received
tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control
register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected.
b2
b3
IRQ
Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the
interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).
RSEL
Register Select. A logic high selects control register B for the next write cycle to the control
register address. After writing to control register B, the following control register write cycle
will be directed to control register A.
Table 6. Control Register A Description
BIT
NAME
DESCRIPTION
b0
BURST
Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec.). Following the pause, the status register will be updated (b1 -
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).
b1
b2
b3
TEST
S/D
Test Mode Control. A logic high enables the test mode; a logic low de-activates the test
mode. When TEST is enabled and DTMF mode is selected (control register A, b1=0), the
signal present on the IRQ/CP pin will be analogous to the state of the DELAYED
STEERING bit of the status register (see Figure 7, signal b3).
Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (control
register B, b3).
C/R
Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (control register B,
b2).
Table 7. Control Register B Description
4-99
MT8888C/MT8888C-1
BIT
NAME
STATUS FLAG SET
STATUS FLAG CLEARED
b0
IRQ
Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
Interrupt is inactive. Cleared after
Status Register is read.
b1
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2
b3
RECEIVE DATA REGISTER
FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is
read.
DELAYED STEERING
Set upon the valid detection of
the absence of a DTMF signal.
Cleared upon the detection of a
valid DTMF signal.
Table 8. Status Register Description
8031/8051
8080/8085
MT8888C/MT8888C-1
A8-A15
CS
A8
RS0
D0-D3
PO
RD
RD
WR
WR
Figure 12 - MT8888C Interface Connections for Various Intel Micros
VDD
MT8888C/MT8888C-1
C3
VDD
St/GT
ESt
IN+
C1
R1
C2
DTMF/CP
INPUT
IN-
R4
GS
R3
R2
D3
VRef
VSS
OSC1
OSC2
TONE
WR
D2
X-tal
D1
D0
To µP
or µC
DTMF
OUTPUT
IRQ/CP
RD
RL
RS0
CS
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 Ω 1%
R4 = 3.3 kΩ 10%
RL = 10 k Ω (min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
X-tal = 3.579545 MHz
* Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT8888C/MT8888C-1 can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
Figure 13 - Application Circuit (Single-Ended Input)
4-100
MT8888C/MT8888C-1
5.0 VDC
5.0 VDC
MMD6150 (or
equivalent)
2.4 kΩ
3 kΩ
TEST POINT
TEST POINT
130 pF
24 kΩ
100 pF
MMD7000 (or
equivalent)
Test load for D0-D3 pins
Test load for IRQ/CP pin
Figure 14 - Test Circuits
INITIALIZATION PROCEDURE
A software reset must be included at the beginning of all programs to initialize the control registers after
power up.The initialization procedure should be implemented 100ms after power up.
Description:
Control
Data
b2
X
0
0
0
0
X
RS0
WR
1
0
0
0
RD
0
1
1
1
b3
X
0
0
1
b1
X
0
b0
X
0
1) Read Status Register
2) Write to Control Register
3) Write to Control Register
4) Write to Control Register
5) Write to Control Register
6) Read Status Register
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
X
0
0
X
X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS
Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.
Sequence:
RS0
WR
RD
b3
b2
b1
b0
1) Write to Control Register A
1
0
1
1
1
0
1
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B
(burst mode)
3) Write to Transmit Data Register
(send a digit 7)
1
0
0
0
1
1
0
0
0
1
0
1
0
1
4) Wait for an interrupt or poll Status Register
5) Read the Status Register
1
1
0
1
X
0
X
1
X
0
X
1
-if bit 1 is set, the Tx is ready for the next tone, in which case...
Write to Transmit Register
(send a digit 5)
0
0
-if bit 2 is set, a DTMF tone has been received, in which case....
Read the Receive Data Register
0
1
0
X
X
X
X
-if both bits are set...
Read the Receive Data Register
Write to Transmit Data Register
0
0
1
0
0
1
X
0
X
1
X
0
X
1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms).
Figure 15 - Application Notes
4-101
MT8888C/MT8888C-1
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
1
2
3
4
5
Power supply voltage V -V
V
6
V
V
DD SS
DD
Voltage on any pin
V
V
-0.3
V
+0.3
DD
I
SS
Current at any pin (Except V
Storage temperature
V
)
10
mA
°C
DD and SS
T
-65
+150
1000
ST
Package power dissipation
P
mW
D
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (V ) unless otherwise stated.
SS
‡
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
Positive power supply
Operating temperature
Crystal clock frequency
V
4.75
-40
5.00
5.25
+85
V
DD
T
°C
O
f
3.575965 3.579545 3.583124
MHz
CLK
‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics† - V =0 V.
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
Operating supply voltage
Operating supply current
Power consumption
V
4.75
5.0
7.0
5.25
11
V
mA
mW
V
DD
S
U
P
I
DD
P
57.8
C
High level input voltage
(OSC1)
V
3.5
2.2
Note 9*
Note 9*
=5V
IHO
I
N
P
U
T
S
5
Low level input voltage
(OSC1)
V
V
1.5
2.5
0.1
V
V
V
V
ILO
TSt
6
7
Steering threshold voltage
2.3
V
DD
Low level output voltage
(OSC2)
No load
Note 9*
V
OLO
OHO
O
U
T
P
U
T
8
9
High level output voltage
(OSC2)
No load
Note 9*
V
4.9
2.4
Output leakage current
(IRQ)
I
1
10
µA
V
V
=2.4 V
OH
OZ
S
10
11
12
13
14
V
V
output voltage
V
2.5
1.3
2.6
No load, V =5V
DD
Ref
Ref
Ref
output resistance
R
kΩ
V
OR
D
i
g
i
Low level input voltage
High level input voltage
Input leakage current
V
0.8
10
IL
V
2.0
V
IH
I
µA
V =V to V
IZ
IN
SS
DD
t
a
l
15
16
17
18
Source current
Sink current
I
I
-1.4
2.0
-0.5
2
-6.6
4.0
-3.0
4
mA
mA
mA
mA
V
V
V
V
=2.4V
OH
OH
Data
Bus
I
=0.4V
OL
OL
ESt
and
St/Gt
Source current
Sink current
=4.6V
OH
OH
I
=0.4V
OL
OL
OL
OL
IRQ/
CP
19
Sink current
I
4
16
mA
V
=0.4V
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25 °C, VDD =5V and for design aid only: not guaranteed and not subject to production testing.
* See “Notes” following AC Electrical Characteristics Tables.
4-102
MT8888C/MT8888C-1
Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V, VDD=5V, TO=25°C.
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
1
2
3
4
5
6
7
8
9
Input leakage current
Input resistance
I
±100
10
nA
MΩ
mV
dB
V
≤ V ≤ V
IN
SS
IN
DD
R
IN
Input offset voltage
V
25
OS
Power supply rejection
Common mode rejection
DC open loop voltage gain
Unity gain bandwidth
Output voltage swing
Allowable capacitive load (GS)
PSRR
CMRR
60
1 kHz
60
dB
0.75 ≤ V ≤ 4.25V
IN
A
65
dB
VOL
BW
1.5
4.5
100
50
MHz
V
V
R ≥ 100 kΩ to V
O
pp
L
SS
C
R
pF
L
L
10 Allowable resistive load (GS)
kΩ
11 Common mode range
V
3.0
V
No Load
CM
pp
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
MT8888C-1 AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1,2,3,5,6
1
2
Valid input signal levels
(each tone of composite
signal)
-31
+1
dBm
21.8
869
mV
1,2,3,5,6
RMS
R
X
Input Signal Level Reject
-37
dBm
mV
1,2,3,5,6
1,2,3,5,6
10.9
RMS
† Characteristics are over recommended temperature and at VDD=5V, using the test circuit shown in Figure 13.
MT8888C AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1,2,3,5,6
1,2,3,5,6
Valid input signal levels
(each tone of composite
signal)
-29
+1
dBm
R
X
1
27.5
869
mV
RMS
† Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13.
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. fC=3.579545 MHz
‡
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
2
3
4
5
6
7
Positive twist accept
Negative twist accept
Freq. deviation accept
Freq. deviation reject
Third tone tolerance
Noise tolerance
8
8
dB
dB
2,3,6,9
2,3,6,9
2,3,5
±1.5%± 2Hz
±3.5%
R
X
2,3,5
-16
-12
22
dB
dB
dB
2,3,4,5,9,10
2,3,4,5,7,9,10
2,3,4,5,8,9
Dial tone tolerance
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing.
* *See “Notes” following AC Electrical Characteristics Tables.
4-103
MT8888C/MT8888C-1
AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated.
‡
Characteristics
Accept Bandwidth
Sym
Min
Typ
Max
Units
Conditions
1
f
310
500
Hz
@ -25 dBm,
A
Note 9
2
3
4
Lower freq. (REJECT)
Upper freq. (REJECT)
f
290
540
Hz
Hz
@ -25 dBm
@ -25 dBm
LR
f
HR
Call progress tone detect level (total
power)
-30
dBm
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics†- DTMF Reception - Typical DTMF tone accept and reject requirements. Actual
values are user selectable as per Figures 5, 6 and 7.
‡
Characteristics
Sym
Min
Typ
Max
Units
Conditions
1
2
3
4
Minimum tone accept duration
Maximum tone reject duration
Minimum interdigit pause duration
Maximum tone drop-out duration
t
t
40
20
40
20
ms
ms
ms
ms
REC
REC
t
ID
t
OD
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics† - Voltages are with respect to ground (VSS), unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Conditions
T
O
N
E
1
2
3
4
Tone present detect time
Tone absent detect time
Delay St to b3
t
t
3
11
4
14
ms Note 11
ms Note 11
DP
DA
0.5
8.5
t
13
8
µs
µs
See Figure 7
See Figure 7
PStb3
I
N
Delay St to RX -RX
t
PStRX
0
3
5
Tone burst duration
t
50
50
52
52
ms DTMF mode
BST
6
Tone pause duration
t
ms DTMF mode
PS
7
Tone burst duration (extended)
Tone pause duration (extended)
High group output level
Low group output level
Pre-emphasis
t
100
100
-6.1
-8.1
0
104
104
-2.1
-4.1
3
ms Call Progress mode
ms Call Progress mode
BSTE
T
O
N
E
8
t
PSE
9
V
dBm R =10kΩ
HOUT
L
10
11
12
13
14
15
16
17
18
19
V
dBm R =10kΩ
L
LOUT
O
U
T
dB
2
dB
dB
R =10kΩ
P
L
Output distortion (Single Tone)
THD
-35
25 kHz Bandwidth
R =10kΩ
L
Frequency deviation
f
±0.7
±1.5
50
%
f =3.579545 MHz
D
C
Output load resistance
Crystal/clock frequency
Clock input rise and fall time
Clock input duty cycle
Capacitive load (OSC2)
R
10
kΩ
LT
f
3.5759 3.5795 3.5831 MHz
C
X
T
A
L
t
110
60
ns
%
Ext. clock
Ext. clock
CLRF
DC
40
50
CL
C
30
pF
LO
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
4-104
MT8888C/MT8888C-1
AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Conditions
Figure 16
1
2
3
4
5
6
7
8
9
RD/WR clock frequency
RD/WR cycle period
f
t
4.0
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
CYC
250
Figure 16
CYC
RD/WR rise and fall time
Address setup time
t
t
20
Figure 16
R, F
t
23
26
22
Figures 17 & 18
Figures 17 & 18
Figures 17 & 18
Figures 17 & 18
Figures 16, 17 & 18
Figures 16, 17 & 18
Figures 17 & 18
Figures 17 & 18
AS
AH
Address hold time
t
Data hold time (read)
RD to valid data delay (read)
RD, WR pulse width low
RD, WR pulse width high
t
t
t
DHR
DDR
PWL
PWH
DSW
DHW
100
150
t
t
100
10 Data setup time (write)
45
10
11 Data hold time (write)
t
12 Input Capacitance (data bus)
C
5
5
IN
13 Output Capacitance (IRQ/CP)
C
OUT
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2) Digit sequence consists of all 16 DTMF tones.
3) Tone duration=40 ms. Tone pause=40 ms.
4) Nominal DTMF frequencies are used.
5) Both tones in the composite signal have an equal amplitude.
6) The tone pair is deviated by ± 1.5%±2 Hz.
7) Bandwidth limited (3 kHz) Gaussian noise.
8) The precise dial tone frequencies are 350 and 440 Hz (±2%).
9) Guaranteed by design and characterization. Not subject to production testing.
10) Referenced to the lowest amplitude tone in the DTMF signal.
11) For guard time calculation purposes.
4-105
MT8888C/MT8888C-1
tCYC
tR
tF
tPWH
tPWL
RD/WR
Figure 16 - RD/WR Clock Pulse
tPWL
RD
tPWH
tAS
tAH
CS, RS0
tDHR
tDDR
DATA BUS
Figure 17 - 8031/8051/8085 Read Timing Diagram
tPWL
RD
tPWH
tAS
tAH
CS, RS0
tDSW
tDHW
DATA BUS
Figure 18 - 8031/8051/8085 Write Timing Diagram
4-106
相关型号：
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